Printed circuit board

Abstract

An aspect of the present disclosure may provide a printed circuit board capable of improving structural stability and electrical characteristics in coupling a plurality of wiring parts.SOLUTION: A first wiring part including a first insulating layer and a first conductor layer, a second wiring part including a second insulating layer and a second conductor layer and disposed on the first wiring part, and a third wiring part disposed between the first and second wiring parts and connecting the first and second wiring parts to each other, the printed circuit board may further include a bonding part including a bonding layer and metal fillers dispersed in the bonding layer, wherein the first wiring part may include a groove formed in a surface thereof facing the bonding part, and the groove may be filled with the bonding part.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, packages containing memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are being used to process data that has increased exponentially.

[0003] Research is ongoing into how to reduce defects that occur during chip mounting on printed circuit boards used in these packages and improve yields. As the number of layers in a board increases, the defect rate for each layer accumulates, potentially reducing overall yields. This reduction in yield can be particularly significant for boards that require fine circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a printed circuit board that can improve structural stability and electrical characteristics when connecting a plurality of wiring portions. [Means for solving the problem]

[0005] As a method for solving the above-mentioned problems, the present invention proposes a novel structure of a printed circuit board through one example. Specifically, a printed circuit board according to one embodiment of the present invention includes a first wiring portion including a first insulating layer and a first conductor layer, a second wiring portion including a second insulating layer and a second conductor layer and disposed on the first wiring portion, and a bonding portion disposed between the first and second wiring portions to connect the first and second wiring portions, the bonding portion including a bonding layer and a metal filler dispersed within the bonding layer, and the first wiring portion includes a groove formed on a surface facing the bonding portion, and the groove is filled with the bonding portion.

[0006] In one embodiment, at least a portion of the second conductor layer connected to the joint portion in the second wiring portion may have a protrusion protruding from the second insulating layer toward the first wiring portion.

[0007] In one embodiment, at least a portion of the protruding portion of the second conductor layer may be disposed in the groove.

[0008] In one embodiment, at least a portion of the second conductor layer arranged in the groove may be electrically isolated from the remaining portion of the second conductor layer within the second wiring portion.

[0009] In one embodiment, the groove of the first wiring portion may be formed in the first insulating layer.

[0010] In one embodiment, the pitch of the first conductor layer arranged at the top in the first wiring portion may be shorter than the pitch of the second conductor layer arranged at the top in the second wiring portion.

[0011] In one embodiment, the groove of the first wiring portion may be formed in the first conductor layer.

[0012] In one embodiment, the first insulating layer may include a through hole formed on its upper surface, and the groove may be formed by the first conductor layer extending from the upper surface of the first insulating layer to the inner wall of the through hole.

[0013] In one embodiment, the groove may have a shape in which the width decreases from the upper surface to the lower surface of the first insulating layer.

[0014] In one embodiment, the groove may be formed only in a portion of the first conductor layer connected to the junction in the first wiring portion.

[0015] In one embodiment, when the direction in which the first and second wiring portions are stacked is defined as a first direction and the direction perpendicular to the first direction is defined as a second direction, the first conductor layer connected to the joint portion and having a groove may be arranged in a first region corresponding to the center of the second direction, and the first conductor layer connected to the joint portion and not having a groove may be arranged in a second region corresponding to the end of the second direction.

[0016] In one embodiment, at least a portion of the second conductor layer connected to the joint portion in the second wiring portion has a protrusion protruding from the second insulating layer toward the first wiring portion, and the height of the protrusion may be greater in the second region than in the first region.

[0017] In one embodiment, the second conductor layer connected to the joint portion in the second wiring portion may be at least partially embedded in the second insulating layer.

[0018] In one embodiment, the lower surface of the second conductor layer connected to the joint in the second wiring portion is positioned higher than the lower surface of the second insulating layer to form a recess, and the joint can fill the recess in the second wiring portion.

[0019] In one embodiment, the first conductor layer disposed at the bottom of the first wiring portion may be at least partially embedded in the first insulating layer.

[0020] In one embodiment, when the direction in which the first and second wiring portions are stacked is defined as a first direction and the direction perpendicular to the first direction is defined as a second direction, the width of the first wiring portion in the second direction may be wider than the width of the second wiring portion and the joint portion in the second direction. [Effects of the Invention]

[0021] In the case of a printed circuit board according to an embodiment of the present invention, structural stability and electrical characteristics can be improved when a plurality of wiring portions are connected. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 4] 1A to 1C are cross-sectional views schematically illustrating a part of a manufacturing process for a printed circuit board. [Figure 5] 1A to 1C are cross-sectional views schematically illustrating a part of a manufacturing process for a printed circuit board. [Figure 6] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 7] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 8] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 9] 1 shows an example of a printed circuit board, with the periphery of a groove in a first conductor layer enlarged. [Figure 10] 1 shows an example of a printed circuit board, with the periphery of a groove in a first conductor layer enlarged. [Figure 11] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 12] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shape and size of elements in the drawings may be exaggerated for clarity, and elements designated by the same reference numerals in the drawings are the same elements.

[0024] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0025] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components described below to form various signal lines 1090.

[0026] Examples of chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that the chip-related components 1020 may include other types of chip-related electronic components. It goes without saying that these chip-related components 1020 may be combined with one another. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0027] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020.

[0028] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components are not limited to these, and may also include passive elements in the form of chip components used for various other applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0029] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of the other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. These may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0030] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and it goes without saying that the electronic device 1000 may be any other electronic device that processes data.

[0031] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0032] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. The smartphone 1100 also houses other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the above-mentioned chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. It goes without saying that the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0033] printed circuit board FIG. 3 is a cross-sectional view schematically illustrating an example of a printed circuit board. Referring to FIG. 3, the printed circuit board 100 according to this embodiment includes a first wiring portion 110 and a second wiring portion 120. The first and second wiring portions 110, 120 are connected by a bonding portion 130 including a bonding layer 131 and a metal filler 132. The first wiring portion 110 includes a groove G formed on a surface facing the bonding portion 130 (the upper surface as viewed in FIG. 3), and the groove G is filled with the bonding portion 130. In this embodiment, the groove G is formed in the first conductor layer 112 of the first wiring portion 110. As will be described later, a groove may also be formed in the first insulating layer 111. By forming the groove G in the first wiring portion 110 and filling it with the bonding portion 130, when the first and second wiring portions 110, 120 are joined, the matching performance and adhesion strength can be improved, thereby improving the structural stability of the printed circuit board 100. In addition to the bonding function, the bonding portion 130 contains a metal filler 132 therein, thereby electrically connecting the first and second wiring portions 110 and 120. Hereinafter, the main components of the printed circuit board 100 will be described in detail.

[0034] The first wiring unit 110 includes a first insulating layer 111 and a first conductor layer 112, each of which may have a structure in which multiple layers are stacked. The first insulating layer 111 may include a first core unit 111B and build-up units 111A and 111C arranged above and below it. In this case, the direction in which the first and second wiring units 110 and 120 are stacked may be defined as a first direction D1, and two directions perpendicular to the first direction D1 and perpendicular to each other may be defined as a second direction D2 and a third direction D3, respectively.

[0035] The first core portion 111B may include an insulating material, which may be, but is not limited to, an insulating resin such as a thermosetting resin like epoxy resin or a thermoplastic resin like polyimide, a material in which these resins are mixed with an inorganic filler like silica, or a resin impregnated in a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, CCL (Copper Clad Laminate). If necessary, a core insulating layer made of other materials, such as a glass substrate, may be introduced into the first core portion 111B, or a metal core layer may be used. The first core portion 111B may be provided with a first through via 114, which may connect the first conductor layers 112 arranged above and below the first core portion 111B.

[0036] The buildup portions 111A and 111C may be disposed on both sides of the first core portion 111B and have a multi-layer structure. The buildup portions 111A and 111C may include an insulating resin, such as a thermosetting resin like epoxy resin or a thermoplastic resin like polyimide, a material in which these resins are mixed with an inorganic filler like silica, or a resin impregnated into a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, Ajinomoto Build-up Film (ABF) or prepreg. If necessary, the buildup portions 111A and 111C may also include a photoimageable dielectric (PID). The regions of the first insulating layer 111 that constitute the buildup portions 111A and 111C may be obtained by stacking multiple insulating layers, and the multiple insulating layers may include the same or different insulating materials.

[0037] The first conductor layer 112 may include, as a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first conductor layer 112 may include an electroless plating layer and an electrolytic plating layer, and may further include copper foil as needed. The first conductor layer 112 may perform various functions depending on the design of the layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as a data signal. Each of these patterns may include a trace, a plane, and / or a pad.

[0038] When the first conductor layer 112 has a multi-layer structure as in this embodiment, a first via 113 may be provided to connect the layers. The first via 113 may include, as a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first via 113 may be formed together with the first conductor layer 112 and may include an electroless plating layer and an electrolytic plating layer. The first via 113 may be a filled type in which a through hole in the first insulating layer 111 is filled with a metal material, but is not limited thereto. It may also be a conformal type in which a metal material is disposed along the wall surface of the through hole. The first via 113 may have a tapered cross section. The first via 113 may perform various functions depending on the design of the layer. For example, the first via 113 may include a ground via, a power via, a signal via, etc. Here, the signal vias may include vias for transmitting various signals, such as data signals, excluding ground vias, power vias, and the like.

[0039] A first solder resist layer 115 may be disposed under the first wiring unit 110. The first solder resist layer 115 may have an opening that partially exposes the first conductor layer 112 disposed at the bottom of the first wiring unit 110. The first solder resist layer 115 may include a known solder resist material and may include, but is not limited to, a photosensitive insulating material.

[0040] The second wiring unit 120 includes a second insulating layer 121 and a second conductor layer 122, each of which may have a structure in which multiple layers are stacked. The second insulating layer 121 may include an insulating resin, such as a thermosetting resin like epoxy resin or a thermoplastic resin like polyimide, a material in which these resins are mixed with an inorganic filler like silica, or a resin impregnated into a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, Ajinomoto Build-up Film (ABF) or prepreg. If necessary, the second insulating layer 121 may also include a photoimageable dielectric (PID). The second insulating layer 121 may be obtained by stacking multiple insulating layers, and the multiple insulating layers may include the same or different insulating materials.

[0041] The second conductor layer 122 may include, as a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second conductor layer 122 may include an electroless plating layer and an electrolytic plating layer, and may further include copper foil as needed. The second conductor layer 122 may perform various functions depending on the design of the layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as data signals. Each of these patterns may include a trace, a plane, and / or a pad. In the case of the second wiring unit 120, the second conductor layer 122 provided therein may be realized to have a relatively narrower pitch than the first conductor layer 112 through a fine circuit process.

[0042] When the second conductor layer 122 has a multi-layer structure as in this embodiment, a second via 123 may be provided to connect the layers. The second via 123 may include, as a metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second via 123 may be formed together with the second conductor layer 122 and may include an electroless plating layer and an electrolytic plating layer. The second via 123 may be a filled type in which a through hole in the second insulating layer 121 is filled with a metal material, but is not limited thereto. It may also be a conformal type in which a metal material is disposed along the wall surface of the through hole. The second via 123 may have a tapered shape in cross section. In this case, the first via 113 and the second via 123 may have tapered shapes in opposite directions depending on the manufacturing process. 3, the second via 123 has a shape in which its width (e.g., width in the second direction) increases from top to bottom in the first direction D1, whereas the first via 121 disposed in the region adjacent to the second wiring unit 120 may have a shape in which its width (e.g., width in the second direction) increases from top to bottom in the first direction D1. Meanwhile, the second via 123 may also perform various functions depending on the design of the corresponding layer. For example, it may include a ground via, a power via, a signal via, etc. Here, the signal via may include a via for transmitting various signals, such as a data signal, other than a ground via, a power via, etc.

[0043] A second solder resist layer 124 may be disposed on the second wiring unit 120. The second solder resist layer 124 may have an opening that partially exposes the second conductor layer 122 disposed on the top of the second wiring unit 120. The second solder resist layer 124 may include a known solder resist material and may include a photosensitive insulating material.

[0044] The bonding portion 130 is disposed between the first and second wiring portions 110 and 120 to connect them. In addition to its bonding function, it also serves as a path for electrical connection. To this end, the bonding portion 130 includes a bonding layer 131 and metal fillers 132 dispersed within the bonding layer 131. The bonding layer 131 may include an insulating resin, a thermally polymerizable compound such as an epoxy compound, or a photopolymerizable compound such as an acrylate compound. The metal fillers 132 may include metal particles such as nickel (Ni), cobalt (Co), silver (Ag), copper (Cu), gold (Au), or palladium (Pd). In this case, copper (Cu) particles may be used.

[0045] The joint 130 may be provided to join multiple wiring units 110 and 120 manufactured separately, thereby efficiently realizing a multilayer substrate. The defect rate increases as the number of layers in a substrate increases, and the decrease in yield is particularly noticeable in substrates requiring fine circuits. If a fine circuit process is required for some wiring units, such as the second wiring unit 120, the pitch of the first conductor layer 112 arranged at the top of the first wiring unit 110 may be shorter than the pitch of the second conductor layer 122 arranged at the top of the second wiring unit 120. In this case, by manufacturing the second wiring unit 120 separately from the first wiring unit 110 in a separate process, the defect rate can be reduced compared to manufacturing them simultaneously. In this case, the first wiring unit 110 with a relatively wide pitch can also be manufactured using a relatively inexpensive process.

[0046] Furthermore, in this embodiment, a groove G is employed in the first wiring unit 110 to improve the matching performance and structural stability in the region where the first wiring unit 110 and the second wiring unit 120 are connected. Specifically, the first wiring unit 110 includes a groove G formed on a surface facing the bonding unit 130 (the upper surface in FIG. 3 ), and the bonding unit 130 is filled into the groove G. The groove G of the first wiring unit 110 may serve to indicate the bonding position of the first and second wiring units 110 and 120. Furthermore, since the bonding unit 130 is filled into the groove G, the bonding and electrical connection area may be increased, thereby improving the physical and electrical bonding strength between the first and second wiring units 110 and 120.

[0047] To further improve the bonding strength, at least a portion of the second conductor layer 122 connected to the bonding portion 130 in the second wiring unit 120 may have a protrusion P protruding from the second insulating layer 121 toward the first wiring unit 110. In this case, as shown in the figure, at least a portion of the protrusion P of the second conductor layer 122 may be disposed in the groove G. The groove G of the first wiring unit 110, which is the region filled with the bonding portion 130, may be formed in the first conductor layer 112. In this case, the first insulating layer 111 may include a through hole formed in the upper surface, and the groove G may be formed by the first conductor layer 112 extending from the upper surface of the first insulating layer 111 to the inner wall of the through hole. Here, the groove G may have a shape whose width decreases as it goes from the upper surface of the first insulating layer 111 toward the lower surface thereof based on the first direction D1.

[0048] 4 and 5, as described above, the first wiring unit 110 and the second wiring unit 120 may be manufactured separately, and the bonding unit 130 may be disposed between them and bonded to them under high temperature and pressure conditions. During this process, the bonding layer 131 may be formed and hardened, thereby physically and electrically connecting the first wiring unit 110 and the second wiring unit 120 to each other. The second wiring unit 120 may be formed on a carrier substrate 140, which may be provided as a detachable copper foil (DCF) substrate. Specifically, the carrier substrate 140 may include an insulating layer 141 and copper foils 142 formed on both sides of the carrier substrate 140. The carrier substrate 140 may further include a barrier layer 142 for a separation process from the second wiring unit 120. Following the bonding process, the carrier substrate 140 is separated from the second wiring unit 120, and then solder resist layers 115 and 124 are formed to obtain the printed circuit board 100.

[0049] Other embodiments of the printed circuit board will be described below with reference to FIGS. 6 to 12. First, as in the embodiment of FIG. 6, the groove G of the first wiring portion 110 may be formed only in a portion of the first conductor layer 112 connected to the joint portion 130. In other words, the groove G may be formed in a portion of the first conductor layer 112 connected to the joint portion 130, while the groove G may not be formed in the remaining portion. In this case, the first conductor layer 112 with and without the groove G may be separated by region depending on the type of components to be disposed thereon. For example, the first conductor layer 112 with the groove G among the first conductor layers 112 connected to the joint portion 130 may be disposed in a first region R1 corresponding to the center in the second direction D2, and the first conductor layer 112 without the groove G among the first conductor layers 112 connected to the joint portion 130 may be disposed in a second region corresponding to the end in the second direction D2. In this case, at least a portion of the second conductor layer 122 connected to the bonding portion 130 in the second wiring unit 120 may have protrusions P1 and P2 protruding from the second insulating layer 121 toward the first wiring unit 110, and the protrusion P2 in the second region R2 may be taller than the protrusion P1 in the first region R1. This allows the groove G and the protrusion P2 to be aligned in the second region R2, and bonding between the pads may be achieved in the first region R1. The pitches of the regions corresponding to the first region R1 and the second region R2 on the second wiring unit 120 may be adjusted to be different from each other depending on the components to be disposed thereon. For example, the pitch of the second conductor layer 122 in the first region R1 may be shorter than the pitch of the second conductor layer 122 in the second region R2, and the pitch of the second conductor layer 122 may be the pitch of the region exposed at the top. In this case, on the second wiring unit 120, the first region R1 can be provided as a chip placement region, and the second region R2 can be provided as a memory placement region.

[0050] Next, as in the embodiment of FIG. 7 , the second conductor layer 122 disposed in the groove G may be electrically isolated from other second conductor layers 122. Specifically, at least a portion of the second conductor layer 122 disposed in the groove G may be electrically isolated from the remaining portion of the second conductor layer 122. In this case, the second conductor layer 122 disposed in the groove G may correspond to a dummy pad for connecting the first and second wiring units 110 and 120 and preventing the bonding layer 131 from leaking during the bonding process. The second conductor layer 122 disposed in the groove G may be disposed in the spare space R3 of the printed circuit board 100, rather than in the component mounting region, for example, the first region R1 and the second region R2. Meanwhile, the structure in which at least a portion of the second conductor layer 122 disposed in the groove G is electrically isolated from the remaining portion of the second conductor layer 122 means that the second conductor layer 122 is isolated within the second wiring unit 120, and the second conductor layer 122 may be electrically connected to each other via the first wiring unit 110, etc.

[0051] Next, as in the embodiment of FIG. 8 , the groove G of the first wiring unit 110 may be formed in the first insulating layer 111. In this case, the bonding portion 130 may be filled in the groove G of the first insulating layer 111 to improve the physical and electrical bonding strength between the first and second wiring units 110 and 120. In this case, as in the embodiment of FIG. 7 , at least a portion of the second conductor layer 122 disposed in the groove G may be electrically isolated from the remaining portion of the second conductor layer 122. In this case, the second conductor layer 122 disposed in the groove G may correspond to a dummy pad for performing the above-described function of connecting the first and second wiring units 110 and 120 and the function of preventing the bonding layer 131 from flowing during the bonding process. The second conductor layer 122 disposed in the groove G may be disposed in a spare space of the printed circuit board 100, rather than in a component mounting area, for example, the above-described first region R1 and second region R2. On the other hand, a structure in which at least a portion of the second conductor layer 122 arranged in the groove G is electrically isolated from the remaining portion of the second conductor layer 122 means that it is isolated within the second wiring unit 120, and can be electrically connected to each other via the first wiring unit 110, etc.

[0052] 9 and 10 are enlarged views of the periphery of a groove in a first conductor layer as an example of a printed circuit board. In the embodiment of FIG. 9, the second conductor layer 122 does not protrude but has an embedded structure. Specifically, the second conductor layer 122 connected to the bonding portion 130 in the second wiring unit 120 may be at least partially embedded in the second insulating layer. Also, as in the embodiment of FIG. 10, the lower surface of the second conductor layer 122 connected to the bonding portion 130 in the second wiring unit 120 may be positioned higher than the lower surface of the second insulating layer 121 to form a recess R. In this case, the bonding portion 130 may fill the recess R in the second wiring unit 120, thereby improving the bonding strength between the first wiring unit 110 and the second wiring unit 120.

[0053] 11, the specific structure of the first wiring unit 110 differs from that of the above-described embodiment. In this case, the first conductor layer 112 disposed at the bottom of the first wiring unit 110 may be at least partially embedded in the first insulating layer 111.

[0054] 12, the first and second wiring portions 110, 120 may have different widths. Specifically, the width of the first wiring portion 110 in the second direction D2 may be wider than the widths of the second wiring portion 120 and the bonding portion 130 in the second direction D2, and the second wiring portion 120 having a relatively narrow width may be used as an interposer. In this case, a solder resist layer 116 may be disposed on the upper surface of the first wiring portion 110.

[0055] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications, and changes can be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0056] 100: Printed circuit board 110: 1st wiring section 111: First insulating layer 112: First conductor layer 113: First via 114: First through via 115: First solder resist layer 120: 2nd wiring section 121: Second insulating layer 122: Second conductor layer 123: Second via 124: Second solder resist layer 130: Joint 131: Bonding layer 132: Metal filler

Claims

1. a first wiring portion including a first insulating layer and a first conductor layer; a second wiring portion including a second insulating layer and a second conductor layer and disposed on the first wiring portion; a bonding portion disposed between the first wiring portion and the second wiring portion to connect the first wiring portion and the second wiring portion, the bonding portion including a bonding layer and a metal filler dispersed in the bonding layer, The printed circuit board, wherein the first wiring portion includes a groove formed on a surface facing the joint portion, and the groove is filled with the joint portion.

2. 2. The printed circuit board according to claim 1, wherein in the second wiring portion, at least a portion of the second conductor layer connected to the joint portion has a protrusion protruding from the second insulating layer toward the first wiring portion.

3. The printed circuit board according to claim 2 , wherein at least a portion of the protruding portion of the second conductor layer is disposed in the groove.

4. 4. The printed circuit board according to claim 3, wherein at least a portion of the second conductor layer disposed in the groove is electrically isolated from the remaining portion of the second conductor layer within a second wiring portion.

5. The printed circuit board according to claim 3 , wherein the groove of the first wiring portion is formed in the first insulating layer.

6. 2. The printed circuit board according to claim 1, wherein a pitch of the first conductor layer arranged at the uppermost part of the first wiring section is shorter than a pitch of the second conductor layer arranged at the uppermost part of the second wiring section.

7. The printed circuit board according to claim 1 , wherein the groove of the first wiring portion is formed in the first conductor layer.

8. the first insulating layer includes a through hole formed in an upper surface thereof; The printed circuit board according to claim 7 , wherein the groove is formed by the first conductor layer extending from the upper surface of the first insulating layer to the inner wall of the through hole.

9. The printed circuit board of claim 8 , wherein the groove has a shape in which the width decreases from the upper surface to the lower surface of the first insulating layer.

10. The printed circuit board according to claim 1 , wherein the groove is formed only in a portion of the first conductor layer connected to the joint portion in the first wiring portion.

11. When a direction in which the first wiring portion and the second wiring portion are stacked is defined as a first direction, and a direction perpendicular to the first direction is defined as a second direction, the first conductor layer having the groove among the first conductor layers connected to the joint portion is disposed in a first region corresponding to a center portion in the second direction, The printed circuit board according to claim 10 , wherein the first conductor layer connected to the joint and having no groove is disposed in a second region corresponding to an end in the second direction.

12. At least a part of the second conductor layer connected to the joint portion in the second wiring portion has a protrusion protruding from the second insulating layer toward the first wiring portion, The printed circuit board of claim 11 , wherein the protrusion has a greater height in the second region than in the first region.

13. The printed circuit board according to claim 1 , wherein the second conductor layer connected to the joint portion in the second wiring portion is at least partially embedded in the second insulating layer.

14. a lower surface of the second conductor layer connected to the junction portion in the second wiring portion is disposed higher than a lower surface of the second insulating layer to form a recess; The printed circuit board of claim 13 , wherein the bonding portion fills a recess in the second wiring portion.

15. The printed circuit board according to claim 13 , wherein the first conductor layer disposed at the bottom of the first wiring portion is at least partially embedded in the first insulating layer.

16. When a direction in which the first and second wiring portions are stacked is defined as a first direction, and a direction perpendicular to the first direction is defined as a second direction, The printed circuit board according to claim 1 , wherein the width of the first wiring portion in the second direction is greater than the widths of the second wiring portion and the joint portion in the second direction.

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