Semiconductor memory device and method of manufacturing the same

Abstract

To provide a semiconductor memory device with improved product reliability.SOLUTION: The semiconductor memory device includes a substrate, a plurality of semiconductor patterns disposed on the substrate to be spaced apart from each other in a first direction parallel to an upper surface of the substrate, a plurality of interlayer insulating patterns each disposed between the plurality of semiconductor patterns adjacent to each other in a third direction perpendicular to the substrate, and a plurality of data storage elements each electrically connected to the plurality of semiconductor patterns corresponding thereto, wherein the plurality of semiconductor patterns include at least one dummy pattern and a plurality of active patterns, and the at least one dummy pattern includes a first element having an atomic size smaller than an atomic size of silicon.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device, and more particularly to a three-dimensional semiconductor memory device with improved electrical characteristics and a method for manufacturing the same. [Background technology]

[0002] To meet consumer demands for superior performance and low prices, there is a demand for increased integration of semiconductor devices. In semiconductor devices, the degree of integration is an important factor in determining the price of the product, and therefore increased integration is particularly desired. In the case of conventional two-dimensional or planar semiconductor devices, the degree of integration is determined mainly by the area occupied by a unit memory cell, and therefore is highly dependent on the level of fine pattern formation technology.

[0003] However, because miniaturization of patterns requires extremely expensive equipment, the integration density of two-dimensional semiconductor devices is still limited, even though it is increasing. For this reason, three-dimensional semiconductor memory elements having memory cells arranged three-dimensionally have been proposed, and improving their performance and characteristics is a daily challenge. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned problems with conventional semiconductor memory devices, and an object of the present invention is to provide a semiconductor memory device with improved product reliability. Another object of the present invention is to provide a method for manufacturing a semiconductor memory device that can manufacture a semiconductor memory device with improved product reliability. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor memory device according to the present invention includes a substrate, a plurality of semiconductor patterns arranged on the substrate at a distance from each other in a first direction parallel to an upper surface of the substrate, a plurality of interlayer insulating patterns respectively arranged between the plurality of semiconductor patterns adjacent to each other in a third direction perpendicular to the substrate, and a plurality of data storage elements electrically connected to the corresponding plurality of semiconductor patterns, wherein the plurality of semiconductor patterns include at least one dummy pattern and a plurality of active patterns, and the at least one dummy pattern includes a first element having an atomic size smaller than the atomic size of silicon.

[0006] In addition, a semiconductor memory device according to an embodiment of the present invention includes a substrate, a plurality of semiconductor patterns spaced apart in a first direction parallel to an upper surface of the substrate, a plurality of word lines electrically connected to the plurality of semiconductor patterns, a plurality of bit lines electrically connected to a plurality of first ends of the plurality of semiconductor patterns, respectively, and a plurality of data storage elements electrically connected to a plurality of second ends of the plurality of semiconductor patterns, wherein the plurality of semiconductor patterns include at least one dummy pattern and a plurality of active patterns, the at least one dummy pattern being disposed at at least one of the upper and lower parts of the plurality of active patterns, and the at least one dummy pattern including a first element having an atomic size smaller than an atomic size of silicon.

[0007] In order to achieve the above object, a method for manufacturing a semiconductor memory device according to the present invention includes the steps of: forming a mold structure including a plurality of sacrificial films and a plurality of semiconductor films alternately stacked on a substrate, the mold structure including a dummy region and a cell region; wherein the plurality of semiconductor films include at least one dummy film in the dummy region and a plurality of active films in the cell region; removing the plurality of sacrificial films to form a plurality of horizontal regions between the plurality of semiconductor films; and etching upper and lower surfaces of the plurality of semiconductor films exposed by the plurality of horizontal regions to form a plurality of semiconductor patterns, the plurality of semiconductor patterns including at least one dummy pattern formed by etching the at least one dummy film and a plurality of active patterns formed by etching the plurality of active films, the plurality of sacrificial films including a compressive stress material and the at least one dummy film including a tensile stress material. [Effects of the Invention]

[0008] In the semiconductor memory device and the manufacturing method thereof according to the present invention, the first mold structure includes a dummy film containing a tensile stress material, which offsets or reduces warpage of the first mold structure, and allows the first mold structure to have a higher number of steps. That is, by adjusting the thickness, material, etc. of the dummy film, the warpage of the first mold structure can be offset or alleviated. This allows the formation of a semiconductor memory device with a higher number of stages. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a simplified circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 2] 1 is a perspective view illustrating a partial schematic configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 3] 1 is a plan view showing a partial schematic configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 4]4 is a cross-sectional view taken along the lines AA and BB in FIG. 3. [Figure 5] FIG. 4 is a cross-sectional view taken along lines CC and DD in FIG. 3. [Figure 6] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 7] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 8] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 9] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 10] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 11] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 12] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 13] 1A and 1B are diagrams for explaining an active pattern of a semiconductor device according to an embodiment of the present invention; [Figure 14] 10 is a graph illustrating the concentration of C in an active pattern according to an embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21]1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 30] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 31] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 32] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 33] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 34] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 35] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 36] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 37] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 38] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 39] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 40] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 41] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 42] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 43] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 44] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 45] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 46] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 47] 10 is a perspective view illustrating a partial schematic configuration of a semiconductor memory device according to another embodiment of the present invention; [Figure 48] 10 is a perspective view illustrating a partial schematic configuration of a semiconductor memory device according to another embodiment of the present invention; [Figure 49] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 50] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 51] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 52] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 53] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 54]10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 55] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; [Figure 56] 10 is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, specific examples of embodiments for carrying out a semiconductor memory device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0011] As used herein, terms such as "first," "second," etc. may modify various elements regardless of order and / or priority, and are not intended to limit exemplary embodiments but are merely used to distinguish one element from another. As used herein, the terms "comprises," "including," "comprises," and / or "comprising" specify the presence of stated elements, but do not exclude the presence of additional elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the term "connected" means an electrical and / or physical connection between elements or components.

[0012] FIG. 1 is a simplified circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a cell array CA of a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a plurality of sub-cell arrays SCA. The sub-cell arrays SCA are arranged along a second direction D2.

[0013] Each sub-cell array SCA includes a plurality of bit lines BL, a plurality of memory cells, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT is arranged between one word line WL and one bit line BL. That is, the memory cell transistor MCT is electrically connected between the word line WL and the bit line BL. In an embodiment of the present invention, the memory cell transistor MCT is configured such that the source is electrically connected to a capacitor, the drain is electrically connected to a bit line, and the gate is electrically connected to a word line, but is not limited to this.

[0014] Referring to FIG. 2, the bit line BL in one sub-cell array SCA is a conductive pattern (eg, a metal conductive line) extending in a direction perpendicular to the substrate (ie, a third direction D3). The bit lines BL are arranged in a first direction D1. Adjacent bit lines BL are spaced apart in the first direction D1. The word lines WL are conductive patterns (for example, metallic conductive lines) stacked on the substrate 100 in the third direction D3. Each word line WL extends in a first direction D1. Adjacent word lines WL are spaced apart from each other in the third direction D3. The gate of the memory cell transistor MCT is electrically connected to a word line WL, and the first source / drain of the memory cell transistor MCT is electrically connected to a bit line BL.

[0015] The second source / drain of the memory cell transistor MCT is electrically connected to the data storage element DS. For example, the data storage element DS may be a capacitor. In embodiments of the present invention, the capacitors are non-polarized capacitors, but are not limited to this, and the data storage elements DS can be any combination and / or variation thereof, including polarized, non-polarized, and variable capacitors. The second source / drain SD2 of the memory cell transistor MCT is electrically connected to the storage electrode (SE in FIGS. 1 to 3) of the capacitor CAP. That is, the first and second source / drain regions (SD1, SD2) in FIG. 2 correspond to the first and second source / drain regions of the memory cell transistor MCT in FIG. 1, respectively. The data storage element DS of FIG. 2 includes a capacitor CAP, which includes a capacitor dielectric film CIL, a storage electrode SE, and a plate electrode PE. In the embodiment of the present invention, the second source / drain SD2 of the memory cell transistor MCT is electrically connected to the storage electrode SE of the data storage element DS as shown in FIG.

[0016] FIG. 2 is a perspective view showing a partial schematic configuration of a semiconductor memory device according to an embodiment of the present invention. 1 and 2, one of the plurality of sub-cell arrays SCA described with reference to FIG. 1 is disposed on a substrate 100. In FIG. The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). In embodiments of the present invention, the substrate 100 may be a silicon substrate or may include other materials such as, but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the substrate 100 is a substrate containing silicon, but is not limited to this. Here, the first direction D1, the second direction D2, and the third direction D3 intersect with each other. The first direction D1 and the second direction D2 are parallel to the upper surface of the substrate 100, and the third direction D3 is perpendicular to the upper surface of the substrate 100. The upper surface, lower surface, top, and bottom are defined with reference to a third direction D3 (for example, the vertical direction).

[0017] The laminated structure ST including the first to third layers (L1, L2, L3) is disposed on the substrate 100. The first to third layers (L1, L2, L3) of the multilayer structure ST are stacked apart from each other in a direction perpendicular to the upper surface of the substrate 100 (that is, a third direction D3). In one embodiment, the first to third layers (L1, L2, L3) of the multilayer structure ST may be stacked apart from each other in the thickness direction of the substrate 100 (ie, the third direction D3). The number of layers L of the laminated structure ST is not limited to this. That is, the number of layers L can be L1 to LN (N is an integer greater than 1). Each of the first to third layers (L1, L2, L3) includes a plurality of semiconductor patterns SP, a plurality of data storage elements DS, and a plurality of word lines WL.

[0018] The semiconductor patterns SP have a line or bar shape extending in the second direction D2. A plurality of semiconductor patterns SP located at the same vertical level (for example, in the third direction D3) are arranged in the first direction D1. For example, the semiconductor patterns SP of the first layer L1 are located at the same vertical level (eg, in the third direction D3) and are arranged in the first direction D1. The semiconductor pattern SP may include a semiconductor material such as silicon, germanium, or silicon-germanium. In one embodiment, the semiconductor pattern SP may include at least one of polysilicon, polysilicon germanium, monocrystalline silicon, and monocrystalline silicon-germanium.

[0019] Each semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH is interposed between the first and second impurity regions (SD1, SD2). The channel region CH corresponds to the channel of the memory cell transistor MCT described with reference to FIG. The first and second impurity regions SD1 and SD2 correspond to the first source / drain and the second source / drain, respectively, of the memory cell transistor MCT described with reference to FIG. The first and second impurity regions SD1 and SD2 are regions in which impurities are doped in the semiconductor pattern SP. As a result, the first and second impurity regions (SD1, SD2) have n-type or p-type conductivity. The first impurity region SD1 is formed at a first end of the semiconductor pattern SP, and the second impurity region SD2 is formed at a second end of the semiconductor pattern SP. The second end faces the first end in the second direction D2.

[0020] The first impurity region SD1 is formed adjacent to the bit line BL. The first impurity region SD1 is electrically and / or physically connected to the bit line BL. The second impurity region SD2 is formed adjacent to the data storage element DS. The second impurity region SD2 is electrically and / or physically connected to the data storage element DS. The data storage element DS is a memory element that can store data. Each data storage element DS may be a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable resistor including a phase change material. In one embodiment, each data storage element DS is a capacitor.

[0021] The word lines WL have a line or bar shape extending in a first direction D1. The word lines WL are stacked and spaced apart from each other along the third direction D3. The word line WL is disposed on at least a part of the outer circumferential surface of the channel region CH of the semiconductor pattern SP. The word lines WL extend in a first direction D1 across the semiconductor patterns SP in one layer. In one embodiment, the word lines WL extend in the first direction D1 and are disposed on respective semiconductor patterns SP spaced apart in the first direction D1 at the same vertical level (eg, third direction D3). The word lines WL extend in a first direction D1 and cross the semiconductor patterns SP at the same vertical level (for example, in a third direction D3). The semiconductor patterns SP are spaced apart in a first direction D1. The width of the word line WL in the first direction D1 is larger than the width of the semiconductor pattern SP in the first direction D1.

[0022] For example, the plurality of semiconductor patterns SP of the first layer L1 are arranged in a first direction D1, each bit line BL is connected to each semiconductor pattern SP of the first layer L1, and the word line WL of the first layer L1 extends in the first direction D1 and intersects with the channel region CH of each semiconductor pattern SP of the first layer L1. In one embodiment, the memory cell transistor MCT may be a gate all around transistor in which the word line WL surrounds the channel region CH. The word line WL surrounds the outer periphery of the channel region CH. The word lines WL extend in the first direction D1 and surround the channel regions CH of the semiconductor patterns SP arranged at the same vertical level (for example, in the third direction D3) and spaced apart in the first direction D1. The word line WL includes a conductive material. In one embodiment, the word line WL may include at least one of a doped semiconductor material (e.g., doped silicon, doped silicon-germanium, doped germanium), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a metal (e.g., tungsten, titanium, tantalum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide), but is not limited thereto.

[0023] A plurality of bit lines BL are provided on the substrate 100, extending in a vertical direction (ie, a third direction D3). Each bit line BL has a line shape or a pillar shape extending in the third direction D3. The bit lines BL are arranged along a first direction D1. Each bit line BL is electrically connected to a first impurity region SD1 of a vertically stacked semiconductor pattern SP. The bit line BL may include a conductive material, for example, but is not limited to, at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0024] FIG. 3 is a plan view showing a partial schematic configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 4 is a cross-sectional view taken along lines AA and BB in FIG. 3, and FIG. 5 is a cross-sectional view taken along lines CC and DD in FIG. 3. For convenience of explanation, the overlapping parts with the contents explained using FIG. 1 and FIG. 2 will be explained briefly, and the differences will be mainly explained. 3 to 5, a semiconductor memory device according to an embodiment of the present invention includes a substrate 100, a plurality of interlayer insulating patterns ILD, a plurality of semiconductor patterns SP, bit lines BL, word lines WL, gate insulating films GI, capping insulating patterns CP, spacer insulating patterns SS, first and second isolation insulating patterns (STI1, STI2), a buried insulating pattern 130, and a capacitor CAP.

[0025] A plurality of interlayer insulating patterns ILD are disposed on the substrate 100 . The interlayer insulating patterns ILD are spaced apart from one another in the third direction D3. The interlayer dielectric pattern ILD includes an insulating material. The interlayer dielectric pattern ILD may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, and a carbon-containing silicon oxynitride layer. As an example, the interlayer insulating pattern ILD includes a silicon oxide film. A plurality of semiconductor patterns SP are disposed on a substrate 100 . The semiconductor patterns SP are disposed between adjacent interlayer insulating patterns ILD in the third direction D3. The semiconductor patterns SP are spaced apart from one another in the third direction D3. The semiconductor patterns SP are arranged on the substrate 100 and spaced apart in a third direction D3. The interlayer insulating patterns ILD are disposed between the semiconductor patterns SP adjacent to each other in the third direction D3.

[0026] Each semiconductor pattern SP extends in the second direction D2. In the cross-sectional view taken along the line BB in FIG. 4, the interlayer insulating pattern ILD protrudes in the second direction D2 beyond the semiconductor pattern SP. The first impurity region SD1 of the semiconductor pattern SP is connected to the bit line BL. The second impurity region SD2 of the semiconductor pattern SP is connected to the storage electrode SE. The semiconductor memory device includes a dummy region DR and a cell region CR. The semiconductor pattern SP includes at least one dummy pattern DP arranged in a dummy region DR and a plurality of active patterns AP arranged in a cell region CR. The cell region CR includes a plurality of interlayer insulating patterns ILD and a plurality of active patterns AP that are alternately stacked. The cell region CR is a region where a cell transistor (for example, memory cell transistor MCT in FIG. 1) of a semiconductor memory device is arranged, and the dummy region DR is a region where a dummy transistor of the semiconductor memory device is arranged.

[0027] The dummy pattern DP includes a tensile stress material. The dummy pattern DP includes silicon and a first element (for example, carbon or boron) having an atomic size smaller than that of silicon. In one embodiment, the dummy pattern DP may include SiC. The active pattern AP includes silicon. In one embodiment, the active pattern AP may be free of carbon. In one embodiment, the dummy region DR may be disposed between the substrate 100 and the cell region CR. The dummy region DR is disposed below the cell region CR. In one embodiment, the dummy region DR may include a plurality of dummy patterns DP. The dummy region DR may include a plurality of interlayer insulating patterns ILD and a plurality of dummy patterns DP that are alternately stacked.

[0028] The bit lines BL extend on the substrate 100 in a third direction D3. The bit lines BL are disposed on the plurality of semiconductor patterns SP and the interlayer insulating pattern ILD. The bit line BL is connected to a plurality of semiconductor patterns SP spaced apart in a third direction D3. In one embodiment, the word lines WL may be arranged between the interlayer insulating patterns ILD adjacent in the third direction D3. The word lines WL cross the semiconductor patterns SP. The word lines WL extend along the periphery of the semiconductor pattern SP. The word lines WL arranged on the dummy patterns DP are dummy word lines, to which no voltage is applied and which are electrically floating. The gate insulating film GI is disposed between the word line WL and the semiconductor pattern SP, and between the word line WL and the interlayer insulating pattern ILD. The gate insulating film GI is formed on the upper and lower surfaces of the word line WL and along one sidewall thereof adjacent to the spacer insulating pattern SS, extending in the third direction D3. In one embodiment, the gate insulating film GI may include at least one of a high dielectric constant insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0029] The capping insulation pattern CP is disposed between the first impurity region SD1 of the semiconductor pattern SP and the interlayer insulation pattern ILD. The capping insulating patterns CP are disposed on the upper and lower surfaces of the semiconductor patterns SP. The capping insulating pattern CP spatially separates the bit lines BL and the word lines WL. The gate insulating film GI is interposed between the capping insulating pattern CP and the interlayer insulating pattern ILD, and between the capping insulating pattern CP and the semiconductor pattern SP. The spacer insulating pattern SS is disposed between the second impurity region SD2 of the semiconductor pattern SP and the interlayer insulating pattern ILD. The spacer insulating patterns SS are disposed on the upper and lower surfaces of the semiconductor patterns SP. The spacer insulating pattern SS is spaced apart from the word line WL with the gate insulating film GI therebetween. The gate insulating film GI is interposed between the spacer insulating pattern SS and the interlayer insulating pattern ILD, and between the spacer insulating pattern SS and the semiconductor pattern SP. In one embodiment, the capping insulating pattern CP and the spacer insulating pattern SS may each include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxynitride film.

[0030] The first and second isolation insulating patterns (STI1, STI2) are disposed on the substrate 100. The first isolation insulation pattern STI1 and the second isolation insulation pattern STI2 are arranged between the bit lines BL adjacent to each other in the first direction D1 and between the storage electrodes SE adjacent to each other in the first direction D1. The buried insulating pattern 130 is disposed on the substrate 100 . The buried insulating pattern 130 covers the sidewalls of the bit lines BL and the sidewalls of the first isolation insulating pattern STI1. The first and second isolation insulating patterns STI1 and STI2 and the buried insulating pattern 130 may be formed of at least one of an insulating material formed using a SOG (spin on glass) technique, silicon oxide, and silicon oxynitride.

[0031] In an embodiment of the present invention, the data storage element (DS in FIG. 2) includes a capacitor CAP. The capacitor CAP is disposed between adjacent semiconductor patterns SP and on the interlayer insulating pattern ILD. The capacitor CAP and the bit line BL are disposed on opposite ends of the semiconductor pattern in the second direction D2. The capacitor CAP includes a capacitor dielectric film CIL, a plurality of storage electrodes SE, and a plate electrode PE. Each capacitor CAP includes a storage electrode SE, a capacitor dielectric layer CIL, and a plate electrode PE, which are arranged between interlayer insulating patterns ILD. The outer periphery of each capacitor CAP is defined by a respective storage electrode SE.

[0032] Each storage electrode SE is disposed between adjacent interlayer insulating patterns ILD in the third direction D3. The storage electrodes SE included in each capacitor CAP are separated from each other. The storage electrodes SE adjacent to each other in the third direction D3 are separated by an interlayer insulating pattern ILD. The storage electrode SE extends along the upper and lower surfaces of the interlayer insulating pattern ILD, the side surfaces of the semiconductor pattern SP, and the side surfaces of the spacer insulating pattern SS. The storage electrode SE does not extend along the side of the interlayer insulating pattern ILD. The capacitor dielectric layer CIL is disposed on the storage electrode SE and the interlayer insulating pattern ILD. The capacitor dielectric layer CIL extends along the profiles of the storage electrodes SE and the side surfaces of the interlayer insulating patterns ILD. The plate electrode PE is disposed on the capacitor dielectric film CIL. A capacitor dielectric layer CIL and a plate electrode PE are sequentially disposed on the storage electrode SE. The capacitor dielectric film CIL and the plate electrode PE included in each capacitor CAP are electrically and / or spatially connected to each other.

[0033] In one embodiment, the storage electrode SE and the plate electrode PE may each include, but are not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide). In one embodiment, the storage electrode SE may include a conductive metal nitride, a metal, and a conductive metal oxide. Conductive metal nitrides, metals, and conductive metal oxides are included in metallic conductive films.

[0034] In one embodiment, the capacitor dielectric film CIL may comprise a high dielectric constant material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof). In the semiconductor memory device according to an embodiment, the capacitor dielectric layer CIL may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In the semiconductor memory device according to an embodiment, the capacitor dielectric layer CIL may include hafnium (Hf).

[0035] 6 to 12 are cross-sectional views of semiconductor memory devices according to other embodiments of the present invention. For reference, FIGS. 6 to 12 are cross-sectional views taken along lines AA and BB in FIG. For the sake of convenience, the following description will focus on differences from the content described using FIGS.

[0036] Referring to FIG. 6, in the semiconductor memory device according to this embodiment, the dummy region DR includes one dummy pattern DP. The thickness of the dummy pattern DP in the third direction D3 is greater than the thickness of the active pattern AP in the third direction D3. 7 and 8, in the semiconductor memory device according to this embodiment, the cell region CR is disposed between the substrate 100 and the dummy region DR. The dummy region DR is disposed above the cell region CR. Referring to FIG. 7, in this embodiment, the dummy region DR includes a plurality of dummy patterns DP. Referring to FIG. 8, in this embodiment, the dummy region DR includes one dummy pattern DP. The thickness of the dummy pattern DP in the third direction D3 is greater than the thickness of the active pattern AP in the third direction D3.

[0037] 9 to 12, in this embodiment, the semiconductor memory device includes a first dummy region DR1, a second dummy region DR2, and a cell region CR. The first dummy region DR1 is arranged in the lower part of the cell region CR, and the second dummy region DR2 is arranged in the upper part of the cell region CR. The cell region CR is disposed between the first dummy region DR1 and the second dummy region DR2. The thickness of the first dummy region DR1 in the third direction D3 may be the same as or different from the thickness of the second dummy region DR2 in the third direction D3. The semiconductor pattern SP includes at least one first dummy pattern DP1 arranged in the first dummy region DR1, a plurality of active patterns AP arranged in the cell region CR, and at least one second dummy pattern DP2 arranged in the second dummy region DR2.

[0038] In one embodiment, the first dummy pattern DP1 and the second dummy pattern DP2 include a first element (eg, carbon or boron) having an atomic size smaller than that of silicon. The average concentration of the first element in the first dummy pattern DP1 may be the same as or different from the average concentration of the first element in the second dummy pattern DP2. In one embodiment, the first and second elements that are different from each other each have an atomic size smaller than that of silicon, and the first dummy pattern DP1 includes the first element and the second dummy pattern DP2 includes the second element. For example, one of the first dummy pattern DP1 and the second dummy pattern DP2 contains carbon, and the other contains boron.

[0039] Referring to FIG. 9, in this embodiment, the first dummy region DR1 includes a plurality of first dummy patterns DP1. The first dummy region DR1 includes a plurality of interlayer insulating patterns ILD and a plurality of first dummy patterns DP1 that are alternately stacked. The second dummy region DR2 includes a plurality of second dummy patterns DP2. The second dummy region DR2 includes a plurality of interlayer insulating patterns ILD and a plurality of second dummy patterns DP2 that are alternately stacked. The number of first dummy patterns DP1 and the number of second dummy patterns DP2 may be the same or different.

[0040] Referring to FIG. 10, in the embodiment of the present invention, the first dummy region DR1 includes a plurality of first dummy patterns DP1, and the second dummy region DR2 includes one second dummy pattern DP2. The thickness of the first dummy pattern DP1 in the third direction D3 may be smaller than or different from the thickness of the second dummy pattern DP2 in the third direction D3. Referring to FIG. 11, in this embodiment, the first dummy region DR1 includes one first dummy pattern DP1, and the second dummy region DR2 includes a plurality of second dummy patterns DP2. The thickness of the second dummy pattern DP2 in the third direction D3 may be smaller than or different from the thickness of the first dummy pattern DP1 in the third direction D3. Referring to FIG. 12, in this embodiment, the first dummy region DR1 includes one first dummy pattern DP1, and the second dummy region DR2 includes one second dummy pattern DP2. The thickness of the first dummy pattern DP1 in the third direction D3 is the same as the thickness of the second dummy pattern DP2 in the third direction D3.

[0041] FIG. 13 is a diagram illustrating an active pattern of a semiconductor device according to an embodiment of the present invention, and FIG. 14 is a graph illustrating the concentration of C in the active pattern according to an embodiment of the present invention. 4 and 6 to 13, the active pattern AP includes first to n-th active patterns (AP1 to APn, n is a natural number of 2 or more). The first active pattern AP1 is the active pattern closest to the substrate 100, and the n-th active pattern APn is the active pattern farthest from the substrate 100.

[0042] In one embodiment, the active pattern AP comprises silicon and carbon. In one embodiment, the average concentration of carbon in each active pattern AP is different. The average concentration of carbon in the first active pattern AP1 is greater than the average concentration of carbon in the nth active pattern APn. The closer the active pattern AP is to the substrate 100, the higher the average concentration of carbon in the active pattern AP.

[0043] 3 to 14, each active pattern AP includes an upper surface APus (eg, a second surface) and a lower surface APbs (eg, a first surface) that are opposite to each other in the third direction D3. In one embodiment, the active pattern AP comprises silicon and carbon. In one embodiment, the concentration of carbon in the active pattern AP on the lower surface APb is different from the concentration of carbon in the active pattern AP on the upper surface APus. The concentration of carbon in the active pattern AP on the lower surface APbs is greater than the concentration of carbon in the active pattern AP on the upper surface APus. Along the direction from the lower surface APbs to the upper surface APus, the concentration of carbon in the active pattern AP decreases and then increases.

[0044] 15 to 43 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. For the sake of convenience, the following description will focus on differences from the content described using FIGS. 15 to 17, a first mold structure MS1 is formed on a substrate 100, the first mold structure MS1 including a plurality of first sacrificial films 10 and a plurality of semiconductor films 20 that are alternately stacked.

[0045] The plurality of first sacrificial films 10 are disposed on the substrate 100 and spaced apart in the third direction D3. The plurality of semiconductor films 20 are disposed between the first sacrificial films 10 adjacent to each other in the third direction D3. The semiconductor films 20 are disposed on the substrate 100 and spaced apart from one another in the third direction D3. The first sacrificial film 10 is disposed between the semiconductor films 20 adjacent to each other in the third direction D3. The thickness of the first sacrificial film 10 in the third direction D3 is smaller than the thickness of the semiconductor film 20 in the third direction D3. The first sacrificial layer 10 is formed of a material having etching selectivity with respect to the semiconductor layer 20 . The first sacrificial film 10 and the semiconductor film 20 are formed by performing an epitaxial growth process.

[0046] The first mold structure MS1 includes a dummy region DR and a cell region CR. The semiconductor film 20 includes at least one dummy film 21 disposed in the dummy region DR and a plurality of active films 22 disposed in the cell region CR. The cell region CR includes a plurality of first sacrificial films 10 and a plurality of active films 22 that are alternately stacked. In another embodiment, the dummy region DR is disposed between the substrate 100 and the cell region CR. In one embodiment, the dummy region DR includes a plurality of dummy films 21. The dummy region DR includes a plurality of first sacrificial films 10 and a plurality of dummy films 21 that are alternately stacked. The first sacrificial film 10 and the dummy film 21 include materials having stresses in different directions. The first sacrificial film 10 includes a compressive stress material, and the dummy film 21 includes a tensile stress material.

[0047] The active film 22 contains silicon, the first sacrificial film 10 contains an element (for example, Ge) having an atomic size larger than that of silicon, and the dummy film 21 contains an element (for example, C or B) having an atomic size smaller than that of silicon. For example, the active film 22 includes silicon, the first sacrificial film 10 includes a material having a larger lattice constant than silicon (eg, SiGe or SiGeC), and the dummy film 21 includes a material having a smaller lattice constant than silicon (eg, SiC). For example, when the dummy film 21 has a thickness of 50 nm or more and 500 nm or less in the third direction D3 and contains SiC, the concentration of carbon in the dummy film 21 may be 5 at % or less. The thickness of the dummy film 21 and the concentration of an element (e.g., C or B) in the dummy film 21 may vary depending on the thickness of the first sacrificial film 10, the concentration of germanium in the first sacrificial film 10, the concentration of carbon in the first sacrificial film 10, etc.

[0048] When the first mold structure MS1 includes a first sacrificial film 10 and an active film 22 alternately stacked, the first sacrificial film 10 contains a compressive stress material, so the first mold structure MS1 is subjected to compressive stress, which may cause the first mold structure MS1 to warp. However, in the method for manufacturing a semiconductor memory device according to an embodiment of the present invention, the first mold structure MS1 includes a dummy film 21 containing a tensile stress material. Therefore, the warpage of the first mold structure MS1 can be offset or alleviated, and a first mold structure MS1 having a higher number of steps can be formed. That is, by adjusting the thickness, material, etc. of the dummy film 21, the warpage of the first mold structure MS1 can be offset or alleviated. This allows the formation of a semiconductor memory device with a higher number of stages.

[0049] An upper insulating film TIL is formed on the first mold structure MS1. The upper insulating film TIL covers the uppermost semiconductor film 20 . The upper insulating film TIL is made of an insulating material having etching selectivity with respect to the first sacrificial film 10 and the semiconductor film 20 . In one embodiment, the upper insulating film TIL is a silicon oxide film. Next, the upper insulating film TIL and the first mold structure MS1 are patterned to form first and second openings OP1 and OP2 that expose the substrate 100. Forming the first and second openings (OP1, OP2) includes forming a mask pattern having openings corresponding to the first and second openings (OP1, OP2) on the first mold structure MS1, and anisotropically etching the first mold structure MS1 using the mask pattern as an etching mask. The first and second openings (OP1, OP2) expose the top surface of the substrate 100, and during the anisotropic etching, the top surface of the substrate 100 below the first and second openings (OP1, OP2) is recessed by over-etching.

[0050] The first openings OP1 are formed spaced apart from each other along the first direction D1. The second openings OP2 are formed spaced apart from each other along the first direction D1, and the second openings OP2 are spaced apart from the first openings OP1 in the second direction D2. A pair of second openings OP2 are formed between the pair of first openings OP1. In the first direction D1, the first and second openings (OP1, OP2) are spaced apart from each other by a first distance. In the second direction D2, the first opening OP1 is spaced apart from the second opening OP2 by a second distance that is smaller than the first distance. In the first direction D1, the first and second openings (OP1, OP2) have the same width. In the second direction D2, the first opening OP1 has a first length, and the second opening OP2 has a second length that is greater than the first length. Next, first and second isolation insulating patterns (STI1, STI2) are respectively filled in the first and second openings (OP1, OP2). The first and second isolation insulating patterns (STI1, STI2) contact the substrate 100. The first and second isolation insulating patterns (STI1, STI2) are formed by depositing an isolation insulating film so that the first and second openings (OP1, OP2) are filled, and then planarizing the isolation insulating film so that the top surface of the upper insulating film TIL is exposed.

[0051] 18 to 20, a plurality of first and second trenches T1, T2 are formed through the first mold structure MS1 to expose the sidewalls of the first sacrificial film 10 and the semiconductor film 20. As shown in FIG. The step of forming the first and second trenches (T1, T2) includes the steps of forming a mask pattern having openings corresponding to the first and second trenches (T1, T2) on the first mold structure MS1, and anisotropically etching the first mold structure MS1 using the mask pattern as an etching mask. The first and second trenches (T1, T2) expose the top surface of the substrate 100, and while anisotropic etching is performed, the top surface of the substrate 100 below the first and second trenches (T1, T2) is recessed by over-etching to form recess regions. The first and second trenches T1 and T2 extend parallel to each other along a first direction D1.

[0052] The first and second trenches T1 and T2 expose the sidewalls of the first sacrificial film 10 and the sidewalls of the semiconductor film 20. The first trench T1 extends in a first direction D1 to expose the sidewalls of the first isolation / insulation pattern STI1. The second trench T2 is formed between the pair of first trenches T1 and extends in the first direction D1 to expose the sidewalls of the second isolation insulating pattern STI2. Next, the first sacrificial layer 10 exposed in the first and second trenches T1 and T2 is removed to form a first horizontal region HR1 between adjacent semiconductor layers 20 in the third direction D3. The step of forming the first horizontal region HR1 includes the step of isotropically etching the first sacrificial layer 10 by performing an etching process having etching selectivity with respect to the substrate 100, the semiconductor layer 20, and the first and second isolation insulating patterns STI1 and STI2. When the first sacrificial layer 10 is removed, the semiconductor layer 20 is separated in a vertical direction (for example, in the third direction D3) without collapsing due to the first and second isolation insulating patterns STI1 and STI2. The thickness of the first horizontal region HR1 in the third direction D3, that is, the distance between adjacent semiconductor films 20 in the third direction D3, is the same as the thickness of the first sacrificial film .

[0053] Referring to FIGS. 21 to 23, an enlargement process is performed to increase the thickness of the first horizontal region HR1 in the third direction D3. For example, the expansion process includes etching the upper and lower surfaces of the semiconductor film 20 exposed in the first horizontal region HR1. The expansion process includes performing an isotropic etching process having etching selectivity to the upper insulating film TIL and the first and second isolation insulating patterns STI1 and STI2. The expansion process reduces the thickness of each semiconductor film 20 . As a result, the semiconductor patterns SP are formed, and second horizontal regions HR2 are formed between the semiconductor patterns SP adjacent to each other in the third direction D3. The semiconductor pattern SP includes an active pattern AP formed by an expansion process on the active film 22 and a dummy pattern DP formed by an expansion process on the dummy film 21 . According to the embodiment, an oxidation process is performed on the semiconductor pattern SP, thereby forming a sacrificial oxide film on the surface of the semiconductor pattern SP. Thereafter, the sacrificial oxide film is removed, and the surface of the semiconductor pattern SP is exposed again. By removing the sacrificial oxide film, the distance between adjacent semiconductor patterns SP in the third direction D3 increases. That is, the second horizontal region HR2 is expanded in the third direction D3.

[0054] 24 to 26, a second sacrificial film 30 and an interlayer insulating film 40 are sequentially deposited on the surface of the semiconductor pattern SP. The second sacrificial layer 30 is formed by depositing a material having etching selectivity with respect to the substrate 100 and the semiconductor pattern SP. In one embodiment, the second sacrificial film 30 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second sacrificial film 30 is formed by atomic layer deposition or chemical vapor deposition. The second sacrificial film 30 is formed to surround each of the semiconductor patterns SP. The second sacrificial film 30 is formed to a thickness that is smaller than half the thickness of each of the second horizontal regions HR2 in the third direction D3. As a result, after the second sacrificial film 30 is deposited, a gap region is defined between the semiconductor patterns SP adjacent to each other in the third direction D3. Next, an interlayer insulating film 40 is formed on the second sacrificial film 30 so as to fill the second horizontal region HR2 in which the second sacrificial film 30 is formed. The interlayer insulating film 40 is formed of an insulating material having etching selectivity with respect to the second sacrificial film 30 and the substrate 100 . In one embodiment, the interlayer insulating film 40 is formed of silicon oxide.

[0055] 27 to 29, partial etching processes are sequentially performed on the interlayer insulating film 40 and the second sacrificial film 30 to form a second mold structure MS2. Specifically, after forming the interlayer insulating film 40, a portion of the interlayer insulating film 40 exposed in the first and second trenches T1 and T2 is etched to form an interlayer insulating pattern ILD. The interlayer insulating pattern ILD is formed by isotropically etching the interlayer insulating film 40 until the second sacrificial film 30 is exposed in the first and second trenches T1 and T2. The isotropic etching process causes the interlayer dielectric pattern ILD to have rounded sidewalls. The interlayer insulating patterns ILD are separated from one another in the third direction D3.

[0056] Next, after forming an interlayer insulating pattern ILD, a second sacrificial pattern 35 is formed by etching a portion of the second sacrificial layer 30 exposed in the first and second trenches T1 and T2. The second sacrificial pattern 35 is formed by isotropically etching the second sacrificial film 30 until the semiconductor pattern SP is exposed. Due to the isotropic etching process, the second sacrificial pattern 35 has rounded sidewalls. The second sacrificial patterns 35 are separated from each other in the third direction D3, and a semiconductor pattern SP is disposed between each pair of second sacrificial patterns 35 adjacent to each other in the third direction D3. As a result, a second mold structure MS2 including the interlayer insulating pattern ILD, the second sacrificial pattern 35, and the semiconductor pattern SP is formed. The second mold structure MS2 includes a plurality of laminated bodies each including an interlayer insulating pattern ILD, a second sacrificial pattern 35, a semiconductor pattern SP, and a second sacrificial pattern 35, which are laminated in sequence. The second mold structure MS2 includes a dummy region DR and a cell region CR. The semiconductor pattern SP includes at least one dummy pattern DP arranged in a dummy region DR and a plurality of active patterns AP arranged in a cell region CR.

[0057] Referring to FIGS. 30 to 32, after the second mold structure MS2 is formed, first and second buried insulating patterns 110 and 120 are formed to fill the first and second trenches T1 and T2. The step of forming the first and second buried insulating patterns 110 and 120 includes the steps of forming a buried insulating film to fill the first and second trenches T1 and T2, and planarizing the buried insulating film to expose the top surface of the upper insulating film TIL. The step of planarizing the buried insulating film is carried out by a planarization technique such as a chemical-mechanical polishing technique or an etch-back technique. The first and second buried insulating patterns 110 and 120 are formed of an insulating material having etching selectivity with respect to the first and second isolation insulating patterns STI1 and STI2.

[0058] In one embodiment, the first and second buried insulating patterns (110, 120) are formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first and second buried insulating patterns (110, 120) are made of a single film or a multi-layer film. After the first and second buried insulating patterns (110, 120) are formed, the first and second isolation insulating patterns (STI1, STI2) are removed, thereby forming the first and second openings (OP1, OP2) again. Here, the first and second openings OP1 and OP2 expose the sidewalls of the semiconductor pattern SP, the sidewalls of the second sacrificial pattern 35, the sidewalls of the interlayer insulating pattern ILD, and a portion of the top surface of the substrate 100. The step of removing the first and second isolation insulating patterns (STI1, STI2) includes performing an etching process having etching selectivity with respect to the substrate 100, the second sacrificial pattern 35, the semiconductor pattern SP, and the first and second buried insulating patterns (110, 120).

[0059] In one embodiment, if the first and second isolation insulating patterns (STI1, STI2) include silicon oxide, a dry etching, chemical etching, or wet etching process is performed on the first and second isolation insulating patterns (STI1, STI2). In one embodiment, a buffered oxide etchant (BOE) or hydrogen fluoride (HF) may be used in the wet etching process for the first and second isolation insulating patterns STI1 and STI2. CF4, NH3, CHF3, C2F6, or BF3 may be used in the dry etching process for the first and second isolation insulating patterns STI1 and STI2. An etching process is performed on the portions of the semiconductor pattern SP exposed through the first and second openings OP1 and OP2. As a result, the semiconductor patterns SP are separated from each other in the first direction D1.

[0060] An isotropic etching process is performed on the semiconductor pattern SP exposed through the first and second openings OP1 and OP2. That is, an etching etchant is supplied through the first and second openings OP1 and OP2, and the semiconductor pattern SP is etched laterally along the first direction D1 and the second direction D2. At this time, since the distance between the first openings OP1 and the distance between the second openings OP2 are larger than the distance between the first and second openings OP1 and OP2, semiconductor patterns SP separated in the first direction D1 are formed. As a result of the isotropic etching process, the width in the first direction D1 of each of the semiconductor patterns SP is greater at the center than at the sidewalls. By forming the semiconductor pattern SP in this manner, a third horizontal region HR3 is formed between the second sacrificial patterns 35, exposing the sidewalls of the semiconductor pattern SP. The third horizontal region HR3 corresponds to the region where the semiconductor pattern SP is etched.

[0061] Referring to FIGS. 30 to 32, after forming the semiconductor pattern SP, the first and second openings OP1 and OP2 are filled with an insulating material again to form the first and second isolation insulating patterns STI1 and STI2. The first and second isolation insulating patterns STI1 and STI2 are formed of an insulating material having etching selectivity with respect to the second sacrificial pattern 35 and the interlayer insulating pattern ILD. In one embodiment, the first and second isolation insulating patterns STI1 and STI2 may be formed of at least one of silicon oxide, silicon oxynitride, and silicon nitride. The first and second isolation insulating patterns STI1 and STI2 are made of a single film or a multi-layer film.

[0062] The step of forming the first and second isolation insulating patterns (STI1, STI2) includes the steps of forming an insulating film filling the first and second openings (OP1, OP2) and planarizing the insulating film to expose the top surface of the upper insulating film TIL. The step of planarizing the insulating film is carried out by a planarization technique such as a chemical-mechanical polishing technique or an etch-back technique. The insulating film filling the first and second openings (OP1, OP2) is formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a spin-on-glass (SOG) process. During the formation of the first and second isolation insulating patterns STI1 and STI2, the third horizontal region HR3 is either filled with an insulating material or left as an empty space. After the first and second isolation insulating patterns STI1 and STI2 are reformed, a mask pattern MP exposing the first buried insulating pattern 110 is formed on the upper insulating film TIL.

[0063] 33 to 35, the first buried insulating pattern 110 is etched using the mask pattern MP as an etching mask to form a first trench T1 exposing the substrate 100 again. Here, the first trench T1 exposes the sidewalls of the semiconductor pattern SP, the sidewalls of the second sacrificial pattern 35, and the sidewalls of the interlayer insulating pattern ILD. Subsequently, a portion of the second sacrificial pattern 35 exposed to the first trench T1 is removed to form a fourth horizontal region HR4 between the semiconductor pattern SP and the interlayer insulating pattern ILD. The fourth horizontal region HR4 is formed by isotropically etching the second sacrificial pattern 35 using an etching recipe having etching selectivity with respect to the semiconductor pattern SP and the interlayer insulating pattern ILD. As an example, if the second sacrificial pattern 35 is a silicon nitride film and the interlayer insulating pattern ILD is a silicon oxide film, the etching step involves isotropically etching the second sacrificial pattern 35 using an etchant containing phosphoric acid, thereby forming the fourth horizontal region HR4. The fourth horizontal region HR4 extends in the first direction D1 between the first and second isolation insulating patterns STI1 and STI2. By forming the fourth horizontal region HR4, a part of the second sacrificial pattern 35 remains, and a third sacrificial pattern 37 is formed. The third sacrificial patterns 37 are separated from one another in the first direction D1 by second isolation insulating patterns STI2.

[0064] Referring to FIGS. 36 to 38, a spacer insulating pattern SS is formed to fill a part of the fourth horizontal region HR4. The step of forming the spacer insulating pattern SS includes the steps of depositing an insulating film to fill the fourth horizontal region HR4, and etching a portion of the insulating film to leave a portion of the insulating film. The spacer insulating patterns SS are separated from each other in the first direction D1 by second isolation insulating patterns STI2. A gate insulating film GI is formed to conformally cover the inner sidewalls of the fourth horizontal region HR4 and the first trench T1. On the gate insulating film GI, a word line WL is formed so as to fill a part of the fourth horizontal region HR4. The word lines WL are formed on the spacer insulating patterns SS. The step of forming the word line WL includes the steps of forming a preliminary conductive pattern that fills the fourth horizontal region HR4 and the first trench T1, and etching a portion of the preliminary conductive pattern to form the word line WL that fills a portion of the fourth horizontal region HR4. The step of etching a portion of the preliminary conductive pattern is performed by an etch-back technique.

[0065] Referring to FIGS. 39 and 41, a capping insulation pattern CP is formed to fill the fourth horizontal region HR4 in which the word lines WL are formed. The step of forming the capping insulation pattern CP includes the steps of forming a capping insulation film on the inner wall of the first trench T1 to fill the fourth horizontal region HR4, and removing the capping insulation film filled in the first trench T1 to expose the sidewall of the interlayer insulation pattern ILD. The capping insulating layer is etched by an isotropic etching process having etching selectivity with respect to the interlayer insulating pattern ILD and the semiconductor pattern SP. Before or after forming the capping insulating pattern CP, a portion of the semiconductor pattern SP exposed by the first trench T1 is doped with impurities. As a result, a first impurity region is formed in the semiconductor pattern SP. The first impurity region is in contact with the bit line BL. The first impurity region is formed by performing a gas phase doping (GPD) process or a plasma doping (PLAD) process through the first trench T1. After forming the capping insulation pattern CP, the bit line BL is formed in the first trench T1. The step of forming the bit line BL includes the steps of depositing a conductive layer on the inner wall of the first trench T1 to fill the gap between the first isolation insulation patterns STI1, and then removing the conductive layer to expose the sidewalls of the first isolation insulation patterns STI1 on the inner wall of the first trench T1. After the bit lines BL are formed, the mask pattern MP is removed.

[0066] Referring to FIGS. 41 to 43, after the bit lines BL are formed, buried insulating patterns 130 are formed in the first trenches T1. The buried insulating pattern 130 extends on the substrate 100 along a first direction D1. Next, the second buried insulating pattern 120 is removed to reform the second trench T2. Here, the top surface of the substrate 100, the sidewalls of the third sacrificial pattern 37, the sidewalls of the semiconductor pattern SP, and the sidewalls of the interlayer insulating pattern ILD are exposed to the second trench T2. Next, the third sacrificial pattern 37 exposed in the second trench T2 is removed to form a fifth horizontal region HR5 exposing the spacer insulating pattern SS. The step of forming the fifth horizontal region HR5 includes the step of isotropically etching the third sacrificial pattern 37 by performing an etching process having etching selectivity with respect to the substrate 100, the semiconductor pattern SP, and the interlayer insulating pattern ILD. When the third sacrificial pattern 37 is isotropically etched, the spacer insulating pattern SS is used as an etching stop film. The fifth horizontal region HR5 is formed vertically between the interlayer insulating pattern ILD and the semiconductor pattern SP, and horizontally between the second isolation insulating patterns STI2. Next, a portion of the semiconductor pattern SP exposed in the fifth horizontal region HR5 is etched to shorten the length of the semiconductor pattern SP in the second direction D2. That is, after the fifth horizontal region HR5 is formed, a part of the semiconductor pattern SP is isotropically etched.

[0067] 3 to 5, impurities are doped into a portion of the semiconductor pattern SP to form a second impurity region SD2. Next, a storage electrode SE is locally formed in the fifth horizontal region HR5. The storage electrode SE is in contact with the second impurity region SD2. The step of forming the storage electrode SE includes the steps of depositing a conductive film conformally covering the inner walls of the fifth horizontal region HR5 and the inner walls of the second trench T2, and removing a portion of the conductive film deposited on the inner walls of the second trench T2 to leave the conductive film locally in the fifth horizontal region HR5. The storage electrodes SE are spaced apart from one another in a first direction D1, a second direction D2, and a third direction D3. The storage electrode SE contacts the semiconductor pattern SP exposed by the fifth horizontal region HR5. Each of the storage electrodes SE defines an empty space in the fifth horizontal region HR5. Each of the storage electrodes SE has a major axis in the second direction D2 and has a hollow cylinder shape. In one embodiment, the storage electrode SE may have a pillar shape with its major axis in the second direction D2. Next, a capacitor dielectric layer CIL is formed to conformally cover the fifth horizontal region HR5 in which the storage electrode SE is formed, and a plate electrode PE is formed to fill the fifth horizontal region HR5 in which the storage electrode SE and the capacitor dielectric layer CIL are formed and the second trench T2.

[0068] 16 and 17, when the first sacrificial layer 10 includes SiGe, a semiconductor memory device including an active pattern AP that does not include carbon is manufactured. 16 and 17, when the first sacrificial film 10 contains SiGeC, the carbon in the first sacrificial film 10 diffuses into the active film 22, forming an active pattern AP containing carbon. In this case, the semiconductor memory device described with reference to FIGS. 13 and 14 is manufactured.

[0069] 44 to 46 are diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. For reference, FIGS. 44 to 46 are cross-sectional views taken along lines AA and BB in FIG. For the sake of convenience, the parts that overlap with the contents explained using FIGS. 1 to 43 will be explained briefly, and the differences will be mainly explained.

[0070] Referring to FIG. 44, in this embodiment, the first sacrificial film 10 includes a plurality of dummy sacrificial films 11 arranged in the dummy region DR and a plurality of cell sacrificial films 12 arranged in the cell region CER. In the dummy region DR of the first mold structure MS1, a plurality of dummy sacrificial films 11 and a plurality of dummy films 21 are alternately stacked. In the cell region CR of the first mold structure MS1, a plurality of cell sacrificial films 12 and a plurality of active films 22 are alternately stacked. The dummy sacrificial layer 11 and the cell sacrificial layer 12 contain different tensile stress materials. In one embodiment, the dummy sacrificial film 11 includes SiGeC, and the cell sacrificial film 12 includes SiGe. Next, the manufacturing method described with reference to FIGS. 18 to 43 is carried out to manufacture the semiconductor memory device described with reference to FIGS. The active pattern AP does not contain carbon.

[0071] In one embodiment, the dummy sacrificial film 11 includes SiGe and the cell sacrificial film 12 includes SiGeC. In this case, the carbon in the cell sacrificial film 12 diffuses into the active film 22 . Next, the manufacturing method described with reference to FIGS. 18 to 43 is carried out to manufacture the semiconductor memory device described with reference to FIGS. In this case, as described with reference to FIGS. 13 and 14, a semiconductor memory device having an active pattern AP containing carbon is manufactured.

[0072] 45 and 46, in one embodiment, the dummy region DR includes one dummy film 21. The dummy region DR includes a dummy film 21 and a first sacrificial film 10 which are stacked in this order. Next, the manufacturing method described with reference to FIGS. 18 to 43 is carried out to manufacture the semiconductor memory device described with reference to FIG. When the first sacrificial layer 10 includes SiGe, a semiconductor memory device including an active pattern AP that does not include carbon is manufactured. When the first sacrificial film 10 contains SiGeC, carbon in the first sacrificial film 10 diffuses into the active film 22, forming an active pattern AP containing carbon. At this time, the semiconductor memory device described with reference to FIGS. 13 and 14 is manufactured.

[0073] Referring to FIG. 45, the first sacrificial film 10 includes a dummy sacrificial film 11 arranged in the dummy region DR and a plurality of cell sacrificial films 12 arranged in the cell region CER. The cell region CR includes a plurality of cell sacrificial films 12 and a plurality of active films 22 that are alternately stacked. The dummy sacrificial layer 11 and the cell sacrificial layer 12 contain different tensile stress materials. Referring to FIG. 46, the dummy sacrificial layer 11 in the dummy region DR and the cell sacrificial layer 12 in the cell region CR contain different tensile stress materials.

[0074] In one embodiment, the dummy sacrificial film 11 includes SiGeC, and the cell sacrificial film 12 includes SiGe. Next, the manufacturing method described with reference to FIGS. 18 to 43 is carried out to manufacture the semiconductor memory device described with reference to FIG. The active pattern AP does not contain carbon.

[0075] In one embodiment, the dummy sacrificial film 11 includes SiGe and the cell sacrificial film 12 includes SiGeC. In this case, the carbon in the cell sacrificial film 12 diffuses into the active film 22 . Next, the manufacturing method described with reference to FIGS. 18 to 43 is carried out to manufacture the semiconductor memory device described with reference to FIG. At this time, as described with reference to FIGS. 13 and 14, a semiconductor memory device having an active pattern AP containing carbon is manufactured.

[0076] FIG. 47 is a perspective view showing a partial schematic configuration of a semiconductor memory device according to another embodiment of the present invention. For the sake of convenience, the parts that overlap with the contents explained using FIGS. 1 to 46 will be explained briefly, and the differences will be mainly explained. Referring to Figure 47, in this embodiment, each word line WL includes a first word line WL1 arranged on opposing first sidewalls of the semiconductor pattern SP and a second word line WL2 arranged on a second sidewall of the semiconductor pattern SP opposite the first sidewall. The first side wall and the second side wall face each other in a third direction D3. Alternatively, in one embodiment, the word lines WL may be disposed on one sidewall of the semiconductor patterns SP that face each other. That is, the second word line WL2 can be omitted.

[0077] FIG. 48 is a perspective view showing a partial schematic configuration of a semiconductor memory device according to another embodiment of the present invention. For the sake of convenience, the portions that overlap with the contents explained using FIGS. 1 to 47 will be explained briefly, and the explanation will focus on the differences. Referring to FIG. 48, in this embodiment, a plurality of bit lines BL extending in a first direction D1 are arranged on a substrate SUB. Each bit line BL has a line or bar shape extending in a first direction D1. The bit lines BL are arranged along a third direction D3. Each bit line BL is electrically connected to a first impurity region SD1 of a semiconductor pattern SP arranged along a first direction D1. The word lines WL have a line or bar shape extending in the third direction D3. The word lines WL are stacked and spaced apart from each other along a first direction D1. Each word line WL extends in a first direction D1 across the stack structure ST. In one embodiment, the word lines WL include a first word line WL1 disposed on opposing first sidewalls of the semiconductor pattern SP and a second word line WL2 disposed on a second sidewall of the semiconductor pattern SP opposite the first sidewall. The first side wall and the second side wall face each other in a first direction D1.

[0078] 49 to 56 are cross-sectional views illustrating semiconductor memory devices according to other embodiments of the present invention. For reference, FIGS. 49 to 56 are exemplary cross-sectional views of the semiconductor patterns SP stacked in the third direction D3 in FIG. 48 cut along the second direction D2. For the sake of convenience, the parts that overlap with the contents explained using FIGS. 1 to 48 will be explained briefly, and the differences will be mainly explained.

[0079] 49 to 56, in this embodiment, the semiconductor patterns SP spaced apart in the third direction D3 are respectively connected to the bit lines BL spaced apart in the third direction D3. The bit lines BL connected to the dummy patterns DP are dummy bit lines, to which no voltage is applied and which are electrically floating. The storage electrode SE extends along the upper and lower surfaces of the interlayer insulating pattern ILD and the side surfaces of the semiconductor pattern SP. In one embodiment, the active pattern AP comprises silicon and does not comprise carbon. The active pattern AP is formed from a first sacrificial film (10 in FIG. 16) or a cell sacrificial film (12 in FIGS. 44 to 16) containing SiGe.

[0080] In one embodiment, the active pattern AP comprises silicon and carbon. The active pattern AP is formed from a first sacrificial film (10 in FIG. 16) or a cell sacrificial film (12 in FIGS. 44 to 46) containing SiGeC. As explained with reference to FIG. 13, the average concentration of carbon in each active pattern AP is different. The closer the active pattern AP is to the substrate 100, the higher the average concentration of carbon in the active pattern AP. As described with reference to FIG. 14, the concentration of carbon in the active pattern AP on the lower surface APbs is different from the concentration of carbon in the active pattern AP on the upper surface APus. Along the direction from the lower surface APbs to the upper surface APus, the concentration of carbon in the active pattern AP decreases and then increases.

[0081] Referring to FIG. 49, in this embodiment, the dummy region DR includes a plurality of interlayer insulating patterns ILD and a plurality of dummy patterns DP that are alternately stacked. The cell region CR includes a plurality of interlayer insulating patterns ILD and a plurality of active patterns AP that are alternately stacked. Referring to FIG. 50, in this embodiment, the dummy region DR includes one dummy pattern DP. The thickness of the dummy pattern DP in the third direction D3 is greater than the thickness of the active pattern AP in the third direction D3.

[0082] 51 and 52, in this embodiment, the cell region CR is disposed between the substrate 100 and the dummy region DR. The dummy region DR is disposed above the cell region CR. Referring to FIG. 51, in this embodiment, the dummy region DR includes a plurality of dummy patterns DP. Referring to FIG. 52, in this embodiment, the dummy region DR includes one dummy pattern DP. The thickness of the dummy pattern DP in the third direction D3 is greater than the thickness of the active pattern AP in the third direction D3.

[0083] 53 to 56, in this embodiment, the semiconductor memory device includes a first dummy region DR1, a second dummy region DR2, and a cell region CR. The first dummy region DR1 is arranged in the lower part of the cell region CR, and the second dummy region DR2 is arranged in the upper part of the cell region CR. The cell region CR is disposed between the first dummy region DR1 and the second dummy region DR2. The thickness of the first dummy region DR1 in the third direction D3 may be the same as or different from the thickness of the second dummy region DR2 in the third direction D3. The semiconductor pattern SP includes at least one first dummy pattern DP1 arranged in the first dummy region DR1, a plurality of active patterns AP arranged in the cell region CR, and at least one second dummy pattern DP2 arranged in the second dummy region DR2.

[0084] In one embodiment, the first dummy pattern DP1 and the second dummy pattern DP2 include a first element (eg, carbon or boron) having an atomic size smaller than that of silicon. The average concentration of the first element in the first dummy pattern DP1 may be the same as or different from the average concentration of the first element in the second dummy pattern DP2. In one embodiment, the first and second elements that are different from each other each have an atomic size smaller than that of silicon, and the first dummy pattern DP1 includes the first element and the second dummy pattern DP2 includes the second element. For example, one of the first dummy pattern DP1 and the second dummy pattern DP2 contains carbon, and the other contains boron.

[0085] Referring to FIG. 53, in this embodiment, the first dummy region DR1 includes a plurality of first dummy patterns DP1. The first dummy region DR1 includes a plurality of interlayer insulating patterns ILD and a plurality of first dummy patterns DP1 that are alternately stacked. The second dummy region DR2 includes a plurality of second dummy patterns DP2. The second dummy region DR2 includes a plurality of interlayer insulating patterns ILD and a plurality of second dummy patterns DP2 that are alternately stacked. The number of first dummy patterns DP1 and the number of second dummy patterns DP2 may be the same or different.

[0086] Referring to FIG. 54, in this embodiment, the first dummy region DR1 includes a plurality of first dummy patterns DP1, and the second dummy region DR2 includes one second dummy pattern DP2. The thickness of the first dummy pattern DP1 in the third direction D3 is smaller than the thickness of the second dummy pattern DP2 in the third direction D3. Referring to FIG. 55, in this embodiment, the first dummy region DR1 includes one first dummy pattern DP1, and the second dummy region DR2 includes a plurality of second dummy patterns DP2. The thickness of the second dummy pattern DP2 in the third direction D3 is smaller than the thickness of the first dummy pattern DP1 in the third direction D3. Referring to FIG. 56, in this embodiment, the first dummy region DR1 includes one first dummy pattern DP1, and the second dummy region DR2 includes one second dummy pattern DP2. The thickness of the first dummy pattern DP1 in the third direction D3 may be the same as or different from the thickness of the second dummy pattern DP2 in the third direction D3.

[0087] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0088] 100 boards 130 Buried insulation pattern AP activity pattern BL bit line CAP capacitor CH channel region CIL Capacitor dielectric film CP Capping Insulation Pattern CR Cell Area DP Dummy Pattern DR dummy area DS Data Storage Element GI gate insulating film ILD Interlayer insulation pattern PE plate electrode SCA Sub-cell Array SD1, SD2 (first, second) impurity regions (source / drain regions) SE storage electrode SP Semiconductor Pattern SS spacer insulating pattern ST laminated structure STI1, STI2 (first and second) isolation patterns TIL upper insulating film WL Word Line

Claims

1. A substrate; a plurality of semiconductor patterns disposed on the substrate and spaced apart in a first direction parallel to an upper surface of the substrate; a plurality of interlayer insulating patterns respectively disposed between the plurality of semiconductor patterns adjacent to each other in a third direction perpendicular to the substrate; a plurality of data storage elements electrically connected to the plurality of corresponding semiconductor patterns, the plurality of semiconductor patterns include at least one dummy pattern and a plurality of active patterns; 10. The semiconductor memory device according to claim 9, wherein the at least one dummy pattern includes a first element having an atomic size smaller than an atomic size of silicon.

2. 2. The semiconductor memory device of claim 1, wherein the at least one dummy pattern is disposed between the substrate and the plurality of active patterns.

3. 2. The semiconductor memory device of claim 1, wherein the plurality of active patterns are disposed between the substrate and the at least one dummy pattern.

4. the at least one dummy pattern includes at least one first dummy pattern and at least one second dummy pattern; 2. The semiconductor memory device of claim 1, wherein the plurality of active patterns are disposed between the at least one first dummy pattern and the at least one second dummy pattern.

5. the plurality of active patterns include a first active pattern and a second active pattern each including carbon; 2. The semiconductor memory device of claim 1, wherein the concentration of the carbon in the first active pattern is different from the concentration of the carbon in the second active pattern.

6. the plurality of active patterns includes a first active pattern including carbon; the first active pattern includes a first surface and a second surface facing each other; 2. The semiconductor memory device of claim 1, wherein the concentration of the carbon on the first surface of the first active pattern is different from the concentration of the carbon on the second surface of the first active pattern.

7. forming a mold structure including a plurality of sacrificial films and a plurality of semiconductor films alternately stacked on a substrate, the mold structure including a dummy region and a cell region; wherein the plurality of semiconductor films include at least one dummy film in the dummy region and a plurality of active films in the cell region; removing the sacrificial layers to form horizontal regions between the semiconductor layers; and etching upper and lower surfaces of the semiconductor film exposed by the horizontal regions to form a plurality of semiconductor patterns; the plurality of semiconductor patterns include at least one dummy pattern formed by etching the at least one dummy film and a plurality of active patterns formed by etching the plurality of active films; the plurality of sacrificial layers include a compressive stress material; 4. A method for manufacturing a semiconductor memory device, wherein the at least one dummy film comprises a tensile stress material.

8. 8. The method of claim 7, wherein each of the plurality of sacrificial films includes SiGe or SiGeC.

9. 8. The method of claim 7, wherein the at least one dummy film includes a first element having an atomic size smaller than an atomic size of silicon.

10. the plurality of semiconductor films includes one dummy film in the dummy region, 8. The method of claim 7, wherein the first thickness of the one dummy layer is greater than the second thickness of the active layer.

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