Memory system and nonvolatile memory

Abstract

To suppress an increase in a data transfer amount between a memory controller and a nonvolatile memory.SOLUTION: According to an embodiment, a memory system includes a nonvolatile memory 20 including a plurality of memory cells MC each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller 10. The nonvolatile memory generates fourth soft-bit data based on a logical OR operation using first soft-bit data of a first bit, second soft-bit data of a second bit, and third soft-bit data of a third bit. The memory controller restores the first to third soft-bit data based on the first hard-bit data of the first bit, the second hard-bit data of the second bit, the third hard-bit data of the third bit, and the fourth soft-bit data.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to memory systems and non-volatile memories. [Background technology]

[0002] 2. Description of the Related Art Memory systems incorporating nonvolatile memories such as NAND flash memories are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-47312 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a memory system and a nonvolatile memory that can suppress an increase in the amount of data transferred between a memory controller and a nonvolatile memory. [Means for solving the problem]

[0005] According to an embodiment, the memory system includes a nonvolatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller for controlling the nonvolatile memory. The nonvolatile memory generates fourth soft bit data based on a logical OR operation using first soft bit data for the first bit, second soft bit data for the second bit, and third soft bit data for the third bit. The memory controller restores the first soft bit data, the second soft bit data, and the third soft bit data based on the first hard bit data for the first bit, the second hard bit data for the second bit, the third hard bit data for the third bit, and the fourth soft bit data. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a data processing device including a memory system according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the configuration of an ECC circuit included in the memory system according to the first embodiment. [Figure 3] FIG. 3 is a block diagram showing the configuration of the SB restoration circuit included in the memory system according to the first embodiment. [Figure 4] FIG. 4 is a block diagram showing the basic configuration of the nonvolatile memory according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram of a memory cell array included in the nonvolatile memory according to the first embodiment. [Figure 6] FIG. 6 is a block diagram of a data register and a sense amplifier included in the nonvolatile memory according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing the relationship between the threshold voltage distribution of the TLC included in the nonvolatile memory according to the first embodiment and data allocation. [Figure 8] FIG. 8 is a diagram showing an example of the relationship between the threshold voltage distributions of the "Er" state and the "A" state and the hard bit data and the soft bit data in the memory system according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing the relationship between the threshold voltage distribution of TLC and hard bit data and compressed soft bit data in the memory system according to the first embodiment. [Figure 10] FIG. 10 is a diagram showing the calculation process for calculating the soft bit data SB_L, SB_M, and SB_U from the results of the read operations on the Lower page, Middle page, and Upper page in the memory system according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing the calculation process for calculating compressed soft bit data from the soft bit data SB_L, SB_M, and SB_U in the memory system according to the first embodiment. [Figure 12]FIG. 12 is a diagram showing the restoration process of the soft bit data SB_L, SB_M, and SB_U in the memory system according to the first embodiment. [Figure 13] FIG. 13 is a flowchart of a read operation in the memory system according to the first embodiment. [Figure 14] FIG. 14 shows a command sequence in the first read mode in the memory system according to the first embodiment. [Figure 15] FIG. 15 shows a command sequence in the second read mode in the memory system according to the first embodiment. [Figure 16] FIG. 16 shows a command sequence in the third read mode in the memory system according to the first embodiment. [Figure 17] FIG. 17 is a flowchart of a read operation in the memory system according to the second embodiment. [Figure 18] FIG. 18 is a block diagram of a data register and a sense amplifier included in the nonvolatile memory according to the third embodiment. [Figure 19] FIG. 19 is a diagram showing the relationship between the threshold voltage distributions and the count number in the "Er" state and the "A" state in the memory system according to the third embodiment. [Figure 20] FIG. 20 is a flowchart of a read operation in the memory system according to the third embodiment. [Figure 21] FIG. 21 shows a command sequence for a read operation in the memory system according to the third embodiment. [Figure 22] FIG. 22 is a diagram showing the relationship between the threshold voltage distribution of the QLC included in the nonvolatile memory according to the fourth embodiment and data allocation. [Figure 23] FIG. 23 is a diagram showing the relationship between the threshold voltage distribution of QLC and hard bit data and compressed soft bit data in the memory system according to the fourth embodiment. [Figure 24]FIG. 24 is a diagram showing the restoration process of the soft bit data SB_L, SB_M, SB_U, and SB_T in the memory system according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Numbers following the letters constituting the reference numerals are used to distinguish between elements having similar configurations.

[0008] 1. First embodiment 1.1 Configuration 1.1.1 Data Processing Device Configuration First, an example of the configuration of a data processing device 1 including a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the data processing device 1. Note that in the example of Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0009] 1, a data processing device 1 includes a host device 2 and a memory system 3. Note that the host device 2 may be connected to a plurality of memory systems 3.

[0010] The host device 2 is an information processing device (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) the memory system 3 to write or read data (hereinafter referred to as "user data").

[0011] The memory system 3 is, for example, a solid state drive (SSD). The memory system 3 is connected to the host device 2.

[0012] 1.1.2 Memory System Configuration Continuing to refer to FIG. 1, an example of the configuration of the memory system 3 will be described.

[0013] As shown in FIG. 1, the memory system 3 includes a memory controller 10 and a nonvolatile memory 20.

[0014] The memory controller 10 issues commands such as read operations, write operations, and erase operations to the nonvolatile memory 20 in response to requests (commands) from the host device 2. The memory controller 10 also manages the memory space of the nonvolatile memory 20.

[0015] The nonvolatile memory 20 is, for example, a NAND flash memory. The NAND flash memory includes multiple blocks. A block is, for example, a unit of data erasure, and data within the same block is erased all at once. Each block includes multiple memory cell transistors (hereinafter also referred to as "memory cells") that store data in a nonvolatile manner. The memory system 3 may include multiple nonvolatile memories 20.

[0016] Next, the internal configuration of the memory controller 10 will be described. The memory controller 10 includes a host interface circuit (host I / F) 11, a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 13, a RAM (Random Access Memory) 14, a buffer memory 15, an ECC (Error Checking and Correcting) circuit 16, and a memory interface circuit (memory I / F) 17. These circuits are connected to each other by, for example, a bus. Note that each function of the memory controller 10 may be realized by a dedicated circuit, or may be realized by the CPU 12 executing firmware.

[0017] The host interface circuit 11 is a hardware interface circuit connected to the host device 2. The host interface circuit 11 performs communication in accordance with an interface standard between the host device 2 and the memory controller 10. The host interface circuit 11 transmits requests and user data received from the host device 2 to the CPU 12 and buffer memory 15, respectively. In addition, the host interface circuit 11 transmits user data in the buffer memory 15 to the host device 2 in response to an instruction from the CPU 12.

[0018] The CPU 12 is a processor that controls the overall operation of the memory controller 10. For example, the CPU 12 commands the nonvolatile memory 20 to perform write, read, and erase operations based on requests received from the host device 2.

[0019] In addition to issuing instructions to the nonvolatile memory 20 to perform predetermined operations based on requests received from the host device 2, the CPU 12 also executes various background processes for managing the nonvolatile memory 20, such as garbage collection, refresh, wear leveling, and patrol read. Furthermore, the CPU 12 executes various calculations, such as data encryption and randomization.

[0020] Garbage collection is also called compaction. Because the nonvolatile memory 20 has different units for erasing data and reading and writing data, as the nonvolatile memory 20 is rewritten, blocks become fragmented due to invalid data, and as the number of fragmented blocks increases, the number of available blocks decreases. Garbage collection is a process for increasing the number of available blocks, and refers to a process for, for example, collecting valid data from multiple active blocks containing valid and invalid data, rewriting it to another block, and securing a free block.

[0021] An active block refers to a block in which valid data is recorded. A free block refers to a block in which no valid data is recorded. A free block can be reused as an erased block after being erased. In this embodiment, free blocks include both blocks before erasure in which no valid data is recorded and erased blocks. Valid data is data associated with a logical address, and invalid data is data not associated with a logical address. When data is written to an erased block, it becomes an active block.

[0022] Refresh is a process in which, when degradation of data in a block is detected, for example, when the number of corrected bits increases in the error correction process by the ECC circuit 16, the data in that block is rewritten to another block.

[0023] Wear leveling is a process of leveling the number of times blocks in non-volatile memory 20 are rewritten or erased, for example, by swapping data stored in blocks that have been rewritten or erased relatively frequently with data stored in blocks that have been rewritten or erased relatively less frequently.

[0024] Patrol read is a process for detecting blocks with an increased number of errors, for example, by reading data stored in the nonvolatile memory 20 in predetermined units and testing the read data based on the error correction results of the ECC circuit 16. This test process, for example, compares the number of error bits in the read data with a threshold, and targets data with an error bit count exceeding the threshold for refreshing.

[0025] The ROM 13 is a non-volatile memory. For example, the ROM 13 is an EEPROM. TM(Electrically Erasable Programmable Read-Only Memory). The ROM 13 is a non-transitory storage medium that stores firmware, programs, etc. For example, the operation of the memory controller 10, which will be described later, is realized by the CPU 12 executing the firmware in the ROM 13.

[0026] The RAM 14 is a volatile memory. The RAM 14 is a dynamic random access memory (DRAM) or a static random access memory (SRAM). The RAM 14 is used as a work area for the CPU 12. The RAM 14 holds firmware for managing the nonvolatile memory 20, various management tables, and the like.

[0027] The buffer memory 15 is a volatile memory. The buffer memory 15 is a DRAM, an SRAM, etc. The buffer memory 15 temporarily stores data read by the memory controller 10 from the nonvolatile memory 20, user data received from the host device 2, etc.

[0028] The ECC circuit 16 is a circuit that performs ECC processing. The ECC processing includes encoding and decoding of data. The ECC circuit 16 encodes data to be written to the nonvolatile memory 20. Encoding methods include BCH (Bose-Chaudhuri-Hocquenghem) code, RS (Reed-Solomon) code, and LDPC (Low-Density Parity-Check) code. The ECC circuit 16 decodes data read from the nonvolatile memory 20. That is, the ECC circuit 16 performs error correction on the data. The configuration of the ECC circuit 16 will be described later.

[0029] The memory interface circuit 17 is a hardware interface circuit connected to the nonvolatile memory 20. The memory interface circuit 17 performs communication in accordance with an interface standard between the memory controller 10 and the nonvolatile memory 20. The memory interface circuit 17 transmits and receives data and various signals to and from the nonvolatile memory 20 under the control of the CPU 12.

[0030] More specifically, the memory interface circuit 17 transmits and receives, for example, an 8-bit signal DQ<7:0> and clock signals DQS and DQSn to and from the nonvolatile memory 20. The signal DQ<7:0> is, for example, data, an address, and a command. Hereinafter, unless otherwise specified, the signal DQ<7:0> will be referred to as the signal DQ. The clock signals DQS and DQSn are clock signals used when inputting and outputting data. The clock signal DQSn is an inverted signal of the clock signal DQS.

[0031] The memory interface circuit 17 also transmits a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn to the nonvolatile memory 20. The memory interface circuit 17 then transmits a ready / busy signal RBn from the nonvolatile memory 20.

[0032] The chip enable signal CEn is a signal for enabling the nonvolatile memory 20, and is asserted, for example, at a low ("L") level. The command latch enable signal CLE is a signal indicating that the signal DQ is a command, and is asserted, for example, at a high ("H") level. The address latch enable signal ALE is a signal indicating that the signal DQ is an address, and is asserted, for example, at an "H" level.

[0033] The write enable signal WEn is a signal for loading a received signal into the nonvolatile memory 20. The signal WEn is asserted, for example, at the "L" level, at the timing when the nonvolatile memory 20 loads a command and an address. Therefore, each time the signal WEn is toggled, the command and address are loaded into the nonvolatile memory 20.

[0034] The read enable signal REn is a signal used by the memory controller 10 to read data from the nonvolatile memory 20. The signal REn is asserted, for example, at an “L” level. For example, when outputting data, the nonvolatile memory 20 generates signals DQS and DQSn based on the signal REn.

[0035] The ready / busy signal RBn is a signal that indicates whether the nonvolatile memory 20 is in a state where it can or cannot receive the signal DQ from the memory controller 10. For example, the ready / busy signal RBn is set to the “L” level when the nonvolatile memory 20 is in a busy state.

[0036] 1.1.3 ECC Circuit Configuration Next, an example of the configuration of the ECC circuit 16 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing the configuration of the ECC circuit 16.

[0037] As shown in FIG. 2, the ECC circuit 16 includes an encoding circuit 160, a hard-decision decoding circuit 161, a soft-decision decoding circuit 162, and an SB restoration circuit 163.

[0038] The encoding circuit 160 is a circuit that encodes data. For example, when the encoding circuit 160 receives a write request from the host device 2, it generates an error correction code (parity) from the user data to be used in ECC processing. The encoding circuit 160 adds the parity to the user data. This process is also referred to as encoding. Therefore, the write data includes the user data and the parity.

[0039] The hard-decision decoding circuit 161 is a circuit that performs hard-decision decoding of read data. Hard-decision decoding is an ECC process that uses hard-decision values ​​received (read) from the nonvolatile memory 20. Hereinafter, hard-decision values ​​are also referred to as hard bits. Hard bits will be described later. Hard bit data is input to the hard-decision decoding circuit 161. The hard-decision decoding circuit 161 decodes user data based on the hard bit data.

[0040] The soft-decision decoding circuit 162 is a circuit that performs soft-decision decoding of read data. Soft-decision decoding is an ECC process that uses soft-decision values ​​received (read) from the nonvolatile memory 20. Hereinafter, soft-decision values ​​are also referred to as soft bits. Soft bits will be described later. Hard bit data and soft bit data are input to the soft-decision decoding circuit 162. The soft-decision decoding circuit 162 decodes user data based on the hard bit data and soft bit data. For decoding, the soft-decision decoding circuit 162 uses a log-likelihood ratio (LLR) table. The LLR table is a table that indicates the correspondence between soft bits and log-likelihood ratios. The LLR table includes log-likelihood ratio values ​​(LLR values). The LLR value is information that expresses the likelihood when data is "0" and the likelihood when data is "1" as a logarithmic ratio. The LLR value indicates the reliability (likelihood) of data read using a certain read voltage. For example, the LLR table is read from the nonvolatile memory 20 to the memory controller 10 when the memory system 3 is started up, and is stored in the RAM 14.

[0041] The SB restoration circuit 163 is a circuit that restores soft bit data. The nonvolatile memory 20 of this embodiment transmits compressed soft bit data to the memory controller 10. The compressed soft bit data is data obtained by compressing a plurality of soft bit data. The compressed soft bit data will be described later. The SB restoration circuit 163 restores the plurality of soft bit data using the hard bit data and the compressed soft bit data.

[0042] An example of restoring soft bit data will be described. For example, the memory cell transistor of the nonvolatile memory 20 is a TLC (Triple Level Cell) that stores three bits of data consisting of a lower bit, a middle bit, and an upper bit. In this case, the nonvolatile memory 20 compresses (integrates) the three bits of soft bit data corresponding to the lower bit, the middle bit, and the upper bit to calculate one bit of compressed soft bit data. The SB restoration circuit 163 restores each of the soft bit data of the lower bit, the middle bit, and the upper bit from the hard bit data of the lower bit, the middle bit, and the upper bit and the compressed soft bit data read from the nonvolatile memory 20.

[0043] 1.1.4 SB restoration circuit configuration Next, an example of the configuration of the SB restoration circuit 163 will be described with reference to Fig. 3. Fig. 3 is a block diagram showing the configuration of the SB restoration circuit 163. Note that the SB restoration circuit 163 shown in Fig. 3 corresponds to the case where the memory cell transistor is a TLC.

[0044] As shown in FIG. 3, the SB restoration circuit 163 includes a demultiplexer (DEMUX: The SB recovery circuit 163 includes a demultiplexer (de-multiplexer) 1001, four buffers 1002 to 1005, and an SB decoder 1006. The number of buffers is set arbitrarily based on the number of bits that the memory cell transistors can store. For example, if the number of bits that the memory cell transistors can store is k bits (k is an integer equal to or greater than 2), the SB recovery circuit 163 may include k+1 buffers.

[0045] The DEMUX 1001 is a connection circuit that electrically connects an input terminal to one of four output terminals connected to the buffers 1002 to 1005, respectively, based on a switching signal received from the CPU 12.

[0046] The buffer 1002 is a buffer that temporarily stores the hard bit data HB_L of the lower bits. The buffer 1002 receives the hard bit data HB_L from the DEMUX 1001. The buffer 1002 stores, for example, hard bit data HB_L having a data length of m bits (m is an integer equal to or greater than 1). The data length that can be stored in the buffer 1002 may be the same as or different from the data length that is collectively ECC processed (hereinafter referred to as an "ECC frame").

[0047] The buffer 1003 is a buffer that temporarily stores hard bit data HB_M of the middle bits. The buffer 1003 receives the hard bit data HB_M from the DEMUX 1001. For example, like the buffer 1002, the buffer 1003 stores hard bit data HB_M having a data length of m bits.

[0048] The buffer 1004 is a buffer that temporarily stores the upper-bit hard bit data HB_U. The buffer 1004 receives the hard bit data HB_U from the DEMUX 1001. For example, like the buffer 1002, the buffer 1004 stores the hard bit data HB_U having a data length of m bits.

[0049] The buffer 1005 is a buffer that temporarily stores the compressed soft bit data SB. The buffer 1005 receives the compressed soft bit data SB from the MUX 1001. For example, like the buffer 1002, the buffer 1005 stores compressed soft bit data SB having a data length of m bits.

[0050] The SB decoder 1006 is a circuit for restoring the soft bit data SB. The SB decoder 1006 receives the hard bit data HB_L, HB_M, and HB_U, and the compressed soft bit data SB. The SB decoder 1006 restores the lower bit soft bit data SB_L, the middle bit soft bit data SB_M, and the upper bit soft bit data SB_U based on the hard bit data HB_L, HB_M, and HB_U, and the compressed soft bit data SB. For example, the SB decoder 1006 transmits the soft bit data SB_L, SB_M, and SB_U to the soft decision decoding circuit 162.

[0051] 1.1.5 Non-volatile Memory Configuration Next, an example of the configuration of the nonvolatile memory 20 will be described with reference to Fig. 4. Fig. 4 is a block diagram showing the basic configuration of the nonvolatile memory 20. In the example of Fig. 4, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to these.

[0052] 4, the nonvolatile memory 20 is, for example, a NAND flash memory. The nonvolatile memory 20 is connected to the memory controller 10. The nonvolatile memory 20 operates based on instructions from the memory controller 10.

[0053] The nonvolatile memory 20 includes an input / output circuit 201, a logic control circuit 202, an address register 203, a command register 204, a status register 205, a sequencer 206, a ready / busy circuit 207, a voltage generation circuit 208, and a plurality of planes PLN.

[0054] The input / output circuit 201 is a circuit that inputs and outputs a signal DQ. The input / output circuit 201 is connected to the memory controller 10. The input / output circuit 201 is also connected to an address register 203, a command register 204, a status register 205, and a data register 214 of each plane PLN. When the input signal DQ is data DAT, the input / output circuit 201 receives the input signal DQ based on clock signals DQS and DQSn. Then, the input / output circuit 201 transmits the data DAT to the data register 214 of the corresponding plane PLN. The input / output circuit 201 also outputs the data DAT and status information STS, along with the clock signals DQS and DQSn, to the memory controller 10. When the input signal DQ is an address ADD, the input / output circuit 201 transmits the address ADD to the address register 203. When the input signal DQ is a command CMD, the input / output circuit 201 transmits the command CMD to the command register 204.

[0055] The logic control circuit 202 is a circuit that performs logic control based on control signals. The logic control circuit 202 is connected to the memory controller 10. The logic control circuit 202 is also connected to the input / output circuit 201 and the sequencer 206. The logic control circuit 202 receives various control signals from the memory controller 10. The logic control circuit 202 controls the input / output circuit 201 and the sequencer 206 based on the received control signals.

[0056] The address register 203 is a register that temporarily stores an address ADD. The address register 203 is connected to the row decoder 212 and the column decoder 215 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 203 transmits the row address RA to the row decoder 212. In addition, the address register 203 transmits the column address CA to the column decoder 215.

[0057] The command register 204 is a register that temporarily stores the command CMD. The command register 204 is connected to the sequencer 206. The command register 204 transmits the command CMD to the sequencer 206.

[0058] The status register 205 is a register that temporarily stores the status information STS. The status register 205 is connected to the sequencer 206. The status register 205 temporarily stores the status information STS in a write operation, a read operation, an erase operation, etc. The status information STS is transmitted to the memory controller 10 via the input / output circuit 201.

[0059] The sequencer 206 controls the overall operation of the nonvolatile memory 20. More specifically, the sequencer 206 controls the ready / busy circuit 207, the voltage generation circuit 208, the row decoder 212, the sense amplifier 213, the data register 214, the column decoder 215, etc. The sequencer 206 executes write operations, read operations, and erase operations based on commands CMD. The sequencer 206 transmits status information STS to the status register 205.

[0060] The ready / busy circuit 207 is a circuit that transmits a ready / busy signal RBn. The ready / busy circuit 207 transmits the ready / busy signal RBn to the memory controller 10 according to the operating status of the sequencer 206.

[0061] The voltage generation circuit 208 generates various voltages used in write, read, and erase operations under the control of the sequencer 206. The voltage generation circuit 208 supplies voltages to the memory cell array 211, row decoder 212, sense amplifier 213, data register 214, column decoder 215, etc. of each plane PLN.

[0062] A plane PLN is a unit that performs data write and read operations. In the example of Fig. 4, the nonvolatile memory 20 includes four planes PLN0, PLN1, PLN2, and PLN3. The number of planes PLN is not limited to four. There may be one plane PLN, or a number other than four. The planes PLN0 to PLN3 can operate independently of each other. Furthermore, the planes PLN0 to PLN3 can also operate in parallel.

[0063] Next, the internal configuration of the plane PLN will be described. In the following, a case where planes PLN0 to PLN3 have the same configuration will be described. Note that the configuration of each plane PLN may be different. Hereinafter, when there is no limitation on any of the planes PLN0 to PLN3, it will be referred to as a "plane PLN." The plane PLN includes a memory cell array 211, a row decoder 212, a sense amplifier 213, a data register 214, and a column decoder 215.

[0064] The memory cell array 211 is a set of a plurality of arranged memory cell transistors. The memory cell array 211 includes a plurality of blocks BLK. In the example of FIG. 4, the memory cell array 211 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 211 is arbitrary. A block BLK is a set of a plurality of memory cell transistors from which data is erased collectively, for example. The configuration of the block BLK will be described in detail later.

[0065] The row decoder 212 is a decoding circuit for the row address RA. Based on the decoding result, the row decoder 212 selects one of the blocks BLK in the memory cell array 211. The row decoder 212 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0066] The sense amplifier 213 is a circuit that writes and reads data DAT. The sense amplifier 213 is connected to the memory cell array 211. During a read operation, the sense amplifier 213 reads data DAT from the memory cell array 211. During a write operation, the sense amplifier 213 supplies a voltage corresponding to the write data DAT to the memory cell array 211. The sense amplifier 213 calculates soft bit data SB based on the read data. The sense amplifier 213 also calculates compressed soft bit data SB from a plurality of soft bit data SB. In other words, the sequencer 206 is a control circuit that controls the sense amplifier 213 to calculate compressed soft bit data SB.

[0067] The data register 214 is a register that temporarily stores data DAT. The data register 214 is connected to the sense amplifier 213. The data register 214 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0068] The column decoder 215 is a circuit that decodes the column address CA. The column decoder 215 receives the column address CA from the address register 203. The column decoder 215 selects a latch circuit in the data register 214 based on the result of decoding the column address CA.

[0069] In addition, some elements of the input / output circuit 201, logic control circuit 202, address register 203, command register 204, status register 205, sequencer 206, ready / busy circuit 207, voltage generation circuit 208, and the row decoder 212, sense amplifier 213, data register 214, and column decoder 215 included in each of the multiple planes PLN may be referred to as control circuits.

[0070] 1.1.6 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 211 will be described with reference to Fig. 5. Fig. 5 is a circuit diagram of the memory cell array 211. Note that the example of Fig. 5 shows the circuit configuration of one block BLK.

[0071] The block BLK includes, for example, four string units SU0 to SU3. Note that the number of string units SU included in the block BLK is arbitrary.

[0072] The string unit SU is, for example, a collection of multiple NAND strings NS that are collectively selected in a write operation or a read operation. The string unit SU includes multiple NAND strings NS.

[0073] A NAND string NS is a set of multiple memory cell transistors MC connected in series. The multiple NAND strings NS in a string unit SU are connected to any of bit lines BL0 to BLn (n is an integer equal to or greater than 1). The NAND string NS includes multiple memory cell transistors MC and select transistors ST1 and ST2. In the example of FIG. 5, the NAND string NS includes eight memory cell transistors MC0 to MC7.

[0074] The memory cell transistor MC is a memory element that stores data nonvolatilely. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductive layer for the charge storage layer.

[0075] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0076] The current paths of the select transistor ST2, memory cell transistors MC0 to MC7, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0077] The control gates of memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, block BLK includes four string units SU0 to SU3. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for memory cell transistors MC1 to MC7.

[0078] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3.

[0079] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, similar to the select gate lines SGD, a different select gate line SGS may be provided for each string unit SU.

[0080] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are each connected to a row decoder 212 in the plane PLN.

[0081] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 213 in the plane PLN.

[0082] The source line SL is shared among, for example, a plurality of blocks BLK.

[0083] A set of multiple memory cell transistors MC connected to a common word line WL within one string unit SU is referred to as a "cell unit CU." For example, when a memory cell transistor MC stores one bit of data, the storage capacity of the cell unit CU is defined as "one page of data." The data length of one page of data can be any bit length.

[0084] The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistor MC. For example, if the memory cell transistor MC is a TLC, the cell unit CU stores three pages of data. The data length of one page of data may be the same as the data length of an ECC frame, or one page of data may include multiple ECC frames.

[0085] 1.1.7 Data Register and Sense Amplifier Configuration Next, an example of the configuration of the data register 214 and the sense amplifier 213 will be described with reference to Fig. 6. Fig. 6 is a block diagram of the data register 214 and the sense amplifier 213.

[0086] 6, the sense amplifier 213 includes a plurality of sense amplifier units SAU provided for each bit line BL, and the data register 214 includes a plurality of latch circuits XDL provided for each sense amplifier unit SAU.

[0087] For example, the sense amplifier unit SAU includes a sense circuit SA, an operation unit OP, and latch circuits SDL, ADL, BDL, CDL, and TDL. The sense circuit SA and the latch circuits SDL, ADL, BDL, CDL, and TDL are commonly connected to the corresponding latch circuit XDL via a bus LBUS. In other words, the latch circuit XDL, the sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, and TDL are connected so as to be able to transmit and receive data to and from each other via the bus LBUS. The number of latch circuits included in the sense amplifier unit SAU can be designed based on the number of bits of data that can be stored in one memory cell transistor MC.

[0088] During a read operation, the sense circuit SA senses the data read out to the corresponding bit line BL and determines whether the read data is "0" or "1." During a write operation, the sense circuit SA applies a voltage to the bit line BL based on the write data.

[0089] The operation unit OP performs various logical operations using the data stored in the latch circuits XDL, SDL, ADL, BDL, CDL, and TDL. Note that the sense amplifier 213 may include a separate operation circuit that performs various logical operations instead of the operation unit OP.

[0090] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store read data or write data. For example, in the case of a read operation, the read data is stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL. Also, for example, in the case of a write operation, the write data of the latch circuit XDL is stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0091] The latch circuit XDL is used as a cache memory for inputting and outputting data between the sense amplifier unit SAU and the input / output circuit 201. More specifically, write data received from the memory controller 10 is transmitted to the latch circuits SDL, ADL, BDL, CDL, and TDL or the sense circuit SA via the latch circuit XDL. Read data stored in the latch circuits SDL, ADL, BDL, CDL, and TDL or the sense circuit SA is transmitted to the memory controller 10 via the latch circuit XDL.

[0092] 1.2 Threshold voltage distribution of memory cell transistors Next, the possible threshold voltage distributions of the memory cell transistors MC will be described. In the following, the case where the memory cell transistors MC are TLC will be described, but this embodiment can be applied as long as the memory cell transistors MC can store data of 2 bits or more.

[0093] 1.2.1 Relationship between memory cell transistor threshold voltage distribution and data allocation First, an example of the relationship between the threshold voltage distribution of memory cell transistors MC and data allocation will be described with reference to Fig. 7. Fig. 7 is a diagram showing the relationship between the threshold voltage distribution of TLC and data allocation.

[0094] 7, for example, the threshold voltage of each memory cell transistor MC takes a value included in one of eight discrete distributions. Hereinafter, the eight distributions will be referred to as "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state, respectively, in order of decreasing threshold voltage.

[0095] The "Er" state corresponds to, for example, the data erasure state. The "A" to "G" states correspond to the state where data is written by injecting charges into the charge storage layer. In the write operation, the verify voltages corresponding to each threshold voltage distribution are set as VA to VG. Then, these voltage values have the relationship of VA < VB < VC < VD < VE < VF < VG < VREAD. The voltage VREAD is the voltage applied to the word line WL connected to the cell unit CU that is not the read target during the read operation. When the voltage VREAD is applied to the gate of the memory cell transistor MC, it is turned on regardless of the data it holds.

[0096] Note that in the write operation, the verify voltages corresponding to each threshold voltage distribution are set as VA to VG, but the method for determining the voltages VA to VG is not limited to this. For example, the voltages VA to VG are written in the ROM fuse of the non-volatile memory 20 (this is referred to as the default voltage). After the shipment of the memory system 3, the CPU 12 may read the voltages VA to VG from the ROM fuse. Also, the CPU 12 may update the voltages VA to VG read from the ROM fuse of the non-volatile memory 20 and save them in any block BLK of the non-volatile memory 20. Further, the CPU 12 can update the voltages VA to VG in accordance with the execution of the shift read or tracking operation. The CPU 12 executes, for example, the shift read or tracking operation in the patrol read.

[0097] The shift read means that the CPU 12 shifts the read voltage and attempts to read data from the non-volatile memory 20 again. At this time, the CPU 12 may update the voltages VA to VG by saving the information on the shift amount from the default voltage.

[0098] In the tracking operation, when adjacent threshold voltage distributions overlap, the CPU 12 finds the intersection and calculates an appropriate read voltage, i.e., a shift amount, from the obtained intersection. Alternatively, instead of finding the intersection, the CPU 12 searches for a voltage that minimizes the number of fail bits in the ECC circuit 16 or a voltage that enables error correction by the ECC circuit 16 when the read voltage is changed.

[0099] The relationship between each state and voltages VA to VG will be described in detail. The threshold voltage included in the "Er" state is less than voltage VA. The threshold voltage included in the "A" state is equal to or greater than voltage VA and less than voltage VB. The threshold voltage included in the "B" state is equal to or greater than voltage VB and less than voltage VC. The threshold voltage included in the "C" state is equal to or greater than voltage VC and less than voltage VD. The threshold voltage included in the "D" state is equal to or greater than voltage VD and less than voltage VE. The threshold voltage included in the "E" state is equal to or greater than voltage VE and less than voltage VF. The threshold voltage included in the "F" state is equal to or greater than voltage VF and less than voltage VG. And the threshold voltage included in the "G" state is equal to or greater than voltage VG and less than voltage VREAD.

[0100] As described above, each memory cell transistor MC can have one of eight threshold voltage distributions, and can take on eight different states. By assigning these states to binary values ​​"000" to "111," each memory cell transistor MC can hold three bits of data. Hereinafter, the three bits of data will be referred to as the lower bit, middle bit, and upper bit, respectively. Furthermore, a set of lower bits that are collectively written (or read) from a cell unit CU will be referred to as a lower page. A set of middle bits will be referred to as a middle page. A set of upper bits will be referred to as an upper page. Note that when there is no need to specify which of the lower page, middle page, and upper page is used, it will simply be referred to as a "page."

[0101] For example, in the case of a read operation of the Lower page, data read at a read voltage VA is stored in, for example, a latch circuit TDL. Subsequently, data read at a read voltage VE is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL. This stored data is sent to the memory controller 10 via the latch circuit XDL as read data of the Lower page.

[0102] In the case of a read operation of the Middle page, data read at the read voltage VB is stored in, for example, the latch circuit TDL. Subsequently, the data read at the read voltage VD is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL. Furthermore, the data read at the read voltage VF is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL. This stored data is sent to the memory controller 10 via the latch circuit XDL as read data of the Middle page.

[0103] In the case of a read operation of the Upper page, data read at the read voltage VC is stored in, for example, the latch circuit TDL. Subsequently, data read at the read voltage VG is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL. This stored data is sent to the memory controller 10 via the latch circuit XDL as read data of the Upper page.

[0104] In the example of FIG. 7, for the memory cell transistors MC included in each threshold voltage distribution, data is allocated to the "Upper bit / Middle bit / Lower bit" as shown below.

[0105] “Er” state: “111” data "A" state: "110" data "B" state: "100" data "C" state: "000" data “D” state: “010” data “E” state: “011” data “F” state: “001” data “G” state: “101” data

[0106] When reading data allocated in this way, the Lower bit is determined by a read operation corresponding to the "A" state and the "E" state. The Middle bit is determined by a read operation corresponding to the "B" state, the "D" state, and the "F" state. The Upper bit is determined by a read operation corresponding to the "C" state and the "G" state. In other words, the values ​​of the Lower bit, Middle bit, and Upper bit are determined by read operations corresponding to two states, three states, and two states, respectively. Hereinafter, this type of data allocation will be referred to as the "2-3-2 code." Note that the allocation of data to the "Er" to "G" states is not limited to the 2-3-2 code.

[0107] 1.2.2 Examples of hard bit data and soft bit data Next, a specific example of hard bit data HB and soft bit data SB will be described with reference to Fig. 8. Fig. 8 is a diagram showing an example of the relationship between the threshold voltage distributions of the "Er" state and the "A" state and the hard bit data HB and soft bit data SB.

[0108] As shown in Figure 8, due to the effects of read disturbance or data retention, the width of the threshold voltage distribution for each state may widen, causing parts of the tails of adjacent threshold voltage distributions to overlap (the shaded area in Figure 8). In such a case, when a read operation is performed, memory cell transistors MC corresponding to the overlapping tail area are likely to become fail bits. More specifically, for example, when a read operation corresponding to the "A" state is performed at voltage VA, memory cell transistors MC in the "Er" state having a threshold voltage equal to or greater than voltage VA and memory cell transistors MC in the "A" state having a threshold voltage less than voltage VA become fail bits. If the number of failed bits that occur exceeds the number of bits that the ECC circuit 16 can correct errors from, it becomes difficult to read data correctly.

[0109] Therefore, in this embodiment, in a read operation for one state, two read voltages are set across a region where the tails of the threshold voltage distributions overlap. More specifically, two read voltages, VAL and VAH, are set for the "A" state. The voltage VAL is a voltage less than the voltage VA. The voltage VAH is a voltage higher than the voltage VA. The region where the "Er" state and the "A" state overlap is located between the voltages VAL and VAH. Note that the magnitude of the voltage difference between the voltages VAL and VA may be the same as or different from the magnitude of the voltage difference between the voltages VA and VAH.

[0110] For example, in a read operation using voltage VAL, the data of a memory cell transistor MC whose threshold voltage is less than voltage VAL is "1," and the data of a memory cell transistor MC whose threshold voltage is equal to or greater than voltage VAL is "0."

[0111] In a read operation using voltage VAH, the data of a memory cell transistor MC whose threshold voltage is less than voltage VAH is "1." The data of a memory cell transistor MC whose threshold voltage is equal to or greater than voltage VAH is "0."

[0112] In this embodiment, of two read voltages corresponding to one state, read data based on the lower read voltage is defined as hard bit data HB.

[0113] The soft bit data SB is calculated by an XOR (exclusive OR) operation of two read data. In the example of FIG. 8, the soft bit data SB of a memory cell transistor MC whose threshold voltage is less than voltage VAL is "0". The soft bit data SB of a memory cell transistor MC whose threshold voltage is equal to or greater than voltage VAL and less than voltage VAH is "1". The soft bit data SB of a memory cell transistor MC whose threshold voltage is equal to or greater than voltage VAH is "0". The operation of the soft bit data SB is not limited to an XOR operation. The operation of the soft bit data SB can be set based on the definition of the soft bit data SB. For example, if the soft bit data SB of a memory cell transistor MC whose threshold voltage is equal to or greater than voltage VAL and less than voltage VAH is defined as "0", an XNOR (exclusive NOR) operation may be used to calculate the soft bit data SB.

[0114] Therefore, the soft bit data SB indicates whether the threshold voltage is located near the boundary between two adjacent threshold voltage distributions. By referring to the hard bit data HB and the soft bit data, it is possible to obtain information on whether the threshold voltage is located at the base of the threshold voltage distribution of the target state.

[0115] 1.2.3 Hard Bits and Compressed Soft Bits for Each State Next, the hard bit data HB and compressed soft bit data SB of each state will be described with reference to Fig. 9. Fig. 9 is a diagram showing the relationship between the threshold voltage distribution of TLC and the hard bit data HB and compressed soft bit data SB.

[0116] As shown in FIG. 9, the two read voltages corresponding to the "A" state are defined as voltage VAL and voltage VAH. The two read voltages corresponding to the "B" state are defined as voltage VBL and voltage VBH. The two read voltages corresponding to the "C" state are defined as voltage VCL and voltage VCH. The two read voltages corresponding to the "D" state are defined as voltage VDL and voltage VDH. The two read voltages corresponding to the "E" state are defined as voltage VEL and voltage VEH. The two read voltages corresponding to the "F" state are defined as voltage VFL and voltage VFH. The two read voltages corresponding to the "G" state are defined as voltage VGL and voltage VGH. These voltages are in the relationship of VAL < VA < VAH < VBL < VB < VBH < VCL < VC < VCH < VDL < VD < VDH < VEL < VE < VEH < VFL < VF < VFH < VGL < VG < VGH < VREAD. The read operations using voltage VAL, voltage VAH, voltage VBL, voltage VBH, voltage VCL, voltage VCH, voltage VDL, voltage VDH, voltage VEL, voltage VEH, voltage VFL, voltage VFH, voltage VGL, and voltage VGH are denoted as ALR read, AHR read, BLR read, BHR read, CLR read, CHR read, DLR read, DHR read, ELR read, EHR read, FLR read, FHR read, GLR read, and GHR read, respectively.

[0117] In the read operation of the Lower page, four read operations of ALR read, AHR read, ELR read, and EHR read are executed. The hard bit data HB_L is the data determined by ALR read and ELR read. The soft bit data SB_L is based on the hard bit data HB_L and the data determined by AHR read and EHR read.

[0118] For example, in the case of the read operation of the hard bit data of the Lower page, the data read with the read voltage VAL is stored in, for example, the latch circuit TDL. Subsequently, the data read with the read voltage VEL is logically operated with the data in the latch circuit TDL in the arithmetic unit OP, and the result is stored in the latch circuit TDL as the hard bit data HB_L.

[0119] Furthermore, for example, in the case of a read operation of soft bit data of the Lower page, data read at a read voltage VAH is stored in, for example, a latch circuit CDL. Subsequently, the data read at a read voltage VEH is logically operated with the data in the latch circuit CDL in the operation unit OP, and the result is stored in the latch circuit CDL. After that, the operation unit OP performs an XOR operation on the data stored in the latch circuit TDL and the data stored in the latch circuit CDL, and stores the result of the operation as soft bit data SB_L in, for example, the latch circuit CDL.

[0120] The read operation for the Middle page involves six read operations: BLR read, BHR read, DLR read, DHR read, FLR read, and FHR read. The hard bit data HB_M is the data determined by the BLR read, DLR read, and FLR read. The soft bit data SB_M is based on the hard bit data HB_M and the data determined by the BHR read, DHR read, and FHR read.

[0121] For example, in the case of a read operation of hard bit data of the Middle page, the data read at the read voltage VBL is stored in, for example, the latch circuit TDL. Subsequently, the data read at the read voltage VDL is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL. Furthermore, the data read at the read voltage VFL is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL as hard bit data HB_M.

[0122] Also, for example, in the case of a read operation of soft bit data of the Middle page, data read at a read voltage VBH is stored in, for example, a latch circuit BDL. Subsequently, the data read at a read voltage VDH is logically operated with the data in the latch circuit BDL in the operation unit OP, and the result is stored in the latch circuit BDL. Furthermore, the data read at a read voltage VFH is logically operated with the data in the latch circuit BDL in the operation unit OP, and the result is stored in the latch circuit BDL. Thereafter, the operation unit OP performs an XOR operation on the hard bit data HB_M stored in the latch circuit TDL and the data stored in the latch circuit BDL, and stores the result of the operation as soft bit data SB_M in, for example, the latch circuit BDL.

[0123] In the read operation of the Upper page, four read operations are executed: CLR read, CHR read, GLR read, and GHR read. The hard bit data HB_U is the data determined by the CLR read and GLR read. The soft bit data SB_U is based on the hard bit data HB_U and the data determined by the CHR read and GHR read.

[0124] For example, in the case of a read operation of hard bit data of the Upper page, the data read at the read voltage VCL is stored in, for example, the latch circuit TDL. Subsequently, the data read at the read voltage VGL is logically operated with the data in the latch circuit TDL in the operation unit OP, and the result is stored in the latch circuit TDL as hard bit data HB_U.

[0125] Furthermore, for example, in the case of a read operation of soft bit data of the Upper page, data read at a read voltage VCH is stored in, for example, a latch circuit ADL. Subsequently, data read at a read voltage VGH is logically operated with the data in the latch circuit ADL in the operation unit OP, and the result is stored in the latch circuit ADL. After that, the operation unit OP performs an XOR operation on the data stored in the latch circuit TDL and the data stored in the latch circuit ADL, and stores the result of the operation as soft bit data SB_U in, for example, the latch circuit ADL.

[0126] The compressed soft bit data SB is data calculated from the soft bit data SB_L, SB_M, and SB_U.

[0127] In the example of FIG. 9, the threshold voltages of the memory cell transistors MC are divided into 15 sections corresponding to 14 read voltages. More specifically, the threshold voltage in section D1 is less than voltage VAL. The threshold voltage in section D2 is equal to or greater than voltage VAL and less than voltage VAH. The threshold voltage in section D3 is equal to or greater than voltage VAH and less than voltage VBL. The threshold voltage in section D4 is equal to or greater than voltage VBL and less than voltage VBH. The threshold voltage in section D5 is equal to or greater than voltage VBH and less than voltage VCL. The threshold voltage in section D6 is equal to or greater than voltage VCL and less than voltage VCH. The threshold voltage in section D7 is equal to or greater than voltage VCH and less than voltage VDL. The threshold voltage in section D8 is equal to or greater than voltage VDL and less than voltage VDH. The threshold voltage in section D9 is equal to or greater than voltage VDH and less than voltage VEL. The threshold voltage in section D10 is equal to or greater than voltage VEL and less than voltage VEH. The threshold voltage of the division D11 is equal to or greater than the voltage VEH and less than the voltage VFL. The threshold voltage of the division D12 is equal to or greater than the voltage VFL and less than the voltage VFH. The threshold voltage of the division D13 is equal to or greater than the voltage VFH and less than the voltage VGL. The threshold voltage of the division D14 is equal to or greater than the voltage VGL and less than the voltage VGH. The threshold voltage of the division D15 is equal to or greater than the voltage VGH and less than the voltage VREAD.

[0128] The combinations of "hard bit data HB_U / HM_M / HB_L" and "compressed soft bit data SB" for each section are as follows:

[0129] Section D1 ("Er" state): "111", "0" Section D2 ("A" state): "110", "1" Section D3 ("A" state): "110", "0" Section D4 ("B" state): "100", "1" Section D5 ("B" state): "100", "0" Section D6 ("C" state): "000", "1" Section D7 ("C" state): "000", "0" Division D8 ("D" state): "010", "1" Division D9 ("D" state): "010", "0" Division D10 ("E" state): "011", "1" Section D11 ("E" state): "011", "0" Division D12 ("F" state): "001", "1" Section D13 ("F" state): "001", "0" Section D14 ("G" state): "101", "1" Section D15 ("G" state): "101", "0"

[0130] 1.3 Softbit data compression method Next, an example of a method for compressing the soft bit data SB will be described with reference to Figures 10 and 11. Figure 10 is a diagram showing the calculation process for calculating the soft bit data SB_L, SB_M, and SB_U from the results of the read operations of the Lower page, Middle page, and Upper page. Figure 11 is a diagram showing the calculation process for calculating the compressed soft bit data SB from the soft bit data SB_L, SB_M, and SB_U.

[0131] 10, for example, after the read operation of the Lower page, the sense amplifier 213 performs an XOR operation on the hard bit data HB_L (ALR / ELR) determined by the ALR read and the ELR read and the data (AHR / EHR) determined by the AHR read and the EHR read. As a result, the soft bit data SB_L is calculated. In this case, the sections D2 and D10 of the soft bit data SB_L are "1" data, and the other sections D are "0" data.

[0132] Next, after the read operation of the Middle page, the sense amplifier 213 performs an XOR operation on the hard bit data HB_M (BLR / DLR / FLR) determined by the BLR read, DLR read, and FLR read and the data (BHR / DHR / FHR) determined by the BHR read, DHR read, and FHR read. As a result, the soft bit data SB_M is calculated. In this case, the sections D4, D8, and D12 of the soft bit data SB_M are "1" data, and the other sections D are "0" data.

[0133] Next, after the read operation of the Upper page, the sense amplifier 213 performs an XOR operation on the hard bit data HB_U (CLR / GLR) determined by the CLR read and GLR read and the data (CHR / GHR) determined by the CHR read and GHR read. As a result, the soft bit data SB_U is calculated. The sections D6 and D14 of the soft bit data SB_U are "1" data, and the other sections D are "0" data.

[0134] 11, the "1" data of the soft bit data SB_L, SB_M, and SB_U have different threshold voltage distributions (states) targeted for the "1" data. Therefore, the "1" data of the soft bit data SB_L, SB_M, and SB_U exist in different sections D. Therefore, the sense amplifier 213 performs an OR (logical sum) operation on the soft bit data SB_L, SB_M, and SB_U. As a result, the compressed soft bit data SB is calculated. That is, the OR operation compresses three pages of data into one page of data.

[0135] For example, when soft bit data SB_U is stored in latch circuit ADL, soft bit data SB_M is stored in latch circuit BDL, and soft bit data SB_L is stored in latch circuit CDL, operation unit OP performs an OR operation on the data stored in latch circuit ADL, the data stored in latch circuit BDL, and the data stored in latch circuit CDL, and stores the operation result as compressed soft bit data SB, for example, in latch circuit ADL. This stored data is transmitted as compressed soft bit data SB to memory controller 10 via latch circuit XDL.

[0136] 1.4 How to recover compressed soft bits Next, an example of a method for restoring the compressed soft bit data SB will be described with reference to Fig. 12. Fig. 12 is a diagram showing the restoration process of the soft bit data SB_L, SB_M, and SB_U.

[0137] The positions (states) where "1" data can occur in the soft bit data SB_L, SB_M, and SB_U are mutually exclusive. Furthermore, a combination of hard bit data HB_L, HB_M, and HB_U can be defined one-to-one with a combination of soft bit data SB_L, SB_M, and SB_U. Utilizing these facts, the soft bit data SB of each page is restored from the hard bit data HB_L, HB_M, and HB_U and the compressed soft bit data SB.

[0138] 12, the SB restoration circuit 163 receives hard bit data HB_L, HB_M, and HB_U and compressed soft bit data SB from the nonvolatile memory 20. The SB decoder 1006 performs the following operations when restoring the soft bit data SB_L, SB_M, and SB_U. In the following arithmetic expressions, "|" indicates an OR operation, and "~" indicates inverted data. In the following arithmetic expressions, the hard bit data HB_L, HB_M, and HB_U are simply represented as "L", "M", and "U".

[0139] SB_L=((~L&M&U)|(L&M&~U))&SB SB_M=((~L&~M&U)|(~L&M&~U)|(L&~M&~U))&SB SB_U=((~L&~M&~U)|(L&~M&U))&SB

[0140] The above arithmetic expressions are used to restore the soft bit data SB_L, SB_M, and SB_U described with reference to Fig. 10. Note that the above arithmetic expressions can be modified as appropriate based on the allocation of data in memory cell transistors MC.

[0141] 1.5 Read Operation 1.5.1 Read operation flow First, the flow of a read operation in the memory system 3 will be described with reference to Fig. 13. Fig. 13 is a flowchart of the read operation. Note that the example in Fig. 13 shows a case where data of multiple pages is read from one cell unit CU.

[0142] 13, the memory controller 10 starts a read operation when it receives a read request from the host device 2. The nonvolatile memory 20 executes a read operation of multiple pages of data stored in the cell unit CU under the control of the memory controller 10 (step S10). For example, if the memory cell transistor MC is a TLC, a read operation of the Lower page, a read operation of the Middle page, and a read operation of the Upper page are executed.

[0143] The sense amplifier 213 compresses the soft bit data SB of multiple pages to calculate compressed soft bit data SB (step S11). More specifically, the sense amplifier 213 compresses (OR operation) the soft bit data SB_L, SB_M, and SB_U to calculate compressed soft bit data SB.

[0144] The memory controller 10 reads multiple pages of hard bit data HB from the nonvolatile memory 20 (step S12). More specifically, for example, the memory controller 10 reads hard bit data HB_L, HB_M, and HB_U from the nonvolatile memory 20. Note that steps S11 and S12 may be at least partially executed in parallel, or step S12 may be started first.

[0145] The hard-decision decoding circuit 161 executes hard-decision decoding processing (step S13). More specifically, for example, the hard-decision decoding circuit 161 executes hard-decision decoding processing on the Lower page, the Middle page, and the Upper page, respectively, using the hard bit data HB_L, HB_M, and HB_U.

[0146] If the hard-decision decoding process is successful (Yes in step S14), the memory controller 10 transmits the decoded user data to the host device 2, and the read operation ends.

[0147] If the hard decision decoding process fails (step S14_No), the memory controller 10 reads out the compressed soft bit data SB from the nonvolatile memory 20 (step S15). Note that the soft bit data SB_L, SB_M, and SB_U are not read out.

[0148] The SB restoration circuit 163 restores the soft bit data SB of each page from the compressed soft bit data SB (step S16). More specifically, for example, the SB restoration circuit 163 restores the soft bit data SB_L, SB_M, and SB_U from the compressed soft bit data SB using the hard bit data HB_L, HB_M, and HB_U.

[0149] The soft-decision decoding circuit 162 performs hard-decision decoding processing (step S13). More specifically, the soft-decision decoding circuit 162 performs soft-decision decoding processing on the Lower page data, Middle page data, and Upper page data, respectively, using the hard bit data HB_L, HB_M, and HB_U, the soft bit data SB_L, SB_M, and SB_U, and the LLR table.

[0150] 1.5.2 Read operations in non-volatile memory Next, a description will be given of a read operation in the nonvolatile memory 20. The read operation in the nonvolatile memory 20 roughly includes a cell read operation and a cache read operation. The cell read operation is an operation of reading data from the memory cell array 211 to the data register 214, i.e., the latch circuit XDL, and the cache read operation is an operation of reading (externally outputting) data from the data register 214 to the memory controller 10 via the input / output circuit 201.

[0151] For example, the nonvolatile memory 20 has at least one of a first read mode, a second read mode, and a third read mode in a read operation, and executes one of the read modes based on a command sequence received from the memory controller 10.

[0152] The first read mode and the second read mode are operation modes in which a command set is sent for each page to read page data. The first read mode is an operation mode in which page data read operations (cell read operation and cache read operation) are executed sequentially. In the first read mode, the ready / busy signal RBn is set to the "L" level while the cell read operation is being executed. Therefore, the cell read operation and the cache read operation cannot be executed in parallel.

[0153] The second read mode is an operation mode in which a cell read operation and a cache read operation of another page can be performed in parallel. In the second read mode, even if a cell read operation is being performed, if a cache read operation can be performed, that is, if data output from the latch circuit XDL is possible, the ready / busy signal RBn is set to the “H” level.

[0154] The third read mode is an operation mode in which multiple pages of data stored in the cell unit CU are successively read out based on one command set.

[0155] 1.5.3 First read mode command sequence Next, an example of a command sequence in the first read mode will be described with reference to Fig. 14. Fig. 14 shows the command sequence in the first read mode. In the example of Fig. 14, to simplify the description, the signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, and only the signal DQ and ready / busy signal RBn are shown. In the signal DQ, commands are written in circular frames, addresses are written in square frames, and data are written in hexagonal frames.

[0156] The example of FIG. 14 shows a case where a read operation of the Lower page, a read operation of the Middle page, and a read operation of the Upper page of one cell unit CU are executed in this order.

[0157] As shown in FIG. 14, first, the memory controller 10 transmits a command set for a cell read operation of the lower page to the nonvolatile memory 20. More specifically, first, the memory controller 10 transmits a command “PFX” to the nonvolatile memory 20. The command “PFX” is a prefix command that notifies the execution of a read operation of the hard bit data HB and a calculation operation of the soft bit data SB. In other words, the command “PFX” is a command that notifies the execution of two read operations using two read voltages for one state and the calculation of the soft bit data SB. Next, the memory controller 10 transmits the commands “01h”, “00h”, an address “ADD”, and a command “30h” successively to the nonvolatile memory 20. The command “01h” is a command that specifies the lower page. The command “00h” is a command that notifies the execution of a cell read operation. The address “ADD” corresponds to the cell unit CU that is the target of the read operation. For example, the address “ADD” includes a row address RA, a column address CA, etc. The command "30h" is a command to execute a cell read operation based on the address "ADD" sent immediately before.

[0158] When the nonvolatile memory 20 receives the command "30h," it sets the ready / busy signal RBn to the "L" level and starts a cell read operation for the Lower page. As a result of the cell read operation, for example, hard bit data HB_L is stored in the latch circuit XDL. For example, the soft bit data SB_L is stored in the latch circuit ADL as cache data of the soft bit data SB (SB cache in FIG. 14).

[0159] When the cell read operation of the Lower page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0160] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Lower page (hard bit data HB_L) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" in succession to the nonvolatile memory 20. The command "05h" is a command notifying that a cache read operation will be performed. The command "E0h" is a command to perform a cache read operation based on the address "ADD" transmitted immediately before.

[0161] The nonvolatile memory 20 transmits the hard bit data HB_L of the data register 214 to the memory controller 10 .

[0162] After reading the hard bit data HB_L from the nonvolatile memory 20, i.e., after the cache read operation is completed, the memory controller 10 transmits a command set for a cell read operation of the Middle page to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the commands "PFX", "02h", "00h", address "ADD", and command "30h" in succession to the nonvolatile memory 20. The command "02h" is a command that specifies the Middle page.

[0163] When the nonvolatile memory 20 receives the command "30h", it sets the ready / busy signal RBn to the "L" level and starts a cell read operation for the Middle page. As a result of the cell read operation, for example, hard bit data HB_M is stored in the latch circuit XDL. For example, the soft bit data SB_M is ORed with the soft bit data SB_L stored in the latch circuit ADL. For example, the OR operation result of the soft bit data SB_L and SB_M (SB_L|SB_M in FIG. 14) is stored in the latch circuit ADL as the SB cache.

[0164] When the cell read operation of the Middle page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0165] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Middle page (hard bit data HB_M) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" successively to the nonvolatile memory 20.

[0166] The nonvolatile memory 20 transmits the hard bit data HB_M of the data register 214 to the memory controller 10 .

[0167] After reading the hard bit data HB_M from the nonvolatile memory 20, the memory controller 10 transmits a command set for a cell read operation of the Upper page to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the commands "PFX", "03h", "00h", address "ADD", and command "30h" in succession to the nonvolatile memory 20. The command "03h" is a command that specifies the Upper page.

[0168] When the nonvolatile memory 20 receives the command "30h", it sets the ready / busy signal RBn to the "L" level and starts a cell read operation of the Upper page. As a result of the cell read operation, for example, hard bit data HB_U is stored in the latch circuit XDL. For example, the soft bit data SB_H is ORed with the SB cache (SB_L|SB_M) stored in the latch circuit ADL. For example, the OR operation result of the soft bit data SB_L, SB_M, and SB_U (SB_L|SB_M|SB_U in FIG. 14) is stored in the latch circuit ADL as the SB cache. That is, the compressed soft bit data SB is stored in the latch circuit ADL.

[0169] When the cell read operation of the Upper page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0170] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Upper page (hard bit data HB_U) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" to the nonvolatile memory 20 in succession.

[0171] The nonvolatile memory 20 transmits the hard bit data HB_U of the data register 214 to the memory controller 10 .

[0172] After reading the hard bit data HB_U from the nonvolatile memory 20, the memory controller 10 transmits a command set to the nonvolatile memory 20 to read (transfer) the compressed soft bit data SB to the latch circuit XDL. More specifically, the memory controller 10 transmits the command "00h", the address "ADD", and the command "XXh" in succession to the nonvolatile memory 20. The command "XXh" is a command to transfer the compressed soft bit data SB to the latch circuit XDL.

[0173] When the nonvolatile memory 20 receives the command "XXh", it sets the ready / busy signal RBn to the "L" level and transfers the compressed soft bit data SB from the latch circuit ADL to the latch circuit XDL, for example.

[0174] When the transfer of the compressed soft bit data SB is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0175] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the compressed soft bit data SB to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", the address "ADD", and the command "E0h" successively to the nonvolatile memory 20.

[0176] The nonvolatile memory 20 transmits the compressed soft bit data SB in the data register 214 to the memory controller 10 .

[0177] 1.5.4 Second read mode command sequence Next, an example of a command sequence in the second read mode will be described with reference to Fig. 15. Fig. 15 shows the command sequence in the second read mode. In the example of Fig. 15, to simplify the description, the signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, and only the signal DQ and ready / busy signal RBn are shown. In the signal DQ, commands are written in circular frames, addresses are written in square frames, and data are written in hexagonal frames.

[0178] The example of FIG. 15 shows a case where a read operation of the Lower page, a read operation of the Middle page, and a read operation of the Upper page of one cell unit CU are executed in this order.

[0179] 15, first, the memory controller 10 transmits a command set for a cell read operation of the Lower page to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the commands “PFX”, “01h”, “00h”, address “ADD”, and command “30h” in succession to the nonvolatile memory 20.

[0180] When the nonvolatile memory 20 receives the command "30h", it sets the ready / busy signal RBn to the "L" level and starts a cell read operation for the Lower page. As a result of the cell read operation, for example, hard bit data HB_L is stored in the latch circuit XDL. For example, soft bit data SB_L is stored in the latch circuit ADL.

[0181] When the cell read operation of the Lower page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0182] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set to reserve a cell read operation of the Middle page to the nonvolatile memory 20. More specifically, the memory controller 10 successively transmits the commands "PFX", "02h", "00h", address "ADD", and command "31h" to the nonvolatile memory 20. The command "31h" is a command for reserving the execution of a command set for a cell read operation including the command "31h" after the cell read operation currently being executed has finished.

[0183] When the nonvolatile memory 20 receives the command "31h", it sets the ready / busy signal RBn to the "L" level and reserves the cell read operation of the Middle page.

[0184] When the reservation is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level. Since the cell read operation of the Lower page has been completed, the nonvolatile memory 20 starts the cell read operation of the Middle page while keeping the ready / busy signal RBn at the "H" level.

[0185] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Lower page (hard bit data HB_L) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" to the nonvolatile memory 20 in succession.

[0186] The nonvolatile memory 20 transmits the hard bit data HB_L of the data register 214 to the memory controller 10 in parallel with the cell read operation of the Middle page.

[0187] After reading the hard bit data HB_L from the nonvolatile memory 20, the memory controller 10 transmits a command set for reserving a cell read operation of the Upper page to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the commands “PFX”, “03h”, “00h”, address “ADD”, and command “31h” in succession to the nonvolatile memory 20.

[0188] When the reservation for the cell read operation of the Upper page is completed but the cell read operation of the Middle page is not completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "L" level. For example, after the hard bit data HB_L is output, the hard bit data HB_M is stored in the latch circuit XDL. The OR operation result (SB_L|SB_M) of the soft bit data SB_L and SB_M is stored in the latch circuit ADL as the SB cache.

[0189] When the cell read operation of the Middle page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level. Since the cell read operation of the Middle page is completed, the nonvolatile memory 20 starts the cell read operation of the Upper page with the ready / busy signal RBn kept at the "H" level.

[0190] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Middle page (hard bit data HB_M) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" successively to the nonvolatile memory 20.

[0191] The nonvolatile memory 20 transmits the hard bit data HB_M of the data register 214 to the memory controller 10 in parallel with the cell read operation of the Upper page.

[0192] When the cache read operation of the Middle page (hard bit data HB_M) is completed, the memory controller 10 transmits the command "3Fh" to the nonvolatile memory 20. The command "3Fh" is a command that reserves the transfer of the read data to the latch circuit XDL after the cell read operation of the last page (Upper page in the example of FIG. 15) is completed.

[0193] When the nonvolatile memory 20 completes the output of the hard bit data HB_M (cache read operation) and becomes ready to transfer data to the latch circuit XDL, it sets the ready / busy signal RBn to the "L" level. Then, the nonvolatile memory 20 transfers the hard bit data HB_U to the latch circuit XDL. At this time, for example, the OR operation result (SB_L|SB_M|SB_U) of the soft bit data SB_L, SB_M, and SB_U is stored in the latch circuit ADL as the SB cache. In other words, the compressed soft bit data SB is stored in the latch circuit ADL.

[0194] When the transfer of the hard bit data HB_U to the latch circuit XDL is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0195] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Upper page (hard bit data HB_U) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" to the nonvolatile memory 20 in succession.

[0196] The nonvolatile memory 20 transmits the hard bit data HB_U of the data register 214 to the memory controller 10 .

[0197] The read operation of the compressed soft bit data SB is the same as in the first operation mode.

[0198] 1.5.5 Third read mode command sequence Next, an example of a command sequence in the third read mode will be described with reference to Fig. 16. Fig. 16 shows the command sequence in the third read mode. In the example of Fig. 16, to simplify the description, the signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, and only the signal DQ and ready / busy signal RBn are shown. In the signal DQ, commands are written in circular frames, addresses are written in square frames, and data are written in hexagonal frames.

[0199] The example of FIG. 16 shows a case where a read operation of the Lower page, a read operation of the Middle page, and a read operation of the Upper page of one cell unit CU are executed consecutively based on one command set.

[0200] 16, first, the memory controller 10 transmits a command set for a read operation in the third read mode to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the commands "PFX", "00h", the address "ADD", and the command "30h" to the nonvolatile memory 20 in succession.

[0201] When the nonvolatile memory 20 receives the command "30h," it sets the ready / busy signal RBn to the "L" level and starts a cell read operation for the Lower page. As a result of the cell read operation, for example, hard bit data HB_L is stored in the latch circuit XDL. For example, soft bit data SB_L is stored in the latch circuit ADL.

[0202] When the cell read operation of the Lower page is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level. Furthermore, the nonvolatile memory 20 starts the cell read operation of the Middle page while keeping the ready / busy signal RBn at the "H" level.

[0203] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Lower page (hard bit data HB_L) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" to the nonvolatile memory 20 in succession.

[0204] The nonvolatile memory 20 transmits the hard bit data HB_L of the data register 214 to the memory controller 10 in parallel with the cell read operation of the Middle page.

[0205] After reading the hard bit data HB_L from the nonvolatile memory 20, the memory controller 10 transmits a command set to the nonvolatile memory 20 to read (transfer) the hard bit data HB_M to the latch circuit XDL. More specifically, the memory controller 10 transmits the command "00h", the address "ADD", and the command "YYh" in succession to the nonvolatile memory 20. The command "YYh" is a command to transfer the hard bit data HB_M to the latch circuit XDL.

[0206] When the nonvolatile memory 20 completes the cell read operation of the Middle page and is ready to transfer data to the latch circuit XDL, it sets the ready / busy signal RBn to the "L" level. Then, the nonvolatile memory 20 transfers the hard bit data HB_M to the latch circuit XDL. At this time, for example, the OR operation result (SB_L|SB_M) of the soft bit data SB_L and SB_M is stored in the latch circuit ADL as the SB cache.

[0207] When the transfer of the hard bit data HB_M to the latch circuit XDL is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level. The nonvolatile memory 20 starts the cell read operation of the Upper page while keeping the ready / busy signal RBn at the "H" level.

[0208] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Middle page (hard bit data HB_M) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" successively to the nonvolatile memory 20.

[0209] The nonvolatile memory 20 transmits the hard bit data HB_M of the data register 214 to the memory controller 10 in parallel with the cell read operation of the Upper page.

[0210] After reading the hard bit data HB_M from the nonvolatile memory 20, the memory controller 10 transmits a command set to the nonvolatile memory 20 to read (transfer) the hard bit data HB_U to the latch circuit XDL. More specifically, the memory controller 10 transmits the command "00h", the address "ADD", and the command "ZZh" in succession to the nonvolatile memory 20. The command "ZZh" is a command to cause the latch circuit XDL to transfer the hard bit data HB_U.

[0211] When the nonvolatile memory 20 completes the cell read operation of the Upper page and is ready to transfer data to the latch circuit XDL, it sets the ready / busy signal RBn to the "L" level. Then, the nonvolatile memory 20 transfers the hard bit data HB_U to the latch circuit XDL. At this time, for example, the latch circuit ADL stores the OR operation result (SB_L|SB_M|SB_U) of the soft bit data SB_L, SB_M, and SB_U as the SB cache. In other words, the latch circuit ADL stores the compressed soft bit data SB.

[0212] When the transfer of the hard bit data HB_U to the latch circuit XDL is completed, the nonvolatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0213] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set for a cache read operation of the Upper page (hard bit data HB_U) to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command "05h", address "ADD", and command "E0h" to the nonvolatile memory 20 in succession.

[0214] The nonvolatile memory 20 transmits the hard bit data HB_U of the data register 214 to the memory controller 10 .

[0215] The read operation of the compressed soft bit data SB is the same as in the first operation mode.

[0216] 1.6 Effects of this embodiment The configuration according to this embodiment can provide a memory system that can suppress an increase in the amount of data transfer. The effect of this embodiment will be described in detail.

[0217] For example, when performing soft-decision decoding, at least one soft bit data is required for one page. Therefore, multiple pages of soft bit data are read from the nonvolatile memory to the memory controller according to the number of pages of the cell unit CU. For example, in the case of TLC, at least six pages of page data are read, including three pages of hard bit data and three pages of soft bit data corresponding to the lower, middle, and upper pages. Therefore, as the number of multi-level memory cell transistors increases, the amount of data transferred from the nonvolatile memory to the memory controller increases. This increases the data transfer time and reduces the processing power of the memory system.

[0218] In contrast, with the configuration according to this embodiment, the nonvolatile memory 20 can compress (by logical OR operation) the soft bit data SB of multiple pages of the cell unit CU to calculate compressed soft bit data SB of one page of data. This can suppress an increase in the amount of data transfer. This can shorten the data transfer time and improve the processing capacity of the memory system 3.

[0219] Furthermore, with the configuration according to this embodiment, the memory controller 10 can restore the soft bit data SB corresponding to each page from the hard bit data HB and the compressed soft bit data SB.

[0220] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a flow of a read operation different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0221] 2.1 Read operation flow First, the flow of a read operation in the memory system 3 will be described with reference to Fig. 17. Fig. 17 is a flowchart of the read operation. Note that the example in Fig. 17 shows a case where data of multiple pages is read from one cell unit CU.

[0222] 17, unlike FIG. 13 of the first embodiment, the hard-decision decoding process (steps S13 and S14) is omitted. After the memory controller 10 reads a plurality of hard bit data HB from the nonvolatile memory 20 (step S12), it subsequently reads compressed soft bit data SB (step S15). The subsequent processes (steps S16 and S17) are the same as those in the first embodiment.

[0223] 2.2 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0224] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a read operation different from those of the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0225] 3.1 Data register and sense amplifier configuration First, an example of the configuration of the data register 214 and the sense amplifier 213 will be described with reference to Fig. 18. Fig. 18 is a block diagram of the data register 214 and the sense amplifier 213.

[0226] As shown in Fig. 18, the sense amplifier 213 of this embodiment includes a counter CT. The other configurations are the same as those of the first embodiment in Fig. 6.

[0227] The counter CT is a counter that counts the number of "1" data (number of bits) in one page of data of the compressed soft bit data SB. The counter CT transfers the count result to the sequencer 206. For example, the sequencer 206 transfers the count result to the status register 205 as status information STS. Note that the data for which the counter CT counts the number of "1" data is not limited to the compressed soft bit data SB. For example, the counter CT may count the number of "1" data in each of the soft bit data SB_L, SB_M, and SB_U. The counter CT may also count the number of "0" data. The counter CT counts the number of data (number of bits) at any logic level of the latch circuit that is the target of the count.

[0228] 3.2 Specific example of the relationship between count number and threshold voltage distribution Next, a specific example of the relationship between the count number by the counter CT and the threshold voltage distribution will be described with reference to Fig. 19. Fig. 19 is a diagram showing the relationship between the count number and the threshold voltage distribution in the "Er" state and the "A" state.

[0229] As shown in FIG. 19 , for example, when the threshold voltage distribution of the “Er” state and the threshold voltage distribution of the “A” state do not overlap, the number of memory cell transistors MC whose threshold voltages are between voltage VAL and voltage VAH is relatively small. In other words, the number of memory cell transistors MC whose soft bit data SB is “1” is relatively small. In such a case, the number of “1” data counted by the counter CT is relatively small. In contrast, when the overlapping region of the threshold voltage distributions becomes larger, the number of memory cell transistors MC whose threshold voltages are between voltage VAL and voltage VAH increases. In other words, the number of memory cell transistors MC whose soft bit data SB is “1” increases. When the overlapping region of the threshold voltage distributions becomes larger, the number of fail bits increases, increasing the possibility of failure of the hard-decision decoding process. Therefore, the difficulty of the hard-decision decoding process can be estimated based on the count of “1” data in the compressed soft bit data SB.

[0230] 3.3 Read operation flow Next, the flow of a read operation in the memory system 3 will be described with reference to Fig. 20. Fig. 20 is a flowchart of the read operation. Note that the example in Fig. 20 shows a case where data of multiple pages is read from one cell unit CU.

[0231] As shown in FIG. 20, steps S10 to S12 are the same as those in the first embodiment.

[0232] After step S12, the memory controller 10 reads the count number of "1" data in the compressed soft bit data SB from the nonvolatile memory 20. Then, the memory controller 10 compares the count number with a preset judgment value (step S20). Note that the nonvolatile memory 20 may compare the count number with the judgment value. In this case, the memory controller 10 reads the comparison result from the nonvolatile memory 20. The nonvolatile memory 20 may also count the number of "1" data in each of the soft bit data SB_L, SB_M, and SB_U. In this case, the memory controller 10 may compare each count number with the judgment value.

[0233] If the count number is less than the decision value (step S21_Yes), the memory controller 10 executes the hard-decision decoding process (step S13). In this case, since the hard-decision decoding process is likely to be successful, the memory controller 10 continues to execute the hard-decision decoding process without reading the compressed soft bit data SB.

[0234] If the count number is equal to or greater than the determination value (step S21_No), the memory controller 10 executes the operations of steps S15 to S17 in the same manner as in the first embodiment.

[0235] 3.4 Command sequence for read operation Next, an example of a command sequence for a read operation will be described with reference to Fig. 21. Fig. 21 shows the command sequence for a read operation. In the example of Fig. 21, to simplify the explanation, the signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, and only the signal DQ and ready / busy signal RBn are shown. In the signal DQ, commands are written in circular frames, addresses are written in rectangular frames, and data are written in hexagonal frames.

[0236] The example in FIG. 21 shows a case where the first read mode is executed, but this embodiment can also be applied to the second read mode or the third read mode.

[0237] As shown in FIG. 21, the command set up to the cache read operation of the hard bit data HB_U is the same as that in FIG. 14 of the first embodiment.

[0238] After reading the hard bit data HB_U from the nonvolatile memory 20, the memory controller 10 transmits a command set to read (transfer) the compressed soft bit data SB to the latch circuit XDL to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command “00h”, the address “ADD”, and the command “XXh” successively to the nonvolatile memory 20.

[0239] When the nonvolatile memory 20 receives the command "XXh," it sets the ready / busy signal RBn to "L" level and transfers the compressed soft bit data SB, for example, from the latch circuit ADL to the latch circuit XDL. At this time, the counter CT counts the number of "1" data in the compressed soft bit data SB. The count number is stored in the status register 205.

[0240] When the nonvolatile memory 20 finishes transferring the compressed soft bit data SB and counting the number of "1" data, it sets the ready / busy signal RBn to "H" level.

[0241] When the memory controller 10 confirms that the ready / busy signal RBn is at the "H" level, it transmits a command set to read the count number. The memory controller 10 reads the count number information as the status information STS from the status register 205. More specifically, the memory controller 10 transmits the command "7Xh" to the nonvolatile memory 20. The command "7Xh" is a command to execute the reading of the status information STS.

[0242] When the nonvolatile memory 20 receives the command "7Xh", it transmits the count information ("1" count in FIG. 21) to the memory controller 10 as the status information STS.

[0243] After receiving the count information, the memory controller 10 transmits a command set for a cache read operation of the compressed soft bit data SB to the nonvolatile memory 20. More specifically, the memory controller 10 transmits the command “05h”, the address “ADD”, and the command “E0h” successively to the nonvolatile memory 20.

[0244] The nonvolatile memory 20 transmits the compressed soft bit data SB in the data register 214 to the memory controller 10 .

[0245] 3.5 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0246] Furthermore, in the configuration according to this embodiment, the nonvolatile memory 20 includes a counter CT that counts the number of "1" data in the compressed soft bit data SB. By counting the number of "1" data, the difficulty of the hard-decision decoding process can be determined. If the count is less than a preset determination value, the memory controller 10 determines that the hard-decision decoding process is likely to be successful, and can omit reading (data transfer) of the compressed soft bit data SB from the nonvolatile memory 20. Therefore, if the hard-decision decoding process is likely to be successful, it is possible to avoid data transfer of compressed soft bit data SB that is likely to be unused. This makes it possible to suppress an increase in the amount of data transfer.

[0247] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a case will be described in which the memory cell transistor MC is a QLC (Quad Level Cell) that stores 4-bit data consisting of a Lower bit, a Middle bit, an Upper bit, and a Top bit. Below, the differences from the first to third embodiments will be mainly described.

[0248] 4.1 Relationship between memory cell transistor threshold voltage distribution and data allocation First, an example of the relationship between the threshold voltage distribution of memory cell transistor MC and data allocation will be described with reference to Fig. 22. Fig. 22 is a diagram showing the relationship between the threshold voltage distribution of QLC and data allocation.

[0249] 22, the threshold voltage of each memory cell transistor MC takes a value included in one of, for example, 16 discrete distributions. Hereinafter, the 16 distributions will be referred to as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, "S7" state, "S8" state, "S9" state, "S10" state, "S11" state, "S12" state, "S13" state, "S14" state, and "S15" state, respectively, in order of decreasing threshold voltage.

[0250] The "S0" state corresponds to, for example, a data erasure state. The "S1" to "S15" states correspond to states in which charges are injected into the charge storage layer and data is written. In the write operation, the verify voltages corresponding to each threshold voltage distribution are set as V1 to V15. Then, these voltage values have the relationship of V1 < V2 < V3 < V4 < V5 < V6 < V7 < V8 < V9 < V10 < V11 < V12 < V13 < V14 < V15 < Vread.

[0251] More specifically, the threshold voltage included in the "S0" state is less than the voltage V1. The threshold voltage included in the "S1" state is greater than or equal to the voltage V1 and less than the voltage V2. The threshold voltage included in the "S2" state is greater than or equal to the voltage V2 and less than the voltage V3. The threshold voltage included in the "S3" state is greater than or equal to the voltage V3 and less than the voltage V4. The threshold voltage included in the "S4" state is greater than or equal to the voltage V4 and less than the voltage V5. The threshold voltage included in the "S5" state is greater than or equal to the voltage V5 and less than the voltage V6. The threshold voltage included in the "S6" state is greater than or equal to the voltage V6 and less than the voltage V7. The threshold voltage included in the "S7" state is greater than or equal to the voltage V7 and less than the voltage V8. The threshold voltage included in the "S8" state is greater than or equal to the voltage V8 and less than the voltage V9. The threshold voltage included in the "S9" state is greater than or equal to the voltage V9 and less than the voltage V10. The threshold voltage included in the "S10" state is greater than or equal to the voltage V10 and less than the voltage V11. The threshold voltage included in the "S11" state is greater than or equal to the voltage V11 and less than the voltage V12. The threshold voltage included in the "S12" state is greater than or equal to the voltage V12 and less than the voltage V13. The threshold voltage included in the "S13" state is greater than or equal to the voltage V13 and less than V14. The threshold voltage included in the "S14" state is greater than or equal to the voltage V14 and less than V15. The threshold voltage included in the "S15" state is greater than or equal to the voltage V15 and less than the voltage VREAD.

[0252] As described above, each memory cell transistor MC can have one of 16 threshold voltage distributions, and can take on 16 different states. By assigning these states to binary values ​​"0000" to "1111," each memory cell transistor MC can hold 4 bits of data. Hereinafter, the 4 bits of data will be referred to as the lower bit, middle bit, upper bit, and top bit. Furthermore, the set of lower bits that are collectively written (or read) from the cell unit CU will be referred to as the lower page. The set of middle bits will be referred to as the middle page. The set of upper bits will be referred to as the upper page. The set of top bits will be referred to as the top page.

[0253] In the example of FIG. 22, data is allocated to the "Top bit / Upper bit / Middle bit / Lower bit" for the memory cell transistors MC included in each threshold voltage distribution as shown below.

[0254] “S0” state: “1111” data “S1” state: “0111” data “S2” state: “0011” data “S3” state: “1011” data “S4” state: “1001” data “S5” state: “1000” data “S6” state: “0000” data “S7” state: “0001” data “S8” state: “0101” data “S9” state: “0100” data “S10” state: “0110” data “S11” state: “0010” data “S12” state: “1010” data “S13” state: “1110” data “S14” state: “1100” data “S15” state: “1101” data

[0255] When reading data allocated in this way, the Lower bit is determined by read operations corresponding to the "S5" state, the "S7" state, the "S9" state, and the "S15" state. The Middle bit is determined by read operations corresponding to the "S4" state, the "S10" state, and the "S14" state. The Upper bit is determined by read operations corresponding to the "S2" state, the "S8" state, the "S11" state, and the "S13" state. The Top bit is determined by read operations corresponding to the "S1" state, the "S3" state, the "S6" state, and the "S12" state. In other words, the values ​​of the Lower bit, Middle bit, Upper bit, and Top bit are determined by read operations corresponding to four states, three states, four states, and four states, respectively. Hereinafter, this data allocation will be referred to as the "4-3-4-4 code." Note that data allocation is not limited to the 4-3-4-4 code.

[0256] 4.2 Hard bit data and compressed soft bit data for each state Next, the hard bit data HB and soft bit data SB of each state will be described with reference to Fig. 23. Fig. 23 is a diagram showing the relationship between the threshold voltage distribution of QLC and the hard bit data HB and compressed soft bit data SB.

[0257] As shown in FIG. 23, the two read voltages corresponding to the "S1" state are set as voltage V1L and voltage V1H. The two read voltages corresponding to the "S2" state are set as voltage V2L and voltage V2H. The two read voltages corresponding to the "S3" state are set as voltage V3L and voltage V3H. The two read voltages corresponding to the "S4" state are set as voltage V4L and voltage V4H. The two read voltages corresponding to the "S5" state are set as voltage V5L and voltage V5H. The two read voltages corresponding to the "S6" state are set as voltage V6L and voltage V6H. The two read voltages corresponding to the "S7" state are set as voltage V7L and voltage V_{7H}. The two read voltages corresponding to the "S8" state are set as voltage V8L and voltage V8H. The two read voltages corresponding to the "S9" state are set as voltage V9L and voltage V9H. The two read voltages corresponding to the "S10" state are set as voltage V10L and voltage V10H. The two read voltages corresponding to the "S11" state are set as voltage V11L and voltage V11H. The two read voltages corresponding to the "S12" state are set as voltage V12L and voltage V12H. The two read voltages corresponding to the "S13" state are set as voltage V13L and voltage V13H. The two read voltages corresponding to the "S14" state are set as voltage V14L and voltage V14H. The two read voltages corresponding to the "S15" state are set as voltage V15L and voltage V15H.

[0258] These voltages are in the relationship of V1L < V1 < V1H < V2L < V2 < V2H < V3L < V3 < V3H < V4L < V4 < V4H < V5L < V5 < V5H < V6L < V6 < V6H < V7L < V7 < V7H < V8L < V8 < V8H < V9L < V9 < V9H < V10L < V10 < V10H < V11L < V11 < V11H < V12L < V12 < V12H < V13L < V13 < V13H < V14L < V14 < V14H < V15L < V15 < V15H < VREAD.

[0259] The read operations using voltages V1L, V1H, V2L, V2H, V3L, V3H, V4L, V4H, V5L, V5H, V6L, V6H, V7L, V7H, V8L, V8H, V9L, V9H, V10L, V10H, V11L, V11H, V12L, V12H, V13L, V13H, V14L, V14H, V15L, and V15H are respectively referred to as 1LR read, 1H read, and 1LR read. These are written as R lead, 2LR lead, 2HR lead, 3LR lead, 3HR lead, 4LR lead, 4HR lead, 5LR lead, 5HR lead, 6LR lead, 6HR lead, 7LR lead, 7HR lead, 8LR lead, 8HR lead, 9LR lead, 9HR lead, 10LR lead, 10HR lead, 11LR lead, 11HR lead, 12LR lead, 12HR lead, 13LR lead, 13HR lead, 14LR lead, 14HR lead, 15LR lead, 15HR lead.

[0260] The read operation for the lower page involves eight read operations: a 5LR read, a 5HR read, a 7LR read, a 7HR read, a 9LR read, a 9HR read, a 15LR read, and a 15HR read. The hard bit data HB_L is the data determined by the 5LR read, the 7LR read, the 9LR read, and the 15LR read. The soft bit data SB_L is based on an XOR operation between the hard bit data HB_L and the data determined by the 5HR read, the 7HR read, the 9HR read, and the 15HR read.

[0261] The read operation for the Middle page involves six read operations: a 4LR read, a 4HR read, a 10LR read, a 10HR read, a 14LR read, and a 14HR read. The hard bit data HB_M is the data determined by the 5LR read, the 10LR read, and the 14LR read. The soft bit data SB_M is based on an XOR operation between the hard bit data HB_M and the data determined by the 4HR read, the 10HR read, and the 14HR read.

[0262] In the read operation of the Upper page, eight read operations are executed: 2LR read, 2HR read, 8LR read, 8HR read, 11LR read, 11HR read, 13LR read, and 13HR read. The hard bit data HB_U is the data determined by the 2LR read, 8LR read, 11LR read, and 13LR read. The soft bit data SB_U is based on the XOR operation of the hard bit data HB_U and the data determined by the 2HR read, 8HR read, 11HR read, and 13HR read.

[0263] The read operation for the Top page involves eight read operations: 1LR read, 1HR read, 3LR read, 3HR read, 6LR read, 6HR read, 12LR read, and 12HR read. The hard bit data HB_T is data determined by the 1LR read, 3LR read, 6LR read, and 12LR read. The soft bit data SB_T is based on an XOR operation between the hard bit data HB_T and the data determined by the 1HR read, 3HR read, 6HR read, and 12HR read.

[0264] The compressed soft bit data SB is data calculated by ORing the soft bit data SB_L, SB_M, SB_U, and SB_T.

[0265] 23, the threshold voltage of the memory cell transistor MC is divided into 31 sections corresponding to 30 read voltages. The combinations of "hard bit data HB_T / HB_U / HM_M / HB_L" and "compressed soft bit data SB" for each section in each state are as follows:

[0266] “S0” state (voltage less than V1L): “1111”, “0” "S1" state (voltage V1L or higher and lower than V1H): "0111", "1" "S1" state (voltage V1H or higher and lower than V2L): "0111", "0" "S2" state (voltage greater than or equal to V2L and less than V2H): "0011", "1" "S2" state (voltage V2H or higher and lower than V3L): "0011", "0" "S3" state (voltage V3L or higher and lower than V3H): "1011", "1" "S3" state (voltage V3H or higher and lower than V4L): "1011", "0" "S4" state (voltage V4L or higher and lower than V4H): "1001", "1" "S4" state (voltage V4H or higher and voltage V5L or lower): "1001", "0" "S5" state (voltage V5L or higher and voltage V5H or lower): "1000", "1" "S5" state (voltage V5H or higher and lower than V6L): "1000", "0" "S6" state (voltage V6L or higher and lower than V6H): "0000", "1" "S6" state (voltage V6H or higher and lower than V7L): "0000", "0" "S7" state (voltage V7L or higher and voltage V7H or lower): "0001", "1" "S7" state (voltage V7H or higher and lower than V8L): "0001", "0" "S8" state (voltage V8L or higher and lower than V8H): "0101", "1" "S8" state (voltage V8H or higher and less than V9L): "0101", "0" "S9" state (voltage V9L or higher and voltage V9H or lower): "0100", "1" "S9" state (voltage V9H or higher and voltage V10L or lower): "0100", "0" "S10" state (voltage V10L or higher and voltage V10H or lower): "0110", "1" "S10" state (voltage V10H or higher and voltage V11L or lower): "0110", "0" "S11" state (voltage V11L or higher and lower than V11H): "0010", "1" "S11" state (voltage V11H or higher and lower than V12L): "0010", "0" "S12" state (voltage V12L or higher and lower than V12H): "1010", "1" "S12" state (voltage V12H or higher and voltage V13L or lower): "1010", "0" "S13" state (voltage V13L or higher and lower than V13H): "1110", "1" "S13" state (voltage V13H or higher and voltage V14L or lower): "1110", "0" "S14" state (voltage V14L or higher and less than V14H): "1100", "1" "S14" state (voltage V14H or higher and voltage V15L or lower): "1100", "0" "S15" state (voltage V15L or higher and voltage V15H or lower): "1101", "1" "S15" state (voltage V15H or higher and lower than voltage VEAD): "1101", "0"

[0267] 4.3 How to recover compressed soft bits Next, a method for restoring the compressed soft bit data SB will be described with reference to Fig. 24. Fig. 24 is a diagram showing the restoration process of the soft bit data SB_L, SB_M, SB_U, and SB_T.

[0268] The positions (states) where "1" data can occur in the soft bit data SB_L, SB_M, SB_U, and SB_T are mutually exclusive. Furthermore, a combination of hard bit data HB_L, HB_M, HB_U, and HB_T can be defined one-to-one with a combination of soft bit data SB_L, SB_M, SB_U, and SB_T. Utilizing these facts, the soft bit data SB of each page is restored from the hard bit data HB_L, HB_M, HB_U, and HB_T and the compressed soft bit data SB.

[0269] 24, the SB restoration circuit 163 receives hard bit data HB_L, HB_M, HB_U, and HB_T and compressed soft bit data SB from the nonvolatile memory 20. The SB decoder 1006 performs the following operations when restoring the soft bit data SB_L, SB_M, SB_U, and SB_T. In the following arithmetic expressions, "|" indicates an OR operation, and "~" indicates inverted data. In the following arithmetic expressions, the hard bit data HB_L, HB_M, HB_U, and HB_T are simply represented as "L", "M", "U", and "T".

[0270] SB_L=((~L&~M&~U&T)|(L&~M&~U&~T)| (~L&~M&U&~T)|(L&~M&U&T))&SB SB_M=((L&~M&~U&T)|(~L&M&U&~T)| (~L&~M&U&T))&SB SB_U=((L&M&~U&~T)|(L&~M&U&~T)| (~L&M&~U&~T)|(~L&M&U&T))&SB SB_T=((L&M&U&~T)|(L&M&~U&T)| (~L&~M&~U&~T)|(~L&M&~U&T))&SB

[0271] The above arithmetic expressions are used to restore the soft bit data SB_L, SB_M, SB_U, and SB_T described with reference to Fig. 24. Note that the above arithmetic expressions can be modified as appropriate based on the allocation of data in memory cell transistors MC.

[0272] 4.4 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0273] This embodiment can be combined with the second or third embodiment.

[0274] 5.Other According to the above embodiment, the memory system includes a nonvolatile memory (20) including a plurality of memory cells (MC) each capable of storing at least a first bit (lower bit), a second bit (middle bit), and a third bit (upper bit), and a memory controller (10) that controls the nonvolatile memory. The nonvolatile memory generates fourth soft bit data (compressed SB) based on a logical OR operation using first soft bit data (SB_L) of the first bit, second soft bit data (SB_M) of the second bit, and third soft bit data (SB_U) of the third bit. The memory controller restores the first soft bit data, the second soft bit data, and the third soft bit data based on the first hard bit data (HB_L) of the first bit, the second hard bit data (HB_M) of the second bit, the third hard bit data (HB_U) of the third bit, and the fourth soft bit data.

[0275] By applying the above-described embodiment, it is possible to provide a memory system that can suppress an increase in the amount of data transferred between the memory controller and the nonvolatile memory.

[0276] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0277] For example, in the third embodiment, either hard-decision decoding processing or soft-decision decoding processing is performed based on the determination result of the count number. However, the operation based on the determination result of the count number is not limited to this. For example, if the hard-decision decoding processing fails, the count number may be determined. In this case, whether or not to perform soft-decision decoding processing may be determined based on the determination result.

[0278] For example, in the above embodiment, the soft bit data SB of multiple pages of one cell unit CU is compressed into one page data, but this is not limiting. For example, multiple soft bit data SB of multiple cell units CU may be compressed into one page data.

[0279] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0280] The embodiments are merely examples, and the scope of the invention is not limited thereto. [Explanation of symbols]

[0281] 1...Data processing device 2...Host device 3. Memory system 10...Memory controller 11...Host interface circuit 12...CPU 13...ROM 14...RAM 15...Buffer memory 16...ECC circuit 17...Memory interface circuit 20...Non-volatile memory 160...encoding circuit 161...Hard decision decoding circuit 162...Soft decision decoding circuit 163...SB restoration circuit 201...input / output circuit 202...Logic control circuit 203...Address register 204...Command register 205...Status register 206...Sequencer 207...Ready / Busy circuit 208...Voltage generating circuit 211...Memory cell array 212...Row decoder 213...Sense amplifier 214...Data register 215...Column decoder 1001...Demultiplexer 1002~1005...Buffer 1006...SB decoder CT...Counter

Claims

1. a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit; a memory controller that controls the nonvolatile memory; Equipped with The nonvolatile memory includes: generating fourth soft bit data based on a logical OR operation using first soft bit data of the first bit, second soft bit data of the second bit, and third soft bit data of the third bit; the memory controller restores the first soft bit data, the second soft bit data, and the third soft bit data based on the first hard bit data of the first bit, the second hard bit data of the second bit, the third hard bit data of the third bit, and the fourth soft bit data; Memory system.

2. the memory controller reads the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data from the nonvolatile memory, and does not read the first soft bit data, the second soft bit data, and the third soft bit data from the nonvolatile memory; 10. The memory system of claim 1.

3. The memory controller performs error correction using the restored first soft bit data.

10. The memory system of claim 1.

4. a data size of the first hard bit data, a data size of the second hard bit data, a data size of the third hard bit data, and a data size of the fourth soft bit data are the same size; 10. The memory system of claim 1.

5. The memory controller Reconstructing the first soft bit data based on the first hard bit data and the fourth soft bit data; Reconstructing the second soft bit data based on the second hard bit data and the fourth soft bit data; restoring the third soft bit data based on the third hard bit data and the fourth soft bit data; 10. The memory system of claim 1.

6. the first bit is determined by a first read operation based on at least a first state; the first read operation includes a second read operation using a first voltage corresponding to the first state and a third read operation using a second voltage corresponding to the first state and higher than the first voltage; the first hard bit data is determined based on at least the second read operation; the first soft bit data is determined based on an operation of the first hard bit data and a result of the third read operation.

10. The memory system of claim 1.

7. the first soft bit data is determined based on an exclusive-OR operation of the first hard bit data and the result of the third read operation.

7. The memory system of claim 6.

8. the memory controller sends a first command set including a first command to the nonvolatile memory; the nonvolatile memory performs the first read operation and determines the first soft bit data based on the first command; 7. The memory system of claim 6.

9. the memory controller performs soft-decision decoding based on the first hard bit data, the second hard bit data, the third hard bit data, the first soft bit data, the second soft bit data, and the third soft bit data.

10. The memory system of claim 1.

10. the memory controller performs a hard-decision decoding process based on the first hard bit data, the second hard bit data, and the third hard bit data, and performs the soft-decision decoding process when the hard-decision decoding process fails.

10. The memory system of claim 9.

11. the nonvolatile memory further includes a counter that counts the number of first logic level data of any one of the first soft bit data, the second soft bit data, the third soft bit data, and the fourth soft bit data; the memory controller reads the number, and if the read number is less than a predetermined determination value, reads the fourth soft bit data from the nonvolatile memory; 10. The memory system of claim 1.

12. a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit; a word line commonly connected to the plurality of memory cells; a plurality of bit lines respectively connected to the plurality of memory cells; a sense amplifier connected to the plurality of bit lines; an input / output circuit connectable to an external memory controller; Equipped with The sense amplifier generating first hard bit data of the first bit; generating second hard bit data of the second bit; generating third hard bit data of the third bit; generating fourth soft bit data based on a logical OR operation using first soft bit data of the first bit, second soft bit data of the second bit, and third soft bit data of the third bit; the input / output circuit is capable of outputting the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data to the external memory controller; Non-volatile memory.

13. a data size of the first hard bit data, a data size of the second hard bit data, a data size of the third hard bit data, and a data size of the fourth soft bit data are the same size; The non-volatile memory of claim 12.

14. The first soft bit data, the second soft bit data, and the third soft bit data can be restored based on the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data. The non-volatile memory of claim 12.

15. The first soft bit data is reconstructable based on the first hard bit data and the fourth soft bit data.

15. The non-volatile memory of claim 14.

16. the first bit is determined by a first read operation based on at least a first state; the first read operation includes a second read operation using a first voltage corresponding to the first state and a third read operation using a second voltage corresponding to the first state and higher than the first voltage; the first hard bit data is determined based on at least the second read operation; the first soft bit data is determined based on an operation of the first hard bit data and a result of the third read operation. The non-volatile memory of claim 12.

17. The operation of the first hard bit data and the result of the third read operation is an exclusive OR operation.

17. The non-volatile memory of claim 16.

18. The nonvolatile memory performs the first read operation and the determination of the first soft bit data in response to a first command set including a first command transmitted from the external memory controller.

17. The non-volatile memory of claim 16.

19. a counter for counting the number of first logic level data of any one of the first soft bit data, the second soft bit data, the third soft bit data, and the fourth soft bit data; The non-volatile memory of claim 12.

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