Signal generating apparatus and signal generating method

Abstract

To generate a signal with a transmission time and a frequency shift amount as defined by a standard.SOLUTION: A signal generation apparatus 1 includes a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source 2, a signal generation source 4 that generates a time-series pattern signal of TestFlow defined by a predetermined standard for performing a ReceiverFrequencyvariationtest at a timing of the jitter clock, and an operation unit 5 that sets a type of a pattern for each Flow of the time-series pattern signal, a manual or automatic switching method for each Flow, and a transmission time of the pattern for each Flow of the automatic switching method in a pattern setting list 21 in a table format. The time-series pattern signal of TestFlow is transmitted to the device under test W according to the setting of the operation unit 5.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal generating device and a signal generating method for generating a signal for performing a Receiver Frequency variation test (a test of clock variation tolerance of a receiver) defined in the CTS (Compliance Test Specification) of the USB4 v2 Gen4 standard. [Background technology]

[0002] 2. Description of the Related Art An error rate measuring device is conventionally known that inputs a known pattern signal to a device under test and measures the bit error rate of input data received from the device under test in response to the input of this pattern signal by comparing it with the pattern signal.

[0003] Among these types of error rate measuring devices, there is one that is configured with multiple modules, such as a pattern generating module, an error measuring module, a modulated signal generating module, a jitter module, an emphasis module, a multiplexing module, and an inverse multiplexing module, and that combines desired modules depending on the measurement content to perform various measurements of the device under test based on standards in various forms, as disclosed in Patent Document 1 below.

[0004] Recently, the USB4 v2 Gen4 Compliance Test Specification (CTS) has defined a Receiver Frequency Variation test as a test item for testing a device's tolerance to clock fluctuations. This test is defined in CTS Revision 0.9, sections 4.3.4, 4.3.5, 6.3.3, etc.

[0005] As shown in the Appendix-Receiver Frequency variation test flow diagram of CTS Revision 0.9, the test flow for the above test defines two patterns, TYPE I and TYPE II, and the transmission patterns are switched one after another in a chronological order. The transmission time for each pattern in the sequence defined by the above standard is at least on the order of a few microseconds. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6651432 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the method of switching patterns by using a control device of a conventional error rate measuring device, including the above-mentioned Patent Document 1, to coordinate the operation of a signal generation source (pattern generation module of Patent Document 1) and a jitter modulation source (jitter module of Patent Document 1), the switching was not fast enough, and the above-mentioned Receiver Frequency variation test sequence could not be realized.

[0008] Furthermore, in the Receiver Frequency variation test, it is necessary to set the clock frequency deviation to change several microseconds after the pattern is switched. This operation also requires an operation on the order of microseconds, which cannot be achieved with the current mechanism.

[0009] Furthermore, in the past, it was difficult for users to grasp on the screen the configuration of the test sequence for performing a Receiver Frequency variation test, which led to problems such as running the test with the test sequence parameters set incorrectly, resulting in test results that were not caused by the DUT, or making it difficult to identify the cause during debugging, thereby reducing the efficiency of DUT development.

[0010] Therefore, the present invention has been made in consideration of the above problems, and an object of the present invention is to provide a signal generator and a signal generation method that can generate a signal with a transmission time and frequency deviation amount that conforms to the definitions of the standard. [Means for solving the problem]

[0011] In order to achieve the above object, a signal generating device according to claim 1 of the present invention comprises: a clock source 2 that generates a clock of a reference frequency; a jitter modulation source 3 that generates a jitter clock by modulating a clock having a reference frequency generated by the clock source; a signal generator 4 that generates a time-series pattern signal of a Test Flow defined by a predetermined standard at the timing of the jitter clock in order to perform a Receiver Frequency variation test; an operation unit 5 for setting a pattern type for each flow of the time-series pattern signal, a manual or automatic switching method for each flow, and a pattern transmission time for each flow of the automatic switching method in a tabular pattern setting list 21; The time-series pattern signal of the Test Flow is transmitted to the device under test in accordance with the settings of the operation unit.

[0012] The signal generating device according to claim 2 of the present invention is the signal generating device according to claim 1, The test sequence configuration 20 is characterized in that the time series pattern signals of the Test Flow are displayed consecutively in the order of the Flow numbers, and the frequency deviation of the clock with the horizontal axis being time is displayed on the vertical axis in correspondence with the Flow numbers.

[0013] The signal generating device according to claim 3 of the present invention is the signal generating device of claim 1, The transmission time of the pattern for each flow in the automatic switching method can be increased or decreased arbitrarily by the operation unit 5 within a predetermined range including the time defined by the standard.

[0014] The signal generating device according to claim 4 of the present invention is the signal generating device according to claim 2, In the test sequence configuration 20, a flow including a portion where the frequency deviation amount of the clock changes is highlighted so as to be distinguishable from other flows.

[0015] The signal generating device according to claim 5 of the present invention is the signal generating device of claim 1, In the pattern setting list 21, the background of the item of the Flow to which the currently transmitted pattern belongs is highlighted.

[0016] A signal generating method according to claim 6 of the present invention includes the steps of: generating a clock having a reference frequency by a clock source 2; generating a jitter clock by a jitter modulation source 3, the jitter clock being modulated from a clock of a reference frequency generated by the clock source; generating a time series pattern signal of a Test Flow defined by a predetermined standard for performing a Receiver Frequency variation test by a signal generator 4 at the timing of the jitter clock; a step of setting, in a tabular pattern setting list 21 by an operation unit 5, the type of pattern for each flow of the time-series pattern signal, the manual or automatic switching method for each flow, and the transmission time of the pattern for each flow of the automatic switching method; and transmitting a time-series pattern signal of the Test Flow to the device under test in accordance with the setting of the operation unit.

[0017] The signal generating method according to claim 7 of the present invention is the signal generating method according to claim 6, The test sequence configuration 20 is characterized by including a step of displaying the time-series pattern signals of the Test Flow in the order of their Flow numbers, and displaying the frequency deviation of the clock, with the horizontal axis representing time, on the vertical axis in correspondence with the Flow numbers.

[0018] The signal generating method according to claim 8 of the present invention is the signal generating method according to claim 6, The switching method is characterized by including a step of arbitrarily increasing or decreasing the transmission time of the pattern for each Flow that has been set to automatic by the operation unit 5 within a predetermined range including the time specified by the standard.

[0019] The signal generating method according to claim 9 of the present invention is the signal generating method according to claim 7, The test sequence configuration 20 is characterized by including a step of highlighting a flow including a portion where the frequency deviation amount of the clock changes so as to be distinguishable from other flows.

[0020] The signal generating method according to claim 10 of the present invention is the signal generating method according to claim 6, The method is characterized in that it includes a step of highlighting the background of the Flow item in the pattern setting list 21 to which the currently transmitted pattern belongs. [Effects of the Invention]

[0021] According to the present invention, it is possible to transmit a test sequence for performing the Receiver Frequency Variation test defined in the CTS of the USB4 v2 Gen4 standard with a transmission time and frequency deviation amount as defined in the standard.

[0022] It also enables users to visually grasp the configuration of the test sequence for performing a Receiver Frequency Variation test. This allows users to easily understand the test sequence configuration on the screen, preventing test results that are not caused by the DUT and eliminating the time-consuming effort of identifying the cause during debugging, thereby improving the development efficiency of the DUT.

[0023] Furthermore, the pattern transmission time can be increased or decreased arbitrarily within a specified range that includes the time specified by the standard, making it easy to test the tolerance (margin) of the DUT for transmission times that deviate from the standard for each flow. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a block diagram showing a schematic configuration of a signal generating device according to the present invention; [Figure 2] 1 is a perspective view showing the appearance of a signal generating device according to the present invention. [Figure 3] FIG. 10 is a diagram showing an example of a pattern setting screen of the signal generating device according to the present invention, which is a pattern setting screen relating to TYPE I of Test Flow of the CTS standard of USB4 v2 Gen4. [Figure 4] FIG. 10 is a diagram showing an example of a pattern setting screen of the signal generating device according to the present invention, which is a pattern setting screen relating to Test Flow TYPE II of the CTS standard for USB4 v2 Gen4. [Figure 5] FIG. 1 is a diagram showing an example of a flowchart of a signal generating method by a signal generating device according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] As shown in FIG. 1, the signal generating device 1 of this embodiment is roughly configured to include a clock source 2, a jitter modulation source 3, a signal generating source 4, an operation unit 5, a display unit 6, and a device control unit 7, and has the function of generating two time-series signal patterns of TYPE I or TYPE II of the Test Flow defined in Appendix F - Receiver Frequency variation test flow diagram in the CTS of the USB4 v2 Gen4 standard, in order to realize a Receiver Frequency variation test sequence (a test of the clock variation tolerance of a receiver).

[0027] It should be noted that this embodiment is not limited to the USB4 v2 Gen4 standard, but can also be applied to high-speed bus standards (e.g., USB4 v2 Gen4 and later standards) that define time-series signals equivalent to the TYPE I and TYPE II signals of the above-mentioned Test Flow.

[0028] The device under test W also incorporates an error detection unit W1 that detects the presence or absence of an error in the time-series signal input from the signal generation source 4 of the signal generating device 1.

[0029] 2, the signal generating device 1 has a device body 1a made of a rectangular housing, and an opening 1b formed in a side portion of the device body 1a. A plurality of slots (eight slots in the example of FIG. 2) 1c are provided in the opening 1b of the device body 1a.

[0030] The clock source 2, jitter modulation source 3, and signal generating source 4 are configured as modules that can be selectively attached to and detached from slots 1c of the device main body 1a. The example in Figure 2 shows a state in which modules are attached to all slots 1c of the device main body 1a. In practice, the device functions as a signal generating device 1 by selectively attaching the modules of the clock source 2, jitter modulation source 3, and signal generating source 4 (three modules) to slots 1c of the device main body 1a. The modules required to generate a signal with a frequency transition pattern defined by a desired standard are attached in appropriate combinations to slots 1c of the device main body 1a, and modules can be added, removed, or rearranged.

[0031] In addition, by installing an error detector module in slot 1c of device main body 1a, it can also function as an error rate measuring device that receives a signal that is returned when a test signal is input to the device under test W and measures the error rate.

[0032] The clock source 2 generates a reference clock (a clock with a reference frequency) under the control of a device control unit 7 connected via, for example, Ethernet (registered trademark), and is composed of an FPGA 2a and a clock generation unit 2b.

[0033] The FPGA 2a includes a module control unit 2aa and a control circuit 2ab. The module control unit 2aa also serves as an interface connecting the device control unit 7 and the control circuit 2ab, and in addition to outputting instructions (commands) from the device control unit 7 to the control circuit 2ab, it also executes some of the processing and control within the clock source 2.

[0034] The control circuit 2ab controls the clock generating unit 2b in response to an instruction (command) from the device control unit 7 so as to generate a clock of a reference frequency.

[0035] The clock generating unit 2b generates a clock of a reference frequency under the control of the control circuit 2ab based on an instruction (command) from the device control unit .

[0036] The jitter modulation source 3 generates a jitter clock by applying a desired modulation to the reference frequency clock generated by the clock source 2 under the control of the device control unit 7 connected, for example, via Ethernet (registered trademark), and is composed of an FPGA 3a and a jitter modulation unit 3b.

[0037] The FPGA 3a includes a module control unit 3aa and a control circuit 3ab. The module control unit 3aa also serves as an interface connecting the device control unit 7 and the control circuit 3ab, and in addition to outputting instructions (commands) from the device control unit 7 to the control circuit 3ab, it also executes some of the processing and control within the jitter modulation source 3.

[0038] The control circuit 3ab controls the jitter modulation unit 3b in response to an instruction (command) from the device control unit 7 so as to generate a jitter clock obtained by applying a desired modulation to the clock of the reference frequency generated by the clock source 2.

[0039] The jitter modulation unit 3b generates a jitter clock by applying a desired modulation to the clock of the reference frequency generated by the clock source 2 under the control of the control circuit 3ab based on an instruction (command) from the device control unit .

[0040] The signal generation source 4 generates a pattern signal (a pulse pattern signal with a desired repeating pattern) specified in the USB4 v2 Gen4 standard to be input to the device under test W under the control of a device control unit 7 connected via Ethernet (registered trademark), using a jitter clock generated by the jitter modulation source 3, and is composed of an FPGA 4a and a data multiplexing unit 4b.

[0041] The FPGA 4a includes a module control unit 4aa and a control circuit 4ab. The module control unit 4aa also serves as an interface connecting the device control unit 7 and the control circuit 4ab, and in addition to outputting instructions (commands) from the device control unit 7 to the control circuit 4ab, it also executes some of the processing and control within the signal generation source 4.

[0042] In response to an instruction (command) from the device control unit 7, the control circuit 4ab outputs a parallel signal that is the source of a pattern signal (serial signal) defined in the USB4 v2 Gen4 standard to the data multiplexing unit 4b.

[0043] The data multiplexing unit 4b multiplexes the parallel signals input from the control circuit 4ab in accordance with the timing of the jitter clock generated by the jitter modulation source 3 to generate a desired serial signal.

[0044] The operation unit 5 is composed of, for example, various keys, switches, buttons, and soft keys on the display screen of the display unit 6 that are equipped on the main body of the signal generating device 1, and the like, and the user operates and inputs various information necessary for the signal generating device 1 to generate the desired signal.

[0045] The display unit 6 is composed of a display device such as a liquid crystal display, an EL (electroluminescence) display, or a CRT, and displays setting item screens (including pattern setting screens in FIGS. 3 and 4 described below) related to the generation of a desired signal, as well as operation objects such as buttons, soft keys, pull-down menus, and input boxes for setting various conditions on the setting item screens, under the control of the device control unit 7. In addition to the above, the signal generating device 1 is also composed of control means including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive).

[0046] 3 and 4 show examples of the pattern setting screen 11 (11A, 11B) of the signal generator 4. To explain further, Fig. 3 shows the pattern setting screen 11A for Test Flow TYPE I of the CTS standard for USB4 v2 Gen4, and Fig. 4 shows the pattern setting screen 11B for Test Flow TYPE II of the CTS standard for USB4 v2 Gen4.

[0047] A pull-down menu 12 for setting the type of signal to be generated is displayed at the top of the pattern setting screens 11A and 11B in FIGS. 3 and 4. The pattern setting screens 11A and 11B in FIGS. 3 and 4 show a state in which "PAM3" is selected from the pull-down menu 12. Below this pull-down menu 12, tabs for multiple items related to signal generation are displayed, including "Output," "Emphasis," "Pattern," "Error Addition," "Misc1," and "Misc2." The pattern setting screens 11A and 11B in FIGS. 3 and 4 show a state in which the "Pattern" tab is selected to set the signal to be generated by the signal generator 4. Below this "Pattern" tab, an item for test patterns, "Test Pattern," is displayed. In this "Test Pattern," the standard of the signal to be generated is selected from a predetermined list using pull-down menus 13 and 14. The pattern setting screen 11 in Figures 3 and 4 shows the state in which "All List" is selected from the "Test Pattern" pull-down menu 13 and "USB4 Gen4 Rx Frequency Variation Training Sequence" is selected from the pull-down menu 14.

[0048] On the pattern setting screens 11A and 11B in FIGS. 3 and 4, a Transmit button 15, a Manual button 16, a Precoder switch button (default: OFF) 17, and a Polarity Inverse switch button (default: OFF) 18 are displayed below "Test Pattern."

[0049] The Transmit button 15 starts and stops the transmission of a pattern. When pressed in the default non-pressed state, it starts transmitting a pattern, and when pressed again in the pressed state, it stops transmitting the pattern that is currently being transmitted.

[0050] The Manual button 16 is used to transition the pattern currently being transmitted to the next Flow, and when pressed, the pattern currently being transmitted is transitioned to the next Flow.

[0051] The Precoder switching button 17 switches Precoder ON / OFF, and is initially set to OFF, and switches ON / OFF every time the Precoder switching button 17 is pressed.

[0052] The Polarity Inverse switch button 18 switches Polarity Inverse (polarity inversion) ON / OFF, and is initially set to OFF, and switches ON / OFF every time the Precoder switch button 18 is pressed.

[0053] A pull-down menu 19 for selecting which of the two Test Flow patterns (TYPE I or TYPE II) defined in the CTS standard to use is displayed below the Transmit button 15. Note that the pattern setting screen 11A in Fig. 3 shows the state where "TYPE I" has been selected from the pull-down menu 19, and the pattern setting screen 11B in Fig. 4 shows the state where "TYPE II" has been selected from the pull-down menu 19.

[0054] 3 and 4, a test sequence configuration 20 is displayed in the center of the pattern setting screens 11A and 11B. This test sequence configuration 20 displays Flow numbers (hereinafter referred to as Flow No.) in numerical order, with the horizontal axis representing time and the vertical axis representing Clock Freq. Variation (clock frequency deviation amount [PPM]) corresponding to Flow No.

[0055] 3 and 4, a tabular pattern setting list 21 corresponding to the test sequence configuration 20 is displayed at the bottom of the pattern setting screens 11A and 11B. The pattern setting list 21 consists of multiple items, namely, "Flow No." 21a, "Break" 21b, "Pattern" 21c, and "Transmission Time" 21d, and these multiple items are set for each flow.

[0056] "Flow No." 21a indicates the flow number of the entire sequence corresponding to the test sequence configuration 20, and is displayed in ascending order starting from #1. On the pattern setting screen 11A of FIG. 3, the flow numbers are displayed in the order of #1, #2, and #3, corresponding to the flow numbers Flow #1, Flow #2, and Flow #3 in the test sequence configuration 20. On the pattern setting screen 11B of FIG. 4, the flow numbers are displayed in the order of #1, #2, #3, and #4, corresponding to the flow numbers Flow #1, Flow #2, TS2clksw, and Flow #4 in the test sequence configuration 20.

[0057] "Break" 21b sets "Manual" or "Auto" as the condition for transitioning to the next Flow signal for the target Flow. When "Manual" is set for "Break", pressing the Manual button transitions to the next Flow. On the other hand, when "Auto" is set, transition to the next Flow occurs when the time set in "Transmission Time" has elapsed after the Flow starts.

[0058] "Pattern" 21c is set by selecting the transmission pattern from a pull-down menu 22 for each flow (22a, 22b, 22c on the pattern setting screen in FIG. 3, and 22a, 22b, 22c, 22d on the pattern setting screen in FIG. 4). On the pattern setting screen 11A in FIG. 3, the setting ranges for Flows #1 to #3 are PRBSn (n=7, 9, 10, 11, 13, 15, 20, 23, 31) and PRTSn (n=7, 19), and the initial value for Flow #1 is set to PRBS11, and the initial values ​​for Flows #2 and #3 are set to PRTS7. In the pattern setting screen 11B of Figure 4, the setting ranges for Flows #1, #2, and #4 are PRBSn (n = 7, 9, 10, 11, 13, 15, 20, 23, 31) and PRTSn (n = 7, 19), the setting range for Flow #3 is fixed to TS2clksw, the initial value of Flow #1 is set to PRBS11, the initial values ​​of Flows #2 and #4 are set to PRTS7, and the initial value of Flow #3 is set to TS2clksw.

[0059] "Transmission Time" 21d is set by inputting a value into input box 23 for each Flow (23a, 23b, 23c on the pattern setting screen of FIG. 3, and 23a, 23b, 23c, 23d on the pattern setting screen of FIG. 4) to indicate how long it takes from the start of transmission of the Flow signal to transition to the next Flow for a Flow for which "Break" is set to "Auto." On pattern setting screen 11A of FIG. 3, the setting range for Flows #1 and #2 is 10.0 to 20.0 μs in 0.1 μs steps, and the setting range for Flow #3 is 1 to 10,000 ms in 1 ms steps. The initial value for "Auto" for Flows #1 and #2 is set to 10.0 μs, and the initial value for "Auto" for Flow #3 is set to 2,000 ms. In the pattern setting screen 11B of FIG. 4, the setting range of Flow #1 to #3 is 10.0 to 20.0 μs in 0.1 μs steps, and the setting range of Flow #4 is 1 to 10,000 ms in 1 ms steps. The initial value of "Auto" for Flow #1 to #3 is set to 10.0 μs, and the initial value of "Auto" for Flow #4 is set to 2,000 ms.

[0060] 3 and 4, the flow including the point where the clock frequency deviation amount changes (Event Start in the figure) is highlighted so as to be distinguishable from other flows. In the test sequence configuration 20 of Fig. 3, Flow #3 indicated by diagonal lines is highlighted so as to be distinguishable, and in the test sequence configuration 20 of Fig. 4, TS2clksw indicated by diagonal lines is highlighted so as to be distinguishable.

[0061] In addition, in the pattern setting list 21 of Figures 3 and 4, in order to make it possible to see which Flow pattern is currently being sent, the background of the Flow item to which the pattern being sent belongs (the entire row of the relevant Flow: all items) is highlighted.

[0062] Furthermore, in the pattern setting screen 11 of Figures 3 and 4, the "Pattern" pull-down menu 22 (22a, 22b, 22c on the pattern setting screen 11A of Figure 3, and 22a, 22b, 22c, 22d on the pattern setting screen 11B of Figure 4) allows the user to set a pattern selected from a pseudo-random pattern that has been arbitrarily set and registered in advance, in addition to a PRBS or PRTS with a predetermined number of stages according to the standard.

[0063] The device control unit 7 controls the clock source 2, jitter modulation source 3, signal generating source 4, operation unit 5, and display unit 6. That is, the device control unit 7 controls the display unit 6 to display various setting screens including the setting screen for the signal generating source 4 shown in Fig. 3, and controls the clock source 2, jitter modulation source 3, and signal generating source 4 to generate a reference frequency clock based on an operation input from the operation unit 5, generate a jitter clock, and generate a desired signal (for example, a signal with a frequency transition pattern defined by a desired standard as shown in Fig. 4).

[0064] Next, an operation will be described in which the signal generating device 1 configured as above generates a signal for performing a Receiver Frequency variation test defined in the CTS of the USB4 v2 Gen4 standard.

[0065] First, the operation when the signal type defined in the Test Flow of the CTS standard is TYPE I will be described.

[0066] When generating a TYPE I signal, "PAM3" is selected from the pull-down menu 12 as the type of signal to be generated on the pattern setting screen 11A of FIG.

[0067] Next, in "Test Pattern" on the pattern setting screen 11A of FIG. 3, select "All List" from the pull-down menu 13, select "USB4 Gen4 Rx Frequency Variation Training Sequence" from the pull-down menu 14, and set the standard of the signal to be generated.

[0068] Next, on the pattern setting screen 11A of FIG. 3, "TYPE I" is selected from the pull-down menu 19 as the signal type and set.

[0069] Then, as necessary, the Precoder switch button 17 and the Polarity Inverse switch button 18 are pressed to switch from "OFF" to "ON."

[0070] Next, in the pattern setting list 21 on the pattern setting screen 11A in Fig. 3, set Break 21b of each Flow No. 21 to "Manual" or "Auto." Here, set Flow #1 and Flow #2 to "Manual," and set Flow #3 to "Auto."

[0071] Next, select and set the "Pattern" 21c for each "Flow No." 21 from the pull-down menu 22 (22a, 22b, 22c). Here, set Flow #1 to "PRBS11" and set Flow #2 and Flow #3 to "PRTS7."

[0072] Then, enter a value into the input box 23 (23a, 23b, 23c) of "Transmission Time" 21d for the "Flow No." for which "Break" 21b is set to "Auto." In this example, enter "2000" ms into the input box 23c of "Transmission Time" 21d for Flow #3 for which "Auto" is set.

[0073] This completes the settings. After that, when the Transmit button 15 is pressed, the device control unit 7 controls the clock source 2, jitter modulation source 3, and signal generation source 4 in accordance with the settings to transmit a TYREI signal defined in the Test Flow of the CTS standard. Specifically, when the Transmit button 15 is pressed, a PRBS11 signal is first transmitted in Flow #1. After that, when the Manual button 16 is pressed, a PRTS7 signal is transmitted in Flow #2. When the Manual button 16 is pressed again, a PRTS7 signal is transmitted in Flow #3, and the clock frequency deviation amount is automatically changed by Event Start within 2000 ms from the start of transmission of this PRTS7 signal.

[0074] Next, the operation when the signal type defined in the Test Flow of the CTS standard is TYRE II will be described.

[0075] When generating a TYPE II signal, "PAM3" is selected from the pull-down menu 12 as the type of signal to be generated on the pattern setting screen 11B of FIG.

[0076] Next, in "Test Pattern" on the pattern setting screen 11B of FIG. 4, select "All List" from the pull-down menu 13, select "USB4 Gen4 Rx Frequency Variation Training Sequence" from the pull-down menu 14, and set the standard of the signal to be generated.

[0077] Next, on the pattern setting screen 11B of FIG. 4, "TYPE II" is selected from the pull-down menu 19 as the signal type and set.

[0078] Then, as necessary, the Precoder switch button 17 and the Polarity Inverse switch button 18 are pressed to switch from "OFF" to "ON."

[0079] Next, in the pattern setting list 21 on the pattern setting screen 11B in Fig. 4, set Break 21b of each Flow No. 21 to "Manual" or "Auto." Here, set Flow #1, Flow #2, and Flow #4 to "Manual," and set Flow #3 to "Auto."

[0080] Next, select and set the "Pattern" 21c for each "Flow No." 21 from the pull-down menu 22 (22a, 22b, 22c, 22d). Here, Flow #1 is set to "PRBS11," Flow #2 and Flow #4 are set to "PRTS7," and Flow #3 is set to "TSclksw."

[0081] Then, enter a value into the input box 23 (23a, 23b, 23c, 23d) for "Transmission Time" 21d for the "Flow No." for which "Break" 21b is set to "Auto." In this example, enter "10.000" μs into the input box 23c for "Transmission Time" 21d for Flow #3 for which "Auto" is set.

[0082] This completes the setup. Then, when the Transmit button 15 is pressed, the device control unit 7 controls the clock source 2, jitter modulation source 3, and signal generation source 4 according to the settings to transmit a TYPE II signal defined by the Test Flow of the CTS standard. Specifically, when the Transmit button 15 is pressed, a PRBS11 signal is first transmitted in Flow #1. Then, when the Manual button 16 is pressed, a PRTS7 signal is transmitted in Flow #2. When the Manual button 16 is pressed again, a TS2clksw signal is transmitted in Flow #3, and the clock frequency deviation amount is automatically changed by Event Start within 10 μs from the start of transmission of the TS2clksw signal. Then, after 10 μs has elapsed, a PRTS7 signal is transmitted in Flow #4.

[0083] 5 shows an example of a flowchart of a signal generation method by the signal generating device 1. In this embodiment, to realize a sequence for a Receiver Frequency variation test (a test of the clock variation tolerance of a receiver), two patterns of time series signals of TYPE I or TYPE II of the Test Flow are generated according to the ST (steps) in FIG.

[0084] The order of some of the STs (steps) in FIG. 5 may be changed, and may be selectively performed as needed, and the order and selection are not limited to those shown in FIG.

[0085] First, as the test sequence configuration 20, the time series pattern signals of the Test Flow are displayed consecutively in the order of the Flow numbers, and the frequency deviation of the clock, with the horizontal axis being time, is displayed on the vertical axis corresponding to the Flow number (ST1 in Figure 5).

[0086] In addition, in the test sequence configuration 20, flows including points where the amount of clock frequency deviation changes (flows indicated by diagonal lines in FIGS. 3 and 4) are highlighted so as to be distinguishable from other flows (ST2 in FIG. 5).

[0087] Next, the type of pattern for each flow of the time-series pattern signal, the manual or automatic switching method for each flow, and the transmission time of the pattern for each flow of the automatic switching method are set in the tabular pattern setting list 21 using the operation unit 5 (ST3 in Figure 5).

[0088] The transmission time for each pattern of the automatic switching method for each flow can be increased or decreased as needed by the operation unit 5 within a predetermined range including the time defined by the standard (ST4 in FIG. 5).

[0089] Then, a clock of the reference frequency is generated by the clock source 2 (ST5 in FIG. 5).

[0090] Next, a jitter clock is generated by a jitter modulation source 3 by modulating the clock of the reference frequency generated by the clock source 2 (ST6 in FIG. 5).

[0091] Next, in order to perform a Receiver Frequency variation test, a time-series pattern signal of the Test Flow defined by a predetermined standard is generated by the signal generation source 4 at the timing of the jitter clock from the jitter modulation source 3 (ST7 in FIG. 5).

[0092] Then, in the pattern setting list 21, the background of the Flow item in the pattern setting list 21 to which the currently transmitted pattern belongs is highlighted (ST8 in FIG. 5).

[0093] As described above, according to this embodiment, it is possible to transmit a test sequence for performing the Receiver Frequency Variation test defined in the CTS of the USB4 v2 Gen4 standard with a transmission time and frequency deviation amount as defined in the standard.

[0094] It also enables users to visually grasp the configuration of the test sequence for performing a Receiver Frequency Variation test. This allows users to easily understand the test sequence configuration on the screen, preventing test results that are not caused by the DUT and eliminating the time-consuming effort of identifying the cause during debugging, thereby improving the development efficiency of the DUT.

[0095] Furthermore, the pattern transmission time can be increased or decreased arbitrarily within a specified range that includes the time specified by the standard, making it easy to test the tolerance (margin) of the DUT for transmission times that deviate from the standard for each flow.

[0096] While the best mode for the signal generating device and signal generating method according to the present invention has been described above, the present invention is not limited to the description and drawings of this mode. In other words, all other modes, embodiments, and operational techniques that can be realized by those skilled in the art based on this mode are naturally included in the scope of the present invention. [Explanation of symbols]

[0097] 1. Signal Generator 1a Device body 1b opening 1c slot 2 Clock Sources 2a FPGA 2aa Module control unit 2ab control circuit 2b Clock generation unit 3 Jitter Modulation Source 3a FPGA 3aa Module control unit 3ab control circuit 3b Jitter modulation section 4. Signal Source 4a FPGA 4aa Module control unit 4ab control circuit 4b Data multiplexing section 5 Control section 6 Display section 7 Device control section 11(11A,11B) Pattern setting screen 12,13,14 Drop-down menu 15 Transmit button 16 Manual button 17 Precoder switch button 18 Polarity Inverse switch button 19 Drop-down menu 20 Test sequence configuration 21 Pattern setting list 21a Flow No. 21b Break 21c Pattern 21d Transmission Time 22(22a,22b,22c,22d) Pull-down menu 23(23a,23b,23c,23d) Input box W Object to be measured W1 Error detection section

Claims

1. A clock source (2) that generates a clock of a reference frequency; a jitter modulation source (3) that generates a jitter clock by modulating a clock having a reference frequency generated by the clock source; a signal generating source (4) that generates a time series pattern signal of a Test Flow defined by a predetermined standard in order to perform a Receiver Frequency variation test, at the timing of the jitter clock; an operation unit (5) for setting, in a tabular pattern setting list (21), the type of pattern for each flow of the time-series pattern signal, a manual or automatic switching method for each flow, and a transmission time of the pattern for each flow in the automatic switching method; a signal generating device that transmits a time-series pattern signal of the Test Flow to a device under test in accordance with settings of the operation unit;

2. 2. The signal generator according to claim 1, wherein the test sequence configuration (20) is such that the time-series pattern signals of the Test Flows are displayed consecutively in order of Flow numbers, and the frequency deviation of the clock, with the horizontal axis representing time, is displayed on the vertical axis in correspondence with the Flow numbers.

3. The signal generating device according to claim 1, characterized in that the transmission time of the pattern for each flow in the automatic switching method can be increased or decreased arbitrarily by the operation unit (5) within a predetermined range including the time specified by the standard.

4. 3. The signal generating device according to claim 2, wherein a flow including a point where the frequency deviation amount of the clock changes in the configuration (20) of the test sequence is highlighted so as to be distinguishable from other flows.

5. 2. The signal generating device according to claim 1, wherein the background of the Flow item to which the currently transmitted pattern belongs is highlighted in the pattern setting list (21).

6. generating a clock of a reference frequency by a clock source (2); A step of generating a jitter clock by a jitter modulation source (3) by modulating a clock of a reference frequency generated by the clock source; generating a time series pattern signal of a Test Flow defined by a predetermined standard for performing a Receiver Frequency variation test using a signal generation source (4) at the timing of the jitter clock; a step of setting, in a tabular pattern setting list (21) by an operation unit (5), a pattern type for each flow of the time-series pattern signal, a manual or automatic switching method for each flow, and a pattern transmission time for each flow of the automatic switching method; transmitting a time-series pattern signal of the Test Flow to a device under test in accordance with settings of the operation unit.

7. 7. The signal generating method according to claim 6, further comprising the step of displaying, as a configuration (20) of the test sequence, the time series pattern signals of the Test Flows in order of their Flow numbers, and displaying, on the vertical axis, the frequency deviation of a clock whose horizontal axis represents time, in correspondence with the Flow numbers.

8. The signal generating method according to claim 6, further comprising a step of arbitrarily increasing or decreasing, by the operation unit (5), the transmission time of the pattern for each Flow for which the switching method is set to automatic, within a predetermined range including a time defined by a standard.

9. 8. The signal generation method according to claim 7, further comprising a step of highlighting a flow including a portion where the frequency deviation of the clock changes in the configuration (20) of the test sequence so as to be distinguishable from other flows.

10. The signal generating method according to claim 6, further comprising a step of highlighting the background of a Flow item in the pattern setting list (21) to which the currently transmitting pattern belongs.

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