Digital biasing and digital cell placement techniques for semiconductor packaging.

Abstract

Lithography methods and software for semiconductor packaging are provided. [Solution] The method includes receiving metrology data for a lithography system, the metrology data corresponding to pillar heights 316 and pillar critical dimensions 318 of a plurality of non-uniform pillars 306 arranged on a die 302, at least two pillars having different pillar heights and different pillar critical dimensions, the lithography system being operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars; updating the mask pattern according to the metrology data to generate a compensated mask pattern; and performing a lithography process by patterning a resist to form a plurality of vias, the vias being formed on the plurality of non-uniform pillars after developing the resist and including a via depth and a via critical dimension.

Description

[Background technology]

[0001] Technical Field

[0001] Embodiments of the present disclosure relate generally to digital lithography systems, and more particularly to systems, software applications, and digital lithography methods for semiconductor packaging.

[0002] 2. Description of Related Art

[0002] Electronic packaging and assembly are typically used to connect small-sized integrated circuits (ICs) to interconnection substrates (e.g., printed circuit boards (PCBs) or interposers). PCBs usually contain several passive components and ICs to construct microelectronic devices, while interposers are connection substrates that are incorporated into packaged chips and have multiple chiplet ICs on them. The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (such as transistors, diodes, resistors, and capacitors). In most cases, improvements in integration density have been driven by repeated reductions in minimum feature size, allowing an increasing number of components to be integrated within a given area. Increasing demand for miniaturization of electronic devices has necessitated techniques to package semiconductor dies in smaller and more innovative ways.

[0003] For the above reasons, there is a need for systems, software applications, and digital lithography methods for semiconductor packaging. Summary of the Invention

[0004]

[0004] Embodiments of the present disclosure relate generally to digital lithography systems, and more particularly to systems, software applications, and digital lithography methods for semiconductor packaging.

[0005] In one embodiment, a method is provided that includes receiving metrology data for a digital lithography system, the metrology data corresponding to pillar heights and pillar critical dimensions of a plurality of non-uniform pillars disposed on a die, at least two pillars having different pillar heights and different pillar critical dimensions, the digital lithography system including a controller is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars, updating the mask pattern according to the metrology data to generate a compensated mask pattern based on the different pillar heights and different pillar critical dimensions, and performing a digital lithography process to pattern resist according to the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of the plurality of non-uniform pillars after developing the resist, and including a via depth and a via critical dimension.

[0006] In another embodiment, a second method is provided, the second method including: performing a metrology scan to identify pillar heights and pillar critical dimensions of a plurality of non-uniform pillars disposed on a die, the metrology scan generating metrology data corresponding to the pillar heights and pillar critical dimensions, and generating a compensated mask pattern using the metrology data; performing a digital lithography process in accordance with the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of the plurality of non-uniform pillars and including a via depth and a via critical dimension; and performing a solder plating process, the solder plating process filling each via of the plurality of vias with a solder bump, each solder bump being secured to one of the non-uniform pillars of the plurality of non-uniform pillars.

[0007] Another embodiment is a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to perform a method. The method executed by the processor of the non-transitory computer-readable medium includes receiving metrology data for a digital lithography system, the metrology data corresponding to pillar heights and pillar critical dimensions of a plurality of non-uniform pillars disposed on a die, at least two pillars having different pillar heights and different pillar critical dimensions, the digital lithography system including a controller is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars, updating the mask pattern according to the metrology data to generate a compensated mask pattern based on the different pillar heights and different pillar critical dimensions, and performing a digital lithography process to pattern resist according to the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of the plurality of non-uniform pillars after developing the resist, and including a via depth and a via critical dimension.

[0008]

[0008] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure may also admit of other equally effective embodiments, and therefore, the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a digital lithography system according to one or more embodiments described herein. [Figure 2]

[0010] FIG. 1 is a perspective view of a digital lithography device according to one or more embodiments described herein. [Figure 3A]

[0011] 1 is a schematic cross-sectional view of a packaging substrate according to one or more embodiments described herein. [Figure 3B]

[0012] FIG. 1 is a schematic top view of a packaging substrate according to one or more embodiments described herein. [Figure 4]

[0013] FIG. 1 is a flow diagram of a digital lithography method according to one or more embodiments described herein. [Figures 5A-5E]

[0014] 1A-1D are schematic cross-sectional views of a die during steps of a digital lithography method according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0015] For ease of understanding, where possible, the same reference numerals have been used to designate identical elements that are common to multiple figures. It is envisioned that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0011]

[0016] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to digital lithography systems, and more particularly to systems, software applications, and digital lithography methods for semiconductor packaging.

[0012]

[0017] Maintaining pillar process uniformity is important in the advanced packaging technology field. Failure to maintain uniformity can result in improper connection between the non-uniform pillar solder bumps and the circuit board, resulting in reduced performance and / or reliability. To maintain process uniformity, digital masks are updated to match desired patterns at a local level. In the disclosed method, a compensated mask pattern is patterned on the resist, allowing for controlled solder plating volume to compensate for pillar non-uniformity. Traditional upstream or downstream optimization methods cannot compensate for non-uniformity when the non-uniformity is random and localized. Therefore, a digital solution for maintaining pillar uniformity through planarization is needed in the advanced packaging technology field.

[0013]

[0018] 1 is a schematic diagram of a digital lithography system 100. As shown, the digital lithography system 100 includes, but is not limited to, a metrology device 104, a digital lithography device 108, a controller 110, and multiple communication links 101. The digital lithography device 108 may be a maskless digital lithography device. The digital lithography system 100 may further include a transport system 103. The digital lithography device 108 and the metrology device 104 may be connected by the transport system 103. The transport system is operable to transport substrates between the digital lithography device 108 and the metrology device 104.

[0014]

[0019] Each of the devices of the digital lithography system (metrology device 104 and digital lithography device 108) is operatively connected to a controller 110 via a communication link 101. The digital lithography system 100 may be located in the same area or production facility, or each of the devices of the digital lithography system may be located in different areas.

[0015]

[0020] Additionally, each of the devices in the multiple digital lithography system is indexed in a digitally connected manner. Each of the metrology device 104, the digital lithography device 108, and the controller 110 includes an on-board processor and memory configured to store instructions corresponding to all portions of the digital lithography method 400 described below. The communication link 101 may include at least one of a wired connection, a wireless connection, a satellite connection, etc. The communication link 101 facilitates sending and receiving files for storing data according to embodiments described later herein. Transmission of data over the communication link 101 may include temporarily or permanently storing the files or data in a cloud before transmitting or copying them to a device in the digital lithography environment.

[0016]

[0021] The controller 110 includes a central processing unit (CPU) 112, support circuits 114, and memory 116. The CPU 112 may be any form of computer processor that may be used in an industrial setting to control devices in a digital lithography system. The memory 116 is coupled to the CPU 112. The memory 116 may be one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The support circuits 114 are coupled to the CPU 112 to support the processor in a conventional manner. Such circuits include cache, power supplies, clock circuits, input / output circuits, subsystems, etc. The controller 110 may include the CPU 112 coupled to the memory 116 and input / output (I / O) devices included in the support circuits 114. The controller 110 is operable to send and transmit the design file to the digital lithography device 108 via the communication link 101 .

[0017]

[0022] The memory 116 may include one or more software applications (e.g., control software programs). The memory 116 may also include stored media data used by the CPU 112 to execute the digital lithography method 400 described herein. The CPU 112 may be a hardware unit or combination of hardware units capable of executing software applications and processing data. In some configurations, the CPU 112 includes a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and / or a combination of such units. The CPU 112 is generally configured to execute one or more software applications and process stored media data, each of which may be included in the memory 116. The controller 110 controls the transfer of data and files between various devices in the digital lithography system. The memory 116 is configured to store instructions corresponding to all steps of the digital lithography method 400 according to embodiments described herein.

[0018]

[0023] The metrology device 104 may include software and hardware for measuring a pillar height 316 and a pillar critical dimension 318. The pillar critical dimension 318 is the width or diameter of the non-uniform pillar 306. The metrology device 104 is operable to convert the pillar height 316 and the pillar critical dimension 318 into a metrology data format and transmit the metrology data to the controller 110. The metrology data generated by the metrology device 104 may be sent to the controller 110 via the communication link 101. The controller 110 may use the metrology data generated via the metrology device 104 to update a mask pattern and generate a compensated mask pattern, as described below in digital lithography method 400. The digital lithography device 108 patterns a resist 322 (e.g., performs a digital lithography process) according to the compensated mask pattern.

[0019]

[0024] 2 is a perspective view of a digital lithography device 108 (e.g., digital lithography system 100) that can benefit from embodiments described herein. The lithography device 108 includes a stage 214 and a processing unit 204. The stage 214 is supported by a pair of tracks 216. A packaging substrate 220 is supported by the stage 214. The stage 214 is operable to move along the pair of tracks 216. An encoder 218 is coupled to the stage 214 to provide position information of the stage 214 to the controller 110.

[0020]

[0025] The controller 110 is generally designed to facilitate control and automation of the processing techniques described herein. The controller 110 may be coupled to or in communication with the processing unit 204, the stage 214, and the encoder 218. The processing unit 204 and the encoder 218 may provide the controller 110 with information regarding substrate processing and substrate alignment. For example, the processing unit 204 may provide the controller 110 with information that substrate processing is complete. The controller 110 facilitates control and validation of the digital lithography process based on a design file. The design file or computer instructions (which may be referred to as an imaging design file) readable by the controller 110 determine which tasks should be performed on the substrate. The design file includes mask pattern data. The mask pattern data includes a mask pattern and code for monitoring and controlling processing time and substrate position. The mask pattern corresponds to a pattern to be written using electromagnetic radiation. As described in the digital lithography method 400, the controller 110 uses the metrology data to update the mask pattern to generate a compensated mask pattern.

[0021]

[0026] The packaging substrate 220 comprises any suitable material (such as glass). In other embodiments, which may be combined with other embodiments described herein, the packaging substrate 220 is made of other materials that can be used as part of a flat panel display. The packaging substrate 220 has resist 322 disposed on and between the non-uniform pillars 306 of at least one die (e.g., the first die 302). The patterned resist 322 is sensitive to electromagnetic radiation (e.g., UV or deep UV) "light." Positive resist includes portions of the resist that are each soluble to a resist developer upon exposure to electromagnetic radiation. The resist developer is applied to the resist 322 after a pattern is written into the photoresist using radiation. The resist is developed after exposure to electromagnetic radiation, leaving patterned resist 324 on the non-uniform pillars 306. The patterned resist 324 includes vias 330 disposed on each of the non-uniform pillars 306. The patterned resist 324 is solder plated. Solder 323 from the solder plating fills the vias 330 patterned in the patterned resist 324. The patterned resist 324 is then removed, partially forming a packaging circuit. In certain embodiments, additional processing may occur, such as heating the solder bumps 314 disposed on each non-uniform pillar of the multiple non-uniform pillars 306, before securing the multiple non-uniform pillars 306 disposed on the die (e.g., the first die 302) to the circuit.

[0022]

[0027] The processing unit 204 is supported by supports 208 so that the processing unit 204 straddles the pair of tracks 216. The supports 208 provide an opening 212 for the pair of tracks 216 and the stage 214 to pass underneath the processing unit 204. The processing unit 204 is a pattern generator configured to receive mask pattern data from the interface and expose a resist using one or more image projection systems 206 (operable to project a writing beam of electromagnetic radiation onto a packaging substrate 220) in a digital lithography process. The pattern generated by the processing unit 204 is projected by the image projection systems 206, exposing the resist of the packaging substrate 220 to the mask pattern written into the resist. In one embodiment, which can be combined with other embodiments described herein, each image projection system 206 includes a spatial light modulator for modulating incident light to create a desired image. Each spatial light modulator includes a plurality of electrically addressable elements that can be individually controlled. Each electrically addressable element can be in an "on" position or an "off" position based on mask pattern data and corrections provided by a positional custom model created through the digital lithography method 400 described herein. When light reaches the spatial light modulator, the electrically addressable elements in the "on" position project multiple writing beams onto a projection lens (not shown). The projection lens then projects the writing beams onto the packaging substrate 220. Electrically addressable elements include, but are not limited to, digital micromirrors, liquid crystal displays (LCDs), liquid crystal on silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, microshutters, microLEDs, VCSELs, or any solid-state electromagnetic radiation emitter.

[0023]

[0028] FIG. 3A is a schematic cross-sectional view of a packaging substrate 300 according to one or more embodiments described herein. FIG. 3B is a schematic top view of the packaging substrate 300 according to one or more embodiments described herein. A first die 302 and a second die 304 are disposed on the packaging substrate 300. In other embodiments, additional dies may be disposed on the packaging substrate 300. In further embodiments, a single die (e.g., the first die 302) is disposed on the packaging substrate 300. A plurality of non-uniform pillars 306 are disposed on the first die 302 and the second die 304. While FIG. 3A shows five non-uniform pillars 306 disposed on each die (e.g., the first die 302 and the second die 304), it should be understood that any number of non-uniform pillars 306 may be disposed on each die (e.g., the first die 302 and the second die 304). Each non-uniform pillar of the plurality of non-uniform pillars 306 can include any pillar height 316 or pillar critical dimension 318. The pillar height 316 is at least 5 μm. For example, as shown in FIG. 3A, the non-uniform pillars 306 can include different pillar heights 316. As a further example, as shown in FIG. 3B, the non-uniform pillars 306 can be rectangular or rounded and can include different widths or diameters. Additionally, as shown in FIGS. 3A and 3B, the non-uniformity can be random and localized. The plurality of non-uniform pillars 306 can include a metal material. For example, the non-uniform pillars 306 can include copper or nickel. Furthermore, the non-uniform pillars 306 can include multiple layers of metal. For example, the non-uniform pillars 306 can include a layer of copper and a layer of nickel. A solder bump 314 is disposed on each non-uniform pillar of the plurality of non-uniform pillars 306. The solder bumps 314 and certain non-uniform pillars of the plurality of non-uniform pillars 306 form structures 312 (e.g., each structure 312 includes a solder bump 314 and certain non-uniform pillars of the plurality of non-uniform pillars 306). Each solder bump 314 on each structure 312 can be of a different volume. The different volumes allow a uniform height 326 to be uniform across all structures 312 disposed on a die (e.g., first die 302).3A, each structure 312 disposed on a die (e.g., first die 302 or second die 304) includes the same uniform height 326. The uniform height 326 can be any height. For example, the uniform height 326 is at least 10 μm.

[0024]

[0029] 4 is a flow diagram of a digital lithography method 400 for processing a structure 312 according to one or more embodiments described herein. Figures 5A-5E are schematic cross-sectional views of non-uniform pillars disposed on a die (e.g., first die 302) during processing steps of the digital lithography method 400 according to one or more embodiments described herein.

[0025]

[0030] In step 410, the metrology device 104 performs a metrology scan to determine a pillar height 316 and a pillar critical dimension 318 of each non-uniform pillar of the plurality of non-uniform pillars 306. As shown in FIG. 5A , the plurality of non-uniform pillars 306 are disposed on the first die 302. The metrology device 104 is operable to convert the pillar heights 316 and the pillar critical dimensions 318 into a metrology data format. The metrology data corresponds to the pillar heights 316 and the pillar critical dimensions 318. In step 420, the metrology data collected in step 410 is provided to the digital lithography system 100. The metrology data is transmitted to the controller 110 via the communication link 101 shown in FIG. 1 . The controller 110 is operable to update a mask pattern based on the metrology data generated via the metrology device 104 in step 410. The mask pattern corresponds to a pattern of a structure (e.g., a pattern for forming the structure 312). In step 430, the controller 110 updates the mask pattern using the metrology data captured by the metrology device 104. The mask pattern is a customized pattern determined by the pillar heights 316 and pillar critical dimensions 318. The metrology data generates a compensated mask pattern based on the various pillar heights 316 and various pillar critical dimensions 318. In step 440, as shown in FIG. 5B, resist 322 is deposited on top of and between the non-uniform pillars 306. The resist 322 is at least as high as necessary to achieve the structure 312 with a uniform height 326.

[0026]

[0031] In step 450, as shown in FIG. 5C , resist 322 is patterned with one or more patterns using digital lithography device 108. The metrology data collected in step 410 includes instructions for digital lithography device 108 to pattern resist 322 according to the compensated mask pattern generated in steps 420 and 430. The compensated mask pattern includes several vias 330. Vias 330 are openings patterned in resist 322. Each via 330 is located over a non-uniform pillar of the plurality of non-uniform pillars 306. Each via 330 can be a different size based on the metrology data collected in step 410. Each via 330 is configured to hold a volume of solder 323 from solder plating such that the solder 323 contacts a non-uniform pillar of the plurality of non-uniform pillars 306 (e.g., via 330 includes a via depth 332 extending from the surface of resist 322 to the top of the plurality of non-uniform pillars 306 and a via critical dimension 334). The via depth 332 varies based on the pillar height 316 and the pillar critical dimension 318. As shown in FIG. 5C , there are five non-uniform pillars 306 and five vias 330. Each via 330 is a different size corresponding to the different pillar heights 316 and pillar critical dimensions 318. For example, a non-uniform pillar 306 with a high pillar height 316 may correspond to a via 330 that contains a smaller volume compared to a non-uniform pillar 306 with a low pillar height 316.

[0027]

[0032] The resist 322 is patterned with one or more patterns using the digital lithography device 108 and then developed in a development process. The patterns are written into the resist 322 using electromagnetic radiation from the digital lithography device 108. A resist developer is applied to the resist 322. After the resist 322 is developed, a patterned resist 324 remains on the first die 302. The patterned resist 324 includes the vias 330 described above.

[0028]

[0033] In step 460, a solder plating process is performed, as shown in FIG. 5D. The solder plating process includes disposing solder 323 within each via 330. Solder plating may include electroplating. The solder 323 disposed within each via includes a volume determined by the dimensions of the via 330. The solder 323 disposed within each via 330 forms a solder bump 314. The customized volume of solder 323 to form each solder bump 314 allows a reliable connection to be formed between the non-uniform pillar 306 and a circuit (not shown).

[0029]

[0034] In step 470, the patterned resist 324 is removed, as shown in FIG. 5E. In step 480, a reflow process is performed to heat the solder bump 314 on each of the non-uniform pillars 306. When heated, the solder bump 314 forms a rounded shape on each non-uniform pillar of the plurality of non-uniform pillars 306. The reflow process allows for planarization of the non-uniform pillars 306. After the reflow process, each structure 312 includes a uniform height 326. The uniform height 326 can be any height. For example, the uniform height 326 is at least 10 μm, and each structure 312 includes this uniform height 326.

[0030]

[0035] After the digital lithography method 400 is completed, further processing may occur. For example, the structure 312 may be coupled to a circuit. Each solder bump 314 provides a means for a reliable connection between the plurality of non-uniform pillars 306 and the circuit. Advantages of the present disclosure include a package assembly having a reliable connection between the plurality of non-uniform pillars 306 disposed on a die (e.g., the first die 302) and the circuit, the pillars having different pillar heights 316 and pillar critical dimensions 318. The devices and methods of forming the devices described herein enable the production of package assemblies with improved performance and quality, while reducing manufacturing time and costs.

[0031]

[0036] While the above description is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the following claims. [Explanation of symbols]

[0032] TIFF2026035534000002.tif255170

Claims

1. 1. A method comprising: receiving metrology data corresponding to pillar height and pillar critical dimension, wherein a digital lithography system including a controller is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars; updating the mask pattern according to the metrology data to generate a compensated mask pattern based on the pillar height and the pillar critical dimension; performing a digital lithography process on a resist according to the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of a plurality of non-uniform pillars after developing the resist, the vias including a via depth and a via critical dimension; A method comprising:

2. 10. The method of claim 1, further comprising: performing a solder plating process, wherein the solder plating process fills each via of the plurality of vias with a solder bump, and each solder bump is secured to one of the plurality of non-uniform pillars.

3. The method of claim 1 further comprising removing the resist.

4. The method of claim 1 , further comprising performing a reflow process, wherein the reflow process forms solder bumps.

5. The method of claim 1 , wherein the metrology data is collected by a metrology device, the metrology device including software for measuring the pillar heights and the pillar critical dimensions of the plurality of non-uniform pillars.

6. the digital lithography system comprises: A measuring device; Digital lithography tools; the controller; a plurality of communication links; The method of claim 1 , comprising:

7. The resist is patterned using a development process, the development process comprising: writing a pattern into the resist; patterning the resist using electromagnetic radiation provided by a digital lithography device; applying a resist developer to the resist such that the resist is soluble in the resist developer; The method of claim 1 , comprising:

8. The method of claim 1 , wherein the via depth and the via critical dimension correspond to the pillar height and the pillar critical dimension.

9. The method of claim 2 wherein the solder plating is electroplating.

10. 5. The method of claim 4, wherein the reflow process includes heating the solder bumps, and heating the solder bumps causes the solder bumps to become rounded.

11. The method of claim 1 , wherein each solder bump and each non-uniform pillar forms a structure, each structure comprising a uniform height.

12. 1. A method comprising: performing a metrology scan to identify a pillar height and a pillar critical dimension for each of a plurality of non-uniform pillars disposed on a die, the metrology scan generating metrology data corresponding to the pillar heights and the pillar critical dimensions of the plurality of non-uniform pillars, the metrology data generating a compensated mask pattern; performing a digital lithography process according to the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of the plurality of non-uniform pillars and including a via depth and a via critical dimension; performing a solder plating process, wherein the solder plating process fills each via of the plurality of vias with a solder bump, each solder bump being secured to one non-uniform pillar of the plurality of non-uniform pillars; A method comprising:

13. depositing resist over and around the plurality of non-uniform pillars; and patterning the resist according to the compensated mask pattern using a development process, the development process comprising: writing a pattern into the resist; patterning the resist using electromagnetic radiation provided by a digital lithography device; and applying a resist developer to the resist such that the resist is soluble in the resist developer.

14. The method of claim 13 further comprising removing the resist.

15. The method of claim 12 , further comprising performing a reflow process, wherein the reflow process forms the solder bumps.

16. The method of claim 12 , wherein each solder bump and each non-uniform pillar forms a structure, each structure comprising a uniform height.

17. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to: receiving metrology data corresponding to pillar height and pillar critical dimensions, wherein a digital lithography system including a controller is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars; updating the mask pattern according to the metrology data to generate a compensated mask pattern based on the pillar height and the pillar critical dimension; performing a digital lithography process to pattern resist according to the compensated mask pattern to form a plurality of vias, the vias being formed on each non-uniform pillar of the plurality of non-uniform pillars after developing the resist, and including a via depth and a via critical dimension; Non-transitory computer-readable medium.

18. The non-transitory computer-readable medium of claim 17 , further comprising removing the resist.

19. 20. The non-transitory computer-readable medium of claim 17, further comprising: performing a solder plating process, wherein the solder plating process fills each via of the plurality of vias with a solder bump, and each solder bump is secured to one non-uniform pillar of the plurality of non-uniform pillars.

20. 20. The non-transitory computer-readable medium of claim 17, wherein each solder bump and each non-uniform pillar form a structure, each structure including a uniform pillar height.

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