Wiring board and manufacturing method thereof

Abstract

There is a demand for the development of a technology that can make via diameters smaller than those achieved by conventional wiring board manufacturing methods. [Solution] This embodiment provides a method for manufacturing a wiring board, the method including: laminating a first insulating layer containing resin and inorganic particles on a first conductive layer; irradiating the first insulating layer with laser light to drill vias having diameters of 5 μm or more and 15 μm or less in an upper surface of the first insulating layer; desmearing the inside of the vias; and forming seed layers on the upper surface of the first insulating layer, wall surfaces of the vias, and bottom surfaces of the vias, wherein the desmearing is performed by irradiating with an ion beam.

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board having vias and a manufacturing method thereof. [Background technology]

[0002] A known conventional method for manufacturing a wiring board is to laser-machine a via in an insulating layer, remove the resin residue generated during the process from the bottom surface of the via by dry desmearing, and then form a via conductor (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-10639 A (paragraph

[0033] , Figure 5) Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for the development of a technology that can reduce the via diameter compared to the conventional manufacturing methods described above. [Means for solving the problem]

[0005] A first aspect of the present invention of the present disclosure relates to a method for manufacturing a wiring board, the method including: laminating a first insulating layer containing a resin and inorganic particles on a first conductive layer; irradiating the first insulating layer with laser light to form vias having diameters of 5 μm or more and 15 μm or less in an upper surface of the first insulating layer; desmearing the insides of the vias; and forming seed layers on the upper surface of the first insulating layer, wall surfaces of the vias, and bottom surfaces of the vias, wherein the desmearing is performed by ion beam irradiation.

[0006] A second aspect of the presently disclosed invention is a wiring board comprising a first conductive layer, a first insulating layer laminated thereon and containing resin and inorganic particles, a second conductive layer laminated thereon, a via penetrating the first insulating layer, and a via conductor filled in the via and connecting the first conductive layer and the second conductive layer, wherein the diameter of the via on the upper surface of the first insulating layer is 5 μm or more and 15 μm or less, and the surface of the resin and the cut surface of the inorganic particles are exposed on the upper surface of the first insulating layer covered with the second conductive layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1A is a cross-sectional view of a wiring board, and FIG. 1B is an enlarged cross-sectional view of the top surface of an insulating layer. [Figure 2] 2A to 2D are cross-sectional views showing the manufacturing process of the wiring board. [Figure 3] 3A to 3D are cross-sectional views showing the manufacturing process of the wiring board. [Figure 4] 4A to 4C are cross-sectional views showing the manufacturing process of the wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0008] A wiring board 10 according to an embodiment of the present disclosure will be described with reference to Figures 1 to 4. As shown in Figure 1, the wiring board 10 of this embodiment includes, for example, a core substrate 11 as an insulating layer, a plurality of conductive layers 20 and a plurality of insulating layers 30 alternately stacked on both the front and back surfaces of the core substrate 11, and a solder resist layer (not shown) as the outermost layer. Note that Figure 1A shows only a portion of the wiring board 10 on the front side of the core substrate 11.

[0009] The core substrate 11 is provided with a plurality of through-hole conductors 12 that connect the conductive layers 20 on both the front and back surfaces of the core substrate 11. The plurality of through-hole conductors 12 are formed on the inner surfaces of a plurality of through-holes 12H that penetrate the core substrate 11, and the interiors are filled with resin 12J. The plurality of through-hole conductors 12 may have a shape that is constricted midway in the axial direction.

[0010] An electric circuit having a predetermined pattern including a plurality of pads 23 and a plurality of wiring portions 24 is formed on the plurality of conductive layers 20. The plurality of wiring portions 24 has a width of, for example, 3 μm or less, and the gap between the wiring portions 24 is 3 μm or less. The plurality of conductive layers 20 has a structure in which a seed layer 20A is laminated on a copper foil (not shown), or an electroplated film 20B is laminated on the seed layer 20A. A protective film 20C is laminated on all or part of the plurality of conductive layers 20 so as to cover the upper and side surfaces of the conductive layer 20.

[0011] A plurality of via conductors 25 that connect adjacent conductive layers 20 in the stacking direction are formed in the plurality of insulating layers 30. The plurality of via conductors 25 are formed by filling a plurality of vias 25H that penetrate each insulating layer 30 with plating, and the diameter of each via 25H on the upper surface of the insulating layer 30 (the diameter of the top of each via 25H) is 5 μm or more and 15 μm or less (preferably 8 μm or more and 10 μm or less).

[0012] In this embodiment, the upper surface 30M of each insulating layer 30 has fewer irregularities than the inner surface 25M of the via 25H. Specifically, the insulating layer 30 is made of, for example, a thermosetting resin 30J (hereinafter simply referred to as "resin 30J") containing spherical inorganic particles 30R. The inner surface 25M of the via 25H has, for example, a plurality of protrusions (not shown) formed by the plurality of inorganic particles 30R. In contrast, as shown in FIG. 1B, the upper surface 30M of the insulating layer 30 is cut so that the plurality of inorganic particles 30R located near the upper surface 30M are substantially flush with the surface of the resin 30J, and does not have the plurality of protrusions. Furthermore, while the inner surface 25M of the via 25H has irregularities due to laser processing of the resin 30J itself, the upper surface 30M of the insulating layer 30 has a smooth surface of the resin 30J itself. More specifically, the surface roughness (Ra) of the inner surface 25M of the via 25H is, for example, 0.15 to 0.6 μm, and the surface roughness (Ra) of the upper surface 30M of the insulating layer 30 is, for example, 0.1 μm or less. Note that the insulating layer 30 uses, for example, silica particles as the inorganic particles 30R and an epoxy resin as the thermosetting resin.

[0013] Next, a method for manufacturing the wiring board 10 of this embodiment will be described. (1) A copper-clad laminate (not shown) is prepared, in which copper foil is laminated on both the front and back surfaces of a core substrate 11. Then, after a plurality of through-holes 12H are formed in the copper-clad laminate and subjected to a desmearing process, conductive layers 20 are laminated on both the front and back surfaces of the core substrate 11 by, for example, a known subtractive method, and a plurality of through-hole conductors 12 are formed (see FIG. 2A).

[0014] (2) Next, as shown in Fig. 2B, an insulating resin film 30F, which will become the insulating layer 30, is superimposed on the conductive layer 20. Here, a support film (not shown) is attached to the bottom surface of the insulating resin film 30F, and a cover film 31 is attached to the top surface. Then, the support film is peeled off, and the insulating resin film 30F is superimposed on the conductive layer 20 with the insulating resin film 30F side facing downward.

[0015] (3) As shown in Fig. 2C, the insulating resin film 30F is pressed with the cover film 31 attached, thereby obtaining the insulating layer 30. The cover film 31 is made of, for example, a PET film, a resist, or a metal foil (copper foil, aluminum foil, etc.).

[0016] (4) As shown in FIG. 2D, the cover film 31 is peeled off.

[0017] (5) As shown in Fig. 3A, in a state where the upper surface 30M of the insulating layer 30 is not covered with the cover film 31, a plurality of vias 25H are formed, for example, by laser processing. At this time, an ultraviolet laser is used as the laser light. The output of the ultraviolet laser is set to be smaller than that when the plurality of vias 25H is formed in a state where the upper surface 30M of the insulating layer 30 is covered with the cover film 31. Then, a plurality of vias 25H having a diameter of 5 µm or more and 15 µm or less on the upper surface of the insulating layer 30 is obtained.

[0018] (6) Next, as shown in FIG. 3B, an ion beam is irradiated onto the bottoms of the vias 25H and the upper surface 30M of the insulating layer 30. The ion beam in this embodiment is, for example, an argon ion beam. Note that, although an example in which argon is used as the ion beam has been described, the ion beam is not limited to this, and may be, for example, helium.

[0019] The ion beam irradiation in this process removes the adhesive (not shown) that temporarily adhered the cover film 31 to the upper surface 30M of the insulating layer 30, and also removes resin residue from the bottoms of the vias 25H. Furthermore, the inorganic particles 30R exposed on or near the upper surface 30M of the insulating layer 30 are half-etched together with the resin 30J, resulting in a smooth surface in which the cut surfaces 30T of the inorganic particles 30R are exposed on the upper surface 30M of the insulating layer 30 (see FIG. 1B).

[0020] (7) As shown in FIG. 3C, a seed layer 20A is deposited by sputtering on the upper surface 30M of the insulating layer 30 and on the bottom and inner surfaces 25M of the vias 25H.

[0021] (8) As shown in FIG. 3D, a plating resist 50 is laminated on the seed layer 20A in a predetermined pattern.

[0022] (9) As shown in FIG. 4A, an electrolytic plating process is performed, filling the vias 25H with electrolytic plating, and forming an electrolytic plated film 20B on the portion of the seed layer 20A exposed from the plating resist 50.

[0023] (10) After the plating resist 50 is peeled off, the seed layer 20A below the plating resist 50 is removed. At this time, since the upper surface 30M of the insulating layer 30 is a smooth surface, the time required for the etching process to remove the seed layer 20A can be relatively short.

[0024] (11) Next, the conductive layer 20 is immersed in a surface treatment agent and washed, thereby covering the conductive layer 20 with a protective film 20C as shown in FIG. 4C.

[0025] (12) The above-mentioned steps (2) to (11) are repeated until the outermost conductive layer 20 is laminated, and then a solder resist layer (not shown) is laminated. In this way, the wiring board 10 is completed.

[0026] Next, the effects of the wiring board 10 of this embodiment will be described. In the manufacturing method of the wiring board 10 of this embodiment, the desmearing of the vias 25H is performed by irradiating the bottom surfaces of the vias 25H with an ion beam. This prevents roughening of the upper surface 30M of the insulating layer 30, eliminating the need for a cover film 31 during the desmearing. Furthermore, the drilling step of the vias 25H is performed without the upper surface 30M of the insulating layer 30 being covered with the cover film 31. This allows the laser output to be reduced to reduce the diameter of the vias 25H. This allows the diameter of the vias 25H to be small, not less than 5 μm and not more than 15 μm, thereby enabling the wiring board 10 to be manufactured with a small diameter, not less than 5 μm, and thus enabling a high level of integration and a miniaturized wiring board 10.

[0027] Furthermore, insulating resin film 30F, which is the base of insulating layer 30, often has cover film 31 attached to its upper surface in advance. Even if cover film 31 is peeled off, adhesive for attaching cover film 31 may remain on the upper surface of insulating resin film 30F. In contrast, according to the manufacturing method for wiring board 10 of the present embodiment, an ion beam is irradiated onto upper surface 30M of insulating layer 30 in the desmearing process to remove the adhesive, so that it is possible to deal with the case where adhesive remains on upper surface 30M of insulating layer 30. Furthermore, the same ion beam can be used to remove the adhesive and desmear the bottom surfaces of vias 25H, thereby making effective use of the ion beam.

[0028] Furthermore, in this embodiment, the inorganic particles 30R near the upper surface 30M of the insulating layer 30 are cut by the irradiation of the ion beam, and the cut surfaces 30T are exposed on the upper surface 30M of the insulating layer 30. That is, the desmearing process using the ion beam reduces the roughness of the upper surface 30M of the insulating layer 30, making it possible to make the surface smooth. This shortens the time required for the etching process of the conductive layer 20 laminated on the upper surface 30M of the insulating layer 30, and enables the multiple wiring portions 24 included in the conductive layer 20 to be finer.

[0029] [Other embodiments] In the above embodiment, the seed layer 20A is formed by sputtering, but the seed layer may also be formed by electroless plating.

[0030] In the above embodiment, the plurality of conductive layers 20 are covered with the protective film 20C, but they may not be covered.

[0031] In the example of the wiring board 10 shown in FIG. 1, there are three conductive layers 20 and two insulating layers 30, but the number of conductive layers 20 and insulating layers 30 may be any number as long as there are at least two conductive layers 20 and one insulating layer 30.

[0032] Furthermore, although a core substrate is formed by the core substrate 11 and the conductive layers 20 on its front and back, the core substrate may not be provided and may instead have a coreless structure in which multiple conductive layers 20 and multiple insulating layers 30 are stacked.

[0033] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone. [Explanation of symbols]

[0034] 10. Wiring board 20 Conductive layer 20A seed layer 25 via conductor 25H via 30 insulating layer 30M top surface 30R inorganic particles 30T cutting surface 31 Cover film

Claims

1. a first insulating layer containing a resin and inorganic particles is laminated on the first conductive layer; a via having a diameter of 5 μm or more and 15 μm or less is drilled on the upper surface of the first insulating layer by irradiating the first insulating layer with laser light; the inside of the via is desmeared; forming a seed layer on an upper surface of the first insulating layer, a wall surface of the via, and a bottom surface of the via, The desmearing process is performed by irradiating an ion beam.

2. 2. The method for manufacturing a wiring board according to claim 1, In the desmearing process, an ion beam is irradiated onto the upper surface of the first insulating layer, forming a smooth surface in which the surface of the resin and the cut surfaces of the inorganic particles are exposed.

3. 2. The method for manufacturing a wiring board according to claim 1, An argon ion beam is used as the ion beam.

4. 2. The method for manufacturing a wiring board according to claim 1, The seed layer is formed by sputtering.

5. 2. The method for manufacturing a wiring board according to claim 1, An ultraviolet laser is used as the laser light.

6. A wiring board comprising: a first conductive layer; a first insulating layer laminated thereon and containing a resin and inorganic particles; a second conductive layer laminated thereon; a via penetrating the first insulating layer; and a via conductor filled in the via and connecting the first conductive layer and the second conductive layer, a diameter of the via on the upper surface of the first insulating layer is not less than 5 μm and not more than 15 μm; On the upper surface of the first insulating layer covered with the second conductive layer, the surface of the resin and the cut surfaces of the inorganic particles are exposed.

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