Semiconductor Devices

Abstract

A semiconductor device is provided in which the occurrence of wiring defects caused by the roughness of the surface of the wiring member (52) is suppressed. [Solution] The semiconductor device includes a wiring layer 52 including a plurality of wirings. The wirings have conductive films 54 and films 55 alternately stacked in a direction substantially perpendicular to the wiring layer 52. The films 55 can stop the growth of crystal grains in the conductive film 54, thereby making it possible to keep the grain size of the conductive film 54 below a predetermined grain size. This can prevent the conductive film 54 from becoming too large, and can suppress (improve) the roughness of the surface of the wiring member 52.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semi-damascene wiring and other wiring are formed by processing a film formed by, for example, chemical vapor deposition (CVD).Due to the roughness of the surface of the film formed by CVD, there is a possibility that pit defects will occur in the wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-244136 [Patent Document 2] Japanese Patent Application Publication No. 11-297697 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing the occurrence of defects is provided. [Means for solving the problem]

[0005] The semiconductor device according to the present embodiment includes a wiring layer including a plurality of wirings, each of which has a conductive film and a first film alternately stacked in a direction substantially perpendicular to the wiring layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 2A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 2B] 2B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 2A. [Figure 3A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 3B] 3B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 3A. [Figure 3C] 3C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 3B. [Figure 3D] 3D is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, following FIG. 3C. [Figure 3E] 3D, a cross-sectional view showing an example of the method for manufacturing the semiconductor device. FIG. [Figure 4] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first comparative example. [Figure 5] 10 is a graph showing an example of the relationship between the film thickness of a conductive film and the occurrence of defects in wiring according to the first embodiment and the first comparative example. [Figure 6A] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first comparative example. [Figure 6B] 6B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 6A. FIG. [Figure 6C] FIG. 6C is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 6C. [Figure 6E] FIG. 6B is a cross-sectional view showing an example of the method for manufacturing the semiconductor device, subsequent to FIG. 6D. [Figure 7] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second comparative example. [Figure 8] FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment, showing a wiring layer 50 used in the semiconductor device.

[0009] The semiconductor device includes a wiring layer 50, an insulating layer 60, a barrier metal film 70, a pillar-shaped electrode (via plug) 80, and an insulating film 90.

[0010] The wiring layer 50 is provided on the XY plane. The wiring layer 50 includes a plurality of wirings 51 within the same layer. When the semiconductor device is a memory (storage element), the wiring layer 50 includes, for example, wiring for a memory cell array and wiring for peripheral circuits such as electric circuits. In the following, a case where the semiconductor device is a memory will be described, but the present invention is not limited to this, and the semiconductor device may also be a logic circuit (logic element) or the like.

[0011] The plurality of wirings 51 are arranged, for example, in a predetermined pattern. The plurality of wirings 51 are arranged, for example, in a line and space pattern. The wirings 51 extend in a direction perpendicular to the paper surface of FIG. 1 (Y direction). The plurality of wirings 51 are arranged side by side in the X direction. The wirings 51 are used, for example, as bit lines of a memory.

[0012] For example, a conductive material such as tungsten (W) is used as the material of the wiring 51. Details of the configuration of the wiring 51 will be described later with reference to FIGS. 3A to 3E.

[0013] The insulating layer 60 provides insulation between the wirings 51. The insulating layer 60 is made of, for example, SiO 2. The insulating layer 60 is formed of, for example, TEOS (Tetraethoxysilane) or the like.

[0014] The barrier metal film 70 suppresses diffusion of W contained in the material of the interconnect 51. The barrier metal film 70 is provided between the interconnect 51 and the insulating layer 60. The barrier metal film 70 is provided between the columnar electrode 80 and the insulating layer 60. The barrier metal film 70 is made of, for example, titanium (Ti), Ta (tantalum), or a tantalum nitride film (TaN).

[0015] The columnar electrode 80 electrically connects the wiring 51 and a lower wiring (not shown). The columnar electrode 80 is provided integrally with the wiring 51 and extends from the bottom of the wiring 51 in a direction (Z direction) substantially perpendicular to the wiring layer 50. The material of the columnar electrode 80 is the same as the material of the wiring 51. The material of the columnar electrode 80 is, for example, a conductive material such as tungsten (W).

[0016] The insulating film 90 is provided on the wiring 51. The insulating film 90 is made of, for example, SiN.

[0017] 2A and 2B are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0018] 2A, a hole H is formed in an insulating film 61, a barrier metal film 70 is formed on the insulating film 61 and in the hole H, a wiring member 52 is formed so as to fill the hole H and be provided on the insulating film 61, an insulating film 90 is formed on the wiring member 52, and a semiconductor film 100 is formed on the insulating film 90. The wiring member 52 is formed by, for example, CVD (Chemical Vapor Deposition). The semiconductor film 100 is made of, for example, amorphous silicon.

[0019] The wiring members 52 embedded in the holes H become the columnar electrodes 80. That is, the columnar electrodes 80 are formed simultaneously with the wiring members 52 that will become the wiring 51 after processing.

[0020] The formation of the wiring member 52 will be described later in detail with reference to FIGS. 3A to 3E.

[0021] 2B, the wiring member 52 is processed to form a plurality of wirings 51 arranged in a predetermined pattern. The wiring member 52 is processed by, for example, RIE (Reactive Ion Etching).

[0022] Thereafter, the spaces between the wirings 51 are filled with the same insulating film as the insulating film 61, and grinding (for example, CMP (Chemical Mechanical Polishing)) is performed until the insulating film 90 is exposed, thereby completing the structure shown in FIG.

[0023] Next, the formation of the wiring member 52 will be described.

[0024] 3A to 3E are cross-sectional views showing an example of the method for manufacturing the semiconductor device according to the first embodiment, in which the barrier metal film 70 is omitted.

[0025] 3A, a nucleation layer 53 is formed on an insulating film 61. The nucleation layer 53 is formed, for example, by alternately supplying diborane (BH) gas and tungsten hexafluoride (WF) gas into a processing chamber.

[0026] Next, as shown in FIG. 3B, a conductive film 54 is formed. The conductive film 54 is formed by the growth and enlargement of metal crystal grains (growth nuclei) contained in the nucleation layer 53. The main component of the conductive film 54 is, for example, tungsten (W). The conductive film 54 is formed, for example, by processing while supplying tungsten hexafluoride (WF) and hydrogen (H) gas into a processing chamber. The conductive film 54 is formed until it has a thickness of, for example, about 15 nm. The thickness of the conductive film 54 is measured in the vertical direction (Z direction) of the page. Note that the thickness of the conductive film 54 is determined within a range that does not cause defects in the wiring 51, as will be described later with reference to FIG. 5. FIG. 3B also shows crystal grain boundaries 54a of the conductive film 54.

[0027] Next, as shown in FIG. 3C, a film 55 is formed on the conductive film 54. The film 55 is an amorphous film. The film 55 is formed, for example, by soaking in diborane. In this case, the film 55 is a film containing diborane adsorbed on the surface of the conductive film 54. The film 55 as a soaked film is formed, for example, by processing while supplying diborane gas into the processing chamber. Note that although the upper surface of the film 55 shown in FIG. 3C is flat, the upper surface of the film 55 does not necessarily have to be flat.

[0028] Next, as shown in Fig. 3D, a conductive film 54 is formed on the film 55. The conductive film 54 is formed to a thickness of about 15 nm, for example, as in Fig. 3B.

[0029] 3C and 3D are then repeatedly performed (cyclic film formation), as shown in Fig. 3E. This forms the wiring member 52. In the example shown in Fig. 3E, a three-layer conductive film 54 is formed.

[0030] The wiring member 52 has conductive films 54 and films 55 alternately stacked in a direction (Z direction) substantially perpendicular to the wiring layer 50. Accordingly, the wiring 51 shown in FIG. 1 also has conductive films 54 and films 55 alternately stacked in a direction (Z direction) substantially perpendicular to the wiring layer 50. The main component of the conductive film 54 is, for example, tungsten (W). The film 55 is a film type different from that of the conductive film 54. In the first embodiment, the main component of the film 55 is boron (B), which is different from the main component of the conductive film 54. The number of stacked conductive films 54 and films 55 is, for example, two or more. For example, when the wiring member 52 is formed to a thickness of 40 nm, three layers of conductive films 54 each having a thickness of approximately 13 nm are formed.

[0031] The auxiliary film 55 functions as a dividing film provided between the two conductive films 54 sandwiching the film 55, dividing the crystal grains of the conductive film 54. The film 55 can stop the growth of the crystal grains of the conductive film 54, thereby making it possible to reduce the grain size of the conductive film 54 to a predetermined size or less. This can prevent the conductive film 54 from becoming too large in grain size, and can reduce (improve) the roughness of the surface of the wiring member 52. As a result, it is possible to prevent defects in the wiring 51 from occurring during the process of processing the wiring member 52. Details of defects in the wiring 51 caused by the roughness of the surface of the wiring member 52 will be described later with reference to FIGS. 6A to 6E.

[0032] Furthermore, the film 55 is formed to a thickness that covers the conductive film 54 and can appropriately disrupt the crystallinity of the conductive film 54. Therefore, the film 55 may be thinner than the conductive film 54. Because the film 55 is a soaked film, the film 55 is formed simply by adsorbing diborane onto the surface of the conductive film 54. Furthermore, because the soaked film containing diborane is used as a reducing agent when forming the conductive film 54, the film 55 becomes even thinner. This allows the ratio of the thickness of the conductive film 54 to the overall thickness of the wiring member 52 to be increased. As a result, the wiring resistance of the wiring 51 can be further reduced.

[0033] As described above, according to the first embodiment, the wiring 51 has the conductive films 54 and the films 55 alternately stacked in a direction (Z direction) substantially perpendicular to the wiring layer 50. The wiring 51 has at least two layers of conductive films 54. This makes it possible to prevent the conductive films 54 from becoming large in grain size, and to suppress (improve) the roughness of the surface of the wiring member 52. As a result, defects in the wiring 51 can be suppressed. The roughness increases as the surface step of the wiring member 52 (see FIG. 5) increases, i.e., as the convex portion of the top surface of the wiring member 52 increases from the reference plane.

[0034] 2A, the wiring member 52 and the columnar electrode 80 are simultaneously and integrally formed by CVD, thereby reducing the number of steps.

[0035] The insulating film 90 is provided on the plurality of interconnects 51. The insulating film 90 is arranged according to the shape of the plurality of interconnects 51 when viewed from a direction substantially perpendicular to the interconnect layer 50 (Z direction). More specifically, the plurality of insulating films 90 are provided along the plurality of interconnects 51. For example, the outer edge shape of the plurality of insulating films 90 may be substantially the same as the outer edge shape of the plurality of interconnects 51 when viewed from a direction substantially perpendicular to the interconnect layer 50 (Z direction). When forming upper columnar electrodes (not shown) electrically connected to the tops of the interconnects 51, portions of the insulating film 90 on the interconnects 51 are recessed (processed) and filled with a conductive material. This allows the shape of the bottom of the upper columnar electrode to be adjusted; for example, the bottom of the upper columnar electrode can be positioned only above the interconnects 51. As a result, concerns about breakdown voltage can be alleviated.

[0036] The film 55 is not limited to the above-described examples, and it is more preferable that the film 55 be a film that can be formed in the same chamber or the same device.

[0037] (First Comparative Example) 4 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Comparative Example 1. Comparative Example 1 differs from the first embodiment in that film 55 is not provided and conductive film 54 continues to grow.

[0038] In the first comparative example, the process shown in FIG. 3B in the first embodiment is continued to form a wiring member 52 having a conductive film 54 with a larger grain size. The larger the grain size of the conductive film 54, the smaller the specific resistance of the wiring 51, and therefore the wiring resistance of the wiring 51 can be reduced. However, the larger the grain size of the conductive film 54, the worse the surface roughness of the wiring member 52. In the example shown in FIG. 4, localized convex portions are formed on the upper surface of the wiring member 52. The convex portion 52a shown in FIG. 4 is the convex portion with the greatest height difference.

[0039] FIG. 5 is a graph showing an example of the relationship between the film thickness of the conductive film 54 and the occurrence of defects in the wiring 51 according to the first embodiment. The horizontal axis of the graph represents the film thickness of the conductive film 54. The vertical axis of the graph represents the surface step. The surface step is the maximum height difference of localized convex portions occurring on the upper surface of the wiring member 52. (In the example shown in FIG. 4, the height difference of the convex portion 52a shown in FIG. 4)

[0040] When the thickness of the conductive film 54 is about 38 nm or more (first comparative example), the surface step of the wiring member 52 is about 35 nm or more, and defects in the wiring 51 may occur.

[0041] On the other hand, when the thickness of the conductive film 54 is approximately 15 nm or less (first embodiment), the surface step of the wiring member 52 is approximately 15 nm or less, and no defects occur in the wiring 51. When the conductive film 54 is formed on the film 55, the conductive film 54 grows from a state in which the thickness of the conductive film 54, which is the horizontal axis of the graph, is reset to zero nm. This makes it possible to suppress the roughness of the surface of the wiring member 52 even if the total thickness of the conductive films 54 increases.

[0042] Next, defects will be described.

[0043] 6A to 6E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first comparative example.

[0044] Fig. 6A shows the wiring member 52 described with reference to Fig. 4. As shown in Fig. 6A, localized convex portions 52a due to surface roughness are generated on the upper surface of the wiring member 52. Convex portions 52a also cause convex portions to be generated on the upper surfaces of the insulating film 90 and the semiconductor film 100 above convex portions 52a.

[0045] First, as shown in FIG. 6A, an insulating film 90, a semiconductor film 100 as a mask film, a mask film 110, and an insulating film 120 are formed in this order on the wiring member 52, a resist 130 is formed in a predetermined region on the insulating film 120, and a spacer 140 is formed on the insulating film and the resist 130.

[0046] The insulating film 120 is, for example, a SOG (Spin On Glass) film. The spacer 140 includes, for example, SiO 2 .

[0047] 6B, the mask film 110, the insulating film 120, the resist 130, and the spacers 140 are processed until the semiconductor film 100 is exposed, thereby forming the spacers 150. The processing is performed by, for example, RIE.

[0048] Next, as shown in Fig. 6C, the mask film 110, the insulating film 120, and the spacers 150 are processed. The processing is performed by, for example, RIE / WET, etc. As shown in Fig. 6C, the spacers 150 provided above the protrusions 52a are thinner than the spacers 150 provided in other positions.

[0049] Next, as shown in FIG. 6D, the semiconductor film 100 is processed using the spacers 150 as a mask. The semiconductor film 100 is processed by, for example, RIE. As shown in FIG. 6D, the spacers 150 provided above the protrusions 52a are completely lost during processing. Because the spacers 150 serving as a mask are lost, the semiconductor film 100 above the protrusions 52a is also lost.

[0050] Next, as shown in FIG. 6E, the wiring member 52 is processed using the spacer 150 as a mask. By processing the wiring member 52, wiring 51 arranged in a predetermined pattern such as a line-and-space pattern is formed. Note that the process from the step shown in FIG. 6D to the step shown in FIG. 6E is performed continuously. As shown in FIG. 6E, due to the disappearance of the spacer 150 serving as a mask, wiring 51 is not formed at the position where the protrusion 52a was formed. In other words, a depression defect occurs in the wiring 51.

[0051] In contrast to this, in the first embodiment, cyclic deposition of the conductive film 54 and the film 55 can prevent the conductive film 54 from becoming large in grain size, thereby improving the roughness of the surface of the wiring member 52. As a result, the generation of the protrusions 52a can be prevented, and defects in the wiring 51 can be suppressed.

[0052] The thickness of the conductive film 54 is determined by, for example, obtaining the relationship between the film thickness of the conductive film 54 and the occurrence of defects in the wiring 51 shown in FIG. 5 through an experiment.

[0053] (Second Comparative Example) 7 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Comparative Example 2. Comparative Example 2 differs from the first embodiment in that the entire wiring member 52 is the nucleation layer 53.

[0054] In the second comparative example, the process shown in FIG. 3A in the first embodiment is continued. The nucleation layer 53 is amorphous. Therefore, the surface roughness of the wiring member 52 is improved compared to the first comparative example. However, the resistivity of the wiring 51 increases. As a result, the wiring resistance of the wiring 51 increases.

[0055] In contrast, in the first embodiment, a plurality of conductive films 54 having a certain degree of particle size are formed, which increases the specific resistance of the wiring 51. As a result, it is possible to form a wiring member 52 having low resistance and improved surface roughness.

[0056] (Second embodiment) The second embodiment differs from the first embodiment in that the film 55 is an oxide film.

[0057] The main component of the film 55 is an oxide of the metal element that is the main component of the conductive film 54 .

[0058] The film 55 as an oxide film is formed, for example, by oxidizing the surface of the conductive film 54. Since the conductive film 54 contains tungsten (W), the film 55 is mainly composed of WO x The film 55 is an amorphous film.

[0059] Since the film 55 is an oxide film, the film 55 can be formed more easily.

[0060] Also, WO xWhen tungsten hexafluoride and hydrogen gas are supplied onto the WO x may be reduced, resulting in a thinner film 55. In this case, the ratio of the thickness of the conductive film 54 to the overall thickness of the wiring member 52 can be increased. As a result, the wiring resistance of the wiring 51 can be further reduced.

[0061] As in the second embodiment, the film 55 may be an oxide film. In this case, the same effects as in the first embodiment can be obtained.

[0062] (Third embodiment) The third embodiment differs from the first embodiment in that the film 55 is a nucleation layer for the conductive film 54.

[0063] The main component of the film 55 is the same as the main component of the conductive film 54. More specifically, the film 55 is a nucleation layer for the conductive film 54.

[0064] The film 55 as the nucleation layer is formed, for example, in the same manner as the nucleation layer 53 in the process shown in FIG. 3A. In this case, the film 55 is a tungsten film containing a large amount of diborane, which is a material gas for forming the nucleation layer. Therefore, the film 55 contains boron (B) based on the diborane. The film 55 is an amorphous film.

[0065] Since the film 55 is a metal film, it has a relatively low resistance, which allows the wiring resistance of the wiring 51 to be further reduced.

[0066] As in the third embodiment, the film 55 may be a nucleation layer. In this case, the same effects as in the first embodiment can be obtained.

[0067] (Fourth embodiment) Fig. 8 is a cross-sectional view showing an example of the structure of a semiconductor device according to the fourth embodiment. The semiconductor device shown in Fig. 8 is a three-dimensional memory in which an array chip C1 and a circuit chip C2 are bonded together.

[0068] The array chip C1 includes a memory cell array 11 including a plurality of memory cells arranged three-dimensionally, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0069] The circuit chip C2 is provided below the array chip C1. The symbol S indicates the bonding surface between the array chip C1 and the circuit chip C2. The circuit chip C2 includes an interlayer insulating film 14 and a substrate 15 below the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is an example of a first substrate, for example, a semiconductor substrate such as a silicon substrate. FIG. 8 shows the X and Y directions parallel to and perpendicular to the surface, i.e., the top surface, of the substrate 15, and the Z direction perpendicular to the surface of the substrate 15. The Y direction is an example of a first direction, the X direction is an example of a second direction intersecting the first direction, and the Z direction is an example of a third direction intersecting the first and second directions.

[0070] The array chip C1 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in the memory cell array 11. FIG. 8 shows a staircase structure 21 of the memory cell array 11. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 24, and is also electrically connected to a source line SL. The source line SL includes a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metal layer. The symbol V denotes a via plug provided below the bit line BL.

[0071] The circuit chip C2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip C2 also includes a plurality of contact plugs 33 provided on the source diffusion layer or the drain diffusion layer of each of the transistors 31, a wiring layer 34 provided on the contact plugs 33 and including a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wires.

[0072] The circuit chip C2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wires, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip C2 functions as a control circuit (logic circuit) that controls the operation of the array chip C1. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 38.

[0073] The array chip C1 includes a plurality of metal pads 41 provided on the metal pads 38 and a plurality of via plugs 42 provided on the metal pads 41. The array chip C1 also includes a wiring layer 43 provided on the via plugs 42 and including a plurality of wires, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wires including bit lines BL. The metal pads 41 are, for example, a Cu layer or an Al layer. The above-mentioned via plugs V are connected to the wiring layer 43 and the bit lines BL.

[0074] The array chip C1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on the via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer, and function as external connection pads (bonding pads) of the semiconductor device shown in FIG. 8. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has openings P that expose the top surfaces of the metal pads 46. The metal pads 46 can be connected to a mounting board or other devices via bonding wires, solder balls, metal bumps, or the like through the openings P.

[0075] Here, the wiring 51 in the wiring layer 50 described in the first to third embodiments corresponds to, for example, the wiring in the wiring layer 44. Note that FIG. 8 is upside down compared to FIG.

[0076] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0077] 11 memory cell array, 50 wiring layer, 51 wiring, 54 conductive film, 55 film, 80 columnar electrode, 90 insulating film, CL columnar portion

Claims

1. a wiring layer including a plurality of wirings; The wiring includes a conductive film and a first film different from the conductive film, which are alternately stacked in a direction substantially perpendicular to the wiring layer.

2. 2. The semiconductor device according to claim 1, wherein said first film is provided between two of said conductive films sandwiching said first film so as to divide crystal grains of said conductive films.

3. The semiconductor device according to claim 1 , wherein a main component of said first film is different from a main component of said conductive film.

4. 4. The semiconductor device according to claim 3, wherein a main component of said first film is boron (B).

5. 4. The semiconductor device according to claim 3, wherein a main component of said first film is an oxide of a metal element that is a main component of said conductive film.

6. 2. The semiconductor device according to claim 1, wherein a main component of said first film is the same as a main component of said conductive film.

7. 7. The semiconductor device according to claim 6, wherein said first film is a nucleation layer of said conductive film.

8. 8. The semiconductor device according to claim 7, wherein said first film contains boron (B).

9. 2. The semiconductor device according to claim 1, wherein said first film is an amorphous film.

10. 2. The semiconductor device according to claim 1, wherein a main component of said conductive film is tungsten (W).

11. The semiconductor device according to claim 1 , wherein the number of layers of said conductive film and said first film is two or more.

12. 2. The semiconductor device according to claim 1, wherein the thickness of said conductive film in a direction substantially perpendicular to said wiring layer is 15 nm or less.

13. 2. The semiconductor device according to claim 1, further comprising a pillar electrode formed integrally with said wiring and extending from a bottom of said wiring in a direction substantially perpendicular to said wiring layer.

14. further comprising an insulating film provided on the plurality of wirings; 14. The semiconductor device according to claim 13, wherein said insulating film is arranged in accordance with the shapes of said plurality of wirings when viewed from a direction substantially perpendicular to said wiring layer.

15. a memory cell array; a plurality of pillars penetrating the memory cell array; Furthermore, The semiconductor device according to claim 1 , wherein the plurality of wirings are electrically connected to the plurality of columnar portions, respectively.

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