Semiconductor device and method for manufacturing the same

Abstract

To increase the output power of nitride transistors. [Solution] The semiconductor device includes a channel layer made of a first nitride semiconductor, a barrier layer made of a second nitride semiconductor having a wider bandgap than the first nitride semiconductor and disposed on the channel layer, a first insulator layer made of a first protective layer disposed on the barrier layer, a second insulator layer made of a second protective layer disposed on the barrier layer and thicker than the first protective layer, a drain electrode, a source electrode, and a gate electrode disposed between the source electrode and the drain electrode and spaced from the barrier layer. The first insulator is more difficult to remove by a specific dry etching method than the second insulator. At least a portion of the gate electrode is disposed in a through-hole that penetrates the second protective layer. A portion of the first protective layer is disposed below the through-hole or within the through-hole.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A field effect transistor (hereinafter referred to as a nitride transistor) having, in this order, a layer of a nitride semiconductor and a layer of another nitride semiconductor having a wider band gap than the nitride semiconductor is a new generation power transistor (see, for example, Patent Documents 1 and 2).

[0003] Nitride transistors typically have a passivation film disposed on a barrier layer (i.e., the above-mentioned "another nitride semiconductor with a wide band gap") (see, for example, Patent Documents 1 to 4). The passivation film on the barrier layer is typically disposed to suppress current collapse (see, for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-170934 A [Patent Document 2] US Patent Application Publication No. 2012 / 0156836 [Patent Document 3] Special publication 2016-539496 [Patent Document 4] US Patent Application Publication No. 2013 / 0153963 Summary of the Invention [Problem to be solved by the invention]

[0005] The barrier layer (e.g., AlGaN layer) of a nitride transistor is configured so that positive polarization charges are generated at the heterointerface between the barrier layer and the channel layer (e.g., GaN layer). These positive polarization charges generate two-dimensional electron gas in the channel layer of the nitride transistor.

[0006] The term "AlGaN layer" in parentheses refers to an AlGaN layer (in other words, a "layer made of AlGaN" or a "layer that is AlGaN"). The same applies to "GaN layer" and similar terms (i.e., "layer of...") described below.

[0007] The concentration of the two-dimensional electron gas generated in the channel layer changes depending on the potential difference (i.e., gate voltage) between the gate electrode and source electrode placed on the barrier layer. When an AC voltage is applied to the gate electrode, the concentration of the two-dimensional electron gas also changes in response to changes in this AC voltage. As a result, a large AC current flows through the nitride transistor. In other words, nitride transistors are transistors with large transconductance.

[0008] The passivation film on the barrier layer typically has a through-hole (i.e., a cavity that penetrates the passivation film), and a gate electrode is disposed in this through-hole. The through-hole in the passivation film is typically formed by dry etching, which has high anisotropy. When the through-hole is completed as the etching progresses, the upper surface of the barrier layer exposed at the bottom of the through-hole is exposed to plasma generated during the dry etching.

[0009] The present inventors have discovered that exposure of a barrier layer to plasma reduces the concentration and mobility of two-dimensional electron gas (more precisely, the mobility of electrons contained in the two-dimensional electron gas). These reductions make it difficult to achieve higher output and higher frequency in nitride transistors. An object of the present invention is to solve such problems.

[0010] The above problem is particularly noticeable in nitride transistors having an InAlGaN barrier layer that is suitable for high output. [Means for solving the problem]

[0011] To solve the above problem, in one embodiment, a semiconductor device includes a channel layer made of a first nitride semiconductor, a barrier layer made of a second nitride semiconductor having a wider bandgap than the first nitride semiconductor and disposed on the channel layer, a first protective layer made of a first insulator and disposed on the barrier layer, a second protective layer made of a second insulator and disposed on the barrier layer and thicker than the first protective layer, a drain electrode into which current flows through the channel layer, a source electrode extending along the drain electrode and from which the current flows out, and a gate electrode disposed between the source electrode and the drain electrode and spaced from the barrier layer. The first insulator is an insulator that is more difficult to remove by a specific dry etching method than the second insulator. At least a portion of the gate electrode is disposed in a through-hole that penetrates the second protective layer. A portion of the first protective layer is disposed below the through-hole or is disposed in the through-hole. [Effects of the Invention]

[0012] According to one aspect of the present invention, a through portion for disposing a gate electrode can be formed in a passivation film (that is, a protective layer) without exposing the barrier layer to plasma, thereby enabling a nitride transistor to have a high output. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view showing an example 2 of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of a portion important to the operation of the nitride transistor 2, taken along the line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view of the first protective layer 14a and the second protective layer 14b in the vicinity of the gate electrode 20. As shown in FIG. [Figure 4] FIG. 4 is a graph comparing the etching rates of SiAlN and SiN. [Figure 5] FIG. 5 is a diagram illustrating an example of the operation of the nitride transistor 2. In FIG. [Figure 6] FIG. 6 is a cross-sectional view of a nitride transistor 202 having a SiN layer 214 in place of the first and second protective layers 14a and 14b. [Figure 7] FIG. 7 is a cross-sectional view of a nitride transistor 302 having a SiN layer 314 with a recess 315 in place of the first and second protective layers 14a and 14b. [Figure 8] FIG. 8 is a cross-sectional view of a nitride transistor 402 having a thin SiAlN layer 414 in place of the first and second protective layers 14a and 14b. [Figure 9] FIG. 9 is a cross-sectional view of a nitride transistor 502 having a substantially thick SiN layer 514 in place of the first and second protective layers 14a and 14b. [Figure 10] 10A to 10C are cross-sectional views showing steps in an example of a method for manufacturing the nitride transistor 2. FIG. [Figure 11] 11A to 11C are cross-sectional views showing steps in an example of a method for manufacturing the nitride transistor 2. FIG. [Figure 12] 12A to 12C are cross-sectional views showing steps in an example of a method for manufacturing the nitride transistor 2. FIG. [Figure 13] FIG. 13 is a cross-sectional view of an example 602 of a semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view of the first protective layer 614a and the second protective layer 614b in the vicinity of the gate electrode 620. As shown in FIG. [Figure 15] 15A to 15C are cross-sectional views showing an example of a method for manufacturing the nitride transistor 602. FIG. [Figure 16] 16A to 16C are cross-sectional views showing an example of a method for manufacturing the nitride transistor 602. FIG. [Figure 17] 17A to 17C are cross-sectional views showing an example of a method for manufacturing the nitride transistor 602. FIG. [Figure 18] 18A to 18C are cross-sectional views showing an example of a method for manufacturing the nitride transistor 602. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and their equivalents. Parts having the same structure are designated by the same reference numerals even in different drawings, and their description will be omitted.

[0015] (Embodiment 1) Fig. 1 is a plan view showing an example 2 of a semiconductor device (hereinafter referred to as a nitride transistor) according to the first embodiment. Fig. 2 is a cross-sectional view of a portion important for the operation of the nitride transistor 2, taken along the line II-II shown in Fig. 1. The same applies to other cross-sectional views described later.

[0016] (1) Structure The nitride transistor 2 includes, in order, a substrate 4, an AlN nucleation layer 6, a channel layer 8, a spacer layer 10, a barrier layer 12, a first protective layer 14a that is an insulator, and a second protective layer 14b that is another insulator. The nitride transistor 2 also includes a drain electrode 16, a source electrode 18, and a gate electrode 20.

[0017] (1-1) Substrate 4 and AlN nucleation layer 6 2, the nitride transistor 2 includes a substrate 4 (for example, a semi-insulating SiC substrate) and an AlN nucleation layer 6. The AlN nucleation layer 6 is also called an AlN low-temperature buffer layer.

[0018] The AlN nucleation layer 6 is a buffer layer that enables the growth of a high-quality nitride semiconductor on a substrate (e.g., a SiC substrate) whose lattice constant is significantly different from that of the nitride semiconductor. The AlN nucleation layer 6 is an AlN polycrystalline or amorphous film formed at low temperature. When using a substrate (e.g., a GaN substrate) having the same or approximately the same lattice constant as the channel layer 8 (e.g., a GaN channel layer), the AlN nucleation layer 6 can be omitted.

[0019] (1-2) Channel layer 8 and barrier layer 12 The nitride transistor 2 further includes a layer 8 (hereinafter referred to as a channel layer) of a nitride semiconductor (suitably referred to as a first nitride semiconductor) on the AlN nucleation layer 6. The first nitride semiconductor (e.g., GaN) is a III-V group semiconductor, and one of its constituent elements is preferably Ga.

[0020] The nitride transistor 2 further includes a barrier layer 12, which is a layer of a nitride semiconductor (appropriately referred to as a second nitride semiconductor) having a wider bandgap than the first nitride semiconductor, and is disposed on the channel layer 8.

[0021] The second nitride semiconductor (e.g., InAlGaN or AlGaN) is also a III-V group semiconductor, and at least two of its constituent elements are preferably two elements selected from the group consisting of In, Al, and Ga. The second nitride semiconductor may be AlN.

[0022] (1-3) Spacer layer 10 The nitride transistor 2 further comprises a spacer layer 10 , which is a layer of nitride semiconductor and is disposed between the channel layer 8 and the barrier layer 12 .

[0023] The spacer layer 10 is a layer (e.g., an AlGaN layer) configured to reduce the strength of the electric field generated in the barrier layer 12 due to the potential difference between the gate electrode 20 and the drain electrode 16. Therefore, the spacer layer 10 can suppress breakdown of the barrier layer 12 caused by electric field concentration near the gate electrode 20 (particularly near the end of the gate electrode on the drain electrode 16 side).

[0024] The spacer layer 10 is beneficial in nitride transistors in which breakdown of the barrier layer 12 due to electric field concentration is likely to occur (for example, nitride transistors having an InAlGaN barrier layer). On the other hand, the spacer layer 10 may be omitted in nitride transistors in which breakdown of the barrier layer 12 due to electric field concentration is unlikely to occur (for example, nitride transistors having an AlGaN barrier layer).

[0025] (1-4) First protective layer 14a The nitride transistor 2 further comprises a first passivation layer 14 a, which is a layer of insulator (conveniently referred to as a first insulator) disposed on the barrier layer 12 .

[0026] The first protective layer 14a is, for example, a layer of SiAlN. SiAlN is a compound formed by combining three elements: silicon (Si), aluminum (Al), and nitrogen (N). Since the resistance of an insulator decreases when it is crystallized, the first protective layer 14a is preferably amorphous.

[0027] (1-5) Second protective layer 14b The nitride transistor 2 further includes a layer of an insulator (referred to as a second insulator as appropriate), a second protective layer 14b, which is disposed on the barrier layer 12 via the first protective layer 14a and is thicker than the first protective layer 14a. As described above, the resistance of an insulator decreases when it is crystallized, so the second protective layer 14b is also preferably amorphous, similar to the first protective layer 14a.

[0028] The second protective layer 14b is, for example, a layer of SiN, which is a compound formed by combining two elements, silicon (Si) and nitrogen (N).

[0029] (1-6) Drain electrode 16 and source electrode 18 The nitride transistor 2 further has a drain electrode 16 into which the current flowing through the channel layer 8 flows, and a source electrode 18 extending along the drain electrode 16 and from which the current flows out (see "(3) Operation").

[0030] 1-2, the source electrode 18 and the drain electrode 16 are ohmic electrodes in contact with the barrier layer 12. However, the source electrode 18 and the drain electrode 16 are not limited to such electrodes.

[0031] For example, the nitride transistor 2 may have a low-resistivity GaN that penetrates the barrier layer 12 and the spacer layer 10 to reach the channel layer 8. The source electrode 18 may be an ohmic electrode in contact with such a low-resistivity GaN. The same applies to the drain electrode 16.

[0032] (1-7) Gate electrode 20 The nitride transistor 2 further includes a gate electrode 20 that is disposed between the source electrode 18 and the drain electrode 16 and is spaced apart from the barrier layer 12 in a plan view.

[0033] (1-8) Gate electrode 20 and through-hole 22 FIG. 3 is a cross-sectional view of the first protective layer 14a and the second protective layer 14b in the vicinity of the gate electrode 20. As shown in FIG.

[0034] A portion of the gate electrode 20 (see FIG. 2) is disposed in a through portion 22 that penetrates the second protective layer 14b (see FIG. 3). A portion 25 of the first protective layer 14a is disposed below the through portion 22.

[0035] 3, a portion of the gate electrode 20 is disposed in the through portion 22. However, when the first protective layer 14a does not have the recess 24 (see "(1-9)" and "(5-5)"), the entire gate electrode 20 may be disposed in the through portion 22.

[0036] The "penetrating portion" refers to a portion (for example, a through-hole or a slit) that penetrates a substance on the outside (ie, the outside) of a certain object (for example, the second protective layer 14b).

[0037] (1-9) Etching resistance of the first insulator The first insulator (i.e., the first protective layer 14a) is an insulator that is more difficult to remove by dry etching than the second insulator (i.e., the second protective layer 14b). That is, when the first insulator is etched together with the second insulator by dry etching, the first insulator is etched slower than the second insulator.

[0038] The through-holes 22 (see FIG. 3) in the second protective layer 14b are typically formed by dry etching, which has high anisotropy. However, since it is difficult to stop the dry etching immediately after the through-holes 22 are completed, the first protective layer 14a is also etched for a certain period of time.

[0039] Therefore, a recess 24 is formed in the first protective layer 14a, but because the etching rate of the first protective layer 14a is slow, a through portion is also formed in the first protective layer 14a, and the gate electrode 20 rarely comes into contact with the barrier layer 12. Therefore, the yield of the nitride transistor 2 according to the first embodiment having the first protective layer 14a is high.

[0040] The reason why it is difficult to stop dry etching simultaneously with the completion of the penetrating portion 22 is that it is difficult to determine the etching rate accurately and with high precision. In addition to this problem, dry etching also has another problem in that the etching rate varies depending on the position on the surface of the object being etched (so-called in-plane distribution of the etching rate).

[0041] This problem can also be solved by using the first protective layer 14a with a slow etching rate, and therefore the yield of the nitride transistor 2 according to the first embodiment can be further increased (see "(4-2) Comparative Example 2").

[0042] It should be noted that the "dry etching" in the above phrase "it is an insulator that is difficult to remove by dry etching" does not refer to dry etching in general, but to a specific dry etching. For example, the above "dry etching" refers to dry etching that etches an insulator using plasma of a fluorine-based gas (e.g., CF4 gas) or a chlorine-based gas (e.g., Cl2 gas). Furthermore, the "etching rate of the first protective layer 14a" refers to the thickness of the first protective layer 14a that is reduced per unit time by etching. The same applies to the "etching rate of the second protective layer 14b" described below.

[0043] Figure 4 compares the etching rates of SiAlN and SiN. The vertical axis represents the etching rate for dry etching using a fluorine-based gas.

[0044] The horizontal axis is the number of Si atoms in SiAlN, N Si and the number of Al atoms in the SiAlN, N Al The sum of (=N Si +N Al ) the number of Al atoms N Al Ratio of CR Al (=N Al / N Si +N Al ) Ratio CR Al is hereafter referred to as the Al composition ratio. The data points on the vertical axis (i.e., data points where the Al composition ratio is zero) are the etching rates of SiN.

[0045] As shown in Figure 4, the etching rate of SiAlN increases with the Al composition ratio CR Al The etching rate of SiN is reduced to less than one-fourth of that of SiN when the Al composition ratio CR increases from 0 to 0.17. Al When is further increased to 0.45, the etching rate of SiAlN becomes 1 / 10 or less of the etching rate of SiN.

[0046] If the etching rate of the first protective layer 14a is equal to or less than one-fourth of the etching rate of the second protective layer 14b, it is easy to stop the dry etching for forming the through-hole at the first protective layer 14a. Therefore, when the first protective layer 14a is made of SiAlN and the second protective layer 14b is made of SiN, the yield of the nitride transistor 2 is sufficiently high. Therefore, in the above case, the Al composition ratio CR of the first protective layer 14a is Al is preferably 0.17 or more.

[0047] However, SiAlN has an Al composition ratio of CR Al As described above, when an insulator crystallizes, its resistance value decreases. AlTherefore, the Al composition ratio CR of the first protective layer 14a is preferably 0.5 or less. Al is preferably 0.17 or more and 0.5 or less.

[0048] In other words, when the first protective layer 14a is SiAlN and the second protective layer 14b is SiN, the first atomic number of Al in the first protective layer 14a is preferably 0.17 to 0.5 times the sum of the second atomic number of Si in the first protective layer 14a and the first atomic number. More preferably, the first atomic number is 0.2 to 0.45 times the sum of the second atomic number and the first atomic number. Most preferably, the first atomic number is 0.25 to 0.4 times the sum of the second atomic number and the first atomic number.

[0049] (1-10) Advantages of Having the First Protective Layer 14a As shown in FIG. 2, the lower part of the gate electrode 20 of the nitride transistor 2 is positioned in a penetration 22 on the first protective layer 14a, rather than in a penetration that penetrates the passivation film on the barrier layer (see "(4-1) Comparative Example 1").

[0050] The penetrations in the passivation film are typically formed by dry etching, which is highly anisotropic. When the barrier layer 12 is exposed to plasma generated during dry etching, the concentration and mobility of the two-dimensional electron gas generated in the channel layer 8 decrease, making it difficult to achieve high output and high frequency in nitride transistors. It is not yet clear why the two-dimensional electron gas in the channel layer that is not exposed to plasma deteriorates (specifically, the concentration and mobility decrease).

[0051] However, in the first embodiment, the through portion 22 where the lower portion of the gate electrode 20 is disposed is located on the first protective layer 14a, so the barrier layer 12 is not exposed to plasma during the formation of the through portion 22 by dry etching. Therefore, according to the first embodiment, the concentration and mobility of the two-dimensional electron gas in the channel layer 8 are not reduced by the exposure of the barrier layer 12 to plasma.

[0052] Furthermore, as described above, the first protective layer 14a is more difficult to etch than the second protective layer 14b, and therefore, according to the first embodiment, the yield of nitride transistors in which the gate electrode is disposed in the through-hole portion is increased (see "(1-9)"). Therefore, according to the first embodiment, it is possible to provide nitride transistors that have a high yield and are capable of achieving high output and high frequency.

[0053] (1-11)Other 2, the first protective layer 14a contacts the barrier layer 12, and the gate electrode 20 contacts the first protective layer 14a below the through portion 22. Such first protective layer 14a and gate electrode 20 minimize the layers interposed between the gate electrode 20 and the channel layer 8, thereby narrowing the gap between the gate electrode 20 and the channel layer 8 and increasing the transconductance of the nitride transistor 2.

[0054] 2, the first protective layer 14a has a recess 24 below the through portion 22 (see FIG. 3). Therefore, the bottom of the gate electrode 20 is disposed in this recess 24.

[0055] However, the first protective layer 14a does not have to have such a recess. For example, when the through-hole 22 is formed by just etching the second protective layer 14b, the recess 24 is not formed in the first protective layer 14a.

[0056] (2) Generation of two-dimensional electron gas and suppression of current collapse (2-1) Generation of two-dimensional electron gas The barrier layer 12 and the channel layer 8 are configured so that two-dimensional electron gas is generated in the channel layer 8.

[0057] Here, a case will be described in which the nitride transistor 2 does not have the spacer layer 10. However, even in the case in which the nitride transistor 2 has the spacer layer 10, the following description is substantially valid as is.

[0058] The channel layer 8 is, for example, a GaN layer (i.e., a GaN channel layer) arranged so that its upper surface (i.e., the surface on the first protective layer 14a side) is a metal surface. The barrier layer 12 is, for example, an InAlGaN layer whose Al composition and In composition are determined as described below and arranged so that its upper surface (i.e., the surface on the first protective layer 14a side) is a metal surface.

[0059] In the InAlGaN layer having a metal surface disposed on its upper surface, spontaneous polarization occurs from its upper surface toward its lower surface (i.e., the surface on the substrate 4 side). This spontaneous polarization generates positive polarization charges on the lower surface of the InAlGaN barrier layer.

[0060] This positive polarization charge creates a potential in the GaN channel layer that decreases toward its upper surface. This potential, combined with the forbidden band of the barrier layer 12, creates a potential well with a triangular profile (hereinafter referred to as a triangular potential) near the upper surface of the GaN channel layer. If this potential well is sufficiently deep, two-dimensional electron gas is generated in the GaN channel layer.

[0061] The triangular potential of the GaN channel layer becomes deeper as the positive polarization charge at the bottom surface of the InAlGaN barrier layer increases. The positive polarization charge at the bottom surface of the InAlGaN barrier layer also increases as the Al composition of the InAlGaN barrier layer increases. Therefore, the Al composition of the InAlGaN barrier layer is set to be sufficiently large so that two-dimensional electron gas is generated in the GaN channel layer.

[0062] However, the lattice mismatch between the GaN channel layer and the InAlGaN barrier layer increases as the Al composition of the InAlGaN barrier layer increases, so the In composition of the InAlGaN barrier layer is determined so that the decrease in the lattice constant due to the increase in the Al composition is suppressed by the increase in the lattice constant due to the increase in the In composition.

[0063] Since it is difficult to suppress such lattice mismatch with an AlGaN barrier layer that does not contain In as a constituent element, an InAlGaN barrier layer enables the generation of a high concentration two-dimensional electron gas, which is difficult to achieve with an AlGaN barrier layer.

[0064] (2-2) Suppression of current collapse The first protective layer 14a and the second protective layer 14b are configured to suppress current collapse.

[0065] Specifically, the first protective layer 14a is, for example, SiAlN (e.g., 4 nm thick SiAlN) grown in situ in the same apparatus as that used to grow the barrier layer 12, subsequent to the barrier layer 12 (see "(5) Manufacturing Method"). The second protective layer 14b is, for example, SiN (e.g., 40 nm thick SiN) grown in situ in the same apparatus as that used to grow the first protective layer 14a, subsequent to the first protective layer 14a, and thicker than the first protective layer 14a.

[0066] Current collapse is a phenomenon in which the drain current temporarily decreases when a large current flows through a nitride transistor when a high voltage is applied to the drain electrode. Current collapse can be suppressed by covering the barrier layer with a passivation film such as SiN. However, if the passivation film is thin, it is difficult to suppress current collapse. Therefore, the second protective layer 14b is made of SiN or the like, which is thicker than the first protective layer 14a.

[0067] Although the mechanism by which current collapse occurs is still unclear, it is possible to suppress current collapse by growing a passivation film (specifically, an insulator layer) after the barrier layer in a device in which the barrier layer has been grown. From this fact, it is thought that current collapse occurs because surface states are generated when the barrier layer surface is exposed to the atmosphere, and electrons traveling at high speed in the channel layer are captured by these surface states, causing the potential well near the top surface of the channel layer to become shallower.

[0068] However, this explanation is merely a hypothesis, and the cause of current collapse has not yet been clarified. Therefore, it is currently difficult to identify the structure of the "first protective layer 14a and second protective layer 14b" that is configured to suppress current collapse. However, it is possible to identify the "first protective layer 14a and second protective layer 14b" by their manufacturing method (i.e., in situ growth).

[0069] (3) Operation FIG. 5 is a diagram illustrating an example of the operation of the nitride transistor 2. In FIG.

[0070] V G (hereinafter referred to as gate voltage) is the potential difference (=Φg-Φs) between the potential Φg of the gate electrode 20 and the potential Φs of the source electrode 18. D (hereinafter referred to as drain voltage) is the potential difference between the potential Φd of the drain electrode 16 and the potential Φs of the source electrode 18 (=Φd−Φs).

[0071] Gate voltage V G When the potential at the source electrode 18 is 0 V, a two-dimensional electron gas 26 (i.e., a group of electrons in the conduction band) is localized in the portion of the channel layer 8 that contacts the spacer layer 10. This two-dimensional electron gas 26 exists in the range extending from directly below the source electrode 18 to directly below the drain electrode 16.

[0072] In this state, the positive drain voltage V D When a current is applied to the drain electrode 16, the two-dimensional electron gas 26 moves at high speed from the source electrode 18 toward the drain electrode 16. As a result, a current (hereinafter referred to as drain current) is generated in the nitride transistor 2, flowing into the drain electrode 16, passing through the channel layer 8, and flowing out from the source electrode 18.

[0073] Gate voltage V Gbecomes negative, the conduction band edge Ec rises at the interface between the channel layer 8 and the spacer layer 10 (hereinafter referred to as the heterointerface). As a result, the triangular potential in contact with the heterointerface in the channel layer 8 immediately below the gate electrode 20 becomes shallower. As a result, the concentration of the two-dimensional electron gas 26 immediately below the gate electrode 20 decreases, and the drain current decreases.

[0074] Gate voltage V G If the potential further decreases below the threshold, the two-dimensional electron gas disappears immediately below the gate electrode 20, and the nitride transistor 2 enters a non-conducting state (that is, an OFF state).

[0075] On the other hand, the gate voltage V G When the voltage Vcc becomes positive, the conduction band edge Ec at the heterointerface drops. As a result, the triangular potential at the heterointerface deepens in the channel layer 8 directly below the gate electrode 20. As a result, the concentration of the two-dimensional electron gas 26 directly below the gate electrode 20 increases, and the drain current increases.

[0076] That is, the nitride transistor 2 is G It is a transistor (i.e., a field effect transistor) whose drain current changes depending on the

[0077] In the above description, the nitride transistor 2 is a transistor having normally-on characteristics. However, the nitride transistor 2 may be a transistor having normally-off characteristics.

[0078] (4) Comparative Example (4-1) Comparative Example 1 6 is a cross-sectional view of a nitride transistor 202 (hereinafter referred to as Comparative Example 1) having a SiN layer 214 instead of the first protective layer 14a (see FIG. 2) and the second protective layer 14b. The SiN layer 214 is a passivation film having a through portion in which a portion of the gate electrode 220 is disposed.

[0079] The nitride transistor 202 has the barrier layer 12 covered with the SiN layer 214, and therefore current collapse can be suppressed by the nitride transistor 202. The same applies to Comparative Examples 2 and 4 described later.

[0080] The penetrations in the passivation film are typically formed by dry etching, which is highly anisotropic. However, since it is difficult to stop the dry etching immediately after the penetrations in the passivation film are completed, the upper surface of the barrier layer 12 is also etched to some extent. At this time, the upper surface of the barrier layer 12 is exposed to plasma generated during the dry etching.

[0081] This plasma exposure reduces the concentration and mobility of two-dimensional electron gas in the channel layer 8 directly below the through-hole, resulting in a decrease in the drain current of the nitride transistor 202.

[0082] Therefore, it is difficult to increase the output power of the nitride transistor 202. Furthermore, due to the decrease in the mobility of the two-dimensional electron gas, it is also difficult to increase the frequency of the nitride transistor 202.

[0083] On the other hand, the nitride transistor 2 according to the first embodiment does not have a through portion that reaches the barrier layer 12. Therefore, the barrier layer 12 is not exposed to plasma, and therefore, according to the first embodiment, it is possible to achieve higher output and higher frequency in the nitride transistor.

[0084] Specifically, the output of nitride transistor 2 according to the first embodiment is, for example, about 1.12 times the output of nitride transistor 202 (that is, comparative example 1).

[0085] (4-2) Comparative Example 2 7 is a cross-sectional view of a nitride transistor 302 (hereinafter referred to as Comparative Example 2) having a SiN layer 314 with a recess 315 instead of the first protective layer 14a (see FIG. 2) and the second protective layer 14b. The lower part of a gate electrode 320 is disposed in the recess 315.

[0086] Dry etching, which has high anisotropy, is suitable for forming the recess 315. However, dry etching has a problem in that the etching rate varies depending on the position on the surface of the insulator to be etched (hereinafter referred to as the in-plane position). For this reason, when multiple nitride transistors 302 are formed on the same substrate, nitride transistors 202 in which a through-hole, rather than a recess, is formed in the SiN layer (i.e., Comparative Example 1) are also formed.

[0087] Dry etching also has the problem that it is difficult to determine an accurate and precise etching rate, so if the depth of the recess 315 is controlled by the etching time, a through hole may be formed instead of a recess. Due to these problems, the yield of the nitride transistor 302 (i.e., Comparative Example 2) is low.

[0088] On the other hand, the first protective layer 14a, which is less susceptible to etching than the second protective layer 14b, is disposed below the second protective layer 14b (see FIG. 2) according to the first embodiment. Therefore, it is rare for the through portion 22 of the second protective layer 14b to penetrate through the first protective layer 14a and reach the barrier layer 12. This results in a high yield of the nitride transistor 2 according to the first embodiment.

[0089] (4-3) Comparative Example 3 FIG. 8 is a cross-sectional view of a nitride transistor 402 (appropriately referred to as Comparative Example 3) having a thin SiAlN layer 414 instead of the first protective layer 14a (see FIG. 2) and the second protective layer 14b.

[0090] The gate electrode 420 of the nitride transistor 402 is disposed on the SiAlN layer 414, not in a through-hole or a recess. Therefore, the nitride transistor 402 does not suffer from the problem of low yield due to dry etching when forming the through-hole or recess.

[0091] However, the nitride transistor 402 has a problem in that the passivation film (ie, the SiAlN layer 414) covering the barrier layer 12 is thin, and therefore current collapse cannot be sufficiently suppressed.

[0092] On the other hand, the nitride transistor 2 according to the first embodiment has a thick second protective layer 14b (e.g., a SiN layer) on the first protective layer 14a (e.g., a thin SiAlN layer). Therefore, according to the first embodiment, it is possible to sufficiently suppress current collapse.

[0093] (4-4) Comparative Example 4 FIG. 9 is a cross-sectional view of a nitride transistor 502 (appropriately referred to as Comparative Example 4) having a sufficiently thick SiN layer 514 instead of the first protective layer 14a (see FIG. 2) and the second protective layer 14b.

[0094] In the nitride transistor 502, the gate electrode 520 is disposed on the SiN layer 514, not in a through-hole or a recess. Therefore, the nitride transistor 502 does not suffer from the problem of low yield due to dry etching when forming the through-hole or the recess. Furthermore, because the barrier layer 12 of the nitride transistor 502 is covered with the thick SiN layer 514, the nitride transistor 502 does not suffer from the problem of insufficient suppression of current collapse.

[0095] However, since nitride transistor 502 has thick SiN layer 514 separating barrier layer 12 and gate electrode 520, nitride transistor 502 (ie, Comparative Example 4) has a problem of low transconductance.

[0096] On the other hand, in the nitride transistor 2 according to the first embodiment, only the thin first protective layer 14a separates the barrier layer 12 from the gate electrode 20. Therefore, according to the first embodiment, the transconductance can be increased.

[0097] (5) Manufacturing method 10-12 are cross-sectional views showing steps in one example of a method for manufacturing the nitride transistor 2. FIG.

[0098] (5-1) Growth of nitride semiconductor layer (see Figure 10(a)) First, an AlN nucleation layer 106, a channel layer 108, a spacer layer 110, and a barrier layer 112 are formed in this order on a substrate 104. The channel layer 108 is a layer of a first nitride semiconductor. The barrier layer 112 is a second nitride semiconductor having a wider band gap than the first nitride semiconductor, and is a layer that generates two-dimensional electron gas in the channel layer 108. The growth of the AlN nucleation layer 106 and the spacer layer 110 can be omitted (see "(1-1)" and "(1-3)" in "(1) Structure").

[0099] Specifically, for example, an AlN nucleation layer 106.ex is grown by metal organic chemical vapor deposition on the (0 0 0 1) plane of a semi-insulating SiC substrate 104.ex (see FIG. 10(a)). The source gas is, for example, a mixed gas of trimethylaluminum (hereinafter referred to as TMAl) gas and ammonia (NH3) gas.

[0100] The SiC substrate 104.ex is an example of the substrate 104. The AlN nucleation layer 106.ex is an example of the AlN nucleation layer 106. The same applies to each layer and electrode (for example, a channel layer 108.ex and a gate electrode 120.ex) described later.

[0101] The carrier gas is hydrogen (H2) gas or nitrogen (N2) gas. During the growth of the AlN nucleation layer 106.ex, the temperature of the SiC substrate 104.ex (hereinafter referred to as the growth temperature) is maintained at, for example, 700°C to 1200°C. During the growth of the AlN nucleation layer 106, the pressure of the growth chamber in which the SiC substrate 104.ex is placed (hereinafter referred to as the growth chamber pressure) is maintained at, for example, 1 kPa to 100 kPa. The carrier gas, growth temperature, and growth chamber pressure are also maintained within these ranges during the growth of the subsequent channel layer 108, etc.

[0102] Thereafter, a GaN channel layer 108.ex is grown on the AlN nucleation layer 106.ex by metal organic chemical vapor deposition. The source gas is, for example, a mixed gas of trimethylgallium (hereinafter referred to as TMGa) gas and ammonia (NH3) gas.

[0103] Then, an AlGaN spacer layer 110.ex is grown on the GaN channel layer 108.ex by metal organic chemical vapor deposition. The source gas is, for example, a mixed gas of TMAl gas, TMGa gas, and ammonia (NH3) gas.

[0104] Thereafter, an InAlGaN barrier layer 112.ex is grown on the AlGaN spacer layer 110.ex by metal organic chemical vapor deposition. The source gas is, for example, a mixed gas of trimethylindium gas, TMAl gas, TMGa gas, and ammonia (NH3) gas.

[0105] (5-2) Growth of the first and second protective layers 114a and 114b (see FIG. 10(b)) Next, a first protective layer 114a, which is a first insulator, and a second protective layer 114b, which is a layer of a second insulator and is thicker than the first protective layer 114a, are formed in this order on the barrier layer 112. The first insulator is an insulator that is more difficult to remove by a specific dry etching method than the second insulator.

[0106] Specifically, first, a SiAlN layer 114a (an example of the first protective layer 114a) is grown on the InAlGaN barrier layer 112a by metal organic chemical vapor deposition using a mixed gas of, for example, silane (SiH4) gas, TMAl gas, and ammonia (NH3) gas.

[0107] The thickness of the SiAlN layer 114a.ex is, for example, 4 nm. The thickness of the SiAlN layer 114a.ex is preferably 2 nm or more and 6 nm or less. More preferably, the thickness of the SiAlN layer 114a.ex is 3 nm or more and 5 nm or less. The Al composition ratio of the SiAlN layer 114a.ex is preferably 0.17 or more and 0.5 or less (e.g., 0.45) (see "(1-9)" in "(1) Structure").

[0108] Then, a SiN layer 114b.ex (an example of the second protective layer 114b) thicker than the SiAlN layer 114a.ex is grown on the SiAlN layer 114a.ex by metal organic chemical vapor deposition. The source gas is, for example, a mixed gas of silane (SiH4) gas and ammonia (NH3) gas.

[0109] The thickness of the SiN layer 114b.ex is, for example, 40 nm. The total thickness of the SiAlN layer 114a.ex and the SiN layer 114b.ex is preferably 10 nm or more and 100 nm or less. More preferably, the total thickness of the SiAlN layer 114a.ex and the SiN layer 114b.ex is 30 nm or more and 70 nm or less.

[0110] The growth of the SiAlN layer 114a.ex and the SiN layer 114b.ex is preferably performed subsequent to the growth of the InAlGaN barrier layer 112.ex in the same apparatus as that used to grow the InAlGaN barrier layer 112.ex (see "(2-2) Suppression of current collapse").

[0111] (5-3) Formation of the drain electrode 116 and the source electrode 118 (see FIG. 11) Next, a drain electrode 116 (see FIG. 11(b)) that makes ohmic contact with the barrier layer 112, and a source electrode 118 that also makes ohmic contact with the barrier layer 112 are formed.

[0112] Specifically, first, a photoresist film (not shown) having lattice- or frame-shaped openings is formed on the SiN layer 114b.ex (see FIG. 10(b)). Then, each layer formed on the SiC substrate 104b.ex is etched through the openings to form element isolation trenches (not shown). The etching is performed by, for example, dry etching. The etching gas is, for example, a chlorine-based gas.

[0113] Instead of the element isolation trenches, for example, the resistance of each semiconductor layer grown on the SiC substrate 104.ex may be increased by ion implantation through the openings in the photoresist film, thereby forming element isolation regions.

[0114] Thereafter, a photoresist film (not shown) having a rectangular opening and a rectangular opening extending along the long side of the rectangular opening is formed on the SiN layer 114b.ex, with the photoresist film being formed so that the two openings are located inside the isolation trench.

[0115] Thereafter, the SiN layer 114b.ex and the SiAlN layer 114a.ex are etched through the two openings to form through-holes TH1 and TH2 penetrating the SiN layer 114b.ex and the SiAlN layer 114a.ex (see FIG. 11(a)). The etching is performed by, for example, dry etching. The etching gas is, for example, a fluorine-based gas or a chlorine-based gas.

[0116] Then, a Ta layer having a thickness of 10 nm to 40 nm (e.g., 20 nm) and an Al layer having a thickness of 100 nm to 400 nm (e.g., 200 nm) are deposited in this order inside the through holes TH1 and TH2 and on the photoresist film. The Ta layer and Al layer on the photoresist film are then removed together with the photoresist film. As a result, a metal layer having the Ta layer and Al layer in this order (hereinafter referred to as a Ta / Al deposited layer) is left in the through holes TH1 and TH2.

[0117] Thereafter, the SiC substrate 104.ex on which the Ta / Al deposited layer is formed is heat-treated at 400°C to 1000°C (for example, 550°C), whereby a drain electrode 116.ex in ohmic contact with the InAlGaN barrier layer 112.ex and a source electrode 118.ex in ohmic contact with the InAlGaN barrier layer 112.ex are formed from the Ta / Al deposited layer in the through holes TH1 and TH2.

[0118] (5-4) Formation of the through-hole 122 (see FIG. 12(a)) Next, a portion of the second protective layer 114b (see FIG. 11(b)) is etched to form a through portion 122 (see FIG. 12(a)) that penetrates the second protective layer 114b between the drain electrode 116 and the source electrode 118.

[0119] Specifically, first, a photoresist film (not shown) having a rectangular opening is formed between the drain electrode 116.ex (see FIG. 11(b)) and the source electrode 118.ex.

[0120] Thereafter, the SiN layer 114b.ex is etched through the opening to form a through-hole 122.ex (see FIG. 12(a)) penetrating the SiN layer 114b.ex. At this time, the SiAlN layer 114a.ex is also slightly etched, and a recess 125.ex (an example of the recess 24 shown in FIG. 3) is formed.

[0121] The etching is performed by, for example, dry etching. The etching gas is, for example, a fluorine-based gas. The etching conditions (for example, high-frequency power for generating plasma) are the same as those used to obtain the data in FIG. 4.

[0122] Even after the etching time expected to complete the through-hole 122 has elapsed, etching is continued to a certain extent to ensure the completion of the through-hole. As a result, a depression 125 is formed in the SiAlN layer 114a. However, since the SiAlN layer 114a is more difficult to etch than the SiN layer 114b, no through-hole is formed through the SiAlN layer 114a.

[0123] (5-5) Formation of gate electrode 120 (see FIG. 12(b)) Finally, the gate electrode 120 (see FIG. 12(b)) is formed, with a part of it disposed in the through portion 122 (see FIG. 12(a)).

[0124] However, in rare cases where the recess 125 is not formed in the first protective layer 114a (see FIG. 12(a)), the entire gate electrode 120 may be formed in the through portion 122.

[0125] Specifically, first, a photoresist film having an opening is formed on the through portion 122.ex. Then, a Ni layer having a thickness of 15 nm to 60 nm (e.g., 30 nm) and an Au layer having a thickness of 200 nm to 800 nm (e.g., 400 nm) are deposited in this order on the photoresist film and inside the opening. Then, the Ni layer and the Au layer on the photoresist film are removed together with the photoresist film. This forms a gate electrode 120.ex (see FIG. 12(b)) having a Ni layer and an Au layer in this order.

[0126] In this way, the nitride transistor 102 is completed. The nitride transistor 102 is an example of the nitride transistor 2 shown in FIG. 2. The first protective layer 114a of the completed nitride transistor 102 is an example of the first protective layer 14a shown in FIG. 2. The same applies to other components of the nitride transistor 102 (for example, the second protective layer 114b and the barrier layer 112). The same applies to a manufacturing method according to the second embodiment, which will be described later.

[0127] (6) Variations 1-2 and the like has the gate electrode 20 in contact with the first protective layer 14a. However, the nitride transistor according to the first embodiment may have the gate electrode spaced apart from the first protective layer 14a.

[0128] For example, the nitride transistor according to the first embodiment may have a gate electrode separated from the first protective layer 14a by a thin insulating film that covers the through portion 22 (see FIG. 3) and the side and bottom surfaces of the recess 24. According to this modification, even if the insulating properties of the first protective layer 14a are insufficient, the gate leakage current can be reliably suppressed.

[0129] Similarly, the nitride transistor according to the first embodiment may have a first protective layer 14a spaced apart from the barrier layer 12. For example, a thin insulating layer may be disposed between the first protective layer 14a and the barrier layer 12.

[0130] The gate electrode 20 according to the first embodiment is disposed in a penetration 22 in the second protective layer 14b on the first protective layer 14a, rather than in a penetration in the passivation film in contact with the barrier layer 12. Therefore, the barrier layer 12 is not exposed to plasma generated during dry etching for forming the penetration. Therefore, according to the first embodiment, it is possible to suppress a decrease in the concentration and mobility of two-dimensional electron gas due to dry etching for forming the penetration, and therefore it is possible to achieve higher output and higher frequency in the nitride transistor.

[0131] Furthermore, since the first protective layer 14a is more difficult to etch than the second protective layer 14b, it is rare for the penetration portion to penetrate the first protective layer 14a and reach the barrier layer 12. Therefore, the yield of the nitride transistor according to the first embodiment is high.

[0132] Therefore, according to the first embodiment, it is possible to provide a nitride transistor that can achieve high output and high frequency and has a high yield.

[0133] (Embodiment 2) The second embodiment is similar to the first embodiment, so the description of the parts common to the first embodiment will be omitted or simplified.

[0134] (1) Structure 13 is a cross-sectional view of an example 602 of a semiconductor device (hereinafter referred to as a nitride transistor) according to the second embodiment. FIG. 14 is a cross-sectional view of the first protective layer 614a and the second protective layer 614b in the vicinity of the gate electrode 620.

[0135] As shown in FIG. 13, the nitride transistor 602 according to the second embodiment has first and second protective layers 614a and 614b that are different in structure and position from the first and second protective layers 14a and 14b according to the first embodiment.

[0136] (1-1) First and second protective layers 614a and 614b As shown in FIG. 13, the first protective layer 614a is disposed between the drain electrode 16 and the source electrode 18 and is spaced apart from the drain electrode 16 and the source electrode 18.

[0137] The second protective layer 614b is disposed on the barrier layer 12 without the first protective layer 614a therebetween. The first protective layer 614a is disposed in a through portion 622 (see FIG. 14) that penetrates the second protective layer 614b.

[0138] (1-2) Gate electrode 620 13, a part of the gate electrode 620 (hereinafter referred to as the gate embedded portion) is disposed so as to be located on the first protective layer 614a in the through portion 622 (see FIG. 14). However, the entire gate electrode 620 may be disposed in the through portion 622.

[0139] Except for these points, nitride transistor 602 according to the second embodiment has substantially the same structure as nitride transistor 2 according to the first embodiment.

[0140] (2) Manufacturing method 15-18 are cross-sectional views showing steps in one example of a method for manufacturing the nitride transistor 602. The method for manufacturing the nitride transistor 602 according to the second embodiment is similar to the method for manufacturing the nitride transistor 2 according to the first embodiment. Descriptions of parts common to the manufacturing method according to the first embodiment will be omitted or simplified.

[0141] (2-1) Growth of nitride semiconductor layer (see FIG. 15(a)) First, an AlN nucleation layer 106, a channel layer 108 made of a first nitride semiconductor, a spacer layer 110, and a barrier layer 112 made of a second nitride semiconductor having a wider band gap than the first nitride semiconductor are formed in this order on a substrate 104 (see FIG. 15(a)).

[0142] Specifically, an AlN nucleation layer 106.ex, a GaN channel layer 108.ex, an AlGaN spacer layer 110.ex, and an InAlGaN barrier layer 112.ex are grown on a semi-insulating SiC substrate 104.ex according to the procedure described in the first embodiment.

[0143] (2-2) Formation of the first protective layer 714a (see FIGS. 15(b) to 16(a)) Next, an island-shaped first protective layer 714a (see FIG. 16(a)), which is a layer of a first insulator, is formed on the barrier layer 112. The first insulator is an insulator that is more difficult to remove by a specific dry etching method than the second insulator, which will be described later.

[0144] Specifically, first, the SiAlN layer 114a.ex is grown according to the procedure described in the first embodiment (see FIG. 15(b)). The thickness of the SiAlN layer 114a.ex is, for example, 2 nm. The Al composition ratio of the SiAlN layer 114a.ex is, for example, 0.34. The preferred ranges for the thickness and Al composition ratio of the SiAlN layer 114a.ex are as described in the first embodiment.

[0145] Next, a rectangular photoresist film (not shown) is formed on the SiAlN layer 114a. Thereafter, the SiAlN layer 114a is etched through the photoresist film by, for example, wet etching that does not generate plasma, to form island-shaped SiAlN layers 714a (see FIG. 16(a)). The island-shaped SiAlN layers 714a are an example of the first protective layer 714a.

[0146] (2-3) Formation of second protective layer 714b (see FIG. 16(b)) Next, a second insulating layer, that is, a second protective layer 714b, which is thicker than the first protective layer 714a, is formed on the barrier layer 112 and the first protective layer 714a (see FIG. 16(b)).

[0147] Specifically, a SiN layer 714b.ex (an example of the second protective layer 714b) thicker than the SiAlN protective layer 714a.ex (an example of the first protective layer 714a) is deposited on the barrier layer 112ex on which the SiAlN protective layer 714a.ex (see FIG. 16(a)) is formed. The thickness of the SiN layer 714b.ex is preferably 10 nm or more and 100 nm or less (more preferably 30 nm or more and 70 nm or less). The SiN layer 714b.ex is deposited by, for example, plasma CVD (Plasma Enhanced Chemical Vapor Deposition).

[0148] (2-4) Formation of the drain electrode 116 and the source electrode 118 (see FIG. 17) Next, a drain electrode 116 (see FIG. 17(b)) that makes ohmic contact with the barrier layer 112, and a source electrode 118 that also makes ohmic contact with the barrier layer 112 are formed.

[0149] Specifically, first, following substantially the same procedure as that exemplified in "(5-3)", an isolation trench (not shown) surrounding the SiAlN layer 714a.ex or an isolation region made highly resistant by ion implantation is formed.

[0150] Thereafter, through-holes TH1 and TH2 penetrating the SiN layer 714b.ex are formed according to substantially the same procedure as that exemplified in "(5-3)" (see FIG. 17(a)). Etching is performed by dry etching. The etching gas is, for example, a fluorine-based gas or a chlorine-based gas.

[0151] Thereafter, in accordance with substantially the same procedure as that exemplified in "(5-3)", a drain electrode 116.ex is formed in the through-hole TH1, and a source electrode 118.ex is formed in the through-hole TH2.

[0152] (2-5) Formation of the through-hole 722 (see FIG. 18(a)) Next, a portion of the second protective layer 714b (see FIG. 17(b)) is etched to form a through-hole 722 (see FIG. 18(a)) that penetrates the second protective layer 714b and exposes the first protective layer 714a.

[0153] Specifically, first, a photoresist film (not shown) having a rectangular opening directly above the SiAlN layer 714a.ex (see FIG. 17(b)) is formed on the SiN layer 714b.ex. Then, the SiN layer 714b.ex is etched through this opening to form a through-portion 722.ex (see FIG. 18(a)) that exposes the SiAlN layer 714a.ex. The through-portion 722.ex is an example of the through-portion 722. The etching is performed by, for example, dry etching. The etching gas is, for example, a fluorine-based gas.

[0154] (2-6) Formation of gate electrode (see Figure 18(b)) Finally, a gate electrode 720 is formed, part of which is disposed in the through portion 722 (see FIG. 18(b)).

[0155] Specifically, the gate electrode 720.ex is formed in accordance with substantially the same procedure as that exemplified in "(5-5)".

[0156] In this manner, the nitride transistor 702 (an example of the nitride transistor 602) is completed.

[0157] According to the second embodiment, the first protective layer 614a, which is difficult to etch, is present between the barrier layer 12 and a part of the gate electrode 620 arranged in the through portion of the second protective layer 614b (see FIG. 13). Therefore, according to the second embodiment, similar to the first embodiment, it is possible to provide a nitride transistor which is capable of achieving high output and high frequency and has a high yield.

[0158] Furthermore, according to the second embodiment, since the first protective layer 614a is separated from the drain electrode 16, even if the insulating properties of the first protective layer 614 are insufficient, it is possible to suppress leakage current flowing between the gate electrode 620 and the drain electrode 16. The same applies to leakage current flowing between the gate electrode 620 and the source electrode 18.

[0159] Although the embodiments of the present invention have been described above, the first and second embodiments are merely illustrative and not limiting. For example, in the examples shown in the first and second embodiments, the first protective layer is SiAlN. However, the first protective layer may be an insulator other than SiAlN. For example, the first protective layer may be Al2O3. Similarly, the second protective layer may be an insulator other than SiN. For example, the second protective layer may be SiO2.

[0160] Furthermore, in the examples shown in the first and second embodiments, the substrate 4 is a SiC substrate. However, the substrate 4 may be a substrate other than SiC. For example, the substrate 4 may be silicon or sapphire.

[0161] Furthermore, in the examples shown in the first and second embodiments, the through-holes in the second protective layer do not reach the outer periphery of the second protective layer. However, the through-holes 22, 622 in the second protective layer may reach the outer periphery of the second protective layer. For example, the through-holes 22, 622 may be a gap that divides the second protective layer in half.

[0162] Furthermore, in the examples shown in the first and second embodiments, the group III constituent elements contained in the first and second nitride semiconductors are one or more of In, Al, and Ga. However, the first and second nitride semiconductors may contain a group III constituent element other than In, Al, and Ga (for example, B).

[0163] The following additional notes are disclosed regarding the above-described embodiment 1-2.

[0164] (Appendix 1) a channel layer made of a first nitride semiconductor; a barrier layer, which is a layer of a second nitride semiconductor having a band gap wider than that of the first nitride semiconductor and is disposed on the channel layer; a first insulating layer disposed on the barrier layer; and a second insulating layer disposed on the barrier layer and thicker than the first protective layer; a drain electrode into which a current flows through the channel layer; a source electrode extending along the drain electrode and from which the current flows; a gate electrode disposed between the source electrode and the drain electrode and spaced apart from the barrier layer; the first insulator is an insulator that is more difficult to remove by a specific dry etching method than the second insulator; at least a portion of the gate electrode is disposed in a through portion that penetrates the second protective layer; The first protective layer is partially disposed under the penetration portion or disposed within the penetration portion. Semiconductor device.

[0165] (Appendix 2) The first insulator is etched slower than the second insulator when etched together with the second insulator by the specific dry etching. The semiconductor device according to claim 1,

[0166] (Appendix 3) the second protective layer is disposed on the barrier layer via the first protective layer. 3. The semiconductor device according to claim 1 or 2.

[0167] (Appendix 4) the first protective layer is in contact with the barrier layer, The gate electrode is in contact with the first protective layer. 3. The semiconductor device according to claim 1 or 2.

[0168] (Appendix 5) The first protective layer and the second protective layer are amorphous. 3. The semiconductor device according to claim 1 or 2.

[0169] (Appendix 6) the first protective layer is a layer of SiAlN, The second protective layer is a SiN layer. 3. The semiconductor device according to claim 1 or 2.

[0170] (Appendix 7) the first number of Al atoms contained in the first protective layer is 0.17 to 0.5 times the sum of the second number of Si atoms contained in the first protective layer and the first number of Si atoms; 7. The semiconductor device according to claim 6,

[0171] (Appendix 8) the second protective layer is disposed on the barrier layer via the first protective layer; The first protective layer has a recess below the through-hole. 3. The semiconductor device according to claim 1 or 2.

[0172] (Appendix 9) a first step of forming, on a substrate, a channel layer made of a first nitride semiconductor and a barrier layer made of a second nitride semiconductor having a wider band gap than the first nitride semiconductor and causing two-dimensional electron gas to be generated in the channel layer, in this order; a second step of forming, after the first step, a first protective layer made of a first insulator and a second protective layer made of a second insulator and thicker than the first protective layer, in this order, on the barrier layer; a third step of etching a portion of the second protective layer after the second step to form a through-portion that penetrates the second protective layer; a fourth step of forming a gate electrode, at least a portion of which is disposed in the through portion, after the third step; The first insulator is more difficult to remove by a specific dry etch than the second insulator. A method for manufacturing a semiconductor device.

[0173] (Appendix 10) the second protective layer is disposed on the barrier layer without the first protective layer therebetween; the first protective layer is disposed between the drain electrode and the source electrode and is spaced apart from the drain electrode and the source electrode; The first protective layer is further disposed in the through-portion that penetrates the second protective layer, At least a portion of the gate electrode is disposed so as to be located on the first protective layer in the through portion. 3. The semiconductor device according to claim 1 or 2.

[0174] (Appendix 11) further comprising a spacer layer of a nitride semiconductor disposed between the channel layer and the barrier layer; The spacer layer is a layer configured to reduce the strength of an electric field generated in the barrier layer due to a potential difference between the gate electrode and the drain electrode. 3. The semiconductor device according to claim 1 or 2.

[0175] (Appendix 12) the barrier layer and the channel layer are configured so that two-dimensional electron gas is generated in the channel layer; The first protective layer and the second protective layer are configured to suppress current collapse. 3. The semiconductor device according to claim 1 or 2.

[0176] (Appendix 13) one of the constituent elements of the first nitride semiconductor is Ga; At least two of the constituent elements of the second nitride semiconductor are two elements selected from the group consisting of In, Al, and Ga. 3. The semiconductor device according to claim 1 or 2.

[0177] (Appendix 14) the first nitride semiconductor is GaN, The second nitride semiconductor is InAlGaN. 14. The semiconductor device according to claim 13, [Explanation of symbols]

[0178] 4: Substrate 8: Channel layer 12: Barrier layer 14a: 1st protective layer 14b :Second protective layer 16: Drain electrode 18: Source electrode 20: Gate electrode 22: Penetration 24: Depression 26: Two-dimensional electron gas

Claims

1. a channel layer made of a first nitride semiconductor; a barrier layer formed on the channel layer, the barrier layer being a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor; a first insulating layer, the first protective layer being disposed on the barrier layer; a second insulating layer disposed on the barrier layer and having a thickness greater than that of the first protective layer; a drain electrode into which a current flows through the channel layer; a source electrode extending along the drain electrode and from which the current flows; a gate electrode disposed between the source electrode and the drain electrode and spaced apart from the barrier layer; the first insulator is an insulator that is more difficult to remove by a specific dry etching method than the second insulator; at least a portion of the gate electrode is disposed in a through portion that penetrates the second protective layer; The first protective layer is partially disposed under the through-hole or disposed within the through-hole. Semiconductor device.

2. The first insulator is etched slower than the second insulator when etched together with the second insulator by the specific dry etching.

2. The semiconductor device according to claim 1.

3. the second protective layer is disposed on the barrier layer via the first protective layer.

3. The semiconductor device according to claim 1 or 2.

4. the first protective layer is in contact with the barrier layer, The gate electrode is in contact with the first protective layer.

3. The semiconductor device according to claim 1 or 2.

5. The first protective layer and the second protective layer are amorphous.

3. The semiconductor device according to claim 1 or 2.

6. the first protective layer is a layer of SiAlN, The second protective layer is a SiN layer.

3. The semiconductor device according to claim 1 or 2.

7. the first number of Al atoms contained in the first protective layer is 0.17 to 0.5 times the sum of the second number of Si atoms contained in the first protective layer and the first number of Si atoms; 7. The semiconductor device according to claim 6.

8. the second protective layer is disposed on the barrier layer via the first protective layer; The first protective layer has a recess below the through-hole.

3. The semiconductor device according to claim 1 or 2.

9. a first step of forming, on a substrate, a channel layer made of a first nitride semiconductor and a barrier layer made of a second nitride semiconductor having a band gap wider than that of the first nitride semiconductor, which barrier layer generates two-dimensional electron gas in the channel layer, in this order; a second step of forming, after the first step, a first protective layer made of a first insulator and a second protective layer made of a second insulator and thicker than the first protective layer, in this order, on the barrier layer; a third step of etching a portion of the second protective layer after the second step to form a through-portion that penetrates the second protective layer; a fourth step of forming a gate electrode, at least a portion of which is disposed in the through portion, after the third step; The first insulator is more difficult to remove by a specific dry etch than the second insulator. A method for manufacturing a semiconductor device.

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