Semiconductor device manufacturing method

Abstract

A method for manufacturing a semiconductor device that reduces evaporation of moisture from a protective film during laser annealing of the back surface of a wafer. The method for manufacturing a semiconductor device includes applying a protective film to a front surface of a semiconductor wafer (S105), patterning the protective film (S107), processing the back surface of the semiconductor wafer (S111) while the patterned protective film on the front surface is supported by a support table in a vacuum chamber (S111), and removing the protective film (S113) after the back surface processing of the semiconductor wafer. The back surface processing may include ion implantation into the back surface of the semiconductor wafer. The protective film may be polyimide.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 states that "The surface protective film is formed by applying, for example, a resist, and the front surface element structure on the front surface side of the n-type semiconductor substrate 10 is protected by the resist film (not shown)" (

[0039] ). Patent Document 2 states that "A resist film is applied to the substrate surface 2 as the surface protective film 3, for example, to a thickness of about 30 μm" (

[0024] ). Patent Document 3 states that "A second protective film 130 is formed above the first protective film 120" (

[0043] ). [Prior art document] [Patent documents] [Patent Document 1] WO 2018 / 179798 [Patent Document 2] JP 2006-54349 A [Patent Document 3] JP 2022-182825 Summary of the Invention [Means for solving the problem]

[0003] A first aspect of the present invention provides a method for manufacturing a semiconductor device, comprising: applying a protective film to a front surface of a semiconductor wafer; patterning the protective film; processing the back surface of the semiconductor wafer in a vacuum chamber while the patterned protective film on the front surface is supported by a support table; and removing the protective film after the back surface processing of the semiconductor wafer.

[0004] In the above-described method for manufacturing a semiconductor device, the back surface treatment may include ion implantation into the back surface of the semiconductor wafer.

[0005] In any of the above methods for manufacturing a semiconductor device, the protective film may be made of polyimide.

[0006] Any of the above semiconductor device manufacturing methods may include forming a front surface structure on the front surface of the semiconductor wafer. Any of the above semiconductor device manufacturing methods may include forming a passivation film above the front surface structure. In any of the above semiconductor device manufacturing methods, applying the protective film to the front surface of the semiconductor wafer may include applying the protective film above the passivation film. In any of the above semiconductor device manufacturing methods, the protective film may be thinner than the passivation film.

[0007] In any of the above methods for manufacturing a semiconductor device, the protective film may have a thickness of 2 μm or more and 5 μm or less.

[0008] In any of the above methods for manufacturing a semiconductor device, the protective film may have a glass transition temperature of 200 degrees or higher.

[0009] In any of the above methods for manufacturing a semiconductor device, the thermal decomposition temperature of the protective film may be 300 degrees or more and 600 degrees or less.

[0010] In any of the above methods for manufacturing a semiconductor device, patterning the protective film may include forming a mask of a predetermined shape on the protective film, and etching the protective film using the mask.

[0011] In any of the above methods for manufacturing a semiconductor device, the mask may be a photoresist.

[0012] Any of the above-described methods for manufacturing a semiconductor device may further include heating the protective film after patterning the protective film.

[0013] In any of the above methods for manufacturing a semiconductor device, patterning the protective film may include leaving the protective film at a pitch of 20 μm or more and 0.3 mm or less.

[0014] In any of the above methods for manufacturing a semiconductor device, patterning the protective film may include leaving the protective film so that the maximum length of the shape is 3 μm or more and 0.2 mm or less.

[0015] In any of the above methods for manufacturing a semiconductor device, patterning the protective film may include leaving the protective film so that a protection rate of the front surface provided by the protective film is 3% or more and 30% or less.

[0016] In any of the above-described methods for manufacturing a semiconductor device, the support base may have a plurality of protrusions on a surface that holds the patterned protective film on the front surface. In any of the above-described methods for manufacturing a semiconductor device, the back surface processing may include processing the back surface of the semiconductor wafer with the patterned protective film supported by the plurality of protrusions.

[0017] In any of the above methods for manufacturing a semiconductor device, the pitch of the patterned protective film may be less than the maximum length of the convex portions.

[0018] In any of the above-described methods for manufacturing a semiconductor device, the support base may have an annular protrusion on an outer edge of a surface that holds the patterned protective film on the front surface. In any of the above-described methods for manufacturing a semiconductor device, patterning the protective film may include forming an annular pattern on the front surface that corresponds to the annular protrusion.

[0019] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a flowchart showing an example of an operation flow of a method for manufacturing a semiconductor device 100 according to an embodiment. [Figure 2]1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device 101 according to a comparative example. [Figure 3] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor device 100 according to an embodiment. [Figure 4] 1 is a plan view showing an example of a patterned protective film 130 on the front surface 11 of a semiconductor wafer 10 in a manufacturing method of a semiconductor device 100 according to an embodiment. [Figure 5] 1 is a plan view showing an example of a support table that supports a patterned protective film 130 on a front surface 11 of a semiconductor wafer 10 in a manufacturing method of a semiconductor device 100 according to an embodiment. [Figure 6] 2 is a flowchart showing an example of a subroutine of step S111 in the operational flow of FIG. 1. [Figure 7] 2 is a flowchart showing an example of a subroutine of step S115 in the operational flow of FIG. 1. [Figure 8] 1 is a diagram showing an example of the arrangement of gate runners 48, well regions, and pad regions of a semiconductor device 100 as viewed from above. [Figure 9] 2 is a diagram showing an example of the arrangement of a passivation film 120 of the semiconductor device 100 when viewed from above. FIG. [Figure 10] 10 is a diagram showing an example of the arrangement of a resist 150 used when patterning a passivation film 120. FIG. [Figure 11] 1 is a diagram showing an example of a cross section of the semiconductor device 100 in an active portion 110. FIG. [Figure 12] This figure shows the relationship between the presence or absence of anti-bounce measures, the beam current, and the number of wafers processed. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0022] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0023] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor wafer are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor wafer is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor wafer, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0024] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0025] Fig. 1 is a flowchart showing an example of an operational flow of a method for manufacturing a semiconductor device 100 according to an embodiment. Fig. 2 is a diagram for explaining a method for manufacturing a semiconductor device 101 according to a comparative example.

[0026] The semiconductor devices 100 and 101 function as, for example, power conversion devices such as inverters. The semiconductor devices 100 and 101 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), an RC (Reverse Conducting)-IGBT that combines these, and a MOS transistor. The semiconductor devices 100 and 101 also function as, for example, pressure sensors. The semiconductor devices 100 and 101 are not limited to these examples. The semiconductor devices 100 and 101 include, for example, an RC-IGBT.

[0027] The semiconductor devices 100 and 101 include a semiconductor wafer 10. For example, the semiconductor wafer 10 has a substantially circular shape in top view and a diameter of 200±5 mm or 300±5 mm. The semiconductor wafer 10 is a substrate made of a semiconductor material. For example, the semiconductor wafer 10 is a silicon substrate, but the material of the semiconductor wafer 10 is not limited to silicon. A plurality of semiconductor devices 100 may be manufactured by dicing the semiconductor wafer 10. The semiconductor wafer 10 has a front surface 11 and a back surface 12.

[0028] The front surface 11 of the semiconductor wafer 10 may be a surface on which a front surface structure such as an IGBT or a MOS transistor is formed. The front surface structure may include at least one of a gate pad, a gate insulating film, a source region, a trench portion, an emitter region, a contact region, and a channel region. The front surface 11 of the semiconductor wafer 10 may be a so-called device surface.

[0029] 1, the operational flow of the manufacturing method of the semiconductor device 100 according to this embodiment begins with, for example, preparing a semiconductor wafer 10. The prepared semiconductor wafer 10 may have impurities implanted into predetermined regions, may be annealed, or may have an insulating film, electrodes, wiring, pad regions, etc. formed on a front surface 11. Note that in FIGS. 2 and 3, configurations of the semiconductor devices 100 and 101 other than the semiconductor wafer 10 are not shown.

[0030] 1, a front surface structure is formed on the front surface 11 of the semiconductor wafer 10 (step S101), and a passivation film 120 is formed above the front surface structure (step S103). Subsequently, a protective film 130 is applied to the front surface 11 of the semiconductor wafer 10 (step S105), the protective film 130 is patterned (step S107), and after patterning, the protective film 130 is heated (step S109). Subsequently, in a vacuum chamber, the semiconductor wafer 10 is subjected to backside processing while the patterned protective film 130 on the front surface 11 is supported by a support table 152 (step S111), the protective film 130 is removed (step S113), and various post-protective film removal processes are performed (step S115), whereupon the operational flow ends.

[0031] Here, a method for manufacturing a semiconductor device 101 according to a comparative example will be described as a comparison with the method for manufacturing the semiconductor device 100 according to the present embodiment, as shown in Fig. 2. The operational flow of the method for manufacturing the semiconductor device 101 according to the comparative example starts with preparing a semiconductor wafer 10. Similar to steps S101 to S103 of the operational flow in Fig. 1, a front surface structure is formed on the front surface 11 of the semiconductor wafer 10 (step S11), and a passivation film 120 is formed above the front surface structure (step S13).

[0032] In step S11, as an example, a resist 138 is provided above an electrode (not shown) provided on the front surface 11 of the semiconductor wafer 10. In step S13, a passivation film 120 is formed above a front surface structure formed on the front surface 11 of the semiconductor wafer 10, thereby patterning the electrode (not shown). Note that ions may be implanted into the front surface 11 of the semiconductor wafer 10, and the resist 138 may be the same resist as that used for the ion implantation. The resist 138 may contain a photosensitive material.

[0033] In step S11, as a specific example, a front surface structure of an RC-IGBT is formed on a low-resistivity p-type silicon wafer having a (0 0 1) principal surface and a thickness of 725 μm. A field oxide film may be formed by thermal oxidation, or a trench structure to serve as a gate may be formed, followed by the formation of a gate oxide film and gate polysilicon. A source n-layer, an interlayer insulating film (BPSG), and a front surface electrode may also be formed. A passivation film 120 is formed above these front surface structures.

[0034] The passivation film 120 may be provided above the emitter electrode 52 (see FIG. 8). The passivation film 120 may be in contact with the upper surface of the emitter electrode 52. The passivation film 120 may be provided above the pad region. The passivation film 120 may protect the front surface 11 of the semiconductor wafer 10, the emitter electrode 52, and the pad region. The emitter electrode 52, the pad region, etc. may be partially exposed from the passivation film 120. For example, the passivation film 120 may be a protective film that becomes a polyimide film by thermal curing, or may be a resist containing a photosensitive material.

[0035] To further protect the front surface 11, the emitter electrode 52, and the pad region of the semiconductor wafer 10, the passivation film 120 may be thermally cured. The thermal curing of the passivation film 120 may be performed using a heat treatment device such as an annealing furnace. The passivation film 120 may be thermally cured at a temperature T1. The treatment time is, for example, one hour. The temperature T1 is, for example, 250°C or higher and 400°C or lower, and may be, for example, 380°C or higher and 400°C or lower.

[0036] Similar to step S105 in the operational flow of FIG. 1 , a protective film 130 is applied to the front surface 11 of the semiconductor wafer 10 (step S15). Applying the protective film 130 to the front surface 11 of the semiconductor wafer 10 may include applying the protective film 130 above the passivation film 120. The protective film 130 may be in contact with the upper surface of the passivation film 120. In the comparative example, the protective film 130 is, for example, a resist containing a photosensitive material.

[0037] In step S15, the protective film 130 may be thermally cured to further protect the front surface 11, the emitter electrode 52, and the pad region of the semiconductor wafer 10. The thermal curing of the protective film 130 may be performed using a heat treatment device such as an annealing furnace. The protective film 130 may be thermally cured at a temperature T2. The treatment time is, for example, 30 minutes. The temperature T2 is, for example, 100 degrees or higher and 200 degrees or lower.

[0038] The steps subsequent to step S15 in the operational flow of the manufacturing method of semiconductor device 101 according to the comparative example differ from the steps subsequent to step S105 in the operational flow of FIG. 1. According to the operational flow of the comparative example, with protective film 130 supported on a table or the like, backside 12 of semiconductor wafer 10 is ground using a grinding wheel of a grinding device such as a back grinder (BG) (step S17). FIG. 2 shows the shape of semiconductor wafer 10 after grinding. Since protective film 130 formed above passivation film 120 on front side 11 is supported on a table or the like instead of directly supporting front side 11 of semiconductor wafer 10, front side 11, emitter electrode 52, and pad region of semiconductor wafer 10 are protected.

[0039] In step S17, a peripheral surplus region 252 is formed on the outer periphery of the semiconductor wafer 10 so as to leave a ring-shaped reinforcing structure on the semiconductor wafer 10. That is, in step S17, the inside of the peripheral surplus region 252 is ground so that the peripheral surplus region 252 remains on the outer periphery of the semiconductor wafer 10. The region of the semiconductor wafer 10 inside the peripheral surplus region 252 after grinding is designated as region 254. Forming the peripheral surplus region 252 suppresses warping of the semiconductor wafer 10, making it easier to handle the semiconductor wafer 10 in subsequent processes.

[0040] In a vacuum chamber, the back surface 12 of the semiconductor wafer 10 is processed with the protective film 130 supported by the support stage 152 (step S19). In the back surface processing of step S19, ions are implanted into a region 254 of the back surface 12. As an example, a resist 140 is provided above the back surface 12 of the semiconductor wafer 10 to selectively implant ions into the back surface 12 of the semiconductor wafer 10, and then a P-type dopant such as boron or an N-type dopant such as phosphorus is implanted into the back surface 12 of the semiconductor wafer 10. As an example, the resist 140 is a resist containing a photosensitive material.

[0041] In step S19, the front surface 11 of the semiconductor wafer 10 is not directly supported by the support table 152, but the protective film 130 formed above the passivation film 120 on the front surface 11 is supported by the support table 152, so that the front surface 11, the emitter electrode 52, and the pad region of the semiconductor wafer 10 are protected.

[0042] The protective film 130 is removed from the support 152 and removed (step S21), and the operation flow ends. The protective film 130 may be removed using a chemical solution such as an organic solvent containing pyrrolidones. The protective film 130 does not remain on the semiconductor device 100.

[0043] In the operational flow of the manufacturing method of semiconductor device 101 according to the comparative example described above, support table 152 used in step S19, which may also be referred to as a platen, has multiple protrusions on its upper surface 154, which is the support surface, and also has an annular protrusion on the outer edge of upper surface 154. Support table 152 chucks the supported object while supporting it using the tips of the multiple protrusions and the tip of the annular protrusion. Because support table 152 has recesses and protrusions on the inside of the annular protrusion, when semiconductor wafer 10 is supported, a space is formed between semiconductor wafer 10, the recessed portion, and the inside of the annular protrusion. To improve the cooling efficiency of semiconductor wafer 10, support table 152 may flow a cooling gas into this space while supporting semiconductor wafer 10. This makes it possible to increase the output of the beam current used when implanting ions into backside surface 12 of semiconductor wafer 10, shorten the backside processing time, and improve the throughput of manufacturing semiconductor device 101.

[0044] However, in the comparative example of the manufacturing method of the semiconductor device 101, ion implantation into the backside 12 of the semiconductor wafer 10 generates a large amount of gas 160 from the protective film 130 and accumulates in the space, as shown in FIG. 2 . The phenomenon of gas 160 generation is referred to as degassing in this specification. Because gas accumulates in the irregularities due to degassing, when the support table 152 dechucks the semiconductor wafer 10 after step S19, the semiconductor wafer 10 bounces. Even if the semiconductor wafer 10 were chucked using a table or the like without multiple protrusions instead of the support table 152, the large amount of gas 160 generated from the protective film 130 during ion implantation into the backside 12 of the semiconductor wafer 10 would accumulate between the semiconductor wafer 10 and the table, resulting in the same problem of the semiconductor wafer 10 bouncing. If a waiting time is required after backside processing of the semiconductor wafer 10 before dechucking in order to prevent such bouncing, the throughput of the manufacturing of the semiconductor device 101 would be reduced by the waiting time.

[0045] Furthermore, in the manufacturing method of the semiconductor device 101 according to the comparative example, if a support table 152 having irregularities is used in step S19, as shown in FIG. 2, the protective film 130 made of resist may get caught in the irregularities of the support table 152 in step S19, causing the semiconductor wafer 10 to stick to the support table 152 and making it impossible to dechuck it.

[0046] Fig. 3 is a diagram illustrating a method for manufacturing the semiconductor device 100 according to one embodiment. A specific example of the operation flow shown in Fig. 1 will be described using Fig. 3. Note that Fig. 3 collectively illustrates the above-mentioned steps S107 and S109.

[0047] In the operational flow of the manufacturing method of the semiconductor device 100 according to this embodiment, steps S101 to S105 described above may be the same as steps S11 to S15 in the operational flow of the comparative example shown in FIG. 2 , and therefore redundant description will be omitted. However, while step S15 of the operational flow of the comparative example was described as heating and curing the protective film 130, step S105 differs in that the protective film 130 is not heated and cured. In step S105, low-temperature baking may be performed to volatilize the solvent in the protective film 130. This low-temperature baking may be performed at a temperature of 80° C. to 150° C. As described above, the protective film 130 may be a resist containing a photosensitive material, or may be a polyimide or the like having higher heat resistance than a resist. In this embodiment, the protective film 130 is, for example, polyimide.

[0048] In step S105, the protective film 130 applied to the front surface 11 of the semiconductor wafer 10 may be thinner than the passivation film 120 on the front surface 11. The thickness of the protective film 130 is, for example, not less than 2 μm and not more than 5 μm.

[0049] Furthermore, in the subsequent back surface treatment in step S111, for example, laser annealing is performed, but as described above, the protective film 130 must remain on the front surface 11 of the semiconductor wafer 10 even during the back surface treatment. Therefore, the glass transition temperature of the protective film 130 is, for example, 200°C or higher. The thermal decomposition temperature of the protective film 130 is, for example, 300°C or higher and 600°C or lower.

[0050] As described above, in step S107, the protective film 130 is patterned, and in step S109, the protective film 130 is heated. In this embodiment, patterning the protective film 130 may include forming a mask of a predetermined shape on the protective film 130 and etching the protective film 130 by exposing and developing the mask. The mask may be a photoresist. In step S109, the temperature at which the protective film 130 is heated and hardened, i.e., the curing temperature of the protective film 130, may be, for example, approximately 250 to 400 degrees. The thickness of the protective film 130 decreases as it hardens; for example, the thickness of 5 μm before hardening decreases to 4 μm after hardening.

[0051] Fig. 4 is a plan view showing an example of a patterned protective film 130 on the front surface 11 of the semiconductor wafer 10 in the method for manufacturing the semiconductor device 100 according to one embodiment. Fig. 5 is a plan view showing an example of a support table that supports the patterned protective film 130 on the front surface 11 of the semiconductor wafer 10 in the method for manufacturing the semiconductor device 100 according to one embodiment.

[0052] 5, the support base 152 has, as an example, a plurality of protrusions 151 on the surface that holds the patterned protective film 130 on the front surface 11 of the semiconductor wafer 10, and also has an annular protrusion 153 on the outer edge of the surface. The protrusions 151 may have a circular shape when viewed from above, as shown in FIG. 5, and in this case, the diameter of the circle, i.e., the maximum length D2 of the protrusions 151, may be just under 1 mm. The pitch of the plurality of protrusions 151 may be about 1 cm.

[0053] As shown in FIG. 4, the patterned protective film 130 has, for example, a plurality of protrusions 131 and a ring-shaped protrusion 133 surrounding the plurality of protrusions 131. The protrusions 131 may have a circular shape in a top view as shown in FIG. 4, for example. In this case, the diameter D1 of the circle may be the same as or different from the pitch P1 of the plurality of protrusions 131. The diameter D1 of the circle may be larger or smaller than the pitch P1 of the plurality of protrusions 131. The diameter D1 of the circle may be 3 μm or more and 0.2 mm or less. The pitch P1 of the plurality of protrusions 131 may be 20 μm or more and 0.3 mm or less.

[0054] Patterning the protective film 130 in step S107 may include leaving the protective film 130 at a pitch P1 of 20 μm or more and 0.3 mm or less, like the multiple protrusions 131 shown in Fig. 4. Patterning the protective film 130 may include leaving the protective film 130 so that the maximum length D1 of the pattern shape is 3 μm or more and 0.2 mm or less, like the multiple protrusions 131 shown in Fig. 4.

[0055] Patterning the protective film 130 may include leaving the protective film 130 so that the protection rate of the front surface 11 by the protective film 130 is 3% or more and 30% or less. Patterning the protective film 130 may include forming an annular pattern, for example, annular protrusions 133, on the front surface 11 corresponding to the annular protrusions 153 of the support base 152 shown in FIG. 5. The pitch P1 of the patterned protective film 130 may be less than the maximum length D2 of the protrusions 151 of the support base 152 shown in FIG. 5. This makes it easier for the protrusions 151 of the support base 152 to come into contact with the protective film 130.

[0056] The protective film 130 patterned in this manner can prevent the front surface structures, such as the emitter electrode and pad region, formed on the front surface 11 of the semiconductor wafer 10 from contacting the support base 152. In other words, the patterned protective film 130 can prevent the front surface structures from coming into contact with the support base 152 and being damaged.

[0057] 3 , in a vacuum chamber, the semiconductor wafer 10 is subjected to backside processing while the patterned protective film 130 on the front surface 11 is supported by the support table 152, the protective film 130 is removed in step S113, and various post-protective film removal processes are performed in step S115, after which the operational flow ends. In step S111, backside processing of the semiconductor wafer 10 may include backside processing of the semiconductor wafer 10 while the patterned protective film 130 is supported by the multiple protrusions 151 of the support table 152. Backside processing of the semiconductor wafer 10 includes ion implantation into the backside of the semiconductor wafer 10.

[0058] Fig. 6 is a flowchart showing an example of a subroutine of step S111 in the operational flow of Fig. 1. Details of step S111 in the manufacturing method of the semiconductor device 100 including the RC-IGBT will be described using Fig. 6.

[0059] In step S111, for example, a BG process for grinding the back surface 12 of the semiconductor wafer 10 is performed (step S131), B ions are implanted into the back surface 12 (step S133), the back surface 12 is patterned using, for example, photoresist (step S135), and cathode P ions are implanted into the back surface 12 (step S137). Furthermore, the resist on the back surface 12 is ashed (step S139), the back surface 12 is laser annealed (step S141), and protons are implanted into the back surface 12 (step S143), completing the process. In step S137, ion implantation of the cathode layer is performed only in the FWD region, so back surface patterning is performed in step S135. Ion implantation of the FS layer may also be performed in step S143. In step S111, at least in steps S133 and S137, the back surface 12 is vacuum-treated in a vacuum chamber. The remaining steps in step S111 may be performed in a non-vacuum state.

[0060] In the ion implantation step on the back surface 12, if the semiconductor device 100 has an IGBT, P+ may be implanted, if it has an RC-IGBT, P+ may be implanted all over the surface to become N+, if it has a MOSFET, N+ may be implanted, and if it has an FWD, N+ may be implanted.

[0061] Regarding the laser annealing in step S141, if the protective film 130 is a highly heat-resistant protective film such as polyimide, which has higher heat resistance than resist, the laser oscillation period of the laser annealing may be shortened compared to when resist is used. A highly heat-resistant protective film does not deteriorate like resist, even if the laser output is increased during the laser annealing process, and therefore the support pedestal 152 and other components are not contaminated or it becomes difficult to peel the protective film 130 from the support pedestal 152. For example, the laser output may be increased from 1 kHz to 3 kHz, shortening the laser oscillation period to one-third. This shortens the backside processing time and makes it possible to approximately double the throughput of manufacturing the semiconductor device 100.

[0062] Fig. 7 is a flowchart showing an example of a subroutine of step S115 in the operational flow of Fig. 1. Details of step S115 in the manufacturing method of the semiconductor device 100 including the RC-IGBT will be described using Fig. 7.

[0063] In step S115, for example, the front surface 11 of the semiconductor wafer 10 is proton-annealed (step S151), the front surface 11 is patterned for He using a resist (step S153), He is irradiated (step S155), and the resist is removed (step S157). Further, He annealing is performed (step S159), the back surface 12 is sputtered (step S161), the back surface 12 is annealed (step S163), and a plating process is performed (step S165), completing the process. After the protective film 130 is removed in step S113 by dissolution or peeling, an annealing process may be performed in step S151 to activate the ions implanted into the FS layer. Then, a back surface electrode may be formed in step S165 to complete the wafer process. In step S115, at least in step S161, the back surface 12 is vacuum-treated in a vacuum chamber, but the degree of vacuum is weaker than in step S111. In the back surface processing such as step S161 included in step S115, the support base 152 is not used, and the front surface structure of the front surface 11 is not damaged.

[0064] According to the manufacturing method of the semiconductor device 100 of this embodiment described above, the protective film 130 is applied to the front surface 11 of the semiconductor wafer 10, the protective film 130 is patterned, the semiconductor wafer 10 is subjected to a backside processing in a vacuum chamber while the patterned protective film 130 on the front surface 11 is supported by the support table 152, and then the protective film 130 is removed. According to the manufacturing method of the semiconductor device 100 of this embodiment, the amount of outgassing during the backside processing can be reduced compared to when the backside processing is performed without patterning the protective film 130, i.e., when the backside processing is performed without reducing the volume of the protective film 130 applied to the front surface 11. This eliminates the need for measures to prevent the semiconductor wafer 10 from jumping, as in the manufacturing method of the semiconductor device 101 of the comparative example, and prevents a decrease in throughput in the manufacturing of the semiconductor device 100.

[0065] The above-described effect of reducing the volume by patterning the protective film 130 can be particularly significant when polyimide is used as the protective film 130. Polyimide has a higher elastic modulus than resist and therefore is unlikely to get caught in the unevenness of the support base 152. As described above, this allows for increased laser output during laser annealing of the rear surface 12. However, since polyimide is more hygroscopic than resist, moisture evaporates from the polyimide film during ion implantation into the rear surface 12, i.e., the amount of degassing increases. Note that, as described above, the material for the protective film 130 is not limited to polyimide. A material for the protective film 130 that is unlikely to get caught in the unevenness of the support base 152 during ion implantation into the rear surface 12, can be patterned to reduce the effects of degassing, and allows for processes similar to those described above may be suitable.

[0066] FIG. 8 is a diagram illustrating an example of the arrangement of gate runners 48, well regions, and pad regions of a semiconductor device 100 in a top view. The semiconductor device 100 illustrated in FIG. 8 may be one of multiple semiconductor devices manufactured by dicing a semiconductor wafer 10 manufactured by the manufacturing method illustrated in FIG. 3. The semiconductor wafer 10 has an edge 108 in a top view. The semiconductor wafer 10 of this example has two pairs of edge sides 108 facing each other in a top view. FIG. 8 illustrates one pair of edge sides 108-1 and 108-2 facing each other. In FIG. 8, the direction parallel to edge sides 108-1 and 108-2 is the X-axis direction, and the direction perpendicular to edge sides 108-1 and 108-2 is the Y-axis direction.

[0067] The semiconductor wafer 10 has an active portion 110. In this example, the semiconductor wafer 10 has active portions 110-1 and 110-2. The active portion 110 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor wafer 10 when the semiconductor device 100 is controlled to an on state. Therefore, the active portion 110 may be a region inside the well region in FIG. 8 . The active portion 110 may be provided with a transistor portion including a transistor element such as an IGBT. The active portion 110 may be provided with a diode portion including a diode element such as an FWD. The active portion 110 may be a region in which at least one of a transistor portion and a diode portion is provided. As illustrated in FIG. 8 , in this example, the active portion 110 includes a transistor portion and a diode portion. The active portion 110 may be a region overlapping with a top surface main electrode in a top view. The top surface main electrode may be the electrode with the largest area in a top view among the electrodes arranged above the top surface of the semiconductor wafer 10. The upper main electrode may be electrically connected to, for example, the emitter region or source region of the transistor portion, or to the anode region of the diode portion. In the example of Figure 8, the emitter electrode 52 is the upper main electrode.

[0068] The semiconductor wafer 10 has a P-type well region. The well region is a P-type region with a higher concentration than the base region of the transistor section or the anode region of the diode section. The base region is a P-type region that is disposed opposite the gate electrode and in which a channel is formed in the portion facing the gate electrode when a predetermined gate voltage is applied to the gate electrode. The semiconductor device 100 has a first well region 111 and a second well region 112. The first well region 111 and the second well region 112 are disposed on either side of the active section 110 in a top view. The first well region 111 and the second well region 112 are disposed on either side of the active section 110 in a predetermined direction (the Y-axis direction in FIG. 8 ). The phrase "two well regions sandwich the active section 110" means that any line connecting the two well regions passes through the active section 110 in a top view.

[0069] The first well region 111 may be disposed near the edge 108-1. That is, the distance between the first well region 111 and the edge 108-1 is smaller than the distance between the first well region 111 and the edge 108-2. The second well region 112 may be disposed near the edge 108-2. That is, the distance between the second well region 112 and the edge 108-2 is smaller than the distance between the second well region 112 and the edge 108-1.

[0070] In this example, the first well region 111 is disposed between the active portion 110 and the edge 108-1 in the Y-axis direction. The active portion 110 is not provided between the first well region 111 and the edge 108-1. In other words, the first well region 111 is disposed between the end of the active portion 110 in the Y-axis direction and the edge 108-1.

[0071] In this example, the second well region 112 is disposed between the active portion 110 and the edge 108-2 in the Y-axis direction. The active portion 110 is not provided between the second well region 112 and the edge 108-2. In other words, the second well region 112 is disposed between the end of the active portion 110 in the Y-axis direction and the edge 108-2.

[0072] The first well region 111 and the second well region 112 may be provided in a range in the X-axis direction that includes a center position Xc between the end sides 108-1 and 108-2. The first well region 111 may be sandwiched between the active portions 110 in the X-axis direction. The second well region 112 may be sandwiched between the active portions 110 in the X-axis direction. The second well region 112 may be provided in a wider range in the X-axis direction than the first well region 111.

[0073] The semiconductor device 100 may have a peripheral well region 113 arranged to surround the active portion 110 in a top view. The peripheral well region 113 may be provided parallel to each edge of the semiconductor wafer 10. In this example, the peripheral well region 113 is an annular region surrounding the active portion 110 in a top view. The width of the peripheral well region 113 may be constant in a direction perpendicular to each edge.

[0074] In this example, the first well region 111 and the second well region 112 protrude further toward the center of the active portion 110 than the peripheral well region 113. In another example, at least one of the first well region 111 and the second well region 112 may be disposed between the peripheral well region 113 and the edge 108 of the semiconductor wafer 10. In this case, the first well region 111 and the second well region 112 protrude from the peripheral well region 113 toward the edge 108.

[0075] The semiconductor device 100 may have divided well regions 114 that divide the active section 110 in a top view. The active section 110 may be divided into active sections 110-1 and 110-2 by well regions including the divided well regions 114. The divided well regions 114 have a longitudinal direction in a predetermined well longitudinal direction. The divided well regions 114 extend in the well longitudinal direction and cross the active section 110. The well longitudinal direction of the divided well regions 114 is the Y-axis direction.

[0076] The divided well region 114 may be provided between the first well region 111 and the second well region 112. One longitudinal end of the divided well region 114 may be connected to the first well region 111, and the other longitudinal end may be connected to the second well region 112. The divided well region 114 may be provided in a region overlapping with the center of the active portion 110.

[0077] The divided well region 114 may have a wide portion 115 whose width in a direction perpendicular to the longitudinal direction of the well (in this example, the X-axis direction) in a top view is wider than other portions. The wide portion 115 is also provided between the first well region 111 and the second well region 112. The wide portion 115 may be provided in a region overlapping with the center of the active portion 110. The wide portion 115 may be arranged in a region including the center of the divided well region 114 in the longitudinal direction of the well.

[0078] The semiconductor device 100 of this example has control electrodes such as a gate pad 50, a current detection pad 172, an anode pad 174, and a cathode pad 176. The gate pad 50, the current detection pad 172, the anode pad 174, and the cathode pad 176 are each an example of a pad region.

[0079] The temperature sensing section 178 is a PN junction diode made of a semiconductor material such as polysilicon. The temperature sensing section 178 is disposed above the wide section 115. That is, at least a portion of the temperature sensing section 178 overlaps with at least a portion of the wide section 115. In this example, more than half of the temperature sensing section 178 overlaps with the wide section 115 when viewed from above. The entire temperature sensing section 178 may overlap with the wide section 115.

[0080] The emitter electrode 52 and each control electrode are electrodes containing a metal such as aluminum. An insulating film is provided between the emitter electrode 52 and each control electrode and the semiconductor wafer 10. The emitter electrode 52 and each control electrode are connected to the semiconductor wafer 10 via contact holes provided in the insulating film. The insulating film and contact holes are omitted from Figure 8.

[0081] The emitter electrode 52 is disposed above the active section 110. The emitter electrode 52 is connected to the active section 110 via the contact hole described above. A wiring member is connected to the upper surface of the emitter electrode 52, and a predetermined emitter voltage is applied thereto. The emitter electrode 52 and each control electrode are provided separately from each other in a top view. A wire or the like is connected to the upper surface of each control electrode. An emitter electrode 52 may be provided for each of the active sections 110-1 and 110-2.

[0082] A predetermined gate voltage is applied to the gate pad 50. The gate voltage applied to the gate pad 50 is supplied to the transistor portion of the active portion 110 by a gate runner or the like, which will be described later. The gate pad 50 is disposed above the first well region 111. That is, at least a portion of the gate pad 50 overlaps with at least a portion of the first well region 111. In this example, more than half of the gate pad 50 in top view overlaps with the first well region 111. The entire gate pad 50 may overlap with the first well region 111. In this example, the gate pad 50 may be disposed near an edge 108-1 of the semiconductor device 100. That is, the gate pad 50 is disposed between the emitter electrode 52 and the edge 108-1 of the semiconductor device 100, and the emitter electrode 52 is not disposed between the gate pad 50 and the edge 108-1. Furthermore, the gate pad 50 may be disposed in a region including the center position Xc of the edge 108-1 of the semiconductor device 100 in the X-axis direction.

[0083] The current detection pad 172 is connected to a current detection unit (not shown) and detects a current flowing through the current detection unit. The anode pad 174 is connected to the anode region of the temperature sensing unit 178 via wiring. The cathode pad 176 is connected to the cathode region of the temperature sensing unit 178 via wiring. The current detection pad 172, anode pad 174, and cathode pad 176 are disposed above the second well region 112. At least a portion of the control electrode of each of the current detection pad 172, anode pad 174, and cathode pad 176 overlaps with at least a portion of the second well region 112. In this example, more than half of the current detection pad 172, anode pad 174, and cathode pad 176 overlap with the second well region 112 when viewed from above. The current detection pad 172, anode pad 174, and cathode pad 176 may entirely overlap with the second well region 112. In this example, the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 may be disposed near the edge 108-2 of the semiconductor device 100. That is, the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 are disposed between the emitter electrode 52 and the edge 108-2 of the semiconductor device 100, with no emitter electrode 52 disposed between each control electrode and the edge 108-2. Furthermore, each control electrode may be disposed in a region including the center position Xc in the X-axis direction of the edge 108-2 of the semiconductor device 100. In this example, the gate pad 50 and the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 may be disposed on opposing edge edges 108-1 and 108-2 of the semiconductor device 100, respectively. Furthermore, they may be disposed opposite each other with the divided well region 114 interposed therebetween.

[0084] 8, the gate runner 48 is indicated by a dashed line. The gate runner 48 is a wiring formed of a conductive material such as impurity-doped polysilicon or metal. The gate runner 48 supplies a gate voltage applied to the gate pad 50 to a transistor portion provided in the active portion 110. The gate runner 48 may be disposed above the well region.

[0085] The semiconductor device 100 may have a gate runner 48-3 arranged to surround the active portion 110 in a top view. The gate runner 48-3 may be arranged above the peripheral well region 113.

[0086] The semiconductor device 100 may have a gate runner 48-1 that surrounds at least a portion of the first well region 111 in a top view. The gate runner 48-1 may be arranged along the edges of the first well region 111 in a top view. The gate runner 48-1 may have portions that are parallel to each edge of the first well region 111.

[0087] The semiconductor device 100 may have a gate runner 48-2 that surrounds at least a portion of the second well region 112 in a top view. The gate runner 48-2 may be arranged along the edges of the second well region 112 in a top view. The gate runner 48-2 may have portions that are parallel to each edge of the second well region 112.

[0088] The semiconductor device 100 may have a gate runner 48-4 arranged above the divided well region 114 in a top view. The semiconductor device 100 may have a gate runner 48-5 surrounding at least a portion of the wide portion 115 in a top view. The gate runner 48-5 may be arranged along the edges of the wide portion 115 in a top view. The gate runner 48-5 may have portions parallel to each edge of the wide portion 115. The gate runner 48-4 and the gate runner 48-5 may divide the active portion 110 in a top view.

[0089] The semiconductor device 100 may include an edge termination structure between the peripheral well region 113 and the edge of the semiconductor wafer 10. The edge termination structure relieves electric field concentration on the top surface side of the semiconductor wafer 10. The edge termination structure may include, for example, a guard ring, a field plate, a resurf, or a combination of these, arranged in an annular shape surrounding the active region 110.

[0090] 9 is a diagram showing an example of the arrangement of the passivation film 120 in a top view of the semiconductor device 100. In FIG. 9, the region where the passivation film 120 is arranged is indicated by hatching with oblique lines.

[0091] The semiconductor device 100 may have a passivation film 120-1 that covers the first well region 111. The passivation film 120-1 may expose a part of the upper surface of the gate pad 50. This allows a wire or the like to be connected to the upper surface of the gate pad 50.

[0092] The semiconductor device 100 may have a passivation film 120-2 that covers the second well region 112. The passivation film 120-2 may expose portions of the upper surfaces of the current detection pad 172, the anode pad 174, and the cathode pad 176. This allows wires and the like to be connected to the upper surfaces of the current detection pad 172, the anode pad 174, and the cathode pad 176.

[0093] The semiconductor device 100 may have a passivation film 120-3 that covers the peripheral well region 113. The passivation film 120-3 may cover the entire peripheral well region 113. The semiconductor device 100 may have a passivation film 120-4 and a passivation film 120-7 that cover the divided well region 114. The divided well region 114 may be entirely covered by the passivation film 120-4 and the passivation film 120-7. In this example, the passivation film 120-4 covers the entire wide portion 115, and the passivation film 120-7 covers the entire divided well region 114 except for the wide portion 115.

[0094] The passivation film 120 exposes a part of the upper surface of the emitter electrode 52. This allows wires or the like to be easily connected to the upper surface of the emitter electrode 52.

[0095] The semiconductor device 100 may have a passivation film 120-5 and a passivation film 120-6 that divide the upper surface of the semiconductor wafer 10. The passivation film 120-5 and the passivation film 120-6 may be provided across the upper surface of the semiconductor wafer 10 in the X-axis direction.

[0096] In summary, the passivation film 120 is not provided over the entire semiconductor wafer 10. In other words, a predetermined pattern is formed on the passivation film 120. The passivation film 120 exposes part of the upper surface of the emitter electrode 52, part of the pads, etc.

[0097] FIG. 10 is a diagram showing an example of the arrangement of a resist 150 used when patterning the passivation film 120. The resist 150 covers the passivation film 120-1, the passivation film 120-2, the passivation film 120-3, the passivation film 120-4, the passivation film 120-5, the passivation film 120-6, and the passivation film 120-7 shown in FIG. 9. Therefore, a predetermined pattern as shown in FIG. 9 can be formed in the passivation film 120. Furthermore, the portion of the passivation film 120 not covered by the resist 150 is removed. The resist 150 may include a photosensitive material.

[0098] 11 is a diagram showing an example of a cross section of the semiconductor device 100 in the active portion 110. This cross section is an XZ plane passing through the emitter region 13 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor wafer 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0099] The transistor section 70 has a P+ type collector region 22 in a region that contacts the lower surface of the semiconductor wafer 10. The transistor section 70 also has a gate structure that is periodically arranged on the upper surface side of the semiconductor wafer 10, the gate structure having an N type emitter region 13, a P type base region 14, a contact region 15, a gate conductive portion, and a gate insulating film.

[0100] The diode section 80 has an N+ type cathode region 82 in a region that contacts the underside of the semiconductor wafer 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided on the underside of the semiconductor wafer 10 in a region other than the cathode region.

[0101] The interlayer insulating film 38 is provided on the upper surface of the semiconductor wafer 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38.

[0102] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor wafer 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor wafer 10. The collector electrode 24 is made of a metal material such as aluminum.

[0103] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction (the X-axis direction in this example). In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are periodically provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0104] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor wafer 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor wafer 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor wafer 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0105] Each mesa portion is provided with a base region 14. The mesa portion 60 of the transistor portion 70 has an emitter region 13 exposed on the upper surface 21 of the semiconductor wafer 10. The emitter region 13 is provided in contact with the gate trench portion 40. Furthermore, the mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface 21 of the semiconductor wafer 10.

[0106] As an example, the contact region and emitter region 13 of the mesa portion 60 are provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. That is, the emitter region 13 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 13.

[0107] In another example, the contact regions 15 and the emitter regions 13 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. In this case, the contact regions 15 and the emitter regions 13 in the mesa portion 60 may be alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0108] The mesa portion 61 of the diode section 80 is not provided with the emitter region 13. The mesa portion 61 may have a base region 14 and a contact region 15 provided on its upper surface.

[0109] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. The accumulation region 16 may also be provided only in the transistor portion 70.

[0110] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided on the lower surface 23 side of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0111] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0112] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor of each region are not limited to the examples described above.

[0113] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor wafer 10. Each trench extends from the top surface 21 of the semiconductor wafer 10, penetrating the base region 14, and reaching the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0114] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor wafer 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and on the inner side of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor wafer 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0115] The gate conductive portion 44 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor wafer 10. The gate conductive portion 44 is electrically connected to a gate runner 48. The gate conductive portion 44 may be connected to a gate pad 50. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0116] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor wafer 10. The dummy conductive portion 34 may be connected to an electrode different from the gate pad 50. For example, the dummy conductive portion 34 may be connected to a dummy pad (not shown) that is connected to an external circuit different from the gate pad 50, and controlled differently from the gate conductive portion 44. The dummy conductive portion 34 may also be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor wafer 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is made of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0117] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor wafer 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0118] The lifetime control section 74 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate. The lifetime killer is a carrier recombination center, and may be a crystal defect, a vacancy, a divacancy, a complex defect formed by these with elements constituting the semiconductor wafer 10, a dislocation, a rare gas element such as helium or neon, or a metal element such as platinum. The lifetime control section 74 can be formed by injecting helium or the like into the semiconductor wafer 10.

[0119] Figure 12 shows the relationship between the number of processed wafers and the presence or absence of bounce countermeasures, the beam current, and the number of wafers processed. The bounce countermeasure is to provide a waiting time before dechucking, as in the comparative example shown in Figure 2. The beam current is the output of the beam current during ion implantation.

[0120] 12, for the same beam current, the number of wafers processed without anti-bounce measures is greater than the number processed with anti-bounce measures. This is because the anti-bounce measures require a waiting time before dechucking, which increases the processing time. The amount of outgassing from the patterned protective film 130 in the method for manufacturing the semiconductor device 100 according to this embodiment is less than the amount of outgassing from the unpatterned protective film 130 in the method for manufacturing the semiconductor device 101 according to the comparative example. Therefore, there is no need to implement anti-bounce measures, and throughput can be improved.

[0121] In addition, by increasing the output of the beam current during ion implantation, the number of wafers that can be processed can be increased. In this embodiment, the support table 152 has an uneven upper surface 154, which allows a cooling gas to flow between the semiconductor wafer 10 and the support table, thereby increasing the output of the beam current during ion implantation.

[0122] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0123] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0124] 10 Semiconductor wafers 11 Front 12 Back side 13 Emitter area 14 Base Area 15 Contact Area 16 Accumulation area 18 Drift Region 20 buffer space 21 Top side 22 Collector region 23 Bottom surface 24 Collector electrode 30 Dummy trench section 32 Dummy insulating film 34 Dummy conductive part 38 Interlayer insulating film 40 Gate trench section 42 Gate insulating film 44 Gate conductive part 48 Gate Runner 50 Gate Pad 52 Emitter electrode 54 Contact Hole 60 Mesa 61 Mesa 70 Transistor section 74 Lifetime control section 80 Diode section 82 Cathode region 100, 101 semiconductor device 108 Edge 110 Active part 111 First well region 112 Second well region 113 Peripheral well area 114 Divided well area 115 Wide section 120 Passivation Film 130 Protective film 131 Convex part 133 Annular convex part 138 Resist 140 Resist 152 Support stand 151 Convex part 153 Annular convex part 154 Top surface 160 Gas 172 Current Sense Pad 174 anode pad 176 cathode pad 178 Temperature sensor 252 Surplus outer area 254 areas

Claims

1. applying a protective film to a front surface of the semiconductor wafer; patterning the protective film; performing back surface processing on the semiconductor wafer in a vacuum chamber while the patterned protective film on the front surface is supported by a support table; removing the protective film after the back surface of the semiconductor wafer is processed; A method for manufacturing a semiconductor device comprising:

2. the backside processing includes ion implanting the backside of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1 .

3. The protective film is polyimide. The method for manufacturing a semiconductor device according to claim 1 .

4. forming a front surface structure on the front surface of the semiconductor wafer; forming a passivation film over the front surface structure; Equipped with applying the protective film to the front surface of the semiconductor wafer includes applying the protective film above the passivation film; The protective film is thinner than the passivation film. The method for manufacturing a semiconductor device according to claim 1 .

5. The thickness of the protective film is 2 μm or more and 5 μm or less. The method for manufacturing a semiconductor device according to claim 4 .

6. The protective film has a glass transition temperature of 200°C or higher. The method for manufacturing a semiconductor device according to claim 1 .

7. The thermal decomposition temperature of the protective film is 300°C or higher and 600°C or lower. The method for manufacturing a semiconductor device according to claim 1 .

8. The patterning of the protective film includes: forming a mask having a predetermined shape on the protective film; Etching the protective film using the mask; The method for manufacturing a semiconductor device according to claim 1 , comprising:

9. The mask is a photoresist. The method for manufacturing a semiconductor device according to claim 8 .

10. heating the protective film after patterning the protective film. The method for manufacturing a semiconductor device according to claim 8 .

11. patterning the protective film includes leaving the protective film at a pitch of 20 μm or more and 0.3 mm or less; The method for manufacturing a semiconductor device according to claim 1 .

12. patterning the protective film includes leaving the protective film so that the maximum length of the shape is 3 μm or more and 0.2 mm or less; The method for manufacturing a semiconductor device according to claim 1 .

13. patterning the protective film includes leaving the protective film so that a protection rate of the front surface by the protective film is 3% or more and 30% or less; The method for manufacturing a semiconductor device according to claim 1 .

14. the support base has a plurality of protrusions on a surface that holds the patterned protective film on the front surface, the rear surface processing includes processing the rear surface of the semiconductor wafer in a state in which the patterned protective film is supported by the plurality of convex portions. The method for manufacturing a semiconductor device according to claim 1 .

15. the pitch of the patterned protective film is less than the maximum length of the convex portions; The method for manufacturing a semiconductor device according to claim 14.

16. the support base has an annular protrusion on an outer edge side of a surface that holds the patterned protective film on the front surface, patterning the protective film includes forming an annular pattern on the front surface corresponding to the annular protrusion; The method for manufacturing a semiconductor device according to claim 14.

Images