semiconductor memory device

Abstract

To improve the driving speed of a semiconductor memory device. [Solution] A semiconductor memory device according to an embodiment includes a first wiring layer arranged across first and second regions arranged in the X direction, a second wiring layer arranged and spaced apart from the first wiring layer in the Z direction, multiple third wiring layers arranged on the opposite side of the second wiring layer from the first wiring layer and spaced apart from each other in the Z direction, first and second members arranged in the Y direction and each extending in the X direction to divide the first and multiple third wiring layers in the Y direction, a third member arranged between the first and second members and dividing the second wiring layer in the Y direction, first and second memory pillars each extending in the Z direction between the first and third members in the second region and between the second and third members, and first and second contacts extending in the Z direction in the first region, wherein the second wiring layer has first and second terrace portions that contact the first and second members, respectively, and do not overlap with the multiple third wiring layers when viewed in the Z direction, and the first and second contacts are electrically connected to the first and second terrace portions, respectively.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory often employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0208780 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the driving speed of a semiconductor memory device. [Means for solving the problem]

[0005] The semiconductor memory device according to the embodiment includes, as viewed in a first direction, a first wiring layer provided across a first region and a second region that are aligned in a second direction intersecting the first direction; a second wiring layer that is aligned and spaced apart from the first wiring layer in the first direction; a plurality of third wiring layers that are provided on the opposite side of the second wiring layer to the first wiring layer and spaced apart from each other in the first direction; first insulating members and second insulating members that are aligned in a third direction intersecting the first and second directions and each extend in the second direction to divide the second wiring layer and the plurality of third wiring layers in the third direction; third insulating members that are provided between the first insulating member and the second insulating member and between the first wiring layer and the plurality of third wiring layers and divide the second wiring layer into a first portion and a second portion in the third direction; and third insulating members that extend in the first direction between the first insulating member and the third insulating member in the second region, contact the first wiring layer, and intersect each of the plurality of third wiring layers. a first memory pillar whose portions intersecting the first insulating member and the third insulating member function as a plurality of first memory cells; a second memory pillar whose portions intersecting the second insulating member and the third insulating member function as a plurality of second memory cells; and a first contact and a second contact extending in the first direction in the first region, wherein the second wiring layer has, in a first portion within the first region, a first terrace portion that contacts the first insulating member and does not overlap with the plurality of third wiring layers when viewed in the first direction, and a second terrace portion that contacts the second insulating member and does not overlap with the plurality of third wiring layers when viewed in the first direction, in a second portion within the first region, wherein the first contact is electrically connected to the first terrace portion of the second wiring layer, and the second contact is electrically connected to the second terrace portion of the second wiring layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 3 is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment. [Figure 4] FIG. 4 is a perspective view showing an outline of a laminated structure of the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 5 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 6 is a plan view showing an example of a planar layout of a memory region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure in a memory region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a memory pillar included in the semiconductor memory device according to the first embodiment. [Figure 9] FIG. 9 is a plan view showing an example of a planar layout of a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 10 is a plan view showing an example of a planar layout of select gate lines SGSa in a lead-out region of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIGS. 9 and 10 in the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing an example of a first manufacturing process of the SGS separation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing an example of a first manufacturing process of the SGS separation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing an example of a second manufacturing process of the SGS separation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing an example of a second manufacturing process of the SGS separation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 16]FIG. 16 is a plan view showing an example of a planar layout of select gate lines SGSa in a lead-out region of a memory cell array included in a semiconductor memory device according to a first modification of the first embodiment. [Figure 17] FIG. 17 is a plan view showing an example of a planar layout of a lead-out region of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 18] FIG. 18 is a plan view showing an example of a planar layout of a lead-out region of a memory cell array included in a semiconductor memory device according to a first modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element via an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will be described. FIG. 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. The memory system 1 is a memory device configured to be connected to an external host device (not shown). The memory system 1 is, for example, a storage device such as an SD TM The memory system 1 includes a memory controller 2 and a semiconductor memory device 3. The memory system 1 may be a memory card such as a card, a Universal Flash Storage (UFS), or a Solid State Drive (SSD).

[0010] The memory controller 2 is configured by an integrated circuit such as an SoC (System on a Chip). The memory controller 2 controls the semiconductor memory device 3 based on a request from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. In addition, the memory controller 2 reads data requested to be read by the external host device from the semiconductor memory device 3 and outputs the data to the external host device.

[0011] The semiconductor memory device 3 is, for example, a NAND flash memory that can store data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the semiconductor memory device 3 complies with, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0013] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 3 according to the first embodiment, with reference to the block diagram shown in Fig. 1, the semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] The memory cell array 10 is a set of memory cell transistors and a collection of components connected to the memory cell transistors. The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cell transistors capable of storing data in a non-volatile manner. The block BLK is used, for example, as an erase unit when erasing data stored in the memory cell transistors. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with, for example, a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals with the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs the data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 outputs each of the command CMD and address information ADD transferred from the memory controller 2 to the register 13. The input / output circuit 11 outputs the status information STA transferred from the register 13 to the memory controller 2.

[0016] The logic control circuit 12 receives a control signal input from the memory controller 2. The logic control circuit 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command CMD, address information ADD, or the like. The logic control circuit 12 instructs the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. In addition, the logic control circuit 12 outputs a signal indicating whether the semiconductor memory device 3 is in a ready state or a busy state to the memory controller 2.

[0017] The register 13 temporarily stores a command CMD, address information ADD, and status information STA. The command CMD includes, for example, an instruction to cause the sequencer 14 to perform a read operation, a write operation, an erase operation, etc. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively. The status information STA is updated under the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc. based on the command CMD stored in the register 13, and executes a read operation, a write operation, an erase operation, etc.

[0019] The driver module 15 generates a plurality of voltages of different magnitudes to be used in read operations, write operations, erase operations, etc. The driver module 15 supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to a signal line corresponding to a word line selected based on a page address PA stored in the register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based on, for example, a block address BA stored in the register 13. The row decoder module 16 transfers, for example, a voltage of a signal line applied by the driver module 15 to a selected word line in the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of an associated bit line, a latch circuit for temporarily storing data, and the like. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line in accordance with write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the voltage of the bit line. Then, the sense amplifier module 17 transfers the determination result to the input / output circuit 11 as read data DAT.

[0022] 1.1.3 Memory cell array circuit configuration 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. Fig. 2 shows block BLK0. Block BLK0 includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes a plurality of NAND strings NS associated with respective bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data in a nonvolatile manner based on the amount of charge in the charge storage film. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0024] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series in this order. The drain of the select transistor ST1 is connected to the associated bit line BL, and the source of the select transistor ST1 is connected to the drain of the memory cell transistor MT7. The drain of the select transistor ST2 is connected to the source of the memory cell transistor MT0, and the source of the select transistor ST2 is connected to the source line SL.

[0025] The control gates of memory cell transistors MT0 to MT7 in the same block BLK are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of select transistor ST2 in string units SU0 to SU1 are connected to select gate line SGS0. The gates of select transistor ST2 in string units SU2 to SU3 are connected to select gate line SGS1.

[0026] A different column address CA is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same column address CA among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0027] A collection of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to be any number. However, it is preferable that the number of string units SU included in each block BLK is an even number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0029] 1.1.4 Appearance of semiconductor memory device The semiconductor memory device 3 according to the first embodiment is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. That is, the semiconductor memory device 3 according to the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is, for example, a silicon substrate. The following describes a case in which the semiconductor substrate W2 is removed during the manufacturing process of the semiconductor memory device 3. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after bonding.

[0030] 3 is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment. Hatching is added to FIG. 3 to improve the visibility of the drawing, but does not necessarily relate to the materials or characteristics of the hatched components. As shown in FIG. 3, the semiconductor memory device 3 has a structure in which, for example, a semiconductor substrate W1, a control circuit layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300 are stacked in this order.

[0031] In the following description, the plane in which the semiconductor substrate W1 extends is referred to as the XY plane. Of the directions in which the laminated structure is stacked, the direction from the semiconductor substrate W1 toward the wiring layer 300 is referred to as the Z1 direction, and the direction from the wiring layer 300 toward the semiconductor substrate W1 is referred to as the Z2 direction. The Z1 direction and the Z2 direction are approximately perpendicular to the semiconductor substrate W1. When the Z1 direction and the Z2 direction are not distinguished, each of the Z1 direction and the Z2 direction will simply be referred to as the Z direction.

[0032] The control circuit layer 100 includes a control circuit formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions and the like according to the design of the control circuit. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0033] The bonding layer B1 is formed using the semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the control circuit provided in the control circuit layer 100 and form part of the semiconductor circuit.

[0034] The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 provided in the memory layer 200 and form part of a semiconductor circuit.

[0035] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2 (not shown).

[0036] The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2. The wiring layer 300 includes wiring connected to the semiconductor circuits provided in the memory layer 200 and a plurality of pads PD. The pads PD are exposed on the surface of the semiconductor memory device 3. The pads PD are used to connect the semiconductor memory device 3 to the memory controller 2, etc.

[0037] 4 is a perspective view showing an outline of the bonding structure of the semiconductor memory device according to the first embodiment. The bonding of the semiconductor substrates W1 and W2 will be described with reference to FIG.

[0038] 4, a plurality of bonding pads BP1 included in bonding layer B1 and a plurality of bonding pads BP2 included in bonding layer B2 are connected to each other. As a result, the control circuit provided in control circuit layer 100 and the memory cell array 10 provided in memory layer 200 are electrically connected to each other via the bonding pads BP1 and BP2. The space between bonding layers B1 and B2 corresponds to the boundary between a layer formed using semiconductor substrate W1 and a layer formed using semiconductor substrate W2 (not shown).

[0039] 1.1.5 Memory Cell Array Structure An example of the structure of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment will be described below. In the following description, the X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. A plane extending in the X and Z directions is referred to as the XZ plane. A plane extending in the Y and Z directions is referred to as the YZ plane. Hatching is added appropriately in the plan view to improve the visibility of the drawing. Hatching added in the plan view does not necessarily relate to the material or properties of the components to which the hatching is added. In the cross-sectional view, illustration of the configuration is omitted appropriately to improve the visibility of the drawing.

[0040] 1.1.5.1 Overview FIG. 5 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. Areas corresponding to six blocks BLK0 to BLK5 are shown in FIG. 5. Serial numbers at the end for distinguishing the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in FIG. 5 is repeatedly arranged in the Y direction. As shown in FIG. 5, the memory cell array 10 includes a plurality of members SLT and a plurality of members SHE. The planar layout of the memory cell array 10 is divided, for example, in the X direction into memory areas MA1 and MA2 and a lead-out area HA. ​​The lead-out area HA is provided between the memory areas MA1 and MA2.

[0041] The memory areas MA1 and MA2 are areas used for storing data and include multiple NAND strings NS. The lead-out area HA is an area used for connecting the row decoder module 16 to stacked wiring formed by stacking multiple wiring layers (e.g., word lines WL0 to WL7 and select gate lines SGS0, SGS1, and SGD) spaced apart from each other in the Z direction.

[0042] The multiple members SLT each extend along the X direction and are aligned in the Y direction. Each member SLT crosses the memory areas MA1 and MA2 in the X direction in the boundary region between adjacent blocks BLK. In other words, each region separated by the member SLT corresponds to one block BLK in the memory cell array 10. Each member SLT has a structure in which, for example, an insulator and a plate-shaped contact are embedded. Each member SLT separates adjacent stacked wirings via the member SLT.

[0043] 5, in this embodiment, among the multiple components SLT lined up in the Y direction, the components SLT arranged in odd numbers counting from the top of the page are referred to as “SLTo,” and the components SLT arranged in even numbers are referred to as “SLTe.” In the memory cell array 10, multiple pairs of the components SLTo and SLTe are lined up in the Y direction.

[0044] A plurality of SHE elements are arranged in each of the memory regions MA1 and MA2. The plurality of SHE elements corresponding to the memory region MA1 are arranged across the memory region MA1 in the X direction and aligned in the Y direction. The plurality of SHE elements corresponding to the memory region MA2 are arranged across the memory region MA2 in the X direction and aligned in the Y direction. The right end of each SHE element corresponding to the memory region MA1 and the left end of each SHE element corresponding to the memory region MA2 are included in the lead-out region HA. For example, in each of the memory regions MA1 and MA2, three SHE elements are arranged between adjacent SLT elements in the Y direction. A combination of each of the regions partitioned by the elements SLT and SHE in the memory region MA1 and each of the regions partitioned by the elements SLT and SHE in the memory region MA2 corresponds to one string unit SU in the memory cell array 10. Each SHE element has, for example, a structure in which an insulator is embedded. Each SHE element separates adjacent select gate lines SGD via the SHE element.

[0045] The planar layout of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number. The number of string units SU formed between adjacent components SLT can be changed based on the number of components SHE arranged between adjacent components SLT. The number of string units SU formed between adjacent components SLT is preferably an even number. In other words, the number of components SHE in one block BLK is preferably an odd number.

[0046] The lead region HA includes a plurality of lead portions HP1 and HP2. Each of the lead portions HP1 and HP2 is provided with a connection portion with a contact in each wiring layer of the stacked wiring. The lead portions HP1 are aligned in the Y direction and are provided for two blocks BLK adjacent in the Y direction with a member SLTo sandwiched between them. In other words, each lead portion HP1 is provided in the lead region HA so as to be sandwiched between two members SLTe that sandwich two adjacent blocks BLK. Each lead portion HP2 is aligned in the Y direction and is provided for two blocks BLK adjacent in the Y direction with a member SLTe sandwiched between them. In other words, each lead portion HP2 is provided in the lead region HA so as to be sandwiched between two members SLTo that sandwich two adjacent blocks BLK.

[0047] The lead-out region HA includes multiple bridge portions BRG. Each bridge portion BRG is provided for each block BLK. In each bridge portion BRG, a portion of each wiring layer of the stacked wiring provided in the memory region MA1 and a portion of each wiring layer of the stacked wiring provided in the memory region MA2 are connected to each other. Each bridge portion BRG includes a first portion BRGa provided between the lead-out portion HP1 and the component SLTe so as to be sandwiched between them in the Y direction, a second portion BRGb provided between the lead-out portion HP2 and the component SLTo so as to be sandwiched between them in the Y direction, and a third portion BRGc provided between the lead-out portion HP1 and the lead-out portion HP2 so as to be sandwiched between them in the X direction and connecting the first portion BRGa and the second portion BRGb. Each bridge portion BRG has, for example, an S-shape.

[0048] 1.1.5.2 Memory Area (flat layout) 6 is a plan view showing an example of a planar layout in a memory region of a memory cell array included in a semiconductor memory device according to the first embodiment. While FIG. 6 shows the structure of one block BLK in memory region MA1 as a representative, the structure of memory region MA2 is similar to that of memory region MA1. As shown in FIG. 6, in memory regions MA1 and MA2, the memory cell array 10 includes multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL. Furthermore, each member SLT includes a contact LI and a spacer SP.

[0049] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the Y direction in the region between two adjacent members SLT. In the example shown in FIG. 6, one member SHE overlaps each of the memory pillars MP in the fifth, tenth, and fifteenth rows counting from the top of the page.

[0050] The multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example shown in FIG. 6, two bit lines BL are arranged so as to overlap one memory pillar MP. When multiple bit lines BL overlap a memory pillar MP, one of the multiple bit lines BL is electrically connected to the corresponding memory pillar MP via a contact CV. Note that when only one bit line BL overlaps a memory pillar MP, the bit line BL is electrically connected to the corresponding memory pillar MP via a contact CV.

[0051] For example, the contact CV between the memory pillar MP in contact with the member SHE and the corresponding bit line BL is omitted. In other words, the contact CV between the memory pillar MP in contact with two different select gate lines SGD and the bit line BL is omitted. The number and arrangement of the memory pillar MP, member SHE, etc. between adjacent members SLT are not limited to the configuration shown in FIG. 6 and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0052] The contact LI is a conductor extending in the XZ plane. The lower surface of the contact LI is in contact with a source line SL (not shown). The spacer SP is an insulator provided on the side surface of the contact LI. In other words, the spacer SP is provided in contact with the contact LI so as to sandwich the contact LI in the Y direction.

[0053] (Cross-sectional structure) 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure in a memory region of the memory cell array included in the semiconductor memory device according to the first embodiment. As shown in FIG. 7, the memory cell array 10 further includes wiring layers 21-25, insulator layers 40-46, and a member SSE. In the following description, the Z2 direction is defined as the upward direction, and the Z1 direction is defined as the downward direction.

[0054] The stacked wiring included in the memory cell array 10 includes a wiring layer 22 corresponding to the select gate lines SGS0 and SGS1, a plurality of wiring layers 23 corresponding to the word lines WL0 to WL7, and a wiring layer 24 corresponding to the select gate line SGD. Hereinafter, when there is no need to distinguish between the select gate lines SGS0 and SGS1, they will simply be referred to as the select gate line SGS.

[0055] In the example shown in FIG. 7, two wiring layers 22 corresponding to the select gate line SGS are provided. In the following description, the select gate line SGS corresponding to the upper wiring layer 22 is referred to as the select gate line SGSa, and the select gate line SGS corresponding to the lower wiring layer 22 is referred to as the select gate line SGSb. The select gate lines SGSa and SGSb are connected to the gates of the select transistors ST2a and ST2b, respectively. The select transistors ST2a and ST2b function as one select transistor ST2. The wiring layer 22 corresponding to the select gate line SGS may be one layer or may be three or more layers. Furthermore, when the wiring layer 22 corresponding to the select gate line SGS is formed from multiple layers, the select transistors ST2a and ST2b may be configured to function independently.

[0056] An insulator layer 41 is stacked above a semiconductor substrate W2 (not shown), and a plurality of wiring layers 22 and a plurality of insulator layers 42 are stacked alternately above the semiconductor substrate W2 (not shown). In the example shown in FIG. 7, two wiring layers 22 and two insulator layers 42 are stacked alternately. The plurality of wiring layers 22 are formed, for example, in a plate shape extending along the X direction on the XY plane. Each of the wiring layers 22 is used as a select gate line SGSa or SGSb. Each of the wiring layers 22 contains, for example, tungsten (W). The insulator layer 41 and each of the plurality of insulator layers 42 contain, for example, silicon oxide (SiO).

[0057] A plurality of wiring layers 23 and a plurality of insulator layers 43 are alternately stacked above the uppermost insulator layer 42. In the example shown in FIG. 7, eight wiring layers 23 and seven insulator layers 43 are alternately stacked. Each wiring layer 23 is formed, for example, in the shape of a plate extending along the X direction on the XY plane. The wiring layers 23 are used as word lines WL0 to WL7, respectively, in order from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten. Each insulator layer 43 contains, for example, silicon oxide.

[0058] An insulator layer 44, a wiring layer 24, and an insulator layer 45 are stacked in this order above the uppermost wiring layer 23. The wiring layer 24 is formed, for example, in a plate shape extending along the X direction on the XY plane. The wiring layer 24 is used as a select gate line SGD. The wiring layer 24 contains, for example, tungsten. The insulator layers 44 and 45 contain, for example, silicon oxide.

[0059] The wiring layer 25 is stacked above the insulating layer 45. The wiring layer 25 is formed, for example, in a line shape extending along the Y direction. The wiring layer 25 is used as a bit line BL. In a region not shown, multiple wiring layers 25 are lined up along the X direction. The wiring layer 25 includes, for example, copper.

[0060] An insulating layer 46 is laminated above the wiring layer 25. The insulating layer 46 is a layer that connects to the bonding layer B2, and includes a plurality of wirings (not shown).

[0061] After the semiconductor substrate W2 is removed, the wiring layer 21 and the insulator layer 40 are provided in this order in the Z1 direction below the insulator layer 41. The wiring layer 21 is formed, for example, in the shape of a plate extending along the X direction on the XY plane. The wiring layer 21 is used as the source line SL. The wiring layer 21 includes, for example, silicon doped with phosphorus. Furthermore, a wiring layer 300 may be provided below the insulator layer 40. The wiring layer 300 includes a plurality of wires (not shown).

[0062] Each of the memory pillars MP is provided extending along the Z direction. The memory pillars MP penetrate through the wiring layers 22 to 24 and the insulator layers 41 to 44. For example, the cross-sectional area of ​​each of the memory pillars MP along the XY plane (XY cross-sectional area) increases from bottom to top.

[0063] Each of the memory pillars MP includes, for example, a core film 30, a semiconductor film 31, and a stacked film 32. The core film 30 is provided to extend along the Z direction. For example, the upper end of the core film 30 is located in the insulator layer 45, and the lower end of the core film 30 is located in the wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide. The semiconductor film 31 covers, for example, the periphery of the core film 30. At the lower end of the memory pillar MP, a portion of the semiconductor film 31 contacts the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The stacked film 32 covers the side surface of the semiconductor film 31 except for the portion where the semiconductor film 31 and the wiring layer 21 contact each other.

[0064] 7, the portion where the memory pillar MP intersects with the wiring layer 22 functions as the select transistor ST2. The portions where the memory pillar MP intersects with each wiring layer 23 function as the memory cell transistors MT0 to MT7. The portion where the memory pillar MP intersects with the wiring layer 24 functions as the select transistor ST1.

[0065] Pillar-shaped contacts CV are provided on the top surface of the semiconductor film 31 in the memory pillars MP. In the region shown in Figure 7, two contacts CV are shown corresponding to two of the six memory pillars MP. In this region, memory pillars MP that do not overlap with the member SHE and are not connected to a contact CV are connected to other contacts CVs in a region not shown.

[0066] One wiring layer 25, i.e., one bit line BL, is in contact with the upper surface of each contact CV. One contact CV is connected to one wiring layer 25 in each space partitioned by the members SLT and SHE. That is, each wiring layer 25 is electrically connected to, for example, one memory pillar MP in each region between adjacent members SLT and SHE, and one memory pillar MP in each region between two adjacent members SHE.

[0067] The members SLT are formed, for example, to extend along the XZ plane. Each of the members SLT penetrates the wiring layers 22 to 24 and the insulator layers 41 to 44. For example, the width of each of the members SLT in the Y direction increases from bottom to top.

[0068] In the member SLT, the contacts LI are provided so as to extend along the XZ plane, and spacers SP are provided between the contacts LI and the wiring layers 22 to 24 and the insulator layers 41 to 45. The upper ends of the contacts LI are located, for example, in the insulator layer 45. The lower ends of the contacts LI are in contact with, for example, the wiring layer 21. The contacts LI may be omitted depending on the structure of the memory cell array 10.

[0069] The member SHE is formed, for example, in the shape of a plate extending along the XZ plane, and divides the wiring layer 24. The upper end of the member SHE is located within the insulator layer 45. The lower end of the member SHE is located, for example, within the uppermost insulator layer 43. The member SHE includes an insulator such as silicon oxide. The upper end of the member SHE and the upper end of the member SLT may or may not be aligned. Furthermore, the upper end of the member SHE and the upper end of the memory pillar MP may or may not be aligned.

[0070] The member SSE is formed in the memory regions MA1 and MA2, for example, in a plate shape extending along the XZ plane, and divides the multiple wiring layers 22. For example, the upper end of the member SSE may be located at the boundary between the uppermost insulator layer 42 and the lowermost wiring layer 23, or may be located inside the uppermost insulator layer 42. For example, the lower end of the member SSE may be located at the boundary between the wiring layer 21 and the insulator layer 41, or may be located inside the insulator layer 41. In the memory regions MA1 and MA2, the member SSE is preferably provided at a position overlapping one member SHE in the Z direction. The member SSE includes an insulator such as silicon oxide. The lower end of the member SSE and the lower end of the member SLT may or may not be aligned.

[0071] Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 7, showing an example of the cross-sectional structure of a memory pillar included in the semiconductor memory device according to the first embodiment. More specifically, Fig. 8 shows the cross-sectional structure of a memory pillar MP in a layer that is parallel to the surface of a semiconductor substrate W2 (not shown) and that includes the wiring layer 23. As shown in Fig. 8, the stacked film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0072] In a cross section including the wiring layer 23, the core film 30 is provided, for example, in the center of the memory pillar MP. The semiconductor film 31 surrounds the side surfaces of the core film 30. The tunnel insulating film 33 surrounds the side surfaces of the semiconductor film 31. The charge storage film 34 surrounds the side surfaces of the tunnel insulating film 33. The block insulating film 35 surrounds the side surfaces of the charge storage film 34. The wiring layer 23 surrounds the side surfaces of the block insulating film 35.

[0073] The semiconductor film 31 is used as the channels (current paths) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The tunnel insulating film 33 and the block insulating film 35 each contain, for example, silicon oxide. The charge storage film 34 has the function of storing charges and contains, for example, silicon nitride (SiN). With this configuration, each memory pillar MP can function as one NAND string NS.

[0074] 1.1.5.3 Drawer area (flat layout) 9 is a plan view showing an example of a planar layout of a lead-out region of a memory cell array included in a semiconductor memory device according to the first embodiment. FIG. 10 is a plan view showing an example of a planar layout of select gate lines SGSa in a lead-out region of a memory cell array included in a semiconductor memory device according to the first embodiment. The lead-out region HA and parts of nearby memory regions MA1 and MA2 are shown in FIGS. 9 and 10. The regions shown in FIGS. 9 and 10 correspond to blocks BLK0 to BLK2. Note that some insulating layers are omitted in FIGS. 9 and 10 for ease of explanation.

[0075] As shown in FIGS. 9 and 10, in the lead-out region HA, the memory cell array 10 further includes a plurality of contacts CC.

[0076] 9, the select gate line SGD includes a first portion SGDa connected to memory area MA1 and a second portion SGDb connected to memory area MA2. The select gate line SGD includes select gate lines SGD0-SGD3 in each of the first portion SGDa and the second portion SGDb, which are divided into four portions in the Y direction by three members SHE. The portions of the select gate lines SGD0-SGD3 divided in the Y direction by the three members SHE are insulated from one another. That is, in one block BLK, the select gate line SGD is divided into eight portions. The corresponding portions of the first portion SGDa and the corresponding portions of the second portion SGDb are electrically connected to one another via contacts CC (described later) and an upper wiring layer (not shown).

[0077] As shown in FIG. 10 , the member SSE divides the select gate line SGS in the Y direction in the lead-out region HA. Although not shown, the member SSE also divides the select gate line SGS in the Y direction in the memory regions MA1 and MA2. The member SSE is formed in a plate shape extending along the XZ plane in the portion extending in the X direction, and in a plate shape extending along the YZ plane in the portion extending in the Y direction. The select gate line SGSa includes select gate lines SGS0a and SGS1a divided in the Y direction by the member SSE. The select gate lines SGS0a and SGS1a are insulated from each other. For example, the select gate line SGS0a is connected to memory pillars MP corresponding to string units SU0 and SU1 in the memory regions MA1 and MA2. The portion of the select gate line SGS0a provided in the memory region MA1 and the portion provided in the memory region MA2 are electrically connected to each other via a portion provided in the bridge portion BRG in the lead-out region HA. The select gate line SGS1a is connected to the memory pillar MP corresponding to the string units SU2 and SU3. The select gate line SGS1a is electrically connected at its portion in the memory region MA1 and its portion in the memory region MA2 via a portion provided in the bridge portion BRG in the lead-out region HA. For example, the select gate line SGS0a and the select gate line SGS1a have shapes that overlap with each other due to Z-axis rotation. The cross-sectional area of ​​the select gate line SGS0a in the XY plane is approximately equal to the cross-sectional area of ​​the select gate line SGS1a in the XY plane. Therefore, the electric capacitance of the select gate line SGS0a is approximately equal to the electric capacitance of the select gate line SGS1a.

[0078] Although not shown, the select gate line SGSb also includes select gate lines SGS0b and SGS1b separated in the Y direction by a member SSE. The select gate lines SGS0b and SGS1b are insulated from each other. For example, the select gate line SGS0b is connected to memory pillars MP corresponding to string units SU0 and SU1 in the memory regions MA1 and MA2. The select gate line SGS0b is electrically connected to a portion of the memory region MA1 and a portion of the memory region MA2 via a portion of the bridge portion BRG in the lead-out region HA. The select gate line SGS1b is connected to memory pillars MP corresponding to string units SU2 and SU3. The select gate line SGS1b is electrically connected to a portion of the memory region MA1 and a portion of the memory region MA2 via a portion of the bridge portion BRG in the lead-out region HA. For example, the select gate lines SGS0b and SGS1b have shapes that overlap each other when rotated about the Z axis. The cross-sectional area of ​​the select gate line SGS0b in the XY plane is approximately equal to that of the select gate line SGS1b, and therefore the capacitance of the select gate line SGS0b is approximately equal to that of the select gate line SGS1b.

[0079] As described above, the structure in which the select gate line SGS is divided into a plurality of parts by the members SSE within one block BLK is called an SGS divided structure.

[0080] The member SSE is provided in the bridge portion BRG in the lead-out region HA so as to bypass the lead-out portions HP1 and HP2 and not overlap with the member SLT in the Z direction. Specifically, the member SSE extends in the X direction in the first portion BRGa and the second portion BRGb of the bridge portion BRG, and extends in the Y direction in the third portion BRGc. The member SSE has, for example, an S-shape in the lead-out region HA. For example, the shape of the member SSE provided in one block BLK is symmetrical in the Y direction with the shape of the member SLT provided in the adjacent block BLK across the member SLT.

[0081] 9, in the lead-out region HA, each of the wiring layers 22 to 23 has a terrace portion that does not overlap with the upper wiring layers 23 and 24. The shape of the terrace portion in the lead-out region HA resembles a step, terrace, rimstone, etc. Contacts CC are connected to the terrace portions of each of the wiring layers 22 to 23.

[0082] 9, a first staircase structure is provided in the lead-out portion HP1, in which terrace portions of the wiring layer 22 corresponding to the select gate lines SGS0a and SGS0b and the wiring layer 23 corresponding to the word lines WL4 to WL7 are aligned in the X direction. The first staircase structure is provided so as to straddle the member SLTo, and has a structure symmetrical with respect to the member SLTo. A second staircase structure is provided in the lead-out portion HP2, in which terrace portions of the wiring layer 22 corresponding to the select gate lines SGS1a and SGS1b and the wiring layer 23 corresponding to the word lines WL0 to WL3 are aligned in the X direction. The second staircase structure is provided so as to straddle the member SLTe, and has a structure symmetrical with respect to the member SLTe.

[0083] The plurality of wiring layers 23 include an inclined portion IP1 in the lead-out portion HP1. The inclined portion IP1 is a step that is provided in a rectangular shape in a plan view and includes ends of the plurality of continuously stacked wiring layers 23 (four in the example shown in FIG. 9). A part of the inclined portion IP1 is provided so as to cross the first staircase structure in the Y direction. In the inclined portion IP1, the ends of the continuously stacked plurality of wiring layers 23 are inclined at approximately the same inclination angle in the oblique directions in the XZ plane and the YZ plane, forming a slope. The inclined portion IP1 is provided so as to surround the terrace portions of the wiring layers 22 corresponding to the select gate lines SGS0a and SGS0b.

[0084] The wiring layers 23 include an inclined portion IP2 in the lead-out portion HP2. The inclined portion IP2 is a step that is rectangular in plan view and includes ends of the multiple (four in the example shown in FIG. 9) continuously stacked wiring layers 23. The inclined portion IP2 is provided so as to surround the second staircase structure. In the inclined portion IP2, the ends of the multiple continuously stacked wiring layers 23 are inclined at approximately the same inclination angle in the oblique directions in the XZ plane and the YZ plane, forming a slope.

[0085] In each of the multiple wiring layers 23, a portion provided in the memory region MA1 and a portion provided in the memory region MA2 are electrically connected to each other via a portion provided in the bridge portion BRG in the lead-out region HA. That is, the same wiring layer 23 has the same potential regardless of the portion.

[0086] A plurality of contacts CC are provided corresponding to the select gate lines SGS0a, SGS1a, SGS0b, SGS1b, and SGD0 to SGD3, and the word lines WL0 to WL7, respectively. As shown in FIG. 9, the contacts CC corresponding to the select gate lines SGD0 to SGD3 are provided side by side in the Y direction in each of the first portion SGDa and the second portion SGDb, one for each region divided by the plurality of members SHE. That is, eight contacts CC are provided for the select gate lines SGD in one block BLK. The contacts CC corresponding to the word lines WL4 to WL7 are provided side by side in the X direction in the lead-out portion HP1. The contacts CC corresponding to the word lines WL0 to WL3 are provided side by side in the X direction in the lead-out portion HP2.

[0087] The contacts CC corresponding to the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b are arranged in different locations depending on whether the block BLK in which the contacts CC are provided is even-numbered or odd-numbered, counting from the top of the page. In even-numbered blocks BLK (BLK0, BLK2, ...), the contacts CC corresponding to the select gate lines SGS0a and SGS0b are provided in the lead-out portion HP1, and the contacts CC corresponding to the select gate lines SGS1a and SGS1b are provided in the lead-out portion HP2. In the example shown in FIG. 9 , in an even-numbered block BLK, for example, the contacts CC provided in the lead-out portion HP1 correspond, from the left side of the page, to the select gate lines SGS0b and SGS0a and the word lines WL4, WL5, WL6, and WL7, respectively. The contacts CC provided in the lead-out portion HP2 correspond, from the left side of the page, to the word lines WL3, WL2, WL1, and WL0 and the select gate lines SGS1a and SGS1b, respectively. On the other hand, in odd-numbered blocks BLK (BLK1, BLK3, ...), contacts CC corresponding to select gate lines SGS0a and SGS0b are provided in lead-out portion HP2, and contacts CC corresponding to select gate lines SGS1a and SGS1b are provided in lead-out portion HP1. In the example shown in Figure 9, in odd-numbered blocks BLK, for example, the contacts CC provided in lead-out portion HP1 correspond, from left to right on the page, to select gate lines SGS1b and SGS1a and word lines WL4, WL5, WL6, and WL7, respectively. The contacts CC provided in lead-out portion HP2 correspond, from left to right on the page, to word lines WL3, WL2, WL1, and WL0 and select gate lines SGS0a and SGS0b, respectively.

[0088] (Cross-sectional structure) 11 is a cross-sectional view of the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment, taken along line XI-XI in FIGS. 9 and 10. An XZ cross section of the lead-out region HA and contacts CC of block BLK1 is shown in FIG. 11. As shown in FIG. 11, the memory cell array 10 further includes a wiring layer 26 in the lead-out region HA.

[0089] 11, a first staircase structure is formed in the drawing section HP1, the first staircase structure having a structure that ascends in the X direction from the memory region MA1 side toward the memory region MA2 side. A second staircase structure is formed in the drawing section HP2, the second staircase structure having a structure that descends in the X direction from the memory region MA1 side toward the memory region MA2 side. An insulator layer 45 is provided so as to embed the first staircase structure and the second staircase structure.

[0090] The contacts CC are provided extending in the Z direction. Each contact CC penetrates (passes through) in the Z direction an insulating layer 45 provided at the position where the contact CC is arranged in a plan view. An upper surface of each contact CC contacts the wiring layer 26. A lower surface of each contact CC contacts one of the wiring layers 22 to 24 corresponding to the contact CC.

[0091] The plurality of wiring layers 26 are provided on the plurality of contacts CC, respectively. Each contact CC is electrically connected to the row decoder module 16 via the wiring layers 26.

[0092] 1.2 SGS Segment Structure Manufacturing Process An example of a manufacturing process for the SGS separation structure in the memory cell array included in the semiconductor memory device 3 according to the first embodiment will be described below. Note that the manufacturing process for the SGS separation structure in the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment can be divided into two manufacturing processes, a first manufacturing process and a second manufacturing process. In this embodiment, a method will be described in which a structure corresponding to each of the wiring layers 22, 23, and 24 is formed from a sacrificial material, and then the sacrificial material is replaced with a conductive material to form each of the wiring layers 22, 23, and 24 (hereinafter referred to as "replacement"), as a method for forming the plurality of wiring layers 22, 23, and 24 corresponding to the select gate lines SGS and SGD and the word lines WL0 to WL7, respectively.

[0093] 1.2.1 First manufacturing process In the first manufacturing process of the SGS isolation structure, a member SSE is formed before replacing the wiring layer, and the sacrificial member corresponding to the select gate line SGS is separated. Figures 12 and 13 are cross-sectional views showing an example of the first manufacturing process of the SGS isolation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. Note that the cross sections shown in Figures 12 and 13 correspond to the cross section of the memory region MA1, but the manufacturing process of the SGS isolation structure in the memory region MA2 and the lead-out region HA is also similar.

[0094] First, an insulator layer 41 is stacked on the semiconductor substrate W2, and sacrificial members 51 and insulator layers 42 are alternately stacked above the insulator layer 41. The sacrificial members 51 are provided at positions corresponding to the wiring layers 22. The sacrificial members 51 include, for example, silicon nitride.

[0095] Thereafter, as shown in FIG. 12, a slit SSH corresponding to the member SSE is provided. Specifically, first, a mask having an opening corresponding to the member SSE is formed by photolithography or the like. Then, the insulator layers 41 and 42 and the sacrificial member 51 are removed by anisotropic etching using the mask. A part of the semiconductor substrate W2 is exposed at the bottom of the slit SSH. The bottom of the slit SSH may be provided in the insulator layer 41. In that case, a part of the insulator layer 41 is exposed at the bottom of the slit SSH. The slit SSH has a tapered shape that narrows in the Z1 direction.

[0096] 13, the slits SSH are filled with an insulator 47 to form the member SSE. The insulator 47 includes, for example, silicon oxide. For example, the surfaces of the insulator layer 42 and the member SSE are planarized by CMP (Chemical Mechanical Polishing).

[0097] Thereafter, sacrificial members and insulator layers corresponding to the wiring layers 23 and 24 are stacked in this order above the insulator layer 42 and the member SSE, forming a staircase structure.

[0098] The member SSE produced by the first manufacturing process has a tapered shape tapering in the Z1 direction.

[0099] 1.2.2 Second manufacturing process In the second manufacturing process of the SGS isolation structure, after replacing the wiring layer, a member SSE is formed to separate the select gate lines SGS. Figures 14 and 15 are cross-sectional views showing an example of the second manufacturing process of the SGS isolation structure in the memory cell array included in the semiconductor memory device according to the first embodiment. Note that the cross sections shown in Figures 14 and 15 correspond to the cross section of the memory region MA1, but the manufacturing process of the SGS isolation structure in the memory region MA2 and the lead-out region HA is also similar.

[0100] First, a memory cell array 10 is formed on a semiconductor substrate W2, which does not include a wiring layer 21 and in which the select gate lines SGSa and SGSb are not separated. Specifically, an insulator layer 41 is formed on the semiconductor substrate W2. The lower ends (upper side of the drawing) of the memory pillars MP are provided within the semiconductor substrate W2. At this time, the semiconductor film 31 is not exposed at the lower ends of the memory pillars MP, but is covered by the stacked film 32. The lower ends (upper side of the drawing) of the members SLT contact the semiconductor substrate W2. Then, as shown in FIG. 4, the control circuit provided in the control circuit layer 100 and the memory cell array 10 provided in the memory layer 200 are electrically connected to each other via bond pads BP1 and BP2.

[0101] Next, the semiconductor substrate W2 is removed. Thereafter, as shown in FIG. 14, a slit SSH corresponding to the member SSE is provided. Specifically, first, a mask having an opening corresponding to the member SSE is formed by photolithography or the like. Then, the insulator layer 41, the wiring layer 22, and a part of the insulator layer 42 are removed by anisotropic etching using the mask. At the bottom of the slit SSH, a part of the uppermost insulator layer 42 (below the paper surface) or a part of the lowermost wiring layer 23 (above the paper surface) is exposed. The slit SSH has a tapered shape that narrows in the Z2 direction.

[0102] Next, the slit SSH is filled with an insulator 47 to form the member SSE. The insulator 47 includes, for example, silicon oxide.

[0103] Thereafter, a portion of the stacked film 32 of the memory pillar MP is removed, exposing a portion of the semiconductor film 31. Next, a wiring layer 21 is formed on the insulator layer 41 and the surface of the member SSE in the Z1 direction. Specifically, for example, a semiconductor layer containing polysilicon is formed on the surface of the insulator layer 41 and the surface of the member SSE in the Z1 direction. Thereafter, a laser annealing process is performed on the semiconductor layer, thereby doping the semiconductor layer with impurities (for example, phosphorus), and forming a conductive wiring layer 21. At this time, the wiring layer 21 and the semiconductor film 31 of the memory pillar MP are electrically connected. Furthermore, an insulator layer 40 is formed on the surface of the wiring layer 21 in the Z1 direction.

[0104] The member SSE produced by the second manufacturing process has a tapered shape tapering in the Z2 direction.

[0105] 1.3 Effects of the First Embodiment According to the first embodiment, the driving speed of the semiconductor memory device can be improved. This effect will be described in detail below.

[0106] In the semiconductor memory device 3 according to the first embodiment, the select gate lines SGSa and SGSb are divided into two within one block BLK. Therefore, when the memory cell array 10 operates, the select gate lines SGSa and SGSb corresponding to the memory pillar MP in which the selected memory cell transistor MT is formed can be selectively driven. Specifically, for example, when reading or writing data from or to the memory pillar MP provided in the string unit SU0, the select gate lines SGS0a and SGS0b are driven, but the select gate lines SGS1a and SGS1b are not driven. Therefore, compared to a structure in which the select gate lines are not divided, the cross-sectional areas of the select gate lines SGS0a and SGS1a in the XY plane are approximately half, and their respective capacitances are also reduced. Therefore, the time required to charge each of the select gate lines SGS0a and SGS1a is shortened, improving drive speed. Similarly, the cross-sectional area of ​​the select gate lines SGS0b and SGS1b in the XY plane is also reduced by approximately half, and the capacitance of each is also reduced, so the time required to charge each of the select gate lines SGS0b and SGS1b is shortened and the driving speed is improved.

[0107] Furthermore, in the semiconductor memory device 3 according to the first embodiment, the portion of each of the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b provided in the memory region MA1 is connected to the portion of each of the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b provided in the memory region MA2 via a bridge portion BRG formed in the lead-out region HA. In other words, the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b are not divided into multiple portions and are not connected via upper-layer wiring or the like. Therefore, compared to a structure in which the select gate lines are divided into multiple portions in the X direction and connected via upper-layer wiring or the like, the capacitance of each of the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b can be reduced. In other words, the time required to charge each of the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b is shortened, improving the driving speed.

[0108] Additionally, in the semiconductor memory device 3 according to the first embodiment, the member SSE is not provided at a position overlapping the member SLT in the Z direction. Therefore, when processing is performed to form a slit corresponding to the member SLT, it is possible to prevent the portion where the member SSE is provided from being dug deeper than other portions due to differences in etching selectivity. Therefore, it is possible to suppress short circuits between the select gate lines SGS0a and SGS1a and between the select gate lines SGS0b and SGS1b that may occur due to dug deeper in the portion where the member SSE is provided, thereby improving the yield of the semiconductor memory device 3.

[0109] 1.4 Variations The semiconductor memory device 3 according to the first embodiment described above can be modified in various ways. Below, a first modification of the first embodiment will be described, focusing on the differences from the first embodiment.

[0110] 16 is a plan view showing an example of a planar layout of the select gate lines SGSa in the lead-out region of the memory cell array included in the semiconductor memory device according to the first modification of the first embodiment. The lead-out region HA and parts of the nearby memory regions MA1 and MA2 are shown in FIG. 16. The region shown in FIG. 16 corresponds to the blocks BLK0 to BLK2. Note that for simplicity of explanation, some insulating layers are omitted from FIG. 16. Also, in FIG. 16, the positions of the wiring layers (word lines WL0 to WL7) provided above the select gate lines SGSa are indicated by dotted lines in a plan view.

[0111] In the memory cell array 10 included in the semiconductor memory device 3 according to the first modification of the first embodiment, the member SSE may be provided in the lead-out portion HP1 or HP2. The member SSE is formed, for example, in a plate shape extending along the XZ plane. The member SSE is provided, for example, below a terrace portion of a wiring layer provided above the select gate line SGSa. When the member SSE is provided in the lead-out portion HP1, the member SSE is provided, in plan view, closer to the member SLTe adjacent to the block BLK in which the member SSE is provided than the terrace portions of the select gate lines SGSa and SGSb. When the member SSE is provided in the lead-out portion HP2, the member SSE is provided, in plan view, closer to the member SLTo adjacent to the block BLK in which the member SSE is provided than the terrace portions of the select gate lines SGSa and SGSb. Furthermore, when there are three or more wiring layers 22 corresponding to the select gate lines SGS, the members SSE are provided for all the wiring layers 22 so as not to divide the wiring layers 22 into the memory area MA1 side and the memory area MA2 side.

[0112] 2. Second embodiment Next, a semiconductor memory device according to a second embodiment will be described. The semiconductor memory device 3 according to the second embodiment differs from the semiconductor memory device 3 according to the first embodiment in that it further includes a member SLTp. In the following explanation, explanations of the same configuration and manufacturing process as those of the first embodiment will be omitted, and the configuration different from that of the first embodiment will be mainly explained.

[0113] 2.1 Memory cell array structure 17 is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to the second embodiment. As shown in FIG. 17, the memory cell array 10 included in the semiconductor memory device 3 according to the second embodiment further includes a plurality of members SLTp. Note that, in the second embodiment, the portion of the member SSE within the lead-out region HA is provided in the bridge portion BRG so as to bypass the lead-out portions HP1 and HP2 and not overlap with the member SLT in the Z direction in plan view.

[0114] Each member SLTp has, for example, a plate-like shape extending on the YZ plane. Each member SLTp has, for example, a structure in which an insulator and a plate-like contact are embedded. Each member SLTp penetrates (passes through) the select gate lines SGSa and SGSb, the word lines WL0 to WL7, and the insulator layers 41, 42, 43, 44, and 45 in the Z direction. Each member SLTp contacts, for example, the wiring layer 21 at its lower end.

[0115] 17, each member SLTp is provided in the lead-out portion HP1 or HP2 so as not to divide the select gate lines SGSa and SGSb and the word lines WL0 to WL7 in the X direction. Therefore, each member SLTp is provided so as not to contact the member SSE. Each member SLTp may be provided at any position in the lead-out region HA as long as it is included in the lead-out portion HP1 or HP2 and does not overlap in the Z direction with a portion that is connected to a corresponding contact CC in the terrace portion of the stacked wiring. Each member SLTp is provided, for example, so as to cross the first staircase structure or the second staircase structure in the Y direction.

[0116] Note that the shape of the member SLTp does not matter as long as it is large enough to allow a conductive material (for example, tungsten) to be poured in when it is replaced in the manufacturing process. For example, the member SLTp may have a pillar-like shape.

[0117] 2.2 Effects of the Second Embodiment According to the second embodiment, like the first embodiment, the driving speed of the semiconductor memory device can be improved.

[0118] Furthermore, according to the second embodiment, the yield of semiconductor memory devices can be improved. This effect will be described in detail below.

[0119] When manufacturing the semiconductor memory device 3 according to the second embodiment, the wiring layer 22 corresponding to the select gate lines SGSa and SGSb is replaced through slits provided in the portions corresponding to the members SLT and SLTp. When the SGS isolation structure is formed using a process similar to the first manufacturing process of the first embodiment, the provision of a slit corresponding to the member SLTp shortens the distance from the far end of the wiring layer 22 to the nearest slit. This prevents the conductive material (e.g., tungsten) from flowing to the far end of the wiring layer 22 during replacement, thereby preventing the occurrence of voids. This improves the yield of the semiconductor memory device 3.

[0120] 2.3 Variations The semiconductor memory device 3 according to the second embodiment described above can be modified in various ways. The following describes the first modification of the second embodiment, focusing on the differences from the second embodiment.

[0121] 18 is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to a first modified example of the second embodiment. As shown in FIG. 18, in the memory cell array 10 included in the semiconductor memory device 3 according to the first modified example of the second embodiment, the member SLTp is in contact with the member SLT in the Y direction and is formed as a single member. In other words, the member SLTp can be considered as a portion of the member SLT that protrudes into the lead-out portion HP1 or HP2. The member SLTp provided in the lead-out portion HP1 is in contact with the member SLTo and is formed as a single member. The member SLTp provided in the lead-out portion HP2 is in contact with the member SLTe and is formed as a single member.

[0122] According to the first modification of the second embodiment, the drive speed of the semiconductor memory device can be improved, as in the second embodiment, and the yield of the semiconductor memory device can be improved, as in the second embodiment.

[0123] 3. Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0124] 1. Memory system 2...Memory controller 3...Semiconductor memory device 10...Memory cell array 11...Input / output circuit 12...Logic control circuit 13...Register 14...Sequencer 15...Driver module 16...Row decoder module 17...Sense amplifier module 21, 22, 23, 24, 25, 26...wiring layer 30...Core membrane 31...Semiconductor film 32...Laminated film 33...Tunnel insulating film 34...Charge storage film 35...Block insulating film 40, 41, 42, 43, 44, 45, 46...Insulator layers 47...Insulator 51...Sacrificial member 100...Control circuit layer 200...Memory layer 300...Wiring layer B1, B2…bonding layer BL...bit line BLK...Block BP1, BP2...bonding pads BRG: Bridge section CC, CV, LI...Contact CU: Cell unit HA…Drawer area HP1, HP2...Drawer part IP1, IP2…Slope part MA1, MA2...Memory area MP…Memory Pillar MT...Memory cell transistor NS...NAND string PD...pad SGD, SGSa, SGSb...Select gate lines SHE, SSE, SLT, SLTe, SLTo, SLTp...components SSH...Slit SL...Source line SP...Spacer ST1, ST2...Select transistors SU...String unit W1, W2: Semiconductor substrate WL...word line

Claims

1. a first wiring layer provided across a first region and a second region aligned in a second direction intersecting the first direction, as viewed in a first direction; a second wiring layer spaced apart from the first wiring layer in the first direction; a plurality of third wiring layers provided on the opposite side of the second wiring layer from the first wiring layer and spaced apart from each other in the first direction; a first insulating member and a second insulating member that are aligned in a third direction intersecting the first direction and the second direction, and that extend in the second direction to divide the second wiring layer and the plurality of third wiring layers in the third direction; a third insulating member provided between the first insulating member and the second insulating member and between the first wiring layer and the plurality of third wiring layers, the third insulating member dividing the second wiring layer into a first portion and a second portion in the third direction; a first memory pillar extending in the first direction between the first insulating member and the third insulating member in the second region, contacting the first wiring layer, and having portions that intersect with each of the plurality of third wiring layers functioning as a plurality of first memory cells; a second memory pillar extending in the first direction between the second insulating member and the third insulating member in the second region, contacting the first wiring layer, and having portions that intersect with each of the plurality of third wiring layers functioning as a plurality of second memory cells; a first contact and a second contact extending in the first direction within the first region; Equipped with The second wiring layer is a first terrace portion in the first portion within the first region, the first terrace portion being in contact with the first insulating member and not overlapping with the plurality of third wiring layers when viewed in the first direction; a second terrace portion in the second portion within the first region, the second terrace portion being in contact with the second insulating member and not overlapping with the plurality of third wiring layers when viewed in the first direction; and the first contact is electrically connected to the first terrace portion of the second wiring layer; the second contact is electrically connected to the second terrace portion of the second wiring layer; Semiconductor memory device.

2. The plurality of third wiring layers are arranged in the first region. a first bridge portion that contacts the second insulating member and extends in the second direction between the first terrace portion of the second wiring layer and the second insulating member; a second bridge portion that contacts the first insulating member and extends in the second direction between the second terrace portion of the second wiring layer and the first insulating member; a third bridge portion extending in the third direction between the first insulating member and the second insulating member and contacting the first bridge portion and the second bridge portion; each having 2. The semiconductor memory device according to claim 1.

3. a third contact and a fourth contact extending in the first direction within the first region; the plurality of third wiring layers include a fourth wiring layer and a fifth wiring layer, the fourth wiring layer has a third terrace portion that is in contact with the first insulating member in the first region and is provided so as not to overlap in the first direction with the plurality of third wiring layers that are upper layers when viewed in the first direction, the fifth wiring layer has a fourth terrace portion that is in contact with the second insulating member in the first region and is provided so as not to overlap in the first direction with the plurality of third wiring layers that are upper layers when viewed in the first direction, the third contact is electrically connected to the third terrace portion of the fourth wiring layer; the fourth contact is electrically connected to the fourth terrace portion of the fifth wiring layer.

3. The semiconductor memory device according to claim 2.

4. the third insulating member is provided in the first region at a position overlapping the first bridge portion, the second bridge portion, and the third bridge portion of the plurality of third wiring layers in the first direction; 4. The semiconductor memory device according to claim 3.

5. The third insulating member is third portions extending in the second direction at positions overlapping the first bridge portions of the third wiring layers in the first direction within the first region; a fourth portion extending in the second direction at a position overlapping the second bridge portion of the third wiring layers in the first direction within the first region; a fifth portion extending in the third direction at a position overlapping with the third bridge portion of the plurality of third wiring layers in the first direction within the first region and contacting the third portion and the fourth portion; 5. The semiconductor memory device according to claim 4, comprising:

6. the capacitance of the first portion of the second wiring layer is approximately equal to the capacitance of the second portion of the second wiring layer; 2. The semiconductor memory device according to claim 1.

7. the third insulating member is provided at a position overlapping the third terrace portion of the fourth wiring layer or the fourth terrace portion of the fifth wiring layer in the first direction; 4. The semiconductor memory device according to claim 3.

8. a control circuit that applies voltages to the first portion and the second portion of the second wiring layer independently of each other; 2. The semiconductor memory device according to claim 1.

9. sixth wiring layers provided on the opposite side of the second wiring layers with respect to the plurality of third wiring layers and spaced apart from each other in the first direction; a fourth insulating member that divides the sixth wiring layer in the third direction between the first insulating member and the second insulating member; Further provided with the first terrace portion and the second terrace portion of the second wiring layer are provided so as not to overlap with the sixth wiring layer when viewed in the first direction, the first memory pillar and the second memory pillar intersect with the sixth wiring layer; In the second region, the third insulating member and the fourth insulating member are provided at positions overlapping each other in the first direction.

2. The semiconductor memory device according to claim 1.

10. the third insulating member is in contact with a wiring layer of the plurality of third wiring layers that is closest to the first wiring layer in the first direction, and has a tapered shape that becomes thinner from the side of the plurality of third wiring layers toward the side of the first wiring layer; 2. The semiconductor memory device according to claim 1.

11. the third insulating member is in contact with the first wiring layer in the first direction and has a tapered shape that narrows from the first wiring layer side toward the plurality of third wiring layers side; 2. The semiconductor memory device according to claim 1.

12. further comprising a third memory pillar and a fourth memory pillar; the first wiring layer, the second wiring layer, and the plurality of third wiring layers further include a third region provided together with the second region so as to sandwich the first region in the second direction; the third memory pillar extends in the first direction between the first insulating member and the third insulating member in the third region, contacts the first wiring layer, and portions intersecting with each of the plurality of third wiring layers function as a plurality of third memory cells; the fourth memory pillar extends in the first direction between the second insulating member and the third insulating member in the third region, contacts the first wiring layer, and portions intersecting with each of the plurality of third wiring layers function as a plurality of fourth memory cells; 2. The semiconductor memory device according to claim 1.

13. sixth wiring layers provided on the opposite side of the second wiring layers with respect to the plurality of third wiring layers and spaced apart from each other in the first direction; a fourth insulating member that divides the sixth wiring layer in the third direction between the first insulating member and the second insulating member; Further provided with the first terrace portion and the second terrace portion of the second wiring layer are provided so as not to overlap with the sixth wiring layer when viewed in the first direction, In the third region, the third insulating member and the fourth insulating member are provided at positions overlapping each other in the first direction.

13. The semiconductor memory device according to claim 12.

14. a fifth insulating member that is located between the first insulating member and the third insulating member within the first region and does not contact the third insulating member, and passes through the first portion of the second wiring layer and the plurality of third wiring layers in the first direction; a sixth insulating member that is located between the second insulating member and the third insulating member within the first region and does not contact the third insulating member, and passes through the second portion of the second wiring layer and the plurality of third wiring layers in the first direction; Further comprising:

2. The semiconductor memory device according to claim 1.

15. the fifth insulating member is in contact with the first insulating member in the third direction, the sixth insulating member is in contact with the second insulating member in the third direction; 15. The semiconductor memory device according to claim 14.

16. the fifth insulating member and the sixth insulating member are provided at positions that do not overlap the first contact and the second contact in the first direction.

16. The semiconductor memory device according to claim 14.

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