Semiconductor Devices

Abstract

A semiconductor device that reduces peeling of an insulating film is provided. [Solution] The semiconductor device comprises a first metal layer provided on a substrate, a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of the upper surface of the first metal layer, a second metal layer provided on the first metal layer and having a central portion of its lower surface in contact with the first metal layer through the first opening and a peripheral portion of its lower surface in contact with the first inorganic insulating film outside the first opening, a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of the upper surface of the second metal layer, and an organic insulating film covering the second inorganic insulating film and having a third opening exposing the central portion of the upper surface of the second metal layer and overlapping the second opening when viewed in the thickness direction of the substrate.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] It is known to provide an insulating film having an opening that exposes the central portion of the upper surface of a metal layer so as to cover the metal layer used as a pad or the like (for example, Patent Document 1). A silicon nitride film is used as the insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-56246 Summary of the Invention [Problem to be solved by the invention]

[0004] In some cases, an organic insulating film is provided on a silicon nitride film having an opening that exposes the center of the upper surface of a metal layer, so as not to overlap the opening. In this case, stress in the organic insulating film causes the insulating film to peel off from the metal layer, starting from the edge of the opening.

[0005] An object of the present disclosure is to provide a semiconductor device that reduces peeling of an insulating film. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a semiconductor device comprising: a first metal layer provided on a substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of an upper surface of the first metal layer; a second metal layer provided on the first metal layer, the central portion of the lower surface contacting the first metal layer through the first opening and the peripheral portion of the lower surface contacting the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of an upper surface of the second metal layer; and an organic insulating film covering the second inorganic insulating film and having a third opening exposing the central portion of the upper surface of the second metal layer and overlapping the second opening when viewed in the thickness direction of the substrate. [Effects of the Invention]

[0007] According to the present disclosure, peeling of the insulating film can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing metal layers and openings in the semiconductor device of the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is an enlarged cross-sectional view of the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7A to 7C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9A to 9C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10]10A to 10C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 12A to 12C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 13A to 13C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 14A to 14C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to Modification 1 of the first embodiment. [Figure 16] 16A to 16C are cross-sectional views showing a method for manufacturing a semiconductor device according to Modification 1 of the first embodiment. [Figure 17] FIG. 17 is a plan view of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) An embodiment of the present disclosure is a semiconductor device including: a first metal layer provided on a substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of an upper surface of the first metal layer; a second metal layer provided on the first metal layer, the second metal layer having a central portion of a lower surface in contact with the first metal layer through the first opening and a peripheral portion of the lower surface in contact with the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of an upper surface of the second metal layer; and an organic insulating film covering the second inorganic insulating film and having a third opening exposing the central portion of an upper surface of the second metal layer and overlapping the second opening when viewed in a thickness direction of the substrate. Thus, even if stress from the organic insulating film is applied to the second inorganic insulating film, a portion of the first inorganic insulating film sandwiched between the first and second metal layers forms a wedge, thereby reducing peeling of the second inorganic insulating film from the second metal layer. (2) In the above (1), the second metal layer may be thinner than the first metal layer, thereby reducing the likelihood of the second inorganic insulating film peeling off from the second metal layer. (3) In the above (1) or (2), the width of the lower surface of the second metal layer may be smaller than the width of the upper surface of the first metal layer, thereby reducing peeling of the second inorganic insulating film from the second metal layer. (4) In any one of the above (1) to (3), the outer periphery of the second opening may be defined by the outer periphery of the third opening, thereby reducing the number of manufacturing steps. (5) In any one of the above (1) to (3), the outer periphery of the second opening may be located inside the outer periphery of the third opening, thereby reducing peeling of the second inorganic insulating film from the second metal layer. (6) In any of the above (1) to (5), the device may further include a third metal layer provided on the substrate, and a third inorganic insulating film covering the third metal layer and having a fourth opening in a central portion of an upper surface of the third metal layer, wherein a central portion of a lower surface of the first metal layer contacts the third metal layer through the third opening, and a peripheral portion of the lower surface of the first metal layer contacts the third inorganic insulating film outside the fourth opening, thereby reducing the intrusion of moisture and the like into the substrate 10. (7) In any one of the above (1) to (6), the organic insulating film may be a polyimide film or a BCB film, which can reduce peeling of the second inorganic insulating film from the second metal layer. (8) In the above (7), the second inorganic insulating film may be a silicon nitride film, and at least the upper surface of the second metal layer may be a gold layer, thereby reducing peeling of the second inorganic insulating film from the second metal layer. (9) In any one of the above (1) to (8), the second metal layer may have an adhesion layer including a lower surface of the second metal layer, and a low-resistivity layer provided on the adhesion layer and having a resistivity lower than that of the adhesion layer, thereby improving adhesion between the peripheral portion of the lower surface of the second metal layer and the first inorganic insulating film. (10) In any one of (1) to (9) above, the region of the upper surface of the second metal layer exposed through the second opening and the third opening may be a bonding region, whereby an external connection member can be bonded to the bonding region.

[0011] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] (First embodiment) The first embodiment is an example of a semiconductor device including a metal layer that functions as a pad. FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing metal layers 15, 16, and 18 and openings 13A, 11A, and 12A of the semiconductor device according to the first embodiment. FIG. 2 illustrates an upper surface 15A of metal layer 15, an upper surface 17A and a lower surface 17B of metal layer 16, and an upper surface 19A and a lower surface 19B of metal layer 18. While the upper surface 17A and the lower surface 17B are not necessarily the same size, and the upper surface 19A and the lower surface 19B are not necessarily the same size, FIG. 2 illustrates the upper surface 17A and the lower surface 17B as being the same size, and the upper surfaces 19A and 18B as being the same size. The thickness direction of the substrate 10 is defined as the Z direction, and directions perpendicular to the Z direction and perpendicular to each other are defined as the X direction and the Y direction.

[0013] 1 and 2, the semiconductor device 100 according to the first embodiment includes a substrate 10, metal layers 15, 16, and 18, inorganic insulating films 11, 12, and 13, and an organic insulating film 14. The substrate 10 includes a substrate 10A and a semiconductor layer 10B provided on the substrate 10A. The metal layer 15 is provided on the substrate 10. The inorganic insulating film 13 is provided on the substrate 10 so as to cover the metal layer 15. The inorganic insulating film 13 has an opening 13A that exposes a central portion of an upper surface 15A of the metal layer 15 but does not expose a peripheral portion of the upper surface 15A of the metal layer 15.

[0014] The metal layer 16 is provided on the metal layer 15 and the inorganic insulating film 13. The central portion of the lower surface 17B of the metal layer 16 contacts the metal layer 15 through the opening 13A. The peripheral portion of the lower surface 17B of the metal layer 16 contacts the inorganic insulating film 13 outside the opening 13A. The metal layer 16 includes a metal layer 16A that contacts the upper surfaces of the metal layer 15 and the inorganic insulating film 13, and a metal layer 16B provided on the metal layer 16A. The metal layer 16A is an adhesion layer that improves adhesion between the metal layer 16B and the metal layer 15 and the inorganic insulating film 13. The metal layer 16B is a low-resistivity layer having a resistivity lower than that of the metal layer 16A. The inorganic insulating film 11 is provided on the substrate 10 so as to cover the metal layer 16 and the inorganic insulating film 13. The inorganic insulating film 11 has an opening 11A that exposes the central portion of the upper surface 17A of the metal layer 16 and does not expose the peripheral portion of the upper surface 17A of the metal layer 16.

[0015] The metal layer 18 is provided on the metal layer 16 and the inorganic insulating film 11. A central portion of the lower surface 19B of the metal layer 18 contacts the metal layer 16 through the opening 11A. A peripheral portion of the lower surface 19B of the metal layer 18 contacts the inorganic insulating film 11 outside the opening 11A. The metal layer 18 includes a metal layer 18A that contacts the upper surfaces of the metal layer 16 and the inorganic insulating film 11, and a metal layer 18B provided on the metal layer 18A. The metal layer 18A is an adhesion layer that improves adhesion between the metal layer 18B and the metal layer 16 and the inorganic insulating film 11. The metal layer 18B is a low-resistivity layer having a resistivity lower than that of the metal layer 18A. The inorganic insulating film 12 is provided on the substrate 10 so as to cover the metal layer 18 and the inorganic insulating film 11. The inorganic insulating film 12 has an opening 12A that exposes the central portion of the upper surface 19A of the metal layer 18 and does not expose the peripheral portion of the upper surface 19A of the metal layer 18.

[0016] The organic insulating film 14 has an opening 14A that exposes the central portion of the upper surface of the metal layer 18 but does not expose the peripheral portion of the upper surface of the metal layer 18. The outer periphery of the opening 12A is defined by the outer periphery of the opening 14A. The outer peripheries of the openings 12A and 14A are approximately the same. The outer peripheries of the openings 12A and 14A do not have to be the same. A member for connecting to the outside, such as a bonding wire or a bump, is bonded to the upper surface of the metal layer 18 exposed from the openings 12A and 14A. In this way, the upper surface of the metal layer 18 exposed from the openings 12A and 14A functions as a pad.

[0017] The semiconductor layer 10B is a nitride semiconductor layer, an arsenide semiconductor layer, or a silicon layer. The nitride semiconductor layer is, for example, gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof. The arsenide semiconductor layer is, for example, gallium arsenide, aluminum arsenide, indium arsenide, or a mixed crystal thereof. When the semiconductor layer 10B is a nitride semiconductor layer, the substrate 10A is, for example, a silicon carbide substrate, a sapphire substrate, or a gallium nitride substrate. When the semiconductor layer 10B is an arsenide semiconductor layer, the substrate 10A is, for example, a gallium arsenide substrate. When the semiconductor layer 10B is a silicon layer, the substrate 10A is, for example, a silicon substrate.

[0018] The inorganic insulating films 11 to 13 are, for example, silicon nitride films, silicon oxide films, silicon nitride oxide films, or aluminum oxide films, and one example is a silicon nitride film. The main components of the inorganic insulating films 11 to 13 may be the same as or different from each other. The organic insulating film 14 is, for example, a polyimide film or a BCB (Benzocyclobutene) film, and one example is a polyimide film. The metal layers 16A and 18A are, for example, a titanium layer, a titanium tungsten layer, a titanium nitride layer, or a titanium tungsten nitride layer. The main components of the metal layers 16A and 18A may be the same as or different from each other. The metal layers 16B and 18B are, for example, a gold layer, a copper layer, or an aluminum layer. The main components of the metal layers 16B and 18B may be the same as or different from each other. The resistivity of the metal layers 16B and 18B may be, for example, ½ or less, or ⅕ or less of the resistivity of the metal layers 16A and 18A.

[0019] (Comparative form) Fig. 3 is a cross-sectional view of a semiconductor device according to a comparative embodiment. As shown in Fig. 3, the semiconductor device 110 according to the comparative embodiment does not include an inorganic insulating film 11 and a metal layer 18. An inorganic insulating film 12 is provided so as to cover the metal layer 16. The inorganic insulating film 12 has an opening 12A that exposes the central portion of the upper surface of the metal layer 16 but does not expose the peripheral portion of the upper surface of the metal layer 16. The other configurations are the same as those of the first embodiment.

[0020] When the inorganic insulating film 12 and the organic insulating film 14 are used as protective films, the organic insulating film 14 generally has a higher linear expansion coefficient than the inorganic insulating film and the metal layer. Therefore, after heat treatment of the organic insulating film 14, a shrinking stress 50 occurs in the organic insulating film 14. The stress concentrates at the edge of the opening 14A in the organic insulating film 14 and at the edge 51 of the opening 12A in the inorganic insulating film 12. Furthermore, adhesion between the inorganic insulating film and the metal layer is generally poor. Therefore, the inorganic insulating film 12 may peel off from the metal layer 16 starting from the edge 51 of the opening 12A in the inorganic insulating film 12. Furthermore, moisture and other contaminants are likely to penetrate the substrate 10 via a path 54 along the interfaces between the metal layers 15 and 16 and the inorganic insulating films 12 and 13, which runs from the edge 51 of the inorganic insulating film 12 to the substrate 10. Once moisture and other contaminants reach the substrate 10, they may reach the transistor via the interface between the substrate 10 and the inorganic insulating film 13.

[0021] FIG. 4 is a cross-sectional view of a semiconductor device according to the first embodiment. As shown in FIGS. 1, 2, and 4, in the semiconductor device 100 of the first embodiment, a metal layer 16 (first metal layer) is provided on a substrate 10. An inorganic insulating film 11 (first inorganic insulating film) covers the metal layer 16 and has an opening 11A (first opening) that exposes a central portion of an upper surface 17A of the metal layer 16. A metal layer 18 (second metal layer) is provided on the metal layer 16, and a central portion of a lower surface 19B contacts the metal layer 16 through the opening 11A, and a peripheral portion of the lower surface 19B contacts the inorganic insulating film 11 outside the opening 11A. An inorganic insulating film 12 (second inorganic insulating film) covers the metal layer 18 and has an opening 12A (second opening) that exposes a central portion of an upper surface 19A of the metal layer 18. The organic insulating film 14 covers the inorganic insulating film 12 and has an opening 14A (third opening) that exposes a central portion of the upper surface 19A of the metal layer 18. When viewed from the Z direction, the opening 14A overlaps with the opening 12A.

[0022] In this manner, a portion of the inorganic insulating film 11 is sandwiched between the metal layers 16 and 18. As a result, even if stress 50 from the organic insulating film 14 is applied to the inorganic insulating film 11, the portion of the inorganic insulating film 11 sandwiched between the metal layers 16 and 18 forms a wedge 52, reducing the likelihood of the inorganic insulating film 12 peeling off from the metal layer 18. Furthermore, the distance of a path 54 from an end 51 of the inorganic insulating film 12 to the substrate 10 along the interfaces between the metal layers 15, 16, and 18 and the inorganic insulating films 11, 12, and 13 is longer than in the comparative example. This reduces the penetration of moisture and the like into the substrate 10 via the path 54 along the interfaces, making it more difficult for moisture to reach transistors and the like. Because the number of bends in the path 54 is greater than in the comparative example, the penetration of moisture and the like into the substrate 10 via the path 54 is further reduced.

[0023] The metal layer 18 is thinner than the metal layer 16. This shortens the distance along the inorganic insulating film 12 from the wedge 52 to the end 51 of the inorganic insulating film 12. Therefore, even if stress is applied to the end 51 of the inorganic insulating film 12, the inorganic insulating film 12 is less likely to peel off from the metal layer 18. The thickness T2 of the metal layer 18 may be 0.9 times or less, or 0.8 times or less, the thickness T1 of the metal layer 16. The thickness T2 of the metal layer 18 may be equal to or greater than the thickness T1 of the metal layer 16.

[0024] The width W2 of the lower surface 19B of the metal layer 18 is smaller than the width W1 of the upper surface 17A of the metal layer 16. This shortens the distance along the inorganic insulating film 12 from the wedge 52 to the end 51 of the inorganic insulating film 12. Therefore, even if stress is applied to the end 51 of the inorganic insulating film 12, the inorganic insulating film 12 is less likely to peel off from the metal layer 18. The width W2 of the metal layer 18 may be set to 0.95 times or less the width W1 of the metal layer 16.

[0025] Metal layer 15 (third metal layer) is provided on substrate 10. Inorganic insulating film 13 (third inorganic insulating film) covers metal layer 15 and has opening 13A (fourth opening) in the center of upper surface 15A of metal layer 15. A central portion of lower surface 17B of metal layer 16 contacts metal layer 15 through opening 13A, and a peripheral portion of lower surface 17B contacts inorganic insulating film 13 outside opening 13A. This reduces the penetration of moisture and the like into substrate 10 via path 54, making it difficult for moisture to reach transistors and the like.

[0026] When the organic insulating film 14 is a polyimide film or a BCB film, stress 50 occurs in the organic insulating film 14. Therefore, by providing the wedge 52, peeling of the inorganic insulating film 12 from the metal layer 18 can be reduced.

[0027] When the inorganic insulating film 12 is a silicon nitride film and at least the upper surface of the metal layer 18 is a gold layer, the adhesion between the inorganic insulating film 12 and the metal layer 18 is weak. Therefore, by providing the wedge 52, peeling of the inorganic insulating film 12 from the metal layer 18 can be reduced.

[0028] 5 is an enlarged cross-sectional view of the semiconductor device according to the first embodiment. In FIG. 5, the distance covered by the inorganic insulating film 12 on the upper surface 19A of the metal layer 18, i.e., the distance between the side surface of the metal layer 18 and the end surface of the inorganic insulating film 12, is D1. If the distance D1 is short, moisture and the like can easily penetrate between the metal layer 18 and the inorganic insulating film 12, resulting in a deterioration in moisture resistance. From the viewpoint of moisture resistance, the distance D1 is, for example, 1 μm or more. From the viewpoint of miniaturization, the distance D1 is, for example, 10 μm or less. Furthermore, the distance D1 may be, for example, 0.2 to 10 times, or 1 to 5 times, the thickness T2 of the metal layer 18.

[0029] The distance covered by inorganic insulating film 11 on lower surface 19B of metal layer 18, i.e., the distance between the side surface of metal layer 18 and the end surface of inorganic insulating film 11, is D2. From the viewpoint of the alignment accuracy between metal layer 18 and inorganic insulating film 12, distance D2 is, for example, 0.5 μm or more. From the viewpoint of increasing the contact area between metal layers 16 and 18, distance D2 is, for example, 10 μm or less. Furthermore, distance D2 may be, for example, 0.1 to 20 times, or 0.5 to 10 times, the thickness T2 of metal layer 18.

[0030] The distance between the side of metal layer 16 and the side of metal layer 18 is D3. From the viewpoint of alignment accuracy between metal layers 16 and 18, distance D3 is, for example, 0.5 μm or more. From the viewpoint of miniaturization, distance D3 is, for example, 5 μm or less. Furthermore, distance D3 may be, for example, 0.1 to 10 times, or 0.5 to 5 times, the thickness T2 of metal layer 18.

[0031] The thickness T1 of the metal layer 16 is, for example, 1 μm or more in order to reduce the current density, and is, for example, 5 μm or less in order to reduce the manufacturing process. The thickness T2 of the metal layer 18 is, for example, 1 μm or more in order to reduce the current density, and is, for example, 5 μm or less in order to reduce the manufacturing process.

[0032] The thickness T3 of the inorganic insulating film 11 is, for example, 0.1 μm or more in order to reduce pinholes and the like, and is, for example, 0.4 μm or less in order to reduce parasitic capacitance. The thickness T4 of the inorganic insulating film 12 is, for example, 0.2 μm or more in order to reduce pinholes and the like, and is, for example, 0.8 μm or less in order to reduce parasitic capacitance.

[0033] The thickness T5 of the organic insulating film 14 near the opening 14A is, for example, 1 μm or more from the viewpoint of functioning as a protective film, and 10 μm or less from the viewpoint of manufacturing steps. To use the organic insulating film 14 as a protective film, the thickness T5 must be large. However, as the thickness T5 increases, the stress applied to the edge 51 also increases. Therefore, when the organic insulating film 14 is thick, providing the metal layers 16 and 18 can reduce peeling of the inorganic insulating film 12.

[0034] (Manufacturing method of the first embodiment) 6 to 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 6, a metal layer 15 is formed on a substrate 10. The metal layer 15 is formed using, for example, a vacuum deposition method and a lift-off method. An inorganic insulating film 13 is formed on the substrate 10 so as to cover the metal layer 15. An opening 13A is formed in the inorganic insulating film 13, exposing the central portion of an upper surface 15A of the metal layer 15 but not exposing the peripheral portion of the upper surface 15A. The inorganic insulating film 11 is formed using, for example, a CVD (Chemical Vapor Deposition) method. The opening 13A is formed using, for example, a photolithography method and a dry etching method.

[0035] As shown in FIG. 7, metal layers 16A and 16C are formed in the opening 13A and on the inorganic insulating film 13. The metal layer 16A is an adhesion layer. The metal layer 16C is a seed layer for forming the metal layer 16B, and the main component of the metal layer 16C is, for example, the same as the main component of the metal layer 16B. The metal layers 16A and 16C are formed using, for example, a sputtering method. A mask layer 40 is formed on the metal layer 16A. The mask layer 40 has an opening 40A that overlaps with the opening 13A when viewed from the Z direction and is larger than the opening 13A. The mask layer 42 is, for example, a photoresist, and is formed by photolithography.

[0036] As shown in FIG. 8, a metal layer 16B is formed in the opening 40A of the mask layer 40. The metal layer 16B is formed by, for example, supplying current from the metal layers 16A and 16B using electroplating. The metal layer 16C is not shown in the following figures. The metal layer 16 is formed from the metal layers 16A and 16B. The mask layer 40 is peeled off. The metal layer 16A is etched using the metal layer 16B as a mask. This removes the metal layer 16A outside the area where the metal layer 16B was formed.

[0037] 9, an inorganic insulating film 11 is formed on the inorganic insulating film 13 so as to cover the metal layer 16. The inorganic insulating film 11 is formed using, for example, a CVD method. An opening 11A is formed in the inorganic insulating film 11, so that the central portion of the upper surface 17A of the metal layer 16 is exposed but the peripheral portion of the upper surface 17A is not exposed. The opening 11A is formed using, for example, a photolithography method and a dry etching method.

[0038] As shown in FIG. 10 , a mask layer 42 is formed on the inorganic insulating film 11. The mask layer 42 has an opening 42A. The opening 42A exposes the metal layer 16 and the inorganic insulating film 11 formed on the side surface of the metal layer 16. The upper surface of the mask layer 42 near the opening 42A is curved, with the thickness of the mask layer 42 gradually decreasing toward the opening 42A. The mask layer 42 is made of, for example, photoresist and is formed by photolithography. After the opening 42A is formed in the mask layer 42, the upper surface of the mask layer 42 becomes curved by heat treatment. Metal layers 18A and 18C are formed on the mask layer 42, on the metal layer 16 in the opening 42A, and on the inorganic insulating film 11 in the opening 42A. The metal layer 18A is an adhesion layer. The metal layer 18C is a seed layer for forming the metal layer 18B, and the main component of the metal layer 18C is, for example, the same as the main component of the metal layer 18B. The metal layers 18A and 18C are formed by, for example, sputtering.

[0039] 11, a mask layer 44 is formed on the metal layer 18A. The mask layer 44 has an opening 44A. The opening 44A is larger than the opening 11A and smaller than the upper surface 17A of the metal layer 16. The mask layer 44 is made of, for example, photoresist, and is formed by photolithography.

[0040] As shown in FIG. 12, a metal layer 18B is formed in the opening 44A of the mask layer 44. The metal layer 18B is formed, for example, by supplying a current from the metal layer 18A using electroplating. In the following figures, the metal layer 18C is not shown. The metal layer 18 is formed from the metal layers 18A and 18B. The mask layer 44 is peeled off. The metal layer 18A is etched using the metal layer 18B as a mask. This removes the metal layer 18A outside the area where the metal layer 18B is formed. The mask layer 42 is peeled off.

[0041] 13, an inorganic insulating film 12 is formed on the inorganic insulating film 11 so as to cover the metal layer 18. The inorganic insulating film 12 is formed by using, for example, a CVD method.

[0042] 14, an organic insulating film 14 is formed on the inorganic insulating film 12. The organic insulating film 14 has an opening 14A. The opening 14A is smaller than an upper surface 19A of the metal layer 18. The organic insulating film 14 is, for example, a photosensitive polyimide film, and is formed by photolithography.

[0043] Thereafter, the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask, thereby forming an opening 12A in the inorganic insulating film 12. In this way, the semiconductor device 100 according to the first embodiment of FIG. 1 is manufactured.

[0044] In the first embodiment, the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask, thereby eliminating the need for a mask layer for forming the opening 12A in the inorganic insulating film 12 and reducing the number of manufacturing steps. Since the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask, the periphery of the opening 12A is defined by the periphery of the opening 14A.

[0045] 10 to 12, the metal layer 18 is formed. In this case, the metal layer 18 has a metal layer 18A (adhesion layer) including a lower surface 19B of the metal layer 18, and a metal layer 18B (low-resistance layer) provided on the metal layer 18A and having a resistivity lower than that of the metal layer 18A. This improves the adhesion between the peripheral portion of the lower surface 19B of the metal layer 18 and the inorganic insulating film 11. Therefore, the metal layer 18 can be formed on the inorganic insulating film 11.

[0046] (Modification 1 of the first embodiment) Fig. 15 is a cross-sectional view of a semiconductor device according to Modification 1 of the first embodiment. As shown in Fig. 15, in a semiconductor device 102 according to Modification 1 of the first embodiment, opening 14A of organic insulating film 14 is formed to be larger than opening 12A of inorganic insulating film 12. End 51 of inorganic insulating film 12 is located inside end 53 of organic insulating film 14. In other words, the outer periphery of opening 12A is located inside the outer periphery of opening 14A.

[0047] In the first modification of the first embodiment, when stress 50 occurs in the organic insulating film 14, the stress is applied to the end 53 of the organic insulating film 14, but the stress applied to the end 51 of the inorganic insulating film 12 is small. Therefore, peeling of the inorganic insulating film 12 from the metal layer 16 can be reduced.

[0048] (Manufacturing method of modified example 1 of the first embodiment) 16 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Modification 1 of the first embodiment. As shown in Fig. 16, after the process shown in Fig. 14 of the first embodiment, a mask layer 46 is formed on the organic insulating film 14. The mask layer 46 has an opening 46A that is smaller than the opening 14A. The mask layer 46 is made of, for example, photoresist, and is formed by photolithography.

[0049] 16, the inorganic insulating film 12 is removed using the mask layer 46 as a mask. The inorganic insulating film 12 is removed by dry etching, for example. Thereafter, the mask layer 46 is peeled off. In this way, the semiconductor device 102 is manufactured.

[0050] (Second embodiment) The second embodiment is an example in which the structures of the metal layers 16 and 18 of the first embodiment and its first modification are used for the pads of a transistor. Fig. 17 is a plan view of the semiconductor device according to the second embodiment.

[0051] 17, the semiconductor device 104 according to the second embodiment includes a substrate 10, a source electrode 20, a drain electrode 21, a gate electrode 22, and pads 24S, 24D, and 24G. The source electrodes 20 and the drain electrodes 21 are arranged alternately in the X direction. The gate electrode 22 is arranged between the source electrodes 20 and the drain electrodes 21 in the X direction. The source electrodes 20, the drain electrodes 21, and the gate electrodes 22 are finger-shaped and extend in the Y direction.

[0052] The width of every third source electrode 20 in the X direction is wider. Via holes 25 penetrating the substrate 10 are connected to the wider source electrodes 20. The wider source electrodes 20 are electrically connected to a metal layer provided on the lower surface of the substrate 10 through the via holes 25. The narrower source electrodes 20 are electrically connected to the wider source electrodes 20 through source wiring 23. The source wiring 23 intersects the gate electrodes 22 without contacting them. The outermost source electrode 20 in the X direction is electrically connected to the pad 24S.

[0053] The drain electrodes 21 are electrically connected to the pad 24D. The gate electrodes 22 are electrically connected to the pad 24G. The pads 24S, 24D, and 24G each have metal layers 16 and 18 and openings 12A and 14A. The structures of the pads 24S, 24D, and 24G are the same as those of the first embodiment and its first modification. The region of the upper surface of the metal layer 18 (not described here) exposed through the openings 12A and 14A is the bonding region 26. This allows an external connection member, such as a bonding wire or a bump, to be bonded to the bonding region 26. Furthermore, a probe for electrical testing can be brought into contact with the bonding region 26. Note that a voltage is supplied to the source electrode 20 from the metal layer on the underside of the substrate 10 via a via hole 25, so an external connection member does not need to be bonded to the pad 24S. The pad 24S comes into contact with the probe for electrical testing.

[0054] The source electrode 20 and the drain electrode 21 are formed by stacking metal layers 15 and 16 from the substrate 10 side. When the semiconductor device 104 is a GaN HEMT, the metal layer 15 is, for example, a titanium layer and an aluminum layer from the substrate 10 side. The gate electrode 22 is, for example, a nickel layer and a gold layer from the substrate 10 side.

[0055] In the second embodiment, a FET is used as a transistor, but the transistor may be a bipolar transistor other than a FET.

[0056] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0057] 10, 10A board 10B Semiconductor layer 11 (first inorganic insulating film), 12 (second inorganic insulating film), 13 (third inorganic insulating film) inorganic insulating film 11A (1st opening), 12A (2nd opening), 13A (4th opening), 14A (3rd opening), 40A, 42A, 44A, 46A opening 14 Organic insulating film 15 (third metal layer), 16 (first metal layer), 16A, 16B, 18 (second metal layer), 18A (adhesion layer), 18B (low resistance layer) metal layer 15A, 17A, 19A top 17B, ​​19B bottom surface 20 Source electrode 21 Drain electrode 22 gate electrode 23 Source wiring 24S, 24D, 24G pads 25 Beer Hall 26 Bonding Area 40, 42, 44, 46 Mask layers 50 Stress 51, 53 End 52 Wedge 54 Routes 100, 102, 104, 110 Semiconductor device

Claims

1. a first metal layer disposed on the substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of an upper surface of the first metal layer; a second metal layer provided on the first metal layer, the second metal layer having a central portion of a lower surface in contact with the first metal layer through the first opening and a peripheral portion of the lower surface in contact with the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of an upper surface of the second metal layer; an organic insulating film covering the second inorganic insulating film, the organic insulating film having a third opening exposing the central portion of the upper surface of the second metal layer and overlapping the second opening when viewed in a thickness direction of the substrate; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein the second metal layer is thinner than the first metal layer.

3. 3. The semiconductor device according to claim 1, wherein a width of a lower surface of said second metal layer is smaller than a width of an upper surface of said first metal layer.

4. 3. The semiconductor device according to claim 1, wherein an outer periphery of said second opening is defined by an outer periphery of said third opening.

5. 3. The semiconductor device according to claim 1, wherein an outer periphery of said second opening is located inside an outer periphery of said third opening.

6. a third metal layer disposed on the substrate; a third inorganic insulating film covering the third metal layer and having a fourth opening in a central portion of an upper surface of the third metal layer; Equipped with 3. The semiconductor device according to claim 1, wherein a central portion of the lower surface of the first metal layer contacts the third metal layer through the third opening, and a peripheral portion of the lower surface of the first metal layer contacts the third inorganic insulating film outside the fourth opening.

7. 3. The semiconductor device according to claim 1, wherein the organic insulating film is a polyimide film or a BCB film.

8. the second inorganic insulating film is a silicon nitride film, 8. The semiconductor device according to claim 7, wherein at least an upper surface of said second metal layer is a gold layer.

9. 3. The semiconductor device according to claim 1, wherein the second metal layer has an adhesion layer including a lower surface of the second metal layer, and a low resistance layer provided on the adhesion layer and having a resistivity lower than that of the adhesion layer.

10. 3. The semiconductor device according to claim 1, wherein a region of the upper surface of said second metal layer exposed from said second opening and said third opening is a bonding region.

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