Semiconductor device, control method thereof, and control program

Abstract

A semiconductor device capable of reducing the circuit scale while suppressing deterioration in the quality of AD conversion, a control method for the semiconductor device, and a control program for the semiconductor device. [Solution] The semiconductor device according to the present disclosure comprises a plurality of sample-and-hold circuits that sample the voltage of an analog input signal at different timings and hold the voltages as a plurality of input voltages, a ramp signal generation circuit that generates a ramp signal whose potential changes linearly, a counter that performs a counting operation triggered by the start of the linear change in the ramp signal, a plurality of AD conversion circuits that output the count values ​​of the counter at the timing when each of a plurality of input voltages matches the voltage of the ramp signal as a plurality of digital signals corresponding to the plurality of input voltages, and a control circuit that controls the slope of the linear change in the ramp signal and the amount of change in the counter count value according to the count value of the counter, and outputs a plurality of digital signals as the result of AD conversion of the input signal.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a control method thereof, and a control program, and more particularly to a semiconductor device, a control method thereof, and a control program suitable for reducing circuit size while suppressing quality degradation of AD conversion, for example. [Background technology]

[0002] Touch panels and the like are equipped with semiconductor devices that perform AD conversion of analog input signals, including sine wave signals (pen signals) with a predetermined frequency whose amplitude increases due to the influence of an antenna coil when a touch pen approaches. These semiconductor devices are required to have a compact circuit scale while suppressing deterioration in AD conversion quality.

[0003] Techniques relating to AD conversion are disclosed in, for example, Patent Document 1, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2024-67061 [Non-patent literature]

[0005] [Non-Patent Document 1] Changbyung Park, et el., "A Pen-Pressure-Sensitive Capacitive Touch System Using Electrically Coupled Resonance Pen", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 1, JANUARY 2016 [Non-patent document 2] SangYun Kim, et el., "A 39.5-dB SNR, 300-Hz Frame-Rate, 56 × 70-Channel Read-Out IC for Electromagnetic Resonance Touch Panels", IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 6, JUNE 2018 [Non-patent document 3] Jun-Eun Park, et el., "A Noise-Immunity-Enhanced Analog Front-End for 36 × 64 Touch-Screen Controllers With 20-VPP Noise Tolerance at 100 kHz", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 5, MAY 2019 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, semiconductor devices mounted on touch panels and the like are required to have a smaller circuit size while suppressing degradation of AD conversion accuracy. However, there is a problem that, for example, if the number of AD converters that sample the voltage of a single input signal at different timings and convert it into a digital signal is reduced in order to reduce the circuit size, the AD conversion accuracy of the input signal will deteriorate. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a plurality of sample-and-hold circuits that sample the voltage of an analog input signal at different timings and hold the voltage as a plurality of input voltages, a ramp signal generation circuit that generates a ramp signal whose potential changes linearly, a counter that performs a counting operation triggered by the start of the linear change of the ramp signal, a plurality of comparison circuits that compare each of the plurality of input voltages with the voltage of the ramp signal, a plurality of latch circuits that output count values ​​of the counter at timings when each of the plurality of input voltages matches the voltage of the ramp signal as a plurality of digital signals corresponding to the plurality of input voltages, and a control circuit that controls the slope of the linear change of the ramp signal and the amount of change in the count value of the counter according to the count value of the counter, and outputs the plurality of digital signals as the results of AD conversion of the input signal.

[0008] A control method for a semiconductor device according to the present disclosure samples the voltage of an analog input signal at different timings, holds the voltages as multiple input voltages, triggers the start of a linear change in a ramp signal whose potential changes linearly to start counting by a counter, and outputs the count value of the counter at the timing when each of the multiple input voltages matches the voltage of the ramp signal as the AD conversion result of the input signal, and controls the slope of the linear change in the ramp signal and the amount of change in the count value of the counter according to the count value of the counter.

[0009] The control program according to the present disclosure is a control program that causes a computer to execute the following processes: sampling the voltage of an analog input signal at different timings and holding each as a plurality of input voltages; starting the counting operation of a counter when triggered by the start of a linear change in a ramp signal whose potential changes linearly; and outputting the count value of the counter at the timing when each of the plurality of input voltages matches the voltage of the ramp signal as the AD conversion result of the input signal; and further causes the computer to execute a process that controls the slope of the linear change of the ramp signal and the amount of change in the count value of the counter according to the count value of the counter. [Effects of the Invention]

[0010] The present disclosure can provide a semiconductor device that can reduce the circuit scale while suppressing deterioration in the quality of AD conversion, a control method for the semiconductor device, and a control program. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram illustrating a configuration example of a part of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating a configuration example of a ramp signal generating circuit provided in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a configuration of a counter provided in the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing an example of the control contents by the control circuit of the counter shown in FIG. [Figure 6] FIG. 6 is a diagram illustrating an example of settings for a high-speed operation mode in a register provided in the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing the signal waveforms of the input signal IN1 and the pen signal components contained therein. [Figure 8] FIG. 8 is a flowchart illustrating the operation of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a timing chart showing the operation of the semiconductor device according to the first embodiment in the high-speed operation mode. [Figure 10] FIG. 10 is a diagram illustrating the relationship between the input voltage and the output result in the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of settings for the normal operation mode of the register provided in the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a timing chart showing the operation of the semiconductor device according to the first embodiment in the normal operation mode. [Figure 13] FIG. 13 is a timing chart showing another example of the operation of the semiconductor device according to the first embodiment in the high-speed operation mode. [Figure 14] FIG. 14 is a block diagram illustrating a configuration example of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a block diagram illustrating a configuration example of a part of a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on the description in the drawings. Furthermore, identical elements are given the same reference numerals, and duplicate explanations will be omitted.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0014] Furthermore, in the following embodiments, the components (including operational steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or approximate to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, numerical values, amounts, ranges, etc.).

[0015] <First Embodiment> 1 is a block diagram showing a configuration example of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 is a device that is mounted on, for example, a touch panel and performs AD conversion on an analog input signal that includes a sine wave signal (hereinafter also referred to as a pen signal) of a predetermined frequency whose amplitude increases due to the influence of an antenna coil when a touch pen approaches.

[0016] 1, the semiconductor device 1 includes m (m is an integer of 2 or more) AD converters 11_1 to 11_m, a ramp signal generating circuit 12, a counter 13, a control circuit 14, and a register (reg) 15. The register 15 may be built into the control circuit 14.

[0017] The AD converters 11_1 to 11_m perform AD conversion on different analog input signals IN1 to INm, respectively. Each of the AD converters 11_1 to 11_m is made up of n (n is an integer of 2 or more) AD conversion circuits.

[0018] Fig. 2 is a block diagram showing a configuration example of a portion of the semiconductor device 1. The example in Fig. 2 shows a configuration example of AD converter 11_1 among AD converters 11_1 to 11_m. AD ​​converter 11_1 is composed of n AD conversion circuits AD1 to ADn. AD converters 11_2 to 11_m have the same configuration as AD converter 11_1 except that input signals IN2 to INm are input instead of input signal IN1, respectively, and therefore description thereof will be omitted.

[0019] The AD conversion circuit AD1 includes a sample-and-hold circuit SH1, a comparison circuit CMP1, and a latch circuit LTC1. The AD conversion circuit AD2 includes a sample-and-hold circuit SH2, a comparison circuit CMP2, and a latch circuit LTC2. Similarly, the AD conversion circuit ADn includes a sample-and-hold circuit SHn, a comparison circuit CMPn, and a latch circuit LTCn.

[0020] The ramp signal generating circuit 12 generates a ramp signal RS whose potential changes linearly. The counter 13 is triggered by the start of the linear change of the ramp signal RS and performs a counting operation in synchronization with the rising edge of the clock signal CLK. The control circuit 14 controls the slope of the linear change of the ramp signal RS and the amount of change in the count value of the counter 13 (the count value that increases per one count-up operation of the counter 13) based on digital codes Ci and Cs extracted from a register 15 in accordance with the count value of the counter 13.

[0021] The sample-and-hold circuits SH1 to SHn sample the voltage of the analog input signal IN1 at different timings and hold the voltage as input voltages V1 to Vn, respectively.

[0022] The comparator circuits CMP1 to CMPn compare the input voltages V1 to Vn with the voltage of the ramp signal RS, the potential of which changes linearly. Note that the comparison by the comparator circuits CMP1 to CMPn starts when the potential of the ramp signal RS starts to change linearly and the counter 13 starts counting.

[0023] The latch circuits LTC1 to LTCn output the count values ​​of the counter 13 at the timing when each of the input voltages V1 to Vn matches the voltage of the ramp signal RS as a plurality of digital signals O1 to On corresponding to the input voltages V1 to Vn, respectively.

[0024] AD converter 11_1 outputs these digital signals O1 to On as the AD conversion result OUT1 of input signal IN1. Similarly, AD converter 11_2 outputs the AD conversion result OUT2 of input signal IN2. AD converter 11_m outputs the AD conversion result OUTm of input signal INm.

[0025] (Configuration example of the ramp signal generating circuit 12) 3 is a diagram illustrating an example of the configuration of the ramp signal generation circuit 12. As illustrated in FIG. 3, the ramp signal generation circuit 12 includes a current DAC (Digital-to-Analog Converter) 121 and an operational amplifier 122. A current corresponding to the digital code Ci from the control circuit 14 flows through the current DAC 121. The operational amplifier 122 outputs, as the ramp signal RS, an output signal corresponding to the potential difference between a voltage obtained by feeding back the output signal of the operational amplifier 122 and an analog voltage corresponding to the current flowing through the current DAC 121. As a result, for example, the potential of the ramp signal RS increases linearly with a slope (slew rate) corresponding to the digital code Ci. Note that as the current flowing through the current DAC 121 decreases according to the digital code Ci, the slope of the linear change in the potential of the ramp signal RS decreases, and as the current flowing through the current DAC 121 increases according to the digital code Ci, the slope of the linear change in the potential of the ramp signal RS increases. For example, when the current flowing through the current DAC121 is 4i, the slope of the linear change in the potential of the ramp signal RS is four times as large as when the current flowing through the current DAC121 is i.

[0026] (Example of counter 13 configuration) Fig. 4 is a diagram showing an example of the configuration of the counter 13. The counter 13 includes p (p is an integer equal to or greater than 2) flip-flops FF1 to FFp and p selectors SEL1 to SELp. In the example of Fig. 4, three flip-flops FF1 to FF3 and three selectors SEL1 to SEL3 are shown.

[0027] The selector SEL1 selects and outputs either a fixed signal representing a fixed value "0" or the clock signal CLK based on the digital code Cs[0] (the value of the least significant bit (first bit) of the digital code Cs). The flip-flop FF1 outputs a count value CNT[0] (the value of the least significant bit (first bit) of the count value CNT) whose logical value changes in synchronization with the rising edge of the output signal of the selector SEL1.

[0028] The selector SEL2 selects and outputs either the inverted signal of the output signal of the flip-flop FF1 or the clock signal CLK based on the digital code Cs[1] (the value of the second bit of the digital code Cs). The flip-flop FF2 outputs the count value CNT[1] (the value of the second bit of the count value CNT) whose logical value changes in synchronization with the rising edge of the output signal of the selector SEL2.

[0029] The selector SEL3 selects and outputs either the inverted signal of the output signal of the flip-flop FF2 or the clock signal CLK based on the digital code Cs[2] (the value of the third bit of the digital code Cs). The flip-flop FF3 outputs the count value CNT[2] (the value of the third bit of the count value CNT) whose logical value changes in synchronization with the rising edge of the output signal of the selector SEL3.

[0030] Similarly, the selector SELp selects and outputs either the inverted signal of the output signal of the flip-flop FFp-1 or the clock signal CLK based on the control signal S[p-1] (the value of the most significant bit (p-th bit) of the control signal S). The flip-flop FFp outputs a count value CNT[p-1] (the value of the most significant bit (p-th bit) of the count value CNT) whose logical value changes in synchronization with the rising edge of the output signal of the selector SELp.

[0031] Fig. 5 is a diagram showing an example of the control of the counter 13 by the control circuit 14. As shown in Fig. 5, for example, when the digital code Cs[0] (the value of the first bit of the digital code Cs) of the p-bit digital code Cs[p-1:0] is set to "1" and the rest are set to "0", the clock signal CLK is selected only by the selector SEL1 of the selectors SEL1 to SELp, and therefore the count value (hereinafter also referred to as a counter step) that increases per count-up operation of the counter 13 becomes "1".

[0032] Furthermore, for example, when digital code Cs[1] (the value of the second bit of digital code Cs) of p-bit width digital code Cs[p-1:0] is set to "1" and the others are set to "0", the clock signal CLK is selected only by selector SEL2 of selectors SEL1 to SELp, and the counter step becomes "2". When the counter step is "2", the amount of change in the count value of counter 13 is doubled compared to when the counter step is "1".

[0033] Furthermore, for example, when digital code Cs[2] (the value of the third bit of digital code Cs) of p-bit wide digital code Cs[p-1:0] is set to "1" and the others are set to "0", clock signal CLK is selected only by selector SEL3 among selectors SEL1 to SELp, and the counter step becomes "4". When the counter step is "4", the amount of change in the count value of counter 13 is four times larger than when the counter step is "1".

[0034] Here, the control circuit 14 adjusts the counter step by causing one of the selectors SEL1 to SELp to select the clock signal CLK in accordance with the count value of the counter 13.

[0035] (Example of register 15 setting) Fig. 6 is a diagram showing an example of the setting contents of the register 15. For example, the register 15 stores a plurality of combinations of the range of the count value of the counter 13 and digital codes Ci and Cs that respectively represent the slope of the linear change of the ramp signal RS (the current value of the current DAC in this example) and the amount of change (counter step) of the count value of the counter 13. In the example of Fig. 6, the register 15 stores setting contents for a high-speed operation mode.

[0036] For example, the register 15 stores, for the high-speed operation mode, a combination of a count value range of "0 to 408" and digital codes Ci and Cs representing a current value of "4i" of the current DAC and a counter step of "4". The register 15 also stores a combination of a count value range of "409 to 613" and digital codes Ci and Cs representing a current value of "i" of the current DAC and a counter step of "1". The register 15 also stores a combination of a count value range of "614 to 1022" and digital codes Ci and Cs representing a current value of "4i" of the current DAC and a counter step of "4".

[0037] (Operation of the semiconductor device 1) Next, the operation of the semiconductor device 1 in the high-speed operation mode will be described with reference to Fig. 7 to Fig. 9. Fig. 7 is a diagram showing the signal waveforms of the input signal IN1 and the pen signal component contained therein. Fig. 8 is a flowchart showing the operation of the semiconductor device 1. Fig. 9 is a timing chart showing the operation of the semiconductor device 1 in the high-speed operation mode.

[0038] Below, the flow of AD conversion processing of input signal IN1 by AD converter 11_1 among AD converters 11_1 to 11_m provided in semiconductor device 1 will be described, but the same can be said for AD conversion processing of input signals IN2 to INm by AD converters 11_2 to 11_m.

[0039] 7, input signal IN1 includes not only a sine wave signal (pen signal) of a predetermined frequency whose amplitude increases due to the influence of the antenna coil when a touch pen approaches the touch panel, but also high-amplitude high-frequency noise components. For example, within the input range of 0.4V to 2.4V of each AD converter, the amplitude of the pen signal is in the range of 1.2V to 1.6V, while the amplitude of the high-frequency noise is in the range of 0.8V to 2V. Therefore, in the high-speed operation mode, semiconductor device 1 according to the present disclosure increases the AD conversion accuracy in the center region of the amplitude of input signals IN1 to INm, which is the region that includes the pen signal component, within the input range of each AD converter 11_1 to 11_m, while decreasing the AD conversion accuracy in the end regions of the amplitude of input signals IN1 to INm, which are the region that includes the noise component, thereby increasing the AD conversion speed.

[0040] First, in the semiconductor device 1, the register 15 is set (step S101). Specifically, the register 15 is set with a combination of the range of the count value of the counter 13, the gradient of the linear change of the ramp signal RS (the current value of the current DAC in this example), and the digital codes Ci and Cs representing the amount of change (counter step) of the count value of the counter 13, as shown in Fig. 6 .

[0041] Thereafter, the counter 13 is initialized (step S102). Specifically, the count value of the counter 13 is initialized to "0".

[0042] Thereafter, the control circuit 14 acquires the digital codes Ci and Cs corresponding to the count value of the counter 13 from the register 15 (step S103). Specifically, the control circuit 14 acquires the digital codes Ci and Cs representing the current value of the current DAC="4i" and the counter step="4", respectively, according to the count value "0".

[0043] Thereafter, the control circuit 14 controls the current value of the current DAC 121 and the change amount (counter step) of the count value of the counter 13 based on the acquired digital codes Ci and Cs (step S104). Specifically, the control circuit 14 controls the current value of the current DAC 121 to “4i” and the counter step to “4.” As a result, the slope of the linear change of the ramp signal RS becomes “4α,” which is four times that of the normal state (i.e., when the current value of the current DAC 121 is “i”), and the count value increased per count-up operation of the counter 13 becomes “4,” which is four times that of the normal state (i.e., when the counter step is “1”). Then, the control circuit 14 starts the count operation by the counter 13 and the generation of the ramp signal RS by the ramp signal generation circuit 12 (step S105). Therefore, in the lower end region of the amplitude of the input signal IN1, which is a region containing noise components, high-speed AD conversion is performed with relatively low accuracy. For example, AD conversion with 8-bit accuracy is performed.

[0044] Here, each AD conversion circuit AD1 to ADn that constitutes the AD converter 11_1 compares the held input voltage with the voltage of the ramp signal RS, and outputs the count value of the counter 13 at the time when the held input voltage matches the voltage of the ramp signal RS as part of the AD conversion result OUT1 (step S106).

[0045] Furthermore, until the count value of the counter 13 overflows (or until a stop signal for the AD conversion process is received), the control circuit 14 acquires the digital codes Ci and Cs corresponding to the count value from the register 15 each time the count value of the counter 13 changes, and controls the current value of the current DAC 121 and the amount of change in the count value of the counter 13 based on the acquired digital codes Ci and Cs (NO in steps S107 → S108 → S109).

[0046] For example, when the count value of the counter 13 reaches "409," the control circuit 14 acquires digital codes Ci and Cs from the register 15, which respectively represent the current value of the current DAC = "i" and the counter step = "1." Based on the acquired digital codes Ci and Cs, the control circuit 14 controls the current value of the current DAC 121 to "i" and the counter step to "1." As a result, the slope of the linear change in the ramp signal RS becomes the normal slope "α," and the count value incremented per count-up operation of the counter 13 becomes "1." Therefore, in the central region of the amplitude of the input signal IN1, which is the region containing the pen signal component, slow but highly accurate AD conversion is performed. For example, AD conversion with 10-bit accuracy is performed.

[0047] Furthermore, when the count value of the counter 13 reaches "614," the control circuit 14 acquires digital codes Ci and Cs from the register 15, representing the current value of the current DAC = "4i" and the counter step = "4," respectively. Based on the acquired digital codes Ci and Cs, the control circuit 14 controls the current value of the current DAC 121 to "4i" and the counter step to "4." As a result, the slope of the linear change of the ramp signal RS becomes "4α," four times the normal slope, and the count value incremented per count-up operation of the counter 13 becomes "4," four times the normal slope. Therefore, in the upper end region of the amplitude of the input signal IN1, which contains noise components, high-speed AD conversion is performed with relatively low accuracy. For example, AD conversion with 8-bit accuracy is performed.

[0048] Each AD conversion circuit AD1 to ADn that constitutes the AD converter 11_1 continues to compare the held input voltage with the voltage of the ramp signal RS until the count value overflows (or until the AD conversion process is stopped by the control circuit 14), and outputs the count value of the counter 13 at the time when the held input voltage matches the voltage of the ramp signal as part of the AD conversion result OUT1 (step S106).

[0049] Thereafter, when the count value of the counter 13 overflows (YES in step S109), the semiconductor device 1 ends the AD conversion process of the sampled input signal IN1 by the AD converter 11_1. Note that, when the semiconductor device 1 performs AD conversion process of the next sampled input signal IN1 by the AD converter 11_1, the semiconductor device 1 repeats the processes of steps S101 to S109.

[0050] 10 is a diagram showing the relationship between the voltage of the input signal IN1 of the AD converter 11_1 and the AD conversion result. As shown in Fig. 10, in the semiconductor device 1, the change amount (counter step) of the count value of the counter 13 is switched in accordance with the change in the slope of the linear change of the ramp signal RS (in this example, the current value of the current DAC), so that even if the AD conversion accuracy is switched midway, the AD conversion result does not deviate from the ideal characteristic.

[0051] (Comparative Example) Fig. 11 is a diagram showing an example of the setting contents for the normal operation mode of the register 15. In the example of Fig. 6, the setting contents for the high-speed operation mode are stored in the register 15. In contrast, in the example of Fig. 11, as a comparative example, the setting contents for the normal operation mode are stored in the register 15. Fig. 12 is a timing chart showing the operation of the semiconductor device 1 in the normal operation mode.

[0052] For example, register 15 stores, for the normal operation mode, a combination of the count value range of "0 to 1023" and digital codes Ci and Cs representing the current value of the current DAC = "i" and the counter step = "1", respectively.

[0053] For example, when the count value of the counter 13 is initialized to “0,” the control circuit 14 acquires digital codes Ci and Cs from the register 15, which respectively represent the current value of the current DAC=“i” and the counter step=“1.” Based on the acquired digital codes Ci and Cs, the control circuit 14 controls the current value of the current DAC 121 to “i” and the counter step to “1.” As a result, the slope of the linear change of the ramp signal RS becomes the normal slope “α,” and the count value incremented per count-up operation of the counter 13 becomes “1.” This setting is maintained until the count value of the counter 13 reaches “1023” and overflows. Therefore, highly accurate AD conversion is always performed on the input signal IN1. In other words, highly accurate but relatively slow AD conversion is performed not only in the central region of the amplitude of the input signal IN1, which contains the pen signal component, but also in both end regions of the amplitude of the input signal IN1, which contains the noise component.

[0054] Comparing the AD conversion of the AD converter 11_1 in the normal operation mode shown in FIG. 12 with the AD conversion of the AD converter 11_1 in the high-speed operation mode shown in FIG. 9, the AD conversion time in the normal operation mode is 1054 clocks, which is the sum of the 30 clocks for the settling time and the 1024 clocks for the comparison time, whereas the AD conversion time in the high-speed operation mode is 441 clocks, which is the sum of the 30 clocks for the settling time and the 411 clocks for the comparison time, which is a reduction of 613 clocks.

[0055] As described above, the semiconductor device 1 according to this embodiment increases the AD conversion accuracy in the central region of the amplitude of the input signals IN1 to INm, which is a region containing pen signal components, within the input range of each AD converter 11_1 to 11_m, while decreasing the AD conversion accuracy in both end regions of the amplitude of the input signals IN1 to INm, which are regions containing noise components, thereby increasing the AD conversion speed. The semiconductor device 1 according to this embodiment switches the amount of change (counter step) in the count value of the counter 13 in response to switching of the slope of the linear change of the ramp signal RS (the current value of the current DAC in this example), thereby preventing the AD conversion result from deviating from the ideal characteristics even when the AD conversion accuracy is switched midway (see FIG. 10). This allows the semiconductor device 1 according to this embodiment to achieve high-speed AD conversion while suppressing quality degradation. Note that achieving high-speed AD conversion means, for example, that it is possible to reduce the number of AD conversion circuits AD1 to ADn required to complete AD conversion of the input signal IN1 by the AD converter 11_1 within a predetermined time. Therefore, the semiconductor device 1 according to this embodiment can reduce the circuit scale while suppressing deterioration in the quality of AD conversion.

[0056] (Modification of Semiconductor Device 1) The semiconductor device 1 is not limited to being applied to a touch panel, but may also be applied to, for example, a CMOS image sensor. In the CMOS image sensor, the count value of the counter 13 at the timing when a pixel signal (corresponding to an input voltage V1 or the like) indicating a potential according to the amount of light received by a pixel and a ramp signal RS coincide is output as a digital signal (corresponding to a digital signal O1 or the like) corresponding to the pixel signal.

[0057] Meanwhile, AD conversion of pixel signals requires higher sensitivity as the luminance of the pixel signal decreases. Therefore, as shown in the timing chart of FIG. 13 , the semiconductor device 1 performs high-precision AD conversion (approximately 10-bit accuracy) on pixel signals with low luminance, medium-precision AD conversion (approximately 9-bit accuracy) on pixel signals with medium luminance, and high-speed AD conversion with relatively low precision (approximately 8-bit accuracy) on pixel signals with high luminance. The semiconductor device 1 prevents the AD conversion result from deviating from the ideal characteristics even when the AD conversion precision is switched midway by switching the slope of the linear change of the ramp signal RS (in this example, the current value of the current DAC) and the change amount (counter step) of the count value of the counter 13. This allows the semiconductor device 1 according to this embodiment to achieve high-speed AD conversion while suppressing quality degradation. Note that achieving high-speed AD conversion means, for example, that it is possible to reduce the number of AD conversion circuits (corresponding to AD1 to ADn) required to complete AD conversion of a predetermined number of pixel signals within a predetermined time. Therefore, the semiconductor device 1 according to this embodiment can reduce the circuit size while suppressing quality degradation of AD conversion. In the example of FIG. 13, the ramp signal RS decreases linearly.

[0058] <Embodiment 2> Fig. 14 is a block diagram showing a configuration example of a semiconductor device 2 according to the second embodiment. Fig. 15 is a block diagram showing a configuration example of a part of the semiconductor device 2. The example of Fig. 15 shows a configuration example of AD converter 11_1 among AD converters 11_1 to 11_m. AD ​​converters 11_2 to 11_m have the same configuration as AD converter 11_1 except that input signals IN2 to INm are input instead of input signal IN1, respectively, and therefore description thereof will be omitted.

[0059] Compared to the semiconductor device 1, the semiconductor device 2 further includes PGAs 21_1 to 21_m and a detection circuit 22. PGA stands for Programmable Gain Amplifier. The other configurations of the semiconductor device 2 are similar to those of the semiconductor device 1, and therefore description thereof will be omitted.

[0060] The detection circuit 22 first detects the waveform amplitudes of the AD conversion results OUT1 to OUTm of the AD converters 11_1 to 11_m. These waveform amplitudes also contain noise components. The detection circuit 22 further resolves the AD conversion results OUT1 to OUTm of the AD converters 11_1 to 11_m into frequency components and outputs them as DFT results. DFT is an abbreviation for Discrete Fourie Transform.

[0061] PGAs 21_1 to 21_m are provided in the preceding stages of AD converters 11_1 to 11_m, respectively. PGAs 21_1 to 21_m adjust the amplitudes of input signals IN1 to INm input to AD converters 11_1 to 11_m to be optimal based on waveform amplitude information detected by detection circuit 22. Specifically, PGAs 21_1 to 21_m adjust the amplitudes of input signals IN1 to INm input to AD converters 11_1 to 11_m to be as large as possible without exceeding the input range of AD converters 11_1 to 11_m. AD ​​converters 11_1 to 11_m perform AD conversion of input signals IN1 to INm whose amplitudes have been adjusted by PGAs 21_1 to 21_m, respectively.

[0062] The control circuit 14 adjusts the setting contents of the register 15 (i.e., the digital code and the range of the count value of the counter 13 corresponding to the digital code) based on the amplitude of the predetermined frequency component (specifically, the frequency component of the pen signal) extracted by the detection circuit 22. In other words, the control circuit 14 adjusts the range in which AD conversion is performed with high precision and the AD conversion precision so that the pen signal component included in the input signal is AD converted accurately and with high precision.

[0063] As a result, the semiconductor device 2 according to this embodiment can achieve effects equivalent to those of the semiconductor device 1. Furthermore, the semiconductor device 2 according to this embodiment can more accurately perform AD conversion of a signal with a desired frequency component by feeding back the result of the detection circuit 22 and causing the control circuit 14 to adjust the setting contents of the register 15 or adjust the gain of the PGA.

[0064] In this embodiment, an example has been described in which the results of the detection circuit 22 are fed back to the PGAs 21_1 to 21_m and the control circuit 14, but this is not limited to this, and the results may be fed back to only one of the PGAs 21_1 to 21_m and the control circuit 14.

[0065] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention.

[0066] In the present disclosure, part or all of the processing of each of the semiconductor devices 1 and 2 can be realized by causing a CPU to execute a computer program.

[0067] The above-described program includes a set of instructions (or software code) that, when loaded into a computer, causes the computer to perform one or more functions described in the embodiments. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, computer-readable media or tangible storage media include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drives (SSD) or other memory technologies, CD-ROMs, digital versatile discs (DVDs), Blu-ray discs or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices. The program may also be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, transitory computer-readable media or communication media include electrical, optical, acoustic, or other forms of propagated signals. [Explanation of symbols]

[0068] 1. Semiconductor device 2. Semiconductor Devices 11_1~11_m AD converter 12 Ramp signal generation circuit 13 Counter 14 Control circuit 15 Register (reg) 21_1~21_m PGA 22 Detection circuit 121 Current DAC 122 operational amplifiers AD1 to ADn AD conversion circuits CMP1 to CMPn comparison circuits FF1~FFp flip-flops LTC1~LTCn latch circuits SEL1~SELp selector SH1~SHn Sample and hold circuits

Claims

1. a plurality of sample-and-hold circuits that sample the voltage of an analog input signal at different timings and hold the sampled voltage as a plurality of input voltages; a ramp signal generating circuit that generates a ramp signal whose potential changes linearly; a counter that performs a counting operation when the start of a linear change in the ramp signal is triggered; a plurality of comparison circuits that compare each of the plurality of input voltages with the voltage of the ramp signal; a plurality of latch circuits configured to output count values ​​of the counter at timings when the plurality of input voltages and the voltage of the ramp signal coincide with each other as a plurality of digital signals corresponding to the plurality of input voltages; a control circuit that controls a slope of the linear change of the ramp signal and an amount of change in the count value of the counter according to the count value of the counter, outputting the plurality of digital signals as AD conversion results of the input signal; Semiconductor device.

2. when the control circuit switches the slope of the linear change of the ramp signal from a first slope to a second slope smaller than the first slope, the control circuit switches the amount of change in the count value of the counter from a first amount of change to a second amount of change smaller than the first amount of change, and when the control circuit switches the slope of the linear change of the ramp signal from the second amount of change to the first amount of change. The semiconductor device according to claim 1 .

3. the control circuit is configured to output a control signal of a digital code corresponding to the count value of the counter; The ramp signal generating circuit a DA conversion circuit that converts the digital code of the control signal into an analog signal; an amplifier circuit that outputs the ramp signal according to a potential difference between an output signal of the DA converter circuit and a feedback signal of the ramp signal; having The semiconductor device according to claim 1 .

4. a first selector that selects and outputs either a fixed signal representing a fixed value or a clock signal; a first flip-flop that outputs a first bit value, which is a least significant bit whose logical value changes in synchronization with a rising edge of an output signal of the first selector, among the values ​​of the plurality of bits that make up the count value; second to m-th selectors for selecting and outputting either the clock signal or an output signal of a corresponding one of first to m-th (m is an integer of 2 or more) flip-flops; second to n-th flip-flops outputting second to n-th (n is m+1) bit values, the logical values ​​of which change in synchronization with rising edges of the output signals of the second to m-th selectors, among the values ​​of the plurality of bits constituting the count value; and the control circuit causes one of the first to nth selectors to select the clock signal in accordance with the count value of the counter; The semiconductor device according to claim 1 .

5. a register storing a plurality of combinations of a range of the count value of the counter, and a digital code representing each of a slope of a linear change of the ramp signal and an amount of change of the count value of the counter; the control circuit controls the slope of the linear change of the ramp signal and the amount of change in the count value of the counter based on the digital code extracted from the register according to the count value of the counter. The semiconductor device according to claim 1 .

6. a detection circuit that decomposes the AD conversion result into frequency components and outputs the result as a DFT (Discrete Fourier Transform) result; the control circuit adjusts the digital code and the range of the count value of the counter corresponding to the digital code based on the amplitude of the predetermined frequency component extracted by the detection circuit. The semiconductor device according to claim 5 .

7. The detection circuit further detects a waveform amplitude of the AD conversion result, The semiconductor device includes: The apparatus further includes a plurality of programmable gain amplifiers that adjust the amplitude of the input signal based on the waveform amplitude detected by the detection circuit. The semiconductor device according to claim 6.

8. The voltage of the analog input signal is sampled at different times and held as multiple input voltages. The start of a linear change in the ramp signal, whose potential changes linearly, is used as a trigger to start the counting operation of the counter; a count value of the counter at a timing when each of the plurality of input voltages and a voltage of the ramp signal coincide with each other is output as an AD conversion result of the input signal; A method for controlling a semiconductor device, comprising: a slope of the linear change of the ramp signal and an amount of change in the count value of the counter are controlled according to the count value of the counter; A method for controlling a semiconductor device.

9. In controlling the slope of the linear change of the ramp signal and the amount of change in the count value of the counter, when the slope of the linear change of the ramp signal is switched from a first slope to a second slope smaller than the first slope, the amount of change in the count value of the counter is switched from a first amount of change to a second amount of change smaller than the first amount of change, and when the slope of the linear change of the ramp signal is switched from the second amount of change to the first amount of change. The method for controlling a semiconductor device according to claim 8.

10. The process of sampling the voltage of an analog input signal at different times and holding each as multiple input voltages. A process of starting a counting operation of a counter using the start of a linear change of a ramp signal whose potential changes linearly as a trigger; a process of outputting a count value of the counter at a timing when each of the plurality of input voltages and a voltage of the ramp signal coincide with each other as an AD conversion result of the input signal; A control program for causing a computer to execute the above, and further causing the computer to execute a process of controlling a gradient of the linear change of the ramp signal and an amount of change in the count value of the counter according to the count value of the counter. Control program.

11. In the process of controlling the gradient of the linear change of the ramp signal and the amount of change in the count value of the counter, when the gradient of the linear change of the ramp signal is switched from a first gradient to a second gradient smaller than the first gradient, the amount of change in the count value of the counter is switched from a first amount of change to a second amount of change smaller than the first amount of change, and when the gradient of the linear change of the ramp signal is switched from the second gradient to the first gradient, the amount of change in the count value of the counter is switched from the second amount of change to the first amount of change. The control program according to claim 10.

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