Semiconductor device and manufacturing method

Abstract

The semiconductor device according to the embodiment provides a semiconductor device that prevents a decrease in breakdown voltage by controlling the shape of the gate electrode. [Solution] The semiconductor device according to an embodiment includes a first electrode, a second electrode, and a first semiconductor layer of a first conductivity type disposed between the first and second electrodes and electrically connected to the first electrode. A second semiconductor layer of a second conductivity type is disposed thereon, and a third semiconductor layer of the first conductivity type is disposed between the second semiconductor layer and the second electrode. A field plate electrode extends in a first direction from the first semiconductor layer to the second semiconductor layer and has a field plate insulating layer surrounding the field plate electrode. The semiconductor device further includes a gate electrode having one side surface disposed between the first semiconductor layer and the field plate electrode, a second side surface facing the first side surface, and a first surface connected to the first and second side surfaces and in contact with the field plate insulating layer, the first side surface being spaced apart from the first side surface and the second side surface and having an apex protruding toward the first electrode.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used as switching elements. During the manufacturing process, etching of the insulating layer surrounding the field plate determines the shape of the polysilicon gate electrode.

[0003] If the shape of the gate electrode is acute at the interface between the gate electrode and the thin insulating layer, localized electric field concentration is likely to occur, leading to breakdown of the gate insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2022-137629 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-115225 [Patent Document 3] Japanese Patent Publication No. 2022-047934 [Patent Document 4] Japanese Patent Publication No. 2021-044314 [Patent Document 5] Japanese Patent Publication No. 2020-150185 [Patent Document 6] Japanese Patent Application Publication No. 2019-145701 [Patent Document 7] Japanese Patent Application Laid-Open No. 2015-023166 [Patent Document 8] Japanese Patent Application Laid-Open No. 2014-187182 Summary of the Invention [Problem to be solved by the invention]

[0005] The semiconductor device according to the embodiment provides a semiconductor device that prevents a decrease in breakdown voltage by controlling the shape of the gate electrode. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a first electrode, a second electrode, and a first semiconductor layer of a first conductivity type disposed between the first and second electrodes and electrically connected to the first electrode. A second semiconductor layer of a second conductivity type is disposed thereon, and a third semiconductor layer of the first conductivity type is disposed between the second semiconductor layer and the second electrode. A field plate electrode extends in a first direction from the first semiconductor layer to the second semiconductor layer and has a field plate insulating layer surrounding the field plate electrode. The semiconductor device further includes a gate electrode having a first side surface disposed between the first semiconductor layer and the field plate electrode, a second side surface facing the first side surface, and a first surface connected to the first and second side surfaces and in contact with the field plate insulating layer, the first side surface being spaced apart from the first side surface and the second side surface and having an apex protruding toward the first electrode. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device 100 according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a portion A surrounded by a dashed line in FIG. [Figure 3] 2A to 2C are schematic cross-sectional views illustrating a part of the manufacturing process of the semiconductor device 100 according to the first embodiment. [Figure 4] 4 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 3. [Figure 5] 5 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 4. [Figure 6] 6 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 5. [Figure 7] 7 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 6. [Figure 8] Schematic cross-sectional view showing part of the manufacturing process following Figure 7 [Figure 9] 9 is a cross-sectional view showing a portion B surrounded by a dashed line in FIG. 8. [Figure 10] 9 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 8. [Figure 11] 11 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 10. [Figure 12] 12 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 11. [Figure 13] 13 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 12. [Figure 14] 14 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 13. [Figure 15] 15 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 14. [Figure 16] 16 is a schematic cross-sectional view showing a part of the manufacturing process following FIG. 15. [Figure 17] FIG. 1 is a schematic cross-sectional view showing a semiconductor device 200 according to a first comparative example. [Figure 18] 18 is a cross-sectional view showing a portion C surrounded by a dashed line in FIG. 17. [Figure 19] 5A to 5C are schematic cross-sectional views illustrating a part of the manufacturing process of the semiconductor device 200 according to the first comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are designated by common reference numerals throughout the drawings.

[0009] It should be noted that this embodiment does not limit the present invention, and the dimensional ratios in the drawings are not limited to those shown. In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but this is not intended to be limiting. The first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0010] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n,- indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The shape is simply n-type, p-type + type, p - The shape is sometimes simply referred to as p-shape.

[0011] [First embodiment] (Structure of the semiconductor device 100) A detailed structure of the semiconductor device 100 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment, and Figure 2 is a cross-sectional view showing a portion A surrounded by a dashed line in Figure 1.

[0012] 1, the semiconductor device 100 includes a drain electrode 10, a gate electrode 13, a source electrode 14, an n-type semiconductor region 22, a p-type semiconductor region 23, an n-type source layer 26, a field plate electrode 30, and a field plate insulating layer 40.

[0013] Here, the drain electrode 10 is an example of a first electrode, and the source electrode 14 is an example of a second electrode.

[0014] The direction from the drain electrode 10 toward the n-type semiconductor region 22 is defined as the Z direction (first direction). The direction perpendicular to the Z direction is defined as the X direction (second direction), and the direction perpendicular to the X and Z directions is defined as the Y direction (third direction). The semiconductor device 100 shown in FIG. 1 is shown in a cross-sectional view in the XZ plane. For the sake of explanation, the direction from the drain electrode 10 toward the n-type semiconductor region 22 will be referred to as "up" and the opposite direction will be referred to as "down."

[0015] 1 includes, for example, an n-type drift layer 20 and a p-type base layer 24. The p-type base layer 24 is provided on the n-type drift layer 20 in the Z direction.

[0016] An n-type source layer 26 and a p-type contact layer 25 are provided in parallel on the p-type base layer 24. On the other hand, an n-type drain layer 21 is provided in the −Z direction of the n-type drift layer 20.

[0017] The n-type semiconductor region 22 is composed of an n-type drift layer 20 and an n-type drain layer 21. The p-type semiconductor layer 23 is composed of a p-type base layer 24 and a p-type contact layer 25. Note that the n-type drain layer 21 and the p-type contact layer 25 are not necessarily required components. The n-type semiconductor region 22 may consist of only the n-type drift layer 20. The p-type semiconductor layer 23 may consist of only the p-type base layer 24.

[0018] Here, the n-type drift layer 20 is an example of a first semiconductor layer of the first conductivity type, the p-type base layer 24 is an example of a second semiconductor layer of the second conductivity type, the n-type source layer 26 is an example of a third semiconductor layer of the first conductivity type, the n-type drain layer 21 is an example of a fourth semiconductor layer of the first conductivity type, and the p-type contact layer 25 is an example of a fifth semiconductor layer of the second conductivity type.

[0019] The n-type impurity concentration of the n-type drain layer 21 is higher than the n-type impurity concentration of the n-type drift layer 20. The p-type impurity concentration of the p-type contact layer 25 is higher than the p-type impurity concentration of the p-type base layer .

[0020] Here, the n-type drain layer 21, the n-type drift layer 20, the p-type base layer 24, the n-type source layer 26, and the p-type contact layer 25 contain silicon (Si) or silicon carbide (SiC) as semiconductor materials. When silicon is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity. Boron (B) can be used as the p-type impurity.

[0021] The semiconductor device 100 has a trench U that extends from the upper surface of the n-type source layer 26, passing through the n-type source layer 26 and the p-type base layer 24, and into the n-type drift layer 20. A field plate electrode 30 is provided inside the trench U, extending in a direction from the p-type base layer 24 toward the n-type drain layer 21. The field plate electrode 30 is surrounded by the n-type drift layer 20 via a field plate insulating layer 40.

[0022] Inside trench U, a gate electrode 13 is provided on the upper end of field plate insulating layer 40 in the Z direction. Gate electrode 13 faces p-type base layer 24 in the X direction. A gate insulating layer 44 is provided between gate electrode 13 and p-type base layer 24. The thickness of gate insulating layer 44 is thinner than that of field plate insulating layer 40.

[0023] Furthermore, a field plate electrode upper end portion 30c is provided at the upper end of the field plate electrode 30 in the Z direction. The field plate electrode upper end portion 30c extends between the two gate electrodes 13 in the X direction. That is, the gate electrodes 13 are located between the field plate electrode 30 and the p-type base layer 24. A first interlayer insulating layer 45 is provided between the field plate electrode upper end portion 30c and the gate electrodes 13.

[0024] A second interlayer insulating layer 46 is provided on the gate electrode 13 and the field plate electrode upper end 30c. A source electrode 14 is provided on the second interlayer insulating layer 46, the n-type source layer 26, and the p-type contact layer 25. The source electrode 14 is electrically connected to the n-type source layer 26 and to the p-type base layer 24 via the p-type contact layer 25. Meanwhile, in the −Z direction of the n-type drift layer 20, a drain electrode 10 is provided on the back surface side of the n-type drain layer 21.

[0025] Here, the drain electrode 10 and the source electrode 14 contain a metal such as Al or Cu. The field plate electrode 30 and the gate electrode 13 are made of, for example, polysilicon and contain phosphorus or boron as conductive impurities. The field plate insulating layer 40, the gate insulating layer 44, the first interlayer insulating layer 45, and the second interlayer insulating layer 46 are insulating films containing, for example, silicon.

[0026] In the semiconductor device 100, the drain current flowing between the drain electrode 10 and the source electrode 14 is controlled by the gate electrode 13. The field plate electrode 30 is wired to connect to the source electrode 14 in a portion not shown, and is electrically connected to the source electrode 14. The field plate electrode 30 controls the electric field in the n-type drift layer 20 located in the −Z direction from the gate electrode 13, thereby improving the breakdown voltage between the drift and the source.

[0027] A gate pad (not shown) connected to an external power supply (or a gate controller) is provided in a portion of the semiconductor device 100, spaced apart from the element region. Gate wiring is electrically connected to the gate pad, and the gate wiring is provided on the surface of the semiconductor device 100. This gate wiring is connected to a gate electrode 13 extended to the surface of the semiconductor device 100.

[0028] Next, the structure of the gate electrode 13 will be described with reference to FIG. 2, which shows the portion A enclosed by the dashed line in FIG.

[0029] 2, gate electrode 13 has sidewall 13a, sidewall 13b, and bottom surface 13c. Sidewall 13a faces p-type base layer 24 via gate insulating layer 44, and sidewall 13b faces field plate electrode 30 via first interlayer insulating layer 45. Bottom surface 13c connects sidewall 13a and sidewall 13b and contacts field plate insulating layer 40 in the -Z direction. In addition, in semiconductor device 100 according to this embodiment, vertex 70 facing the -Z direction is formed near the center of bottom surface 13c. Vertex 70 is the lowest point or minimum value of bottom surface 13c in the -Z direction.

[0030] Next, the structural features of the field plate insulating layer 40 will be described with reference to FIG.

[0031] Field plate insulating layer 40 has a first insulating layer 41 in contact with n-type drift layer 20, a second insulating layer 42 provided between first insulating layer 41 and field plate electrode 30, and a third insulating layer 43 provided between second insulating layer 42 and field plate electrode 30. Second insulating layer 42 is located between first insulating layer 41 and third insulating layer 43, and field plate insulating layer 40 has a three-layer structure.

[0032] Furthermore, sharp vertices 70 generally tend to concentrate an electric field because the electric field changes abruptly. For this reason, it is desirable to position vertex 70 near the center of field plate insulating layer 40 in the X direction. For example, if vertex 70 is formed at a position in contact with side surface 13a, electric field concentration tends to occur near the bottom end of gate insulating layer 44, which is thin in the X direction. In order to prevent electric field concentration in such a thin portion of the insulating layer, vertex 70 may be in contact with second insulating layer 42, for example.

[0033] (Method of manufacturing the semiconductor device 100) Next, a manufacturing process for the semiconductor device 100 according to this embodiment will be described with reference to Figures 3 to 16. Figures 3 to 16 are schematic cross-sectional views showing part of the manufacturing process for the semiconductor device according to this embodiment.

[0034] 3, the n-type drift layer 20 is formed on the n-type drain layer 21. At this time, the n-type drain layer 21 has a higher n-type impurity concentration than the n-type drift layer. The n-type impurity concentration of the n-type drain layer 21 is, for example, 1×10 17 cm -3 5x10 or more 17 cm -3 The following is the result.

[0035] Next, as shown in FIG. 4, a plurality of trenches U extending along the −Z direction are formed in the n-type drift layer 20 from the upper surface thereof by RIE (Reactive Ion Etching).

[0036] 5, a first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 are formed in this order on the top surface of the n-type drift layer 20 and on the entire inner surface including the side and bottom surfaces of the trench U to form a field plate insulating layer 40. The field plate insulating layer 40 is made up of three layers in which insulating films with different etching rates in wet etching are in contact with each other.

[0037] Specifically, the second insulating layer 42 is made of an insulating film that has a faster etching rate in wet etching than the first insulating layer 41 and the third insulating layer 43.

[0038] For example, insulating films with slow etching rates may be SiN (Silicon Nitride) film made of silicon and nitrogen, D-SiN (Dual frequency Silicon Nitride) film, SInSiN (Semi-Insulated Silicon Nitride) film, which is a semi-insulating silicon nitride film, or SiON (Silicon Oxynitride) film for the first insulating layer 41 and the third insulating layer 43. D-SiN is SiN formed by plasma CVD using dual frequency plasma.

[0039] Silicon nitride films such as SiN, D-SiN, and SInSiN have a denser structure than silicon oxide films that can be deposited using the general CVD (Chemical Vapor Deposition) method, and are characterized by a slower etching rate when wet etched.

[0040] That is, the second insulating layer 42 is a silicon oxide film, and the first insulating layer 41 and the third insulating layer 43 are silicon nitride films. The second insulating layer 42 may be made of an insulating film with a high wet etching rate, such as a silicon oxide film containing phosphorus and boron (Boron Phosphorus Silicon Glass: BPSG).

[0041] The insulating films are formed in the following order, for example: first insulating layer 41 is formed, then second insulating layer 42 is formed, and finally third insulating layer 43 is formed.

[0042] The first to third insulating layers are not limited to the above embodiment, and may be formed of a film having the property that the etching rate of the first insulating layer 41 and the third insulating layer 43 by wet etching is slower than the etching rate of the second insulating layer 42.

[0043] Next, the field plate electrode 30 is formed. As shown in Fig. 6, a conductive layer 30a is formed by CVD on the first surface 40a, which is the upper surface of the field plate insulating layer 40, so as to fill the trench U. The conductive layer 30a is made of, for example, polysilicon, and contains, for example, phosphorus or boron as conductive impurities.

[0044] Next, as shown in FIG. 7, the conductive layer 30a is removed by RIE so that a portion thereof remains in the trench U, and the field plate electrode 30 is formed.

[0045] Next, the field plate insulating layer 40 is selectively etched by wet etching to recess it in the −Z direction from the top surface of the n-type drift layer 20, exposing the top surface of the n-type drift layer 20. By further proceeding with the etching, a groove 60 is formed at the top end of the field plate insulating layer 40 in the trench U, as shown in FIG. 8 . The groove 60 is formed at the top end of the field plate insulating layer 40 in the Z direction. The groove 60 is provided inside the trench U and faces the field plate electrode 30 and the n-type drift layer 20 in the X direction.

[0046] In this embodiment, grooves 60 having a desired shape are formed by utilizing the difference in etching rate during wet etching of the first to third insulating layers that make up field plate insulating layer 40. That is, field plate insulating layer 40 is made up of three layers, and second insulating layer 42 has a property that its etching rate during wet etching is faster than that of first insulating layer 41 and third insulating layer 43. Therefore, etching of second insulating layer 42 progresses more quickly.

[0047] Furthermore, by using an etching solution that is selective to polysilicon, the field plate insulating layer 40 is selectively etched without etching the field plate electrode 30. An etching solution that etches the second insulating layer 42 faster than the first insulating layer 41 and the third insulating layer 43 is used. When the second insulating layer 42 is a silicon oxide film and the first insulating layer 41 and the third insulating layer 43 are silicon nitride films, an etching solution using hydrofluoric acid or the like, which etches silicon oxide films faster, can be used. For example, when the hydrofluoric acid concentration is 37% and the temperature is 65°C, the etching rate for silicon oxide films is approximately 45 nm / sec and the etching rate for silicon nitride films is approximately 3 nm / sec. Thus, the etching rate ratio can be adjusted by adjusting the concentration and temperature. When the first insulating layer 41 and the third insulating layer 43 are SiON films, the etching rate can be slowed by increasing the nitrogen ratio.

[0048] Fig. 9 shows part B surrounded by a dashed line in Fig. 8. As shown in Fig. 9, a groove 60 in which gate electrode 13 will be formed is formed at the upper end of field plate insulating layer 40 by wet etching field plate insulating layer 40. Groove 60 has an upper surface 41a of first insulating layer 41, an upper surface 42a of second insulating layer 42, and an upper surface 43a of third insulating layer 43.

[0049] 9, the upper surface 42a of the second insulating layer 42 is located in the −Z direction relative to the upper surface 41a of the first insulating layer 41 and the upper surface 43a of the third insulating layer 43. At this time, the n-type drift layer 20 is exposed on the sidewall of the trench U.

[0050] Next, a thermal oxidation process is performed to oxidize the top surface of the n-type drift layer 20, the side surfaces of the n-type drift layer 20 exposed on the side walls of the trench U, and the top and side surfaces of the field plate electrode 30. As shown in Fig. 10, a gate insulating layer 44 is newly formed to cover the top surface of the n-type drift layer 20 and the side surfaces of the n-type drift layer 20 exposed on the side walls of the trench U, and a first interlayer insulating layer 45 is newly formed to cover the top of the field plate electrode 30. At this time, oxidation also progresses on the top surface of the field plate insulating layer 40.

[0051] When the first interlayer insulating layer 45 is formed, a portion of the field plate electrode 30 is oxidized, leaving an upper end portion 30c of the field plate electrode with a narrower width.

[0052] 11, a conductive layer 13a is formed by CVD on the n-type drift layer 20 and to fill the groove portion 60 of the trench U. The conductive layer 13a includes polysilicon. The conductive layer 13a includes conductive impurities such as phosphorus or boron.

[0053] 12, the conductive layer 13a is etched to form the gate electrode 13 on the field plate insulating layer 40. At this time, the conductive layer 13a is etched back until the first interlayer insulating layer 45 is exposed. The gate electrode 13 is formed between the field plate electrode upper end 30c and the n-type drift layer 20. A pair of gate electrodes 13 are arranged side by side so as to sandwich the field plate electrode upper end 30c therebetween.

[0054] 13, a p-type base layer 24 is formed on the top of the n-type drift layer 20. For example, p-type impurities are ion-implanted into the top surface of the n-type drift layer 20 and activated by heat treatment. The p-type impurities are diffused to a predetermined depth during the heat treatment.

[0055] Next, the n-type source layer 26 is formed on the p-type base layer 24. The n-type source layer 26 faces the upper end of the gate electrode 13 in the X direction, with the gate insulating layer 44 interposed therebetween. The n-type source layer 26 is formed, for example, by selectively ion-implanting n-type impurities from the upper surface of the p-type base layer 24 and activating them by heat treatment. The lower end of the n-type source layer 26 in the -Z direction overlaps with the upper end of the gate electrode 13 in the X direction.

[0056] Next, the p-type contact layer 25 is formed on the upper part of the p-type base layer 24. The p-type contact layer 25 is formed, for example, by selectively ion-implanting p-type impurities from the upper surface of the p-type base layer 24 and activating them by heat treatment. The p-type contact layer 25 is arranged in parallel with the n-type source layer 26 in the X direction.

[0057] Next, as shown in FIG. 14, an insulating layer 46a covering the trench U is formed on the gate electrode 13, the field plate electrode 30, the n-type source layer 26, and the p-type base layer 24. Then, as shown in FIG. 15, a portion of the insulating layer 46a on the n-type source layer 26 and the p-type base layer 24 and a portion of the gate insulating layer 44 are removed to form a second interlayer insulating layer 46.

[0058] Subsequently, as shown in FIG. 16, the source electrode 14 is formed on the n-type source layer 26 and the p-type contact layer 25.

[0059] Furthermore, the drain electrode 10 is formed under the n-type drain layer 21. Through the above steps, the semiconductor device 100 shown in FIG.

[0060] [First Comparative Example] Next, FIG. 17 is a schematic cross-sectional view showing a semiconductor device 200 according to a first comparative example.

[0061] The semiconductor device 200 is different from the semiconductor device 100 according to the first embodiment in the cross-sectional shape of the gate electrode 15. Furthermore, the field plate insulating layer 48 is configured as a single layer. Alternatively, the field plate insulating layer 48 may be configured as two layers.

[0062] The structure of the gate electrode 15 of the semiconductor device 200 will be described with reference to FIG. 18, which is an enlarged view of a portion C enclosed by a dashed line in FIG.

[0063] The gate electrode 15 of the semiconductor device 200 has a sidewall 15b that contacts the field plate electrode 30 via the first interlayer insulating layer 45, and a sidewall 15a that contacts a part of the n-type drift layer 20, the p-type base layer 24, and the n-type source layer 26 via the gate insulating layer 44.

[0064] In the semiconductor device 200, a vertex 70 in the −Z direction formed on the lower surface 15c of the gate electrode 15 is located at the connection between the sidewall 15a and the lower surface 15c.

[0065] 18 occurs, for example, in the boundary region between the active region and the termination region, in a portion where field plate electrode 30 is drawn onto the surface of drift layer 20. When field plate electrode 30 is etched by RIE, the portion of field plate electrode 30 drawn onto the surface of drift layer 20 in the termination region is protected by resist or the like. It is believed that when field plate insulating layer 48 is etched by RIE in this state, residues of the resist applied to the termination region have an effect.

[0066] The first comparative example is configured with a single or double field plate insulating layer 48. Note that field plate insulating layer 48 may be any of the first to third insulating layers used in the first embodiment.

[0067] FIG. 19 is a schematic cross-sectional view of the first comparative example after the field plate insulating layer 48 has been recessed in the −Z direction by wet etching. As shown in FIG. 19, the sidewall of trench U where the n-type drift layer 20 is exposed is deeper in the −Z direction than the exposed sidewall of the field plate electrode 30 that faces it in the X direction. As mentioned above, this is due to the effect of the applied resist residue on the RIE etching. In other words, etching of the insulating layer 48 along the sidewall of the field plate electrode 30, which is near the resist residue, progresses slowly, while etching of the insulating layer 48 along the sidewall of trench U progresses more quickly. This results in a difference in the cross-sectional shape of the gate electrode embedded in groove 61.

[0068] 18, the semiconductor device 200 has a structure in which the sharp apex 70 of the gate electrode 15 is formed along the sidewall 15a, unlike the first embodiment. Such a structure causes electric field concentration in the vicinity of an extremely thin insulating layer such as the gate insulating layer 44, making it impossible to ensure a sufficient dielectric strength, increasing the risk of product breakdown.

[0069] [Advantages of the first embodiment] According to the first embodiment, etching of the field plate insulating layer 40 tends to progress at the center in the X direction. Therefore, the structure is such that sharp vertices 70 in the −Z direction are unlikely to be formed on the sidewalls 13a and 13b of the gate electrode 13.

[0070] Furthermore, in the semiconductor device 100 according to the first embodiment, even if a sharp apex 70 is formed at the lower end of the gate electrode 13 in a portion along the center of the field plate insulating layer 40, the thickness of the field plate insulating layer between the apex 70 of the gate electrode 13 where electric field concentration occurs and the n-type drift layer can be ensured to be thicker than in the first comparative example.

[0071] As described above in detail, in the semiconductor device 100 according to the first embodiment, the position of the vertex 70 where electric field concentration is likely to occur can be controlled, and a decrease in breakdown voltage can be prevented.

[0072] Although the embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0073] 10 Drain electrode 13, 15 Gate electrode 14 Source electrode 20 n-type drift layer 21 n-type drain layer 24 p-type base layer 25 p-type contact layer 26 n-type source layer 30, 30a Field plate electrode 30c Top end of field plate electrode 40 Three field plate insulating layers 41 First insulating layer 42 Second insulating layer 43 Third insulating layer 44 Gate insulating layer 45 First interlayer insulating layer 46 Second interlayer insulating layer 48 One field plate insulating layer 60, 61 Groove 13a, 13b side wall 13c Bottom side 15a, 15b side wall 15c Bottom side 70 Vertex

Claims

1. A first electrode; A second electrode; a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode; a field plate electrode extending in a first direction from the first semiconductor layer toward the second semiconductor layer in the first semiconductor layer; a field plate insulating layer provided between the first semiconductor layer and the field plate electrode; a gate electrode having a first side surface facing the second semiconductor layer, a second side surface facing the first side surface, and a first surface connected to the first side surface and the second side surface and in contact with the field plate insulating layer, the first surface having an apex protruding in a direction opposite to the first direction at a position spaced apart from the first side surface and the second side surface; a first interlayer insulating layer provided between the field plate electrode and the gate electrode; a second interlayer insulating layer provided between the gate electrode and the second electrode; A semiconductor device having:

2. The field plate insulating layer is a first insulating layer in contact with the first semiconductor layer; a second insulating layer provided between the first insulating layer and the field plate electrode; a third insulating layer provided between the second insulating layer and the field plate electrode; The semiconductor device according to claim 1 ,

3. The semiconductor device according to claim 2 , wherein the apex is the lowest point of the first surface and is in contact with the second insulating layer.

4. the first and third insulating layers are silicon nitride films, the second insulating layer is a silicon oxide film; The semiconductor device according to claim 2 .

5. 3. The semiconductor device according to claim 2, wherein an etching rate of the first and third insulating layers in the first etching step is slower than an etching rate of the second insulating layer in the first etching step.

6. 2. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer of the first conductivity type between the first semiconductor layer and the first electrode, the fourth semiconductor layer having a higher impurity concentration of the first conductivity type than the first semiconductor layer.

7. 2. The semiconductor device according to claim 1, further comprising a fifth semiconductor layer of the second conductivity type between the second semiconductor layer and the second electrode, the fifth semiconductor layer having a higher impurity concentration of the second conductivity type than the second semiconductor layer.

8. forming a trench extending from a second surface of a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface on which a first electrode is provided and a second surface on which a second electrode is provided, toward the first electrode; forming a first insulating layer overlying the sidewalls of the trench; forming a second insulating layer on the first insulating layer, the second insulating layer having a wet etching rate faster than the first insulating layer; forming a third insulating layer on the second insulating layer, the third insulating layer having a slower etching rate by the wet etching than the second insulating layer; burying a field plate electrode in the trench via the third insulating layer; by the wet etching, moving upper ends of the first insulating layer, the second insulating layer, and the third insulating layer between the first semiconductor layer and the field plate electrode away from the second surface in a direction opposite to the first direction, thereby exposing a part of a sidewall of the trench and a part of the field plate electrode; oxidizing a portion of the exposed sidewalls of the trench and the exposed portion of the field plate electrode; forming a gate electrode on the top end of each of the first insulating layer, the second insulating layer, and the third insulating layer; A method for manufacturing a semiconductor device comprising:

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the first and third insulating layers are silicon nitride films, and the second insulating layer is a silicon oxide film.

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