Wiring board and manufacturing method thereof

Abstract

To provide a technology for suppressing the occurrence of voids between wirings. [Solution] The wiring board of this embodiment has a conductive layer including a parallel wiring section in which multiple wires are arranged in parallel, and an insulating layer laminated on the conductive layer and including a resin and an inorganic filler, in which the multiple wires of the parallel wiring section are covered with an adhesive film, and the insulating layer has a single layer including a first component section filled between the wires of the parallel wiring section, and a second component section located above the parallel wiring section and having a higher content of the inorganic filler than the first component section.

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board in which an insulating layer is laminated on a conductive layer including a parallel wiring portion in which a plurality of wirings are arranged in parallel, and a manufacturing method thereof. [Background technology]

[0002] For this type of wiring board, a technique for increasing the integration density of parallel wiring portions has been proposed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2024-015869 A (paragraph

[0010] and Figure 1) Summary of the Invention [Problem to be solved by the invention]

[0004] However, as parallel wiring sections become more highly integrated, the resin in the insulating layer does not penetrate between the wires in the parallel wiring section, causing voids to form between the wires. Therefore, the present disclosure provides a technology for suppressing the formation of voids between the wires. [Means for solving the problem]

[0005] A first aspect of the invention according to the present disclosure, made in consideration of the above-mentioned problems, is a wiring board having a conductive layer including a parallel wiring section in which a plurality of wires are arranged in parallel, and an insulating layer laminated on the conductive layer and including a resin and an inorganic filler, wherein the plurality of wires in the parallel wiring section are covered with an adhesive film, and the insulating layer has a single layer including a first component portion filled between the wires in the parallel wiring section, and a second component portion located above the parallel wiring section and having a higher content of the inorganic filler than the first component portion. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a cross-sectional view of a wiring substrate according to an embodiment of the present disclosure; [Figure 2] Enlarged cross-sectional side view of the parallel wiring section [Figure 3] 3A and 3B are side cross-sectional views showing a method for manufacturing a wiring board. [Figure 4] 4A to 4D are side cross-sectional views showing a method for manufacturing a wiring board. [Figure 5] 5A to 5C are side cross-sectional views showing a method for manufacturing a wiring board.

[0007] An embodiment of the present disclosure will be described below with reference to FIGS. 1 to 5. A wiring board 10 of this embodiment shown in FIG. 1 includes, for example, a core substrate 11, multiple conductive layers 20 and multiple insulating layers 21 alternately stacked on both the front and back surfaces of the core substrate 11, and a solder resist layer (not shown) as the outermost layer. FIG. 1 illustrates a side cross-sectional view of the wiring board 10, showing only the front side of the wiring board 10 from the core substrate 11, with the solder resist layer omitted. The following description will focus on the front side of the wiring board 10. Furthermore, when distinguishing between the conductive layers 20 in the wiring board 10, the conductive layers 20 will be referred to as a "first conductive layer 20A," a "second conductive layer 20B," and a "third conductive layer 20C" in order from the side closest to the core substrate 11. When distinguishing between the insulating layers 21, the insulating layers 21 will be referred to as a "first insulating layer 21A," a "second insulating layer 21B," and a "second insulating layer 21B" in order from the side closest to the core substrate 11.

[0008] The core substrate 11 has an insulating base material 11K and first conductive layers 20A laminated on both the front and back surfaces of the insulating base material 11K. The insulating base material 11K has a structure in which, for example, a plurality of prepregs (B-stage sheets formed by resin-impregnating a core material made of fibers such as glass cloth) are laminated. The insulating layer 21, which will be described in detail later, does not have a core material and is formed of a resin sheet containing resin and inorganic filler 41. The outermost layer, a solder resist layer (not shown), is an ultraviolet-curable photosensitive film made of, for example, epoxy resin. The insulating base material 11K may have a structure in which a plurality of resin sheets are laminated. The solder resist layer may also be formed by curing a liquid.

[0009] A plurality of through holes 15H are formed in insulating base material 11K of core substrate 11, and the interiors of these through holes 15H are filled with through hole conductors 15. The first conductive layers 20A on the front and back of core substrate 11 are connected to each other by the plurality of through hole conductors 15.

[0010] A conductor pattern is formed on each of the plurality of conductive layers 20 to form a predetermined electric circuit. Each conductive layer 20 is entirely covered with an insulating layer 21 laminated thereon. A plurality of vias 12H are formed in each of the plurality of insulating layers 21, and via conductors 12 are filled inside the vias 12H. The electric circuits of the plurality of conductive layers 20 are connected to each other on both the front and back sides of the core substrate 11 by the plurality of via conductors 12. Pads 16 included in the conductor pattern of the third conductive layer 20C are exposed through openings formed in a solder resist layer (not shown), and are connected to, for example, electric components.

[0011] The conductor pattern of the second conductive layer 20B includes parallel wiring portions 30A, 30B in which a plurality of wirings 31 extend in parallel. The parallel wiring portions 30A, 30B are high-density wiring portions in which the spacing between the wirings 31 is narrow. For example, each wiring 31 has a width L of 3 μm or less, and the spacing S between adjacent wirings 31 is 3 μm or less. In this embodiment, the width L of each wiring 31 is 2 μm, and the spacing S between adjacent wirings 31 is 2 μm (see FIG. 2). Note that each wiring 31 is a signal line connecting lands (not shown) included in the second conductive layer 20B.

[0012] In this embodiment, the second conductive layer 20B is covered with an adhesive film 40. Specifically, the adhesive film 40 is disposed between the second conductive layer 20B and the second insulating layer 21B laminated thereon, and covers the surfaces (top and side surfaces) of the second conductive layer 20B, as shown in FIG. 2. The adhesive film 40 improves the adhesion between the conductive layer 20 and the insulating layer 21, and also ensures the insulation reliability between the conductor patterns of the conductive layer 20. The thickness of the adhesive film 40 is preferably 10 nm to 500 nm.

[0013] The material of the adhesive film 40 is preferably a material capable of bonding with both the resin (organic material) constituting the insulating layer 21 and the metal (inorganic material) constituting the conductive layer 20. For example, a silane coupling agent having both a reactive group R1 capable of chemically bonding with an organic material and a reactive group R2 capable of chemically bonding with an inorganic material is preferred. Examples of the reactive group R1 of the silane coupling agent include an amino group, an epoxy group, a vinyl group, a methacryl group, an acrylic group, a mercapto group, a sulfide group, and an isocyanate group. Examples of the reactive group R2 include an alkoxy group such as a methoxy group or an ethoxy group, an azole group, and a silanol group. In this embodiment, a silane coupling agent containing an azole silane compound such as a triazole compound is used as the material of the adhesive film 40. Note that the adhesive film 40 is not limited to a silane coupling agent, and may be, for example, a titanium coupling agent, an azole compound, a thiol compound, or a triazine thiol compound, as long as it improves the adhesion between the conductive layer 20 and the insulating layer 21. Adhesive film 40 may also be an inorganic material, such as silicon nitride, silicon dioxide, or the like.

[0014] As described above, the insulating layer 21 is composed of a resin sheet containing a resin and an inorganic filler 41. The resin may be a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a mixture thereof, such as an epoxy resin, an acrylic resin, a phenolic resin, a melamine resin, a silicone resin, a polyimide resin, a liquid crystal polymer, or a fluororesin, or a combination of two or more thereof. Examples of the inorganic filler 41 include fine particles of silica, alumina, mica, silicon nitride, and aluminum nitride. The inclusion of the inorganic filler 41 in the insulating layer 21 improves the mechanical strength and thermal conductivity of the insulating layer 21 and enables adjustment of the thermal expansion coefficient, compared to an insulating layer 21 composed solely of resin. The average particle diameter of the inorganic filler 41 is preferably 0.05 μm to 0.2 μm.

[0015] In this embodiment, the content of the inorganic filler 41 in the insulating layer 21 near the parallel wiring portions 30A and 30B varies depending on the positional relationship with the wiring 31.

[0016] 2, in the vicinity of the parallel wiring portions 30A, 30B, a first component C1 between the wires 31 of the parallel wiring portions 30A, 30B, a second component C2 above the parallel wiring portions 30A, 30B, and a third component C3 further above the second component C2 have different inorganic filler 41 content rates. The first component C1 has a lower inorganic filler 41 content rate than the second and third component portions C2, C3, and the third component C3 has a higher inorganic filler 41 content rate than the first component C1 and a lower inorganic filler 41 content rate than the second component portion C2. For example, the content of inorganic filler 41 in the first component C1 is 15 wt% to 55 wt%, the content of inorganic filler 41 in the second component C2 is 75 wt% to 85 wt%, and the content of inorganic filler 41 in the third component C3 is 65 wt% to 80 wt%.

[0017] This concludes the description of the structure of wiring board 10 of this embodiment. Next, an example of a method for manufacturing wiring board 10 will be described with reference to FIGS. (1) As shown in FIG. 3A, a laminate 11S is prepared in which metal foils 11D are laminated on both sides of an insulating base material 11K. A plurality of through-holes 15H are formed by drilling or laser irradiation, and smears inside the through-holes 15H are removed by desmearing.

[0018] (2) Next, as shown in Fig. 3B, the laminate 11S and the inside of the through-holes 15H are subjected to, for example, known subtractive processes such as electroless plating, electrolytic plating, and etching, to laminate the first conductive layers 20A on both the front and back surfaces of the insulating base material 11K, and fill the through-holes 15H with through-hole conductors 15. This completes the formation of the core substrate 11. The through-hole conductors 15 may be made of a conductive paste or the like.

[0019] (3) Next, as shown in Fig. 4A, a resin sheet is placed on core substrate 11 and pressurized under heat. At this time, the resin sheet melts and penetrates into the gaps between the conductor patterns of first conductive layer 20A, and first insulating layer 21A with a flat upper surface is laminated. Note that Figs. 4 and 5 show only the front surface of wiring substrate 10.

[0020] (4) After the first insulating layer 21A has cooled, a laser is irradiated onto predetermined locations of the first insulating layer 21A to form a plurality of vias 12H, as shown in FIG. 4B, and then smears inside the vias 12H are removed by a desmearing process.

[0021] (5) Next, the first insulating layer 21A and the inside of the via 12H are subjected to electroless plating, plating resist treatment, and electrolytic plating treatment, for example, as a known semi-additive method. As a result, the second conductive layer 20B is laminated and the via 12H is filled with the via conductor 12. In detail, the electronic circuit of the second conductive layer 20B is formed in the portion of the first insulating layer 21A not covered with the plating resist, and the first insulating layer 21A is exposed in the portion covered with the plating resist (see FIG. 4C). The conductor pattern of the second conductive layer 20B includes parallel wiring portions 30A and 30B each having a plurality of wirings 31.

[0022] (6) Next, an adhesive film 40 is formed on the surface of the second conductive layer 20B. The adhesive film 40 can be formed, for example, by immersing the core substrate 11, on which the first insulating layer 21A and the second conductive layer 20B are laminated, in a diluted solution of a silane coupling agent and then drying it. Since the silane coupling agent bonds with the metal, the adhesive film 40 can be easily formed only on the surface of the second conductive layer 20B. FIG. 4D shows an enlarged view of the area enclosed by the two-dot chain line in FIG. 4C after the adhesive film 40 has been formed. The concentration of the diluted solution of the silane coupling agent is preferably 0.1% to 10%.

[0023] In the step of forming the adhesive film 40, the core substrate 11 on which the first insulating layer 21A and the second conductive layer 20B are laminated may be subjected to acid washing and water washing before being immersed in a diluted solution of the silane coupling agent, and then water washing after the immersion and before drying may be performed, thereby suppressing unevenness in the film thickness. Also, instead of immersing the core substrate 11 in a diluted solution of the silane coupling agent, the diluted solution of the silane coupling agent may be sprayed or applied to the surface of the second conductive layer 20B.

[0024] (7) Next, the second insulating layer 21B is formed in the same manner as in step (3) (see FIG. 5A).

[0025] Here, the resin sheet used to form the first and second insulating layers 21A and 21B is a sheet in which inorganic filler 41 is uniformly dispersed in resin. The content of inorganic filler 41 in this resin sheet before processing is preferably 65 wt% to 80 wt%. When this resin sheet is placed on the first and second conductive layers 20A and 20B and pressurized in a heated state, the resin sheet melts and fills the gaps between the conductive patterns of the first and second conductive layers 20A and 20B. At this time, as described above, a gradient in the content of inorganic filler 41 occurs in the formed second insulating layer 21B near the parallel wiring portions 30A and 30B. This is presumably due to the following reason.

[0026] That is, in the second insulating layer 21B, the adhesive film 40 is coated on the second conductive layer 20B, so that the adhesive film 40 is densely present between the wirings 31 of the parallel wiring sections 30A and 30B, which are high-wiring integration sections. As a result, the first component section C1 between the wirings 31 becomes a region that has a higher affinity for the resin than the inorganic filler 41 compared to other regions, making it easier for the resin from the molten resin sheet to penetrate. As a result, the inorganic filler 41 content of the first component section C1 decreases. As a result, the inorganic filler 41 that did not penetrate the first component section C1 accumulates in the second component section C2 above the first component section C1, increasing the inorganic filler 41 content of the second component section C2. On the other hand, the adhesive film 40 is less likely to affect the third component section C3 above the second component section C2, and the inorganic filler 41 content of the third component section C3 approaches that of the resin sheet before processing (see FIG. 2).

[0027] (8) After the second insulating layer 21B has cooled, multiple vias 12H are formed in the second insulating layer 21B (see Figure 5B) in the same manner as in step (4), and then a third conductive layer 20C and via conductors 12 are formed (see Figure 5C) in the same manner as in step (5).

[0028] After step (8), a solder resist layer is laminated on the third conductive layer 20C.

[0029] 1 to 5 and the structures, shapes, and materials exemplified in this specification. For example, wiring board 10 may be a coreless substrate that does not include core substrate 11. Wiring board 10 may have any number of conductive layers 20 and multiple insulating layers 21. In this embodiment, the front and back of core substrate 11 may differ in the number of conductive layers 20 and insulating layers 21, and in the configuration of the electronic circuits of conductive layers 20.

[0030] The structure of the wiring board 10 and its manufacturing method according to this embodiment have been described above. Next, the effects of the wiring board 10 will be described. In the wiring board 10 according to the present disclosure, the insulating layer 21 covering the parallel wiring sections 30A and 30B has a first component C1 between the wires 31 of the parallel wiring sections 30A and 30B and a second component C2 above the parallel wiring sections 30A and 30B, with different inorganic filler 41 content ratios. The second component C2 has a higher inorganic filler 41 content ratio than the first component C1, and conversely, the first component C1 has a lower inorganic filler 41 content ratio than the second component C2. In a highly integrated wiring section where the wiring spacing of the wires 31 is 3 μm or less, as in this embodiment, during the manufacturing of the wiring board 10, the inorganic filler 41 penetrates between the wires 31, making it difficult for the resin to penetrate, and voids are more likely to occur. Furthermore, if the average particle diameter of the inorganic filler 41 is 0.2 μm or less, voids are even more likely to occur. However, in this embodiment, the content of inorganic filler 41 between the wires 31 is low, so that the resin in the insulating layer 21 can easily enter between the wires 31, thereby preventing the occurrence of voids.

[0031] In the wiring board 10 of this embodiment, the surface of the second conductive layer 20B is coated with an adhesive film 40. As a result, the adhesive film 40 is densely present in the first component portion C1 between the wires 31 of the parallel wiring portions 30A and 30B, which is a highly integrated wiring portion. This is presumably a region with a higher affinity for the resin than the inorganic filler 41 compared to other regions. When the resin sheet is heated and pressurized on the second conductive layer 20B in this state, as described above, the resin in the molten resin sheet is more likely to penetrate between the wires 31 of the parallel wiring portions 30A and 30B. This presumably reduces the content of inorganic filler 41 in the first component portion C1. Furthermore, the inorganic filler 41 that does not penetrate the first component portion C1 accumulates in the second component portion C2 above the first component portion C1. This presumably increases the content of inorganic filler 41 in the second component portion C2 above the first component portion C1. In other words, by covering the surface of each wiring 31 of the parallel wiring sections 30A, 30B with an adhesive film 40, a resin sheet with a uniform content of inorganic filler 41 can be used to manufacture a single layer of insulating layer 21 in which the first component section C1 and the second component section C2 have different contents of inorganic filler 41.

[0032] [Other embodiments] In the above embodiment, only the second conductive layer 20B among the plurality of conductive layers 20 includes parallel wiring portions 30A, 30B having a plurality of wirings 3131, but the other conductive layers 20A, 20C may also include parallel wiring portions 30A, 30B.

[0033] In the above embodiment, the entire surface of the second conductive layer 20B was covered with the adhesive film 40, but only the surfaces of the multiple wirings 31 of the parallel wiring portions 30A, 30B of the second conductive layer 20B may be covered with the adhesive film 40.

[0034] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone. [Explanation of symbols]

[0035] 10. Wiring board 20 Conductive layer 21 Insulating layer 30A,30B Parallel wiring section 31 Wiring 40 Adhesive film 41 Inorganic filler C1 1st component C2 2nd component C3 3rd component

Claims

1. a conductive layer including a parallel wiring portion in which a plurality of wirings are arranged in parallel; a wiring board having an insulating layer laminated on the conductive layer and containing a resin and an inorganic filler, the plurality of wires in the parallel wiring section are covered with an adhesive film; The insulating layer is a first component portion filled between the wires of the parallel wiring portion; a second component portion located above the parallel wiring portion and having a higher content of the inorganic filler than the first component portion;

2. 2. The wiring board according to claim 1, The insulating layer includes a third component located above the second component, the third component having a lower inorganic filler content than the second component and a higher inorganic filler content than the first component.

3. 3. The wiring board according to claim 1, The distance between the wires in the parallel wiring portion is 3 μm or less.

4. 4. The wiring board according to claim 3, The inorganic filler has an average particle size of 0.2 μm or less.

5. forming a conductive layer including a parallel wiring portion in which a plurality of wirings are arranged in parallel; coating the conductive layer with an adhesive film; forming an insulating layer on the conductive layer, The formation of the insulating layer a first component portion filled between the wires of the parallel wiring portion; a second component portion located above the parallel wiring portion and having a higher inorganic filler content than the first component portion, The resin sheet in which the inorganic filler is uniformly dispersed is pressed under heat.

6. 6. The method for manufacturing a wiring board according to claim 5, The inorganic filler has an average particle size of 0.2 μm or less.

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