Manufacturing method of wiring boards

Abstract

Improved connection reliability between the conductor layer and the through-conductor. [Solution] The manufacturing method of the wiring board of the embodiment includes forming a conductor layer 111 and an insulating layer 110 covering the conductor layer 111, forming a through hole 110vh that penetrates the insulating layer 110 and exposes the upper surface of the conductor layer 111 by irradiating the insulating layer 110 with laser light, and forming a through conductor by filling the through hole 110vh with a conductor. The manufacturing method of the embodiment includes a plasma treatment step of exposing the upper surface of the conductor layer 111 exposed in the through hole 110vh to a plasma containing fluorine, and the plasma treatment step is a step of forming a layer 200 containing fluorine on the upper surface of the conductor layer 111 exposed in the through hole 110vh.

Description

Technical Field

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[0001] The present invention relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board. An upper insulating layer is laminated on a lower insulating layer on which a lower wiring conductor is formed. Via holes are formed by irradiating the upper insulating layer with laser light. A desmear treatment is performed to remove resin residues remaining in the via holes. An upper wiring conductor is formed in the via holes.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing a wiring board of Patent Document 1, when a via hole is formed and the lower wiring conductor is exposed, an oxide film of the metal constituting the wiring conductor is formed on the upper surface of the lower wiring conductor. It is considered that the contact resistance between the lower wiring conductor and the upper wiring conductor may be relatively large. Also, desired reliability may not be obtained regarding the connection between the upper and lower wiring conductors.

Means for Solving the Problems

[0005] The present invention provides a method for manufacturing a wiring board, comprising: forming a conductor layer and an insulating layer covering the conductor layer; irradiating the insulating layer with laser light to form through-holes that penetrate the insulating layer and expose the upper surface of the conductor layer; and filling the through-holes with a conductor to form a through-conductor. The manufacturing method includes a plasma treatment step of exposing the upper surface of the conductor layer exposed in the through-holes to a plasma containing fluorine, wherein the plasma treatment step is a step of forming a layer containing fluorine on the upper surface of the conductor layer exposed in the through-holes.

[0006] According to embodiments of the present invention, a fluorine-containing layer is formed on the upper surface of the conductor layer exposed in the through hole, which is thought to suppress the formation of an oxide film on the conductor layer, thereby reducing contact resistance between the conductor layer and the through conductor and improving connection reliability. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board manufactured by the method of one embodiment of the present invention. [Figure 2] A magnified view of a portion of the wiring board shown in Figure 1. [Figure 3A] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3B] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3C] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3D] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3E] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3F] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3G] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3H] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3I]Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3J] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3K] Figure 1 shows an example of a manufacturing method for a wiring board. [Figure 3L] Figure 1 shows an example of a manufacturing method for a wiring board. [Modes for carrying out the invention]

[0008] Next, a method for manufacturing a wiring board according to one embodiment of the present invention will be described with reference to the drawings. Note that in the drawings referred to below, the precise proportions of each component are not intended to be shown, but rather they are drawn in a way that makes it easy to understand the features of the present invention. Figure 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board manufactured by the manufacturing method of this embodiment. The wiring board 1 has a core substrate 100 having one surface 100A and the other surface 100B which is the opposite surface of the first surface 100A. A first build-up portion 11 is formed on the first surface 100A. A second build-up portion 12 is formed on the other surface 100B. The core substrate 100 has an insulating layer 10 and conductive layers 111 and 121.

[0009] In the following explanation, for each element constituting the wiring board 1, the side furthest from the insulating layer 10 will be referred to as "top," "upper side," "outside," or "outer," and the side closer to the insulating layer 10 will be referred to as "bottom," "lower side," "inside," or "inner." Furthermore, for each insulating layer and conductor layer, the surface facing away from the insulating layer 10 will be referred to as the "top surface," and the surface facing the insulating layer 10 will be referred to as the "bottom surface." Therefore, for example, in the explanation of each element constituting the core substrate 100, the first build-up section 11, and the second build-up section 12, the side furthest from the insulating layer 10 will be referred to as "top," "upper side," "upper layer side," "outside," or simply "top" or "outer," and the side closer to the insulating layer 10 will be referred to as "bottom," "downward," "lower layer side," "inside," or simply "bottom" or "inner."

[0010] The conductor layers 111 and 121 that make up the core substrate 100 are connected by through-hole conductors 113 that penetrate the insulating layer 10 in the thickness direction. The through-hole conductors 113 are made of conductors that cover the inner wall of the through-holes 10th that penetrate the insulating layer 10 in the thickness direction. The hollow portion inside the through-hole conductors 113 is filled with filler material 113f.

[0011] The first build-up section 11 is composed of insulating layers 110 and conductive layers 112 alternately laminated on one surface 100A of the core substrate 100. The second build-up section 12 is composed of insulating layers 120 and conductive layers 122 alternately laminated on the other surface 100B of the core substrate 100. The insulating layer 110 constituting the first build-up section 11 and the insulating layer 120 constituting the second build-up section 12 each include through conductors (via conductors) 13 and 23 that connect conductive layers formed in contact with two opposite surfaces in the thickness direction. The through conductor 13 is integrally formed with the conductive layer 112 above it. The through conductor 23 is integrally formed with the conductive layer 122 above it.

[0012] A solder resist layer SR1 is formed on the first build-up section 11. A solder resist layer SR2 is formed on the second build-up section 12. An opening SR1o is formed in the solder resist layer SR1, and the conductor pad 112p of the outermost conductor layer 112 in the first build-up section 11 is exposed through the opening SR1o. An opening SR2o is formed in the solder resist layer SR2, and the conductor pad 122p of the outermost conductor layer 122 in the second build-up section 12 is exposed through the opening SR2o.

[0013] The conductor pad 112p can be a connection pad used for mounting external electronic components (not shown), for example. On the other hand, the conductor pad 122p can be a connection pad used for connection to an external motherboard (not shown), for example. A surface protection film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, or a heat-resistant preflux may be formed on the exposed surfaces of the conductor pads 112p and 122p.

[0014] The insulating layer 10, the insulating layer 110 constituting the first build-up portion 11, and the insulating layer 120 constituting the second build-up portion 12 are each formed using an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin, for example. Each of the insulating layers 10, 110, and 120 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. In the illustrated example, the insulating layer 10 contains a core material, and the other insulating layers 110 and 120 do not contain a core material.

[0015] The solder resist layers SR1 and SR2 are formed using a photosensitive epoxy resin or a polyimide resin, for example. The filler 113f filling the hollow portion of the through-hole conductor 113 can be an insulating resin such as epoxy, acrylic, or phenol, for example. The filler 113f may be a cured product of a conductive paste or conductive ink containing conductive particles such as silver particles.

[0016] The conductor layers 111, 121, 112, 122, through conductors 13, 23, and through-hole conductors 113 can be formed using any metal such as copper or nickel. For example, the conductor layers 111, 121 can be formed by a metal foil such as a copper foil and / or a metal film formed by plating or sputtering. The conductor layers 112, 122 can be formed by a metal film formed by plating or sputtering. The conductor layers 111, 121, 112, 122, through conductors 13, 23, and through-hole conductors 113 are shown in a single-layer structure in FIG. 1 for ease of viewing, but may have a multilayer structure of two or more layers. The conductor layers 112, 122, through conductors 13, 23 can have, for example, a two-layer structure including a metal film layer (e.g., a copper sputter film) and an electrolytic plating film layer.

[0017] Each of the conductor layers 111, 121, 112, 122 included in the wiring substrate 1 is patterned to have a predetermined conductor pattern. The conductor layer 112 is formed in a pattern including a conductor pad integrally formed with the through conductor 13 formed in the insulating layer 110. The conductor layer 122 is formed in a pattern including a conductor pad integrally formed with the through conductor 23 formed in the insulating layer 120.

[0018] Next, referring to FIG. 2, which is an enlarged view of the region II surrounded by a dashed-dotted line in FIG. 1, the insulating layer 110, through conductor 13, and conductor layer 112, which are at least included in the wiring substrate manufactured by the method of the embodiment, will be described in detail.

[0019] The insulating layer 110 included in the wiring substrate manufactured by the method of the embodiment has a first surface 110A and a second surface 110B on the opposite side of the first surface 110A. In the drawing, the first surface 110A is in contact with the conductor layer 112 formed on the first surface 100A, and the second surface 110B is in contact with the conductor layer 111 formed under the insulating layer 110. A through-hole 110vh penetrating the insulating layer 110 in the thickness direction is formed in the insulating layer 110 from the first surface 110A to the second surface 110B. The through conductor 13 is formed by a conductor filling the through-hole 110vh.

[0020] In Figure 2, the through conductor 13 and the conductor layer 112 are shown as a two-layer structure consisting of a metal film layer 112a, which is, for example, a copper sputtered film, and a plating film layer 112b, which is, for example, an electrolytic copper plating film layer. In the illustrated example, the through conductor 13 is a so-called filled via that fills the through hole 110vh, and is composed of a metal film layer 112a and a plating film layer 112b that cover the bottom surface and inner wall surface (side surface) of the through hole 110vh. The conductor layer 112, which is formed integrally with the through conductor 13 on the first surface 110A, is composed of a metal film layer 112a in contact with the first surface 110A and a plating film layer 112b on the metal film layer 112a.

[0021] In the illustrated example, the through-hole 110vh (through-conductor 13) has a tapered shape that decreases in diameter from the first surface 110A to the opposite second surface 110B, but the shape of the through-hole 110vh is not limited to this. The through-hole 110vh may be formed as a cylindrical shape that is approximately the same diameter in the thickness direction of the insulating layer 110 and is approximately perpendicular to the conductor layer 112. For convenience, the term "reduced diameter" is used, but the opening shape of the through-hole 110vh in plan view is not necessarily limited to a circle. "Diameter" means the straight-line distance between the two furthest apart points on the outer edge of the object when the object is viewed in plan view. "Reduced diameter" simply means that the straight-line distance between the two furthest apart points on the outer edge in the horizontal cross-section of the through-hole 110vh is reduced. "Plan view" means viewing the object with a line of sight parallel to the thickness direction of the wiring board 1 (i.e., the thickness direction of the insulating layer 110).

[0022] Next, using the case where the wiring board 1 shown in Figure 1 is manufactured as an example, an example of a manufacturing method for a wiring board according to one embodiment will be explained with reference to Figures 3A to 3L. In Figures 3A to 3L, Figures 3A, 3B, 3K, and 3L show the area corresponding to Figure 1, and each conductor layer is shown as a single layer. In Figures 3C to 3J, the area corresponding to Figure 2 is shown, and each of the multiple layers constituting the conductor layer (metal film layer and plating film layer) is shown.

[0023] First, as shown in Figure 3A, a core substrate 100 is prepared. For example, through holes 10th are formed in a double-sided copper-clad laminate including an insulating layer 10, for example by drilling. Then, the core substrate 100 is prepared by forming through-hole conductors 113 in the through-holes 10th, for example by a subtractive method, and forming conductor layers 111 and 121 that cover both sides of the insulating layer 10. The hollow portion inside the through-hole conductors 113 is filled with a filler 113f, for example, a resin such as epoxy, acrylic, or phenol.

[0024] Next, as shown in Figure 3B, an insulating layer 110 is laminated on one surface 100A of the core substrate 100 to form a through hole 110vh, and then a conductor layer 112 is formed on the insulating layer 110. A through conductor 13 is formed simultaneously with the formation of the conductor layer 112. An insulating layer 120 is laminated on the other surface 100B of the core substrate 100 to form a through hole 120vh, and then a conductor layer 122 is formed on the insulating layer 120. A through conductor 23 is formed simultaneously with the formation of the conductor layer 122.

[0025] The manufacturing method of the wiring board according to the embodiment includes at least the formation of an insulating layer 110, the formation of through holes 110vh, and the formation of through conductors 13. The methods for forming the insulating layer 110, the through holes 110vh, and the through conductors 13 are described in detail below with reference to Figures 3C to 3J, which correspond to the range shown in Figure 2.

[0026] First, in the formation of the insulating layer 110, as shown in Figure 3C, a film-like insulating resin (e.g., epoxy resin) is heat-pressed onto one surface 100A of the core substrate 100. The insulating layer 110 is equipped with a protective film PF that covers the upper surface of the insulating layer 110, which may be, for example, a polyethylene terephthalate (PET) film or a polyethylene naphthalate (PEN) film.

[0027] Next, as shown in Figure 3D, a through-hole 110vh is formed at the position where the through-conductor 13 (see Figure 2) is to be formed. This through-hole 110vh penetrates the protective film PF and the insulating layer 110 in the thickness direction, exposing the upper surface of the conductor layer 111. The through-hole 110vh is formed by irradiating the protective film PF from the outside, for example, with ultraviolet laser light. The ultraviolet laser light used has a wavelength of 100 nm or more and 500 nm or less. The through-hole 110vh may be formed such that the diameter of the opening on the first surface 110A is, for example, 7 μm or more and 18 μm or less. The through-hole 110vh may also be formed using laser light other than ultraviolet laser light, for example, carbon dioxide laser light or excimer laser light.

[0028] After the formation of the through-hole 110vh, a desmear treatment may be performed to remove the processing-modified material generated within the through-hole 110vh. The desmear treatment may be a dry desmear treatment using a plasma gas containing a fluorine-based gas and oxygen. The desmear treatment may also be a wet desmear treatment, which includes immersion in a chemical solution such as a permanganate solution. When a wet desmear treatment is performed, it is preferable to remove the oxide film generated on the upper surface of the conductor layer 111 by the wet desmear treatment after the desmear treatment and before the plasma treatment described below. The desmear treatment may be performed while protecting the first surface 110A of the insulating layer 110, with the first surface 110A of the insulating layer 110 covered by a protective film PF.

[0029] Next, the through-hole 110vh is subjected to plasma treatment by exposing it to a plasma gas containing a fluorine-based gas but free of oxygen. Through plasma treatment, a fluorine-containing layer 200 may be formed on the surface of the conductor layer 111 exposed within the through-hole 110vh, as shown in Figure 3E. The fluorine-containing layer 200 may be a layer that fluorinated the upper surface of the conductor layer 111 exposed within the through-hole 110vh. The fluorine-containing layer 200 may be a compound layer coating the upper surface of the conductor layer 111. The compound layer coating the upper surface of the conductor layer 111 may also coat the inner wall surface of the through-hole 110vh. The upper surface of the conductor layer 111 with the fluorine-containing layer 200 formed thereon becomes oxidation-resistant, and the formation of an oxide film (e.g., copper oxide) on the upper surface of the conductor layer 111 is suppressed. The thickness of the fluorine-containing layer 200 is preferably 25 to 100 nm.

[0030] The fluorine-containing layer 200 is formed when the upper surface of the conductive layer 111 is exposed to a fluorine-containing plasma, for example, a plasma formed from carbon tetrafluoride (CF4) gas. The fluorine-containing layer 200 can be formed by appropriately controlling the plasma treatment conditions, such as the type and concentration of the fluorine-containing plasma gas, temperature, pressure, and applied voltage. When performing plasma treatment using a fluorine-based gas similar to that used in dry desmear treatment, it is preferable to perform the plasma treatment at an applied voltage several tens of percent lower than that used in dry desmear treatment.

[0031] According to this embodiment, by forming a fluorine-containing layer on the upper surface of the conductor layer 111, the formation of an oxide film on the upper surface of the conductor layer 111 can be suppressed, and the adhesion between the conductor layer 111 and the metal film layer 112a (see Figure 3G) can be improved. By forming the metal film layer 112a in close contact with the upper surface of the conductor layer 111, the contact resistance and connection reliability between the conductor layer 111 and the through conductor 13 (see Figure 3J) can be improved.

[0032] Next, as shown in Figure 3F, the protective film PF is removed from the first surface 110A of the insulating layer 110, and the fluorine-containing layer 200 is removed from the upper surface of the conductive layer 111. The fluorine-containing layer 200 can be removed, for example, by ion gun treatment. "Ion gun treatment" is a treatment method in which a raw material gas supplied from an ion source is plasma-generated in a vacuum, and the plasma-generated ions are made to collide with the object to be treated (the upper surface of the conductive layer 111 in Figure 3F). For example, argon is used as the raw material gas in ion gun treatment.

[0033] Next, as shown in Figure 3G, a metal film layer 112a, such as a copper sputtered film, is formed over the inner surface (bottom surface and inner wall surface) of the through hole 110vh and over the entire first surface 110A of the insulating layer 110. The removal of the fluorine-containing film 200, as described in Figure 3F, may be performed as a pretreatment for forming the copper sputtered film.

[0034] Next, as shown in Figure 3H, a plating resist 112r for electroplating is formed on the metal film layer 112a. The plating resist 112r is formed by forming a resin layer containing, for example, a photosensitive polyhydroxyether resin, epoxy resin, phenol resin, or polyimide resin, followed by exposure and development using a mask having an appropriate aperture pattern. The plating resist 112r is formed to have an aperture 112ro corresponding to the conductive pattern that the conductive layer 112 (see Figure 1) in contact with the first surface 110A of the insulating layer 110 should have. As shown, the aperture 112ro is formed to overlap the entire through hole 110vh and, in a plan view, a portion of the first surface 110A of the insulating layer 110 surrounding the through hole 110vh.

[0035] Next, as shown in Figure 3I, electroplating using the metal film layer 112a as a seed layer fills the inside of the through hole 110vh and the opening 112ro of the plating resist 112r with the plating film layer 112b. A through conductor 13 is formed, and a conductor layer 112 integrated with the through conductor 13 is also formed.

[0036] Next, the plating resist 112r is removed. The metal film layer 112a exposed by the removal of the plating resist 112r is removed by etching, and the first surface 110A of the insulating layer 110 is exposed, as shown in Figure 3J. As shown in Figure 3B, the formation of the insulating layer 110, via conductor 13, and conductor layer 112 closest to the first surface 100A of the core substrate 100 is completed. On the second surface 100B side of the core substrate 100, the insulating layer 120, via conductor 23, and conductor layer 122 can be formed simultaneously with the insulating layer 110 and conductor layer 112 by the same process as described with reference to Figures 3C to 3J.

[0037] Next, as shown in Figure 3K, the same process as described above for forming the insulating layer 110, the conductor layer 112, and the through conductor 13 is repeated on the upper side of one face 100A of the core substrate 100. On the other face 100B of the core substrate 100, the same process as described above for forming the insulating layer 120, the conductor layer 122, and the through conductor 23 is repeated. The formation of the first build-up section 11 and the second build-up section 12 is completed. The outermost conductor layer 112 of the first build-up section 11 may be formed in a pattern including a conductor pad 112p. The outermost conductor layer 122 of the second build-up section 12 may be formed in a pattern including a conductor pad 122p.

[0038] Next, as shown in Figure 3L, a solder resist layer SR1 is formed on the first build-up section 11, and a solder resist layer SR2 is formed on the second build-up section 12. Solder resist layers SR1 and SR2 are formed by, for example, forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and then exposure and development using a mask having an appropriate aperture pattern. Solder resist layers SR1 and SR2 are formed to have apertures SR1o and SR2o that expose the conductor pads 112p and 122p. A surface protective film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, or heat-resistant preflux may be formed on the exposed surfaces of the conductor pads 112p and 122p by electroless plating, solder leveling, or spray coating. The wiring board 1 is completed by going through the above steps.

[0039] The wiring boards manufactured by the wiring board manufacturing method of the embodiment are not limited to having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. The described wiring board 1 includes a core substrate 100, a first build-up section 11, and a second build-up section 12, but the wiring boards manufactured by the wiring board manufacturing method of the embodiment only need to include at least an insulating layer 110, a through conductor 13, and a conductor layer 112, and may have a configuration that does not include the core substrate 100 and the second build-up section 12.

[0040] The method for manufacturing the wiring board of this embodiment is not limited to the method described with reference to Figures 3A to 3L. In the method for manufacturing the wiring board of this embodiment, any additional steps may be added in addition to the steps described above, and any part of the steps described above may be omitted. [Explanation of symbols]

[0041] 1 Wiring board 10 Insulating layer 11. First Build-up Department 12. Second Build-up Department 13, 23 Through conductor (via conductor) 100 core boards 110, 120 insulating layer 111, 121 Conductor layer 112, 122 Conductor layer 10th, 110vth through hole SR1, SR2 Solder Resist 200 Fluorine-containing layer

Claims

1. Forming a conductive layer and an insulating layer covering the conductive layer, By irradiating the insulating layer with laser light, a through-hole is formed that penetrates the insulating layer and exposes the upper surface of the conductor layer. A through conductor is formed by filling the through hole with a conductor, A method for manufacturing a wiring board, including, The manufacturing method includes a plasma treatment step of exposing the upper surface of the conductive layer exposed in the through hole to a plasma containing fluorine, The plasma treatment step is a step of forming a fluorine-containing layer on the upper surface of the conductor layer exposed in the through hole.

2. A method for manufacturing a wiring board according to claim 1, The plasma treatment process is CF 4 This is a step of forming the fluorine-containing layer using the plasma generated from the gas.

3. A method for manufacturing a wiring board according to claim 1, The thickness of the fluorine-containing layer is 25 to 100 nm.

4. A method for manufacturing a wiring board according to claim 1, further, The process includes a step of desmearing the through-hole before the plasma treatment.

5. A method for manufacturing a wiring board according to claim 4, The aforementioned desmear treatment is a wet treatment using a permanganate solution.

6. A method for manufacturing a wiring board according to claim 4, The aforementioned desmear treatment is a dry treatment using gas.

7. A method for manufacturing a wiring board according to claim 1, further, The process includes removing the fluorine-containing layer on the upper surface of the conductor layer before forming the through-conductor.

8. A method for manufacturing a wiring board according to claim 7, The step of removing the fluorine-containing layer is performed using an ion gun.

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