Semiconductor equipment and Doherty amplifiers

Abstract

We provide a semiconductor device for Doherty amplifiers that improves their characteristics. [Solution] The semiconductor device for the Doherty amplifier includes a first FET 11 having a first nitride semiconductor layer 35a and a first source electrode 40a, a first gate electrode 42a, and a first drain electrode 44a provided on the first nitride semiconductor layer, and a main amplifier that amplifies a first signal distributed from an input signal, and a second FET having a second nitride semiconductor layer and a second source electrode, a second gate electrode, and a second drain electrode provided on the second nitride semiconductor layer, and a peak amplifier that amplifies a second signal distributed from an input signal, wherein the buffer layer 32a of the first FET is thicker than the buffer layer of the second FET, so that the energy of the conduction band bottom in the buffer layer near the two-dimensional electron gas 36 in the first FET is lower than that of the second FET, and for this reason the drain conductance of the first FET is greater than the drain conductance of the second FET.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and Doherty amplifiers. [Background technology]

[0002] Doherty amplifiers are known as amplifiers that amplify high-frequency signals such as microwaves. In a Doherty amplifier, the main amplifier and the peak amplifier amplify the input signal in parallel, and the amplified signals are combined by a combiner. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2005 / 119787 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In Doherty amplifiers, there is a need to improve efficiency and reduce distortion.

[0005] This disclosure aims to provide semiconductor devices and Doherty amplifiers with improved characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier, comprising: a first FET having a first nitride semiconductor layer and a first source electrode, a first gate electrode, and a first drain electrode provided on the first nitride semiconductor layer, a main amplifier that amplifies a first signal distributed from an input signal; and a second FET having a second nitride semiconductor layer and a second source electrode, a second gate electrode, and a second drain electrode provided on the second nitride semiconductor layer, a peak amplifier that amplifies a second signal distributed from the input signal, wherein the first drain conductance when a gate voltage obtained by adding a constant voltage from a pinch-off voltage and a constant drain voltage are applied to the first FET is greater than the second drain conductance when a gate voltage that allows a drain current of the same value as the drain current flowing through the first FET when the first drain conductance is measured and the constant drain voltage are applied to the second FET. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide semiconductor devices and Doherty amplifiers with improved characteristics. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram of the Doherty amplifier in Embodiment 1. [Figure 2] Figure 2 shows the drain characteristics of FET11. [Figure 3] Figure 3 shows the drain characteristics of FET13. [Figure 4] Figure 4 shows the gain and drain efficiency DE of a Doherty amplifier with respect to output power Pout. [Figure 5] Figure 5 shows the impedances Zm and Zp with respect to the output power Pout of a Doherty amplifier. [Figure 6] Figure 6 is a schematic diagram showing the drain current as a function of time in the main amplifier. [Figure 7]FIG. 7 is a schematic diagram showing the gain with respect to the input power Pin in the main amplifier. [Figure 8] FIG. 8 is a diagram showing the distortion with respect to the off - leak current. [Figure 9] FIG. 9 is a schematic diagram showing the drain lag with respect to the drain conductance. [Figure 10] FIG. 10 is a cross - sectional view showing Structural Example 1 of FET11. [Figure 11] FIG. 11 is a cross - sectional view showing Structural Example 1 of FET13. [Figure 12] FIG. 12 is a cross - sectional view showing Structural Example 2 of FET13. [Figure 13] FIG. 13 is a cross - sectional view showing Structural Example 3 of FET13. [Figure 14] FIG. 14 is a cross - sectional view showing Structural Example 4 of FET13. <000□085> [Figure 15] FIG. 15 is a cross - sectional view showing Structural Example 5 of FET13. <□□□□□87> [Figure 16] FIG. 16 is a cross - sectional view showing Structural Example 6 of FET13. [Figure 17] FIG. 17 is a cross - sectional view showing Structural Example 7 of FET13. [Figure 18] FIG. 18 is a cross - sectional view showing Structural Example 8 of FET13. [Figure 19] FIG. 19 is a cross - sectional view showing Structural Example 2 of FET11. [Figure 20] FIG. 20 is a cross - sectional view showing Structural Example 9 of FET13. [Figure 21] FIG. 21 is a cross - sectional view showing Structural Example 10 of FET13. [Figure 22] FIG. 22 is a plan view showing Example 1 of the semiconductor device used in Embodiment 1. [Figure 23] FIG. 23 is a plan view showing Example 2 of the semiconductor device used in Embodiment 1.

MODE FOR CARRYING OUT THE INVENTION

[0009] <□□□□□8>[DESCRIPTION OF EMBODIMENTS OF THE PRESENT DISCLOSURE] First, the embodiments of this disclosure will be listed and described.

[0010] (1) One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier, comprising: a first FET having a first nitride semiconductor layer and a first source electrode, a first gate electrode, and a first drain electrode provided on the first nitride semiconductor layer, a main amplifier that amplifies a first signal distributed from an input signal; and a second FET having a second nitride semiconductor layer and a second source electrode, a second gate electrode, and a second drain electrode provided on the second nitride semiconductor layer, a peak amplifier that amplifies a second signal distributed from the input signal, wherein the first drain conductance when a gate voltage obtained by adding a constant voltage from a pinch-off voltage and a constant drain voltage are applied to the first FET is greater than the second drain conductance when a gate voltage that allows a drain current of the same value as the drain current flowing through the first FET when the first drain conductance is measured and the constant drain voltage is applied to the second FET. This makes it possible to achieve both efficiency and distortion and improve characteristics. (2) In (1) above, the first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer, and the second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer, and the first buffer layer may be thicker than the second buffer layer. This makes the drain conductance of the first FET greater than the conductance of the second FET. (3) In (1) or (2) above, the first nitride semiconductor layer comprises a first aluminum nitride layer provided on a first substrate, a first gallium nitride buffer layer provided on the first aluminum nitride layer, and a first electron supply layer provided on the first gallium nitride buffer layer, and the second nitride semiconductor layer comprises a second aluminum nitride layer provided on a second substrate, a second gallium nitride buffer layer provided on the second aluminum nitride layer, and a second electron supply layer provided on the second gallium nitride buffer layer, and the first aluminum nitride layer may be thinner than the second aluminum nitride layer. This makes the drain conductance of the first FET greater than the conductance of the second FET. (4) In any of (1) to (3) above, the first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer, and the second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer, and the distance between the first buffer layer and the first gate electrode in the thickness direction of the first nitride semiconductor layer may be greater than the distance between the second buffer layer and the second gate electrode in the thickness direction of the second nitride semiconductor layer. This makes the drain conductance of the first FET greater than the conductance of the second FET. (5) In any of (1) to (4) above, the first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer, and the second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer, and the carbon concentration of the first buffer layer may be lower than the carbon concentration of the second buffer layer. This makes the drain conductance of the first FET greater than the conductance of the second FET. (6) In any of (1) to (5) above, the gate length of the first gate electrode may be smaller than the gate length of the second gate electrode. This makes the drain conductance of the first FET larger than the conductance of the second FET. (7) In any of (1) to (6) above, the first gate electrode may overhang at least toward the first drain electrode, and the second gate electrode may overhang at least toward the second drain electrode, and the length of the overhang of the first gate electrode toward the first drain electrode may be smaller than the length of the overhang of the second gate electrode toward the second drain electrode. This makes the drain conductance of the first FET larger than the conductance of the second FET. (8) In any of (1) to (7) above, the first FET includes a first field plate provided above the first nitride semiconductor layer between the first gate electrode and the first drain electrode, and the second FET includes a second field plate provided above the second nitride semiconductor layer between the second gate electrode and the second drain electrode, and the distance between the first nitride semiconductor layer and the first field plate in the thickness direction of the first nitride semiconductor layer may be greater than the distance between the second nitride semiconductor layer and the second field plate in the thickness direction of the second nitride semiconductor layer. This makes the drain conductance of the first FET greater than the conductance of the second FET. (9) In any of (1) to (8) above, the first FET includes a first field plate provided above the first nitride semiconductor layer between the first gate electrode and the first drain electrode, and the second FET includes a second field plate provided above the second nitride semiconductor layer between the second gate electrode and the second drain electrode, and the distance between the end of the first gate electrode closest to the first drain electrode and the end of the first field plate closest to the first drain electrode may be smaller than the distance between the end of the second gate electrode closest to the second drain electrode and the end of the second field plate closest to the second drain electrode. This makes the drain conductance of the first FET larger than the conductance of the second FET. (10) A Doherty amplifier may also be provided, comprising any semiconductor device described in (1) to (9) above, a distributor that distributes the input signal into a first signal and a second signal, and a combiner that combines the first signal amplified by the main amplifier and the second signal amplified by the peak amplifier. This allows for a balance between efficiency and distortion, and improves the characteristics.

[0011] [Details of the embodiments of this disclosure] Specific examples of semiconductor devices and Doherty amplifiers according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0012] (Embodiment 1) Figure 1 is a block diagram of a Doherty amplifier in Embodiment 1. As shown in Figure 1, in the Doherty amplifier 100, a main amplifier 10 and a peak amplifier 12 are connected in parallel between the input terminal Tin and the output terminal Tout. A high-frequency signal is input to the input terminal Tin as the input signal Sin. The distributor 14 distributes the input signal Sin into two signals S1 (first signal) and S2 (second signal). When the Doherty amplifier 100 is used as a power pump for a mobile communication base station, the frequency of the input signal Sin is, for example, from 0.5 GHz to 20 GHz.

[0013] Signal S1 is input to the main amplifier 10 via the matching circuit 20. The matching circuit 20 matches the impedance seen from the distributor 14 to the matching circuit 20 with the impedance seen from the matching circuit 20 to the main amplifier 10. The main amplifier 10 amplifies the input signal S1 and outputs the amplified signal S3 (third signal). Signal S3 is input to the combiner 16 via the matching circuit 22. The matching circuit 22 matches the impedance seen from the main amplifier 10 to the matching circuit 22 with the impedance seen from the matching circuit 22 to the combiner 16.

[0014] Signal S2 is input to the peak amplifier 12 via the matching circuit 21. The matching circuit 21 matches the impedance seen from the distributor 14 to the matching circuit 21 with the impedance seen from the matching circuit 21 to the peak amplifier 12. The peak amplifier 12 amplifies the input signal S2 and outputs the amplified signal S4 (fourth signal). Signal S4 is input to the combiner 16 via the matching circuit 23. The matching circuit 23 matches the impedance seen from the peak amplifier 12 to the matching circuit 23 with the impedance seen from the matching circuit 23 to the combiner 16. The combiner 16 is equipped with an impedance converter 18. Signal S3 input to the combiner 16 is combined with signal S4 at node N1 via the impedance converter 18. The combined signals S3 and S4 are output as output signal Sout to the output terminal Tout.

[0015] The main amplifier 10 and the peak amplifier 12 each include FETs (Field Effect Transistors) 11 (first FET) and 13 (second FET), respectively. FETs 11 and 13 are provided in a nitride semiconductor layer and are, for example, GaN (gallium nitride) HEMT (High Electron Mobility Transistor). In FETs 11 and 13, the source S is grounded, signals S1 and S2 are input to the gate G, respectively, and signals S3 and S4 are output from the drain D, respectively.

[0016] The main amplifier 10 operates in Class AB or Class B, and the peak amplifier 12 operates in Class C. As a result, when the input power of the input signal Sin is small, the main amplifier 10 primarily amplifies the input signal Sin. As the input power gradually increases, the peak amplifier 12, in addition to the main amplifier 10, amplifies the input signal Sin. The output power of the output signal Sout just before the peak amplifier 12 begins to operate is called the back-off power Pbo. When the input power increases further and both the main amplifier 10 and the peak amplifier 12 reach saturation power, the output power is called the saturation power Psat.

[0017] The matching circuit 22 is designed so that the efficiency of the main amplifier 10 is high when the back-off power is Pbo, and so that the output power of the main amplifier 10 is improved when the saturation power is Psat. The matching circuit 23 is designed so that the output power of the peak amplifier 12 is improved when the saturation power is Psat. Let Zo be the impedance seen from node N1 to the output terminal Tout. Zo is approximately a real number. The impedance converter 18 is designed so that at the back-off power Pbo, the impedance Zm seen from node N1 through the impedance converter 18 to the main amplifier 10 is Zo, and at the saturation power Psat, the impedance Zm becomes 2 × Zo. The matching circuit 23 is designed so that at the back-off power Pbo, the impedance Zp seen from node N1 to the peak amplifier 12 is approximately infinite, and at the saturation power Psat, the impedance Zp becomes 2 × Zo. Note that the impedance Zm and Zp become 2 × Zo when the Doherty amplifier 100 is a symmetrical Doherty amplifier (i.e., when the magnitudes of the main amplifier 10 and the peak amplifier 12 are the same). If the Doherty amplifier 100 is an asymmetric Doherty amplifier, the impedances Zm and Zp are designed appropriately at the saturation power Psat.

[0018] (Explanation of drain conductance of FETs 11 and 13) Figures 2 and 3 show the drain characteristics of FETs 11 and 13, respectively. In Figures 2 and 3, the horizontal axis represents the drain voltage Vds, and the vertical axis represents the drain current Ids. Vds0 is the drain bias voltage applied to FETs 11 and 13 during operation. The pinch-off voltages of FETs 11 and 13 are Vp1 and Vp3, respectively. The gate voltage Vgs is applied in constant voltage steps relative to the pinch-off voltages Vp1 and Vp3. The gate bias voltage Vgs1 of FET 11 is Vp1 + ΔV1. The gate bias voltage Vgs3 of FET 13 is negatively greater than the pinch-off voltage Vp3. That is, when the gate voltage Vgs of FET 13 is Vgs3, FET 13 is pinched off. The drain conductance Gd corresponds to the slope of the drain current Ids with respect to the drain voltage Vds. For example, in FET11, the drain conductance Gd1 is defined as the drain conductance when the drain voltage Vds is Vds0 and the gate voltage Vgs is Vp1 + ΔV1. In FET13, the drain conductance Gd3 is defined as the drain conductance when the drain voltage Vds is Vds0 and the gate voltage Vgs is Vp3 + ΔV3. Here, ΔV3 in FET11 and FET13 is set to such that the drain current Ids0 in FET13 is the same as the drain current Ids0 in FET11 when the gate voltage is Vp1 + ΔV1. The drain conductance Gd3 of FET13 is smaller than the drain conductance Gd1 of FET11.

[0019] (Reasons for reducing the drain conductance Gd3 of FET13) In Embodiment 1, the reason for making the drain conductance Gd3 of FET13 smaller than the drain conductance Gd1 of FET11 will be explained. First, a simulation was performed on the Doherty amplifier, specifically the case where the drain conductance of FET13 of the peak amplifier 12 was changed. In the simulation, it was assumed that changing the gate bias voltage Vgs3 of FET13 was equivalent to changing the drain conductance Gd3. That is, making the gate bias voltage Vgs3 negatively small would result in less pinch-off, which was considered equivalent to a large drain conductance. The simulation did not consider the reactance components of FET11 and 13. Therefore, although the values ​​of each numerical value are not accurate, the trend of each numerical value was simulated.

[0020] Figure 4 shows the gain and drain efficiency DE of a Doherty amplifier with respect to output power Pout. The horizontal axis represents the output power Pout of the output signal Sout, and the vertical axis represents the linear gain and drain efficiency DE. Figure 5 shows the impedances Zm and Zp of a Doherty amplifier with respect to output power Pout. The horizontal axis represents the output power Pout, and the vertical axis represents the impedance Zm as seen from node N1 to the main amplifier 10, and the impedance Zp as seen from node N1 to the peak amplifier 12. Since the reactance component is not considered, the impedances Zm and Zp are real numbers. The impedance Zo is assumed to be 25Ω. The solid, dashed, and dotted lines correspond to the cases where the drain conductance Gd3 is small, medium, and large, respectively. When the output power is 35dBm and 41dBm, these correspond to the back-off power Pbo and saturation power Psat, respectively.

[0021] As shown in Figure 4, at saturation power Psat, the drain efficiency DE is approximately the same regardless of the drain conductance Gd3. At backoff power Pbo, as the drain conductance Gd3 increases, the drain efficiency DE decreases.

[0022] As shown in Figure 5, when the drain conductance Gd3 is small, at saturation power Psat, the impedances Zm and Zp are approximately 50Ω, and at back-off power Pbo, the impedances Zm and Zp are approximately 25Ω and almost infinite, respectively. Thus, the impedances Zm and Zp are close to the designed values. When the drain conductance Gd3 is large, at saturation power Psat, the impedances Zm and Zp are approximately 50Ω. However, at back-off power Pbo, the impedance Zp becomes less than infinity, and the impedance Zm becomes greater than 25Ω. When the drain conductance Gd3 is large, FET13 is more likely to turn on even when the input power is small, and FET13 is not turned off at back-off power Pbo. Therefore, the impedance Zp becomes less than infinity. Also, the impedance Zm becomes greater than 25Ω. As a result, the load impedance matching condition of the main amplifier 10 at back-off power Pbo deviates from the condition that improves efficiency. Therefore, as shown in Figure 4, the drain efficiency DE decreases near the backoff power Pbo. As described above, efficiency can be improved by reducing the drain conductance Gd3 of the peak amplifier 12.

[0023] (Explanation of drain lag) This section describes the drain lag in a FET using a nitride semiconductor layer. Figure 6 is a schematic diagram showing the drain current as a function of time in the main amplifier. The horizontal axis represents periods T1 and T3, during which the input power is small and the main amplifier 10 does not amplify the input signal Sin. Period T2 represents the period during which the input power is large and the main amplifier 10 amplifies the input signal Sin. The vertical axis represents the drain bias current from period T1 to T3. As shown in Figure 6, in the initial period T1, the drain current is Ids1. In period T2, the drain current increases to Ids2. Immediately after transitioning from period T2 to period T3, the drain current decreases below Ids1, as shown by the dashed circle 50, and then increases with time to become Ids1.

[0024] Figure 7 is a schematic diagram showing the gain of the main amplifier with respect to the input power Pin. The solid line shows the case without a drain lag, and the dashed line shows the case with a drain lag. Pbo on the horizontal axis represents the input power Pin corresponding to the back-off power. As shown in Figure 7, in the case without a drain lag, the gain is almost constant when the input power Pin is less than or equal to Pbo, and the gain decreases when the input power Pin exceeds Pbo. As indicated by arrow 52, ​​even if the input power Pin changes over time, the gain characteristic with respect to the input power Pin remains unchanged below Pbo.

[0025] In the case of a drain lag, the state in which the input power Pin becomes small, as indicated by the leftward arrow 52, ​​corresponds to the state immediately after transitioning from period T2 to T3 in Figure 6. As a result, the drain current decreases, and the gain decreases. Consequently, the gain decreases as shown by the dashed circle 51. Thus, because the gain is not constant at input power Pin below Pbo, the AM (Amplitude Modulation)-AM distortion becomes large.

[0026] (Relationship between drain lag and drain conductance) To investigate the relationship between drain lag and drain conductance, the correlation between off-leak current and the distortion characteristics of a Doherty amplifier in a GaN HEMT was examined. The distortion characteristics of the Doherty amplifier are those of a Doherty amplifier fabricated using the same wafer from which the pinch-off characteristics were measured.

[0027] Figure 8 shows the distortion with respect to off-leak current. The off-leak current on the horizontal axis is the current that mainly flows through the buffer layer when the FET is completely pinched off. The distortion on the vertical axis shows the modulation wave distortion of the Doherty amplifier, and it is shown that the distortion characteristics deteriorate as the distortion increases. Each dot indicates a measurement point, and the structure of the GaN HEMT is the same for the same type of dot (circle, triangle, and square). The structure of the GaN HEMT is different for different types of dots. Variations within the same dot are due to manufacturing variations, etc. As shown in Figure 8, the distortion improves as the off-leak current increases, and the distortion deteriorates as the off-leak current decreases. A large off-leak current indicates poor pinch-off characteristics of the FET and corresponds to a large drain conductance. As explained in Figure 7, poor distortion is thought to correspond to a large drain lag.

[0028] Figure 9 is a schematic diagram showing the relationship between drain lag and drain conductance. The vertical axis, representing the drain lag, indicates that a larger drain lag corresponds to a greater decrease in drain current at the dashed circle 51 in Figure 7. The dots represent the drain lag for several types of GaN HEMTs against their respective drain conductances. As shown in Figure 9, a larger drain conductance results in a smaller drain lag, and a smaller drain conductance results in a larger drain lag.

[0029] (Comparison between the comparison target and Embodiment 1) Table 1 shows the drain conductance, efficiency, distortion, FETs, and design policy for amplifiers A through D.

[0030] [Table 1]

[0031] Amplifiers A and B correspond to the comparison targets, and amplifiers C and D correspond to Embodiment 1. Drain conductance indicates whether the drain conductance in the main amplifier 10 and peak amplifier 12 is large or small. Efficiency indicates whether the drain efficiency of the Doherty amplifier at back-off power Pbo is poor or good. Distortion indicates whether the modulated wave distortion is poor or good. FET indicates whether FET 11 and FET 13 have the same or different structures.

[0032] As shown in Table 1, in amplifier A, both the main amplifier 10 and the peak amplifier 12 have large drain conductances. Therefore, the drain efficiency at the back-off power Pbo is poor. Modulation wave distortion is improved. The structures of FETs 11 and 13 can be the same. Amplifier A is designed with an emphasis on distortion reduction over efficiency.

[0033] In amplifier B, both the main amplifier 10 and the peak amplifier 12 have low drain conductance. This improves drain efficiency at back-off power Pbo. Modulation wave distortion worsens. The structure of FETs 11 and 13 can be the same. Amplifier B is designed with efficiency in mind over distortion. Since FETs other than those with a nitride semiconductor layer have a small drain lag, adopting amplifier B makes it possible to achieve both efficiency and distortion.

[0034] In amplifier C, the drain conductance of the main amplifier 10 is increased as shown by the dashed circle 54 in Figure 9, and the drain conductance of the peak amplifier 12 is decreased as shown by the dashed circle 55. By decreasing the drain conductance of the peak amplifier 12, the drain efficiency DE at the back-off power Pbo can be increased. Even if the drain conductance of the main amplifier 10 is large, it has little effect on the efficiency at the back-off power Pbo. Therefore, the efficiency at the back-off power Pbo is improved. Increasing the drain conductance of the main amplifier 10 reduces the drain lag of the main amplifier 10. This reduces the modulation wave distortion. When the drain conductance of the peak amplifier 12 is small, the drain lag of the peak amplifier 12 becomes large. However, since the input signal Sin is mainly amplified by the main amplifier 10, even if the drain lag of the peak amplifier 12 is large, it does not have much effect on the modulation wave distortion. It is difficult to realize amplifier C if the structure of FETs 11 and 13 is the same.

[0035] Amplifier D has the same drain conductance, efficiency, and distortion as amplifier C. The difference from amplifier C lies in the different structures of FETs 11 and 13. This facilitates implementation. Amplifier D achieves a balance between efficiency and distortion, resulting in improved characteristics.

[0036] In the Doherty amplifier 100 of Embodiment 1, as shown in Figures 2 and 3, the drain conductance Gd1 (first drain conductance) when a gate voltage Vgs is applied to FET 11 by adding a constant voltage ΔV1 (positive value) from the pinch-off voltage Vp1, and a constant drain voltage Vds is applied, is greater than the drain conductance Gd3 (second drain conductance) when a gate voltage Vgs is applied to FET 13, through which a drain current Ids0 of the same value as the drain current Ids0 flowing through FET 11 when measuring the drain conductance Gd1, and a constant drain voltage Vds is applied. Here, the constant drain voltage applied to FET 11 and the constant drain voltage applied to FET 13 are the same within an error range. The drain current Ids0 flowing through FET 11 when measuring the drain conductance Gd1 and the drain current Ids0 flowing through FET 13 when measuring the drain conductance Gd3 are the same within an error range. Note that the drain current is the drain current per unit gate width. As a result, as shown in Table 1, it is possible to achieve both efficiency and reduced distortion, thereby improving the characteristics.

[0037] If the gate widths of FETs 11 and 13 are different, Gd1 and Gd3 are compared using a value normalized by the gate width [S / mm]. The method for measuring the drain conductances Gd1 and Gd3 is as follows: Using a network analyzer, the S-parameters are measured by applying predetermined gate voltage Vgs and drain voltage Vds. The drain conductance (reciprocal of the drain resistance) can be extracted from the measured S-parameters using the equivalent circuit of the FET.

[0038] Examples of setting the gate voltage Vgs and drain voltage Vds are described below. For example, set ΔV1 so that Vp1 + ΔV1 becomes the operating point of the main amplifier 10. The drain voltages Vds of FETs 11 and 13 are set to the same voltage, and this is the drain bias voltage Vds0 applied to FETs 11 and 13 when the Doherty amplifier 100 is operating. The pinch-off voltages Vp1 and Vp3 are defined as the gate voltage Vgs at which the drain current [A / mm] per unit gate width is a predetermined value when the drain bias voltage Vds0 is applied as the drain voltage Vds of FETs 11 and 13.

[0039] The drain conductance Gd1 is, for example, 1.1 times or more, 1.2 times or more, and 2 times or more than Gd3. If the drain conductance Gd1 is too large, the high-frequency characteristics will deteriorate. From this perspective, the drain conductance Gd1 is, for example, 10 times or less of Gd3. When Vds is 50V and the drain current Ids0 at a unit gate width is 10mA / mm, the drain conductance Gd1 is, for example, 0.1mS / mm to 10mS / mm, and as an example, 1mS / mm, and the drain conductance Gd3 is, for example, 0.1mS / mm to 10mS / mm, and as an example, 0.5mS / mm.

[0040] (FET11 structural example 1) Figure 10 is a cross-sectional view showing example 1 of the structure of FET 11. The direction from the source electrode 40a to the drain electrode 44a is the X direction, the thickness direction of the nitride semiconductor layer 35a is the Z direction, and the direction perpendicular to the X and Z directions is the Y direction. As shown in Figure 10, in FET 11, a nitride semiconductor layer 35a (first nitride semiconductor layer) is provided on a substrate 30a (first substrate). The nitride semiconductor layer 35a includes a nucleation layer 31a (first aluminum nitride layer) provided on the substrate 30a, a buffer layer 32a (first buffer layer or first gallium nitride buffer layer) provided on the nucleation layer 31a, an electron supply layer 33a (first electron supply layer) provided on the buffer layer 32a, and a cap layer 34a provided on the electron supply layer 33a. The source electrode 40a (first source electrode) and the drain electrode 44a (first drain electrode) are provided on the nitride semiconductor layer 35a. A gate electrode 42a (first gate electrode) is provided between the source electrode 40a and the drain electrode 44a on the nitride semiconductor layer 35a. An insulating layer 46a is provided on the nitride semiconductor layer 35a so as to cover the gate electrode 42a.

[0041] (FET13 structural example 1) Figure 11 is a cross-sectional view showing structural example 1 of FET 13. As shown in Figure 11, a nitride semiconductor layer 35b (second nitride semiconductor layer) is provided on a substrate 30b (second substrate). The nitride semiconductor layer 35b comprises a nucleation layer 31b (second aluminum nitride layer), a buffer layer 32b (second buffer layer or second gallium nitride buffer layer), an electron supply layer 33b (second electron supply layer), and a cap layer 34b. A source electrode 40b (second source electrode), a gate electrode 42b (second gate electrode), a drain electrode 44b (second drain electrode), and an insulating layer 46b are provided on the nitride semiconductor layer 35b. In FET 13, the thickness T32 of the buffer layer 32b is smaller than the thickness T32 of the buffer layer 32a in FET 11. The thickness, dimensions, and materials of the other layers are the same as those of FET 11 in Figure 10. Here, "same thickness, dimensions, and materials" does not mean strictly identical, but rather allows for differences of a manufacturing tolerance. The same applies to the following structural examples.

[0042] Substrates 30a and 30b are semiconductor substrates or insulating substrates, such as silicon carbide (SiC) substrates, sapphire substrates, or gallium nitride (GaN) substrates. Nucleation layers 31a and 31b are, for example, aluminum nitride (AlN) layers, and are layers for generating nuclei when depositing buffer layers 32a and 32b. Buffer layers 32a and 32b are, for example, gallium nitride (GaN) layers. Electron supply layers 33a and 33b are, for example, aluminum gallium nitride (AlGaN) layers. The band gap energies of electron supply layers 33a and 33b are greater than the band gap energies of buffer layers 32a and 32b. A two-dimensional electron gas 36 is formed in the vicinity of the electron supply layers 33a and 33b in the buffer layers 32a and 32b. The two-dimensional electron gas 36 functions as a channel. Cap layers 34a and 34b are, for example, gallium nitride layers, and function as protective layers for electron supply layers 33a and 33b.

[0043] At least one of the nucleation layers 31a, 31b and the cap layers 34a and 34b may be omitted. The materials of the nucleation layers 31a, 31b, buffer layers 32a, 32b, electron supply layers 33a, 33b, and cap layers 34a and 34b may be nitride semiconductor layers. For example, the materials of the nucleation layers 31a and 31b are the same, the materials of the buffer layers 32a and 32b are the same, the materials of the electron supply layers 33a and 33b are the same, and the materials of the cap layers 34a and 34b are the same.

[0044] The thicknesses of the nucleation layer 31a, buffer layer 32a, electron supply layer 33a, and cap layer 34a are T31a, T32a, T33a, and T34a, respectively. The distance between the buffer layer 32a and the gate electrode 42a in the thickness direction of the nitride semiconductor layer 35a is L3a. The thicknesses of the nucleation layer 31b, buffer layer 32b, electron supply layer 33b, and cap layer 34b are T31b, T32b, T33b, and T34b, respectively. The distance between the buffer layer 32b and the gate electrode 42b in the thickness direction of the nitride semiconductor layer 35b is L3b.

[0045] The source electrodes 40a and 40b and the drain electrodes 44a and 44b are metal layers, for example, titanium and aluminum films, respectively, from the side closest to the nitride semiconductor layers 35a and 35b. The gate electrodes 42a and 42b are metal layers, for example, nickel and gold films, respectively, from the side closest to the nitride semiconductor layers 35a and 35b. The insulating layers 46a and 46b are inorganic insulating layers, for example, silicon nitride layers. The lengths of the gate electrodes 42a and 42b in the X direction where they contact the nitride semiconductor layers 35a and 35b are gate lengths Lga and Lgb, respectively. The cross-sectional shape of the gate electrodes 42a and 42b in the XY plane is an overhang structure. That is, the gate electrodes 42a and 42b have a first portion that contacts the nitride semiconductor layers 35a and 35b, and a second portion that is on the first portion and is wider in the X direction than the first portion. The overhang lengths Loa and Lob of the gate electrodes 42a and 42b, which overhang toward the drain electrodes 44a and 44b, are the distance in the X direction between the position of the gate electrodes 42a and 42b closest to the drain electrodes 44a and 44b within the region where the gate electrodes 42a and 42b are in contact with the nitride semiconductor layers 35a and 35b, and the position of the gate electrodes 42a and 42b closest to the drain electrodes 44a and 44b.

[0046] Thicknesses T31a and T31b are, for example, 5 nm to 50 nm, and 15 nm as an example. Thicknesses T32a and T32b are, for example, 50 nm to 1000 nm, and 500 nm as an example. Thicknesses T33a and T33b are, for example, 5 nm to 30 nm, and 20 nm as an example. Thicknesses T34a and T34b are, for example, 1 nm to 10 nm, and 5 nm as an example. Distances L3a and L3b are, for example, 6 nm to 40 nm, and 25 nm as an example. Gate lengths Lga and Lgb are, for example, 0.1 μm to 1.0 μm, and 0.5 μm as an example. Overhang lengths Loa and Lob are, for example, 0.05 μm to 0.50 μm, and 0.20 μm as an example.

[0047] As shown in Figures 10 and 11, buffer layer 32a is thicker than buffer layer 32b. As a result, the energy of the conduction band bottom in buffer layer 32a near the two-dimensional electron gas 36 in FET 11 is lower than the energy of the conduction band bottom in buffer layer 32b near the two-dimensional electron gas 36 in FET 13. Therefore, the drain conductance Gd1 of FET 11 can be made larger than Gd3.

[0048] The thickness T32a is, for example, 1.05 times or more, 1.1 times or more, and 1.2 times or more than the thickness T32b. If the thickness T32a is too large, the drain conductance Gd1 of FET11 becomes too large, and the high-frequency characteristics deteriorate. From this viewpoint, the thickness T32a can be set to twice or less than the thickness T32b.

[0049] (FET13 structural example 2) Figure 12 is a cross-sectional view showing structural example 2 of FET13. As shown in Figure 12, the thickness T31b of the nucleation layer 31b of FET13 is greater than the thickness T31a of the nucleation layer 31a of FET11 in Figure 10. The thickness, dimensions, and materials of the other layers are the same as those of FET11 in Figure 10.

[0050] As shown in Figures 10 and 12, the nucleation layer 31a is thinner than the nucleation layer 31b. The nucleation layers 31a and 31b are aluminum nitride, and the buffer layers 32a and 32b are gallium nitride. Therefore, the band gap energies of the nucleation layers 31a and 31b are greater than the band gap energies of the buffer layers 32a and 32b. As a result, the energy of the conduction band bottom in the buffer layer 32a near the two-dimensional electron gas 36 in FET 11, which has a thin thickness T31a, is lower than the energy of the conduction band bottom in the buffer layer 32b near the two-dimensional electron gas 36 in FET 13. Therefore, the drain conductance Gd1 of FET 11 can be made larger than Gd3.

[0051] The thickness T31a is, for example, 0.98 times or less, 0.95 times or less, or 0.9 times or less than the thickness T31b. If the thickness T31a of FET11 is too small, it becomes difficult to deposit the buffer layer 32a. From this viewpoint, the thickness T31a can be 0.5 times or more the thickness T31b.

[0052] (FET13 structural example 3) Figure 13 is a cross-sectional view showing structural example 3 of FET 13. As shown in Figure 13, the thickness T34b of the cap layer 34b of FET 13 is smaller than the thickness T34a of the cap layer 34a of FET 11 in Figure 10. As a result, the distance L3b of FET 13 is smaller than the distance L3a of FET 11. The thickness, dimensions, and materials of the other layers are the same as those of FET 11 in Figure 10.

[0053] As shown in Figures 10 and 13, the distance L3a of FET 11 is greater than the distance L3b of FET 13. When the aspect ratio of the regions directly below the gate electrodes 42a and 42b (i.e., L3a / Lg3 and L3b / Lgb) increases, the drain conductance increases. Therefore, the drain conductance Gd1 of FET 11 can be made greater than Gd3.

[0054] The distance L3a is, for example, 1.05 times or more, 1.1 times or more, and 1.2 times or more than the distance L3b. If the distance L3a is too large, the drain conductance Gd1 of FET11 becomes too large, and the high-frequency characteristics deteriorate. From this point of view, the distance L3a can be set to twice or less than L3b. An example where thicknesses T33a and T33b are the same was explained, but thickness T33a may be larger than T33b.

[0055] (FET13 structural example 4) Figure 14 is a cross-sectional view showing structural example 4 of FET13. As shown in Figure 14, the carbon concentration of the buffer layer 32b of FET13 is higher than that of the buffer layer 32a of FET11 in Figure 10. The thickness, dimensions, and materials of the other layers are the same as those of FET11 in Figure 10.

[0056] As shown in FIGS. 10 and 14, the carbon concentration of the buffer layer 32a is lower than that of the buffer layer 32b. In the nitride semiconductor layer, carbon functions as an acceptor. Therefore, the energy of the bottom of the conduction band in the buffer layer 32a near the two-dimensional electron gas 36 in the FET 11 with a low carbon concentration is lower than the energy of the bottom of the conduction band in the buffer layer 32b near the two-dimensional electron gas 36 in the FET 13. Therefore, the drain conductance Gd1 of the FET 11 can be made larger than Gd3.

[0057] The carbon concentration of the buffer layer 32a is, for example, 2 times or less, 5 times or less, and 10 times or less that of the buffer layer 32b. If the carbon concentration of the buffer layer 32a is too low, the drain conductance Gd1 of the FET 11 becomes too large and the high-frequency characteristics deteriorate. From this viewpoint, the carbon concentration of the buffer layer 32a can be 100 times or more that of the buffer layer 32b. The carbon concentration of the buffer layer 32a is, for example, from 1×10 15 cm -3 to 1×10 18 cm -3 and the carbon concentration of the buffer layer 32b is, for example, from 1×10 15 cm -3 to 1×10 18 cm -3 . The difference between the carbon concentration of the buffer layer 32b and the carbon concentration of the buffer layer 32a is, for example, 1×10 16 cm -3 or more, 2×10 16 cm -3 or more, and 5×10 16 cm -3 or more.

[0058] (Structural Example 5 of FET13) FIG. 15 is a cross-sectional view showing a structural example 5 of the FET 13. As shown in FIG. 15, the gate length Lgb of the FET 13 is larger than the gate length Lga of the FET 11 in FIG. 10. The thicknesses, dimensions, materials, etc. of the other layers are the same as those of the FET 11 in FIG. 10.

[0059] As shown in Figures 10 and 15, the gate length Lga of FET11 is smaller than the gate length Lgb of FET13. A shorter gate length increases the drain conductance. Therefore, the drain conductance Gd1 of FET11 can be made larger than Gd3.

[0060] The gate length Lga is, for example, 0.9 times or less, 0.9 times or less, and 0.8 times or less of the gate length Lgb. If the gate length Lga is too short, the drain conductance Gd1 of FET11 becomes too large, and the high-frequency characteristics deteriorate. From this perspective, the gate length Lga can be 0.5 times or more of the gate length Lgb. The difference between the gate length Lga and the gate length Lgb is, for example, 50 nm or more, 100 nm or more, and 200 nm or more.

[0061] (FET13 structural example 6) Figure 16 is a cross-sectional view showing structural example 6 of FET13. As shown in Figure 16, the overhang length Lob of FET13 is greater than the overhang length Loa of FET11 in Figure 10. The thickness, dimensions, and materials of the other layers are the same as those of FET11 in Figure 10.

[0062] As shown in Figures 10 and 16, the overhang length Loa of FET 11 is smaller than the overhang length Lob of FET 13. The potential of the upper surface of the nitride semiconductor layers 35a and 35b below the overhanging gate electrodes 42a and 42b approaches the gate potential, relaxing the electric field within the nitride semiconductor layers 35a and 35b, and reducing the drain conductance. As a result, the drain conductance Gd1 of FET 11, which has a shorter overhang length Loa, becomes larger. Therefore, the drain conductance Gd1 of FET 11 can be made larger than Gd3.

[0063] The overhang length Loa is, for example, 0.9 times or less, 0.9 times or less, and 0.8 times or less of the overhang length Lob. If the overhang length Loa is too short, the drain conductance Gd1 of FET11 becomes too large, and the high-frequency characteristics deteriorate. From this viewpoint, the overhang length Loa can be 0.5 times or more of the overhang length Lob. The difference between the overhang length Loa and Lob is, for example, 50 nm or more, 100 nm or more, and 200 nm or more.

[0064] (FET13 structural example 7) Figure 17 is a cross-sectional view showing structural example 7 of FET 13. As shown in Figure 17, a recess 38 is provided on the upper surface of the nitride semiconductor layer 35b. The bottom surface of the recess 38 is located within the cap layer 34b and does not reach the electron supply layer 33b. The gate electrode 42b is in contact with the nitride semiconductor layer 35b within the recess 38. The thickness, dimensions, and materials of the other layers are the same as those of FET 11 in Figure 10.

[0065] As shown in Figures 10 and 17, when a recess 38 is provided in FET 13, the distance L3a of FET 11 becomes larger than the distance L3b of FET 13. This increases the aspect ratio L3a / Lga of FET 11, and thus increases the drain conductance Gd1. Therefore, the drain conductance Gd1 of FET 11 can be made larger than Gd3.

[0066] A recess 38 may also be provided in FET11. When the recess depth in the case where recess 38 is not provided is set to 0 nm, the difference between the recess depth of FET13 and the recess depth of FET11 is, for example, 5 nm or more, 10 nm or more, and 20 nm or more. The recess 38 may reach the electron supply layer 33b.

[0067] (FET13 structural example 8) Figure 18 is a cross-sectional view showing structural example 8 of FET 13. As shown in Figure 18, a buffer layer 37 is provided between the nucleation layer 31b and the buffer layer 32b. The band gap energy of buffer layer 37 is greater than the band gap energy of buffer layer 32b. When buffer layer 32b is a gallium nitride layer, buffer layer 37 is, for example, an aluminum gallium nitride layer. The sum of the thicknesses T37 and T32b of buffer layer 37 is approximately the same as the thickness T32a in Figure 10.

[0068] As shown in Figure 18, when a buffer layer 37 is provided, the energy of the conduction band bottom in buffer layer 32b near the two-dimensional electron gas 36 in FET 13 becomes higher than the energy of the conduction band bottom in buffer layer 32a near the two-dimensional electron gas 36 in FET 11. Therefore, the drain conductance Gd1 of FET 11 can be made larger than Gd3.

[0069] (FET11 structural example 2) Figure 19 is a cross-sectional view showing structural example 2 of FET 11. As shown in Figure 19, a field plate 48a (first field plate) is provided on the insulating layer 46a, extending from above the gate electrode 42a to above the region between the gate electrode 42a and the drain electrode 44a. An insulating layer 47a is provided on the insulating layer 46a so as to cover the field plate 48a. The other configurations are the same as structural example 1 of FET 11 in Figure 1.

[0070] (FET13 structural example 9) Figure 20 is a cross-sectional view showing structural example 9 of FET 13. As shown in Figure 20, in FET 13, a field plate 48b (second field plate) is provided on an insulating layer 46b, and an insulating layer 47b is provided so as to cover the field plate 48b. The thickness T46b of the insulating layer 46b is smaller than the thickness T46a of the insulating layer 46a in Figure 19. The other configurations are the same as structural example 2 of FET 11 in Figure 19.

[0071] The field plates 48a and 48b are metal layers, such as a gold film. The insulating layers 47a and 47b are inorganic insulating layers, such as a silicon nitride layer. The thicknesses T46a and T46b correspond to the distance between the nitride semiconductor layers 35a and 35b and the field plates 48a and 48b in the Z direction. The distances L1a and L1b are the distance between the ends of the gate electrodes 42a and 42b that are close to the drain electrodes 44a and 44b and the ends of the field plates 48a and 48b that are close to the drain electrodes 44a and 44b. The thicknesses T46a and T46b are, for example, from 50 nm to 500 nm, and 200 nm as an example. The distances L1a and L1b are, for example, from 0.5 μm to 2.5 μm, and 1.0 μm as an example.

[0072] The field plates 48a and 48b are electrically connected to the source electrodes 40a and 40b, and the same potential as the source electrodes 40a and 40b is supplied to the field plates 48a and 48b. When the field plates 48a and 48b are provided, the potential of the upper surface of the nitride semiconductor layers 35a and 35b below the field plates 48a and 48b approaches the source potential, the electric field within the nitride semiconductor layers 35a and 35b is relaxed, and the drain conductance is reduced. The field plates 48a and 48b may be provided above the nitride semiconductor layers 35a and 35b between the gate electrodes 42a and 42b and the drain electrodes 44a and 44b, but may not be provided above the gate electrodes 42a and 42b.

[0073] As shown in Figures 19 and 20, the thickness T46a of the insulating layer 46a is greater than the thickness T46b of the insulating layer 46b. This allows the drain conductance Gd1 of the FET 11 to be greater than Gd3.

[0074] The thickness T46a is, for example, 1.05 times or more, 1.1 times or more, or 1.2 times or more than the thickness T46b. If the thickness T46b is too thin, leakage current will easily flow between the field plate 48b and the nitride semiconductor layer 35b in the FET 13. From this viewpoint, the thickness T46a can be twice or less the thickness T46b.

[0075] (FET13 structural example 10) Figure 21 is a cross-sectional view showing structural example 10 of FET13. As shown in Figure 21, the distance L1b of FET13 is greater than the distance L1a of FET11 in Figure 19. The thickness, dimensions, and materials of the other layers are the same as those of FET11 in Figure 19.

[0076] As shown in Figures 19 and 21, the distance L1a of FET 11 is smaller than the distance L1b of FET 13. This relaxes the electric field within the nitride semiconductor layers 35a and 35b, allowing the drain conductance Gd1 of FET 11 to be greater than Gd3.

[0077] Distance L1a is, for example, 0.9 times or less, 0.9 times or less, and 0.8 times or less of distance L1b. If distance L1a is too short, the field plate 48a will not function. From this perspective, distance L1a can be 0.5 times or more of distance L1b. The difference between distance L1a and L1b is, for example, 50 nm or more, 100 nm or more, and 200 nm or more.

[0078] At least two of the structural examples 1 to 10 of FET13 may be used in combination. For example, if structural example 1 and structural example 2 of FET13 are used in combination, the thickness T31a of the buffer layer 32a of FET11 will be greater than the thickness T31b of the buffer layer 32b of FET13, and the thickness T31a of the nucleation layer 31a of FET11 will be smaller than the thickness T31b of the nucleation layer 31b of FET13.

[0079] [Example 1 of a semiconductor device] Figure 22 is a plan view showing Example 1 of a semiconductor device used in Embodiment 1. The thickness direction of the base 61 is the Z direction, the arrangement direction from leads 63a and 63b to 64a and 64b is the Y direction, and the direction intersecting the Z and Y directions is the X direction. As shown in Figure 22, in the semiconductor device 102, the package 60 comprises a base 61 and a frame 62. The base 61 is conductive at least on its upper surface and is, for example, a laminate of a copper layer and a molybdenum layer. The frame 62 is an inorganic insulating layer, for example, an alumina layer. Leads 63a and 63b are arranged in the X direction on the - direction side of the frame 62 in the Y direction. Leads 64a and 64b are provided on the + direction side of the frame 62 in the Y direction. Leads 63a, 63b, 64a and 64b are metal plates, for example, copper plates.

[0080] A capacitive component 75a and a semiconductor chip 70a are mounted on a base 61 between leads 63a and 64a. A capacitive component 75b and a semiconductor chip 70b are mounted on a base 61 between leads 63b and 64a. The semiconductor chip 70a comprises a substrate 71, an FET 11 provided on the substrate 71, and pads 72 and 73. The semiconductor chip 70b comprises a substrate 71, an FET 13 provided on the substrate 71, and pads 72 and 73. Electrodes (not shown) are provided on the underside of the substrate 71. The pads 72 and 73 and the electrodes on the underside of the substrate 71 are electrically connected to the gate electrode, drain electrode, and source electrode of the FETs 11 and 13, respectively. The electrodes on the underside of the substrate 71 are electrically connected to the base 61 and are short-circuited. The substrate 71 is, for example, a semiconductor substrate, and if the FETs 11 and 13 are GaN HEMTs, it is, for example, a silicon carbide substrate. The pads 72 and 73 and the electrodes on the underside of the substrate 71 are, for example, metal layers such as a gold layer or a copper layer.

[0081] Each of the capacitive components 75a and 75b comprises a substrate 76, an electrode 77 provided on the upper surface of the substrate 76, and an electrode (not shown) provided on the lower surface of the substrate 71. The substrate 76, the electrode 77 sandwiching the substrate 76, and the electrode on the lower surface of the substrate 76 form a capacitor. The electrode on the lower surface of the substrate 76 is electrically connected to the base 61 and short-circuited. The substrate 76 is a dielectric substrate, such as an aluminum oxide substrate or a barium titanate substrate. The electrode 77 and the electrode on the lower surface of the substrate 76 are metal layers, such as a gold layer or a copper layer.

[0082] Bonding wires 80a and 80b electrically connect leads 63a and 63b to electrodes 77 of capacitive components 75a and 75b, respectively. Bonding wire 81a electrically connects electrodes 77 of capacitive components 75a and 75b to pads 72 of semiconductor chips 70a and 70b, respectively. Bonding wires 82a and 82b electrically connect pads 73 of semiconductor chips 70a and 70b to leads 64a and 64b, respectively. Bonding wires 80a, 80b, 81a, 81b, 82a and 82b are metal wires, such as gold or aluminum wires. Bonding wires 80a, 81a and capacitive component 75a form a T-shaped circuit of the LCL, which is at least part of the matching circuit 20 in Figure 1. The bonding wires 80b, 81b and the capacitive component 75b form a T-shaped circuit of the LCL, which is at least part of the matching circuit 21 in Figure 1.

[0083] Signals S1 and S2 input from leads 63a and 63b reach pads 72 of semiconductor chips 70a and 70b, respectively, via capacitive components 75a and 75b. Signals S3 and S4 output from pads 73 of semiconductor chips 70a and 70b are output from leads 64a and 64b, respectively.

[0084] In the semiconductor device example, FETs 11 and 13 are mounted on different substrates 71. This allows for the use of structural examples 1 to 10 as appropriate for FET 13. As shown in amplifier D in Table 1, the difference between FETs 11 and 13 makes it possible to achieve both low distortion and high efficiency.

[0085] [Example of a semiconductor device 2] Figure 23 is a plan view showing Example 2 of a semiconductor device used in Embodiment 1. As shown in Figure 23, in semiconductor device 104, FETs 11 and 13 are provided on the same semiconductor chip 70. The other configurations are the same as in Example 1 of the semiconductor device and will not be described. In Example 2 of the semiconductor device, it is difficult to adopt a different structure for the nitride semiconductor layer 35b of FET 13 from the nitride semiconductor layer 35a of FET 11, as shown in Structure Examples 1 to 4 of FET 13. However, if the same structure as the nitride semiconductor layer 35a is adopted for the nitride semiconductor layer 35b, as shown in Structure Examples 5 to 10 of FET 13, it becomes easier to realize.

[0086] Examples 1 and 2 of the semiconductor device describe an example in which semiconductor chips 70a and 70b or 70 are mounted on a package 60. However, the semiconductor device may also be a module in which semiconductor chips 70a and 70b or 70 are mounted on a circuit in which at least a portion of the distributor 14, combiner 16, and matching circuits 20 to 23 are formed. Alternatively, the semiconductor device may be an MMIC (Monolithic Microwave Integrated Circuit) in which FETs 11 and 13 and at least a portion of the distributor 14, combiner 16, and matching circuits 20 to 23 are provided on a substrate 71.

[0087] Although a 2-way Doherty amplifier with one peak amplifier 12 was used as an example for the Doherty amplifier, the Doherty amplifier may also be an N-way amplifier circuit (N is 2 or more) with two or more peak amplifiers 12. If two or more peak amplifiers 12 are provided, at least one of the multiple peak amplifiers 12 should be a FET 13 structure example from structure example 1 to structure example 10.

[0088] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications are intended to be in the sense and scope equivalent to the claims. [Explanation of Symbols]

[0089] 10: Main amplifier 11 (1st FET), 13 (2nd FET): FET 12: Peak Amplifier 14:Distributor 16: Synthesizer 18: Impedance Converter 20, 21, 22, 23: matching circuit 30a (First substrate), 30b (Second substrate): Substrate 31a (first aluminum nitride layer), 31b (second aluminum nitride layer): nucleation layer 32a (First buffer layer, first gallium nitride buffer layer), 32b (Second buffer layer, second gallium nitride buffer layer), 37: Buffer layer 33a (first electron supply layer), 33b (second electron supply layer): electron supply layer 34a, 34b: Cap layer 35a (first nitride semiconductor layer), 35b (second nitride semiconductor layer): Nitride semiconductor layer 36: 2-dimensional electron gas 38: Recess 40a, 40b: Source electrodes 42a (first gate electrode), 42b (second gate electrode): gate electrode 44a (first drain electrode), 44b (second drain electrode): Drain electrodes 46a, 46b, 47a, 47b insulating layer 48a (First field plate), 48b (Second field plate): Field plate 50, 51, 54, 55: Dashed circles 52: Arrow 60: Package 61: Bass 62: Frame 63a, 63b, 64a, 64b: Lead 70, 70a, 70b: Semiconductor chips 72, 73: Pad 75a, 75b: Capacitive components 76: Circuit board 77: Electrode 80a, 80b, 81a, 81b, 82a, 82b: Bonding wires 100: Doherty Amplifier 102, 104: Semiconductor devices

Claims

1. A main amplifier comprising a first FET having a first nitride semiconductor layer and a first source electrode, a first gate electrode, and a first drain electrode provided on the first nitride semiconductor layer, amplifies a first signal distributed from an input signal. A second FET comprising a second nitride semiconductor layer and a second source electrode, a second gate electrode, and a second drain electrode provided on the second nitride semiconductor layer, and a peak amplifier that amplifies a second signal distributed from the input signal, Equipped with, A semiconductor device for a Doherty amplifier, wherein the first drain conductance of the first FET when a gate voltage obtained by adding a constant voltage from the pinch-off voltage and a constant drain voltage are applied is greater than the second drain conductance of the second FET when a gate voltage that allows a drain current equal to the drain current flowing through the first FET when the first drain conductance is measured and the constant drain voltage are applied.

2. The first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer. The second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer. The semiconductor device according to claim 1, wherein the first buffer layer is thicker than the second buffer layer.

3. The first nitride semiconductor layer comprises a first aluminum nitride layer provided on a first substrate, a first gallium nitride buffer layer provided on the first aluminum nitride layer, and a first electron supply layer provided on the first gallium nitride buffer layer. The second nitride semiconductor layer comprises a second aluminum nitride layer provided on a second substrate, a second gallium nitride buffer layer provided on the second aluminum nitride layer, and a second electron supply layer provided on the second gallium nitride buffer layer. The semiconductor device according to claim 1 or claim 2, wherein the first aluminum nitride layer is thinner than the second aluminum nitride layer.

4. The first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer. The second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer. The semiconductor device according to claim 1 or claim 2, wherein the distance between the first buffer layer and the first gate electrode in the thickness direction of the first nitride semiconductor layer is greater than the distance between the second buffer layer and the second gate electrode in the thickness direction of the second nitride semiconductor layer.

5. The first nitride semiconductor layer comprises a first buffer layer provided on a first substrate and a first electron supply layer provided on the first buffer layer. The second nitride semiconductor layer comprises a second buffer layer provided on a second substrate and a second electron supply layer provided on the second buffer layer. The semiconductor device according to claim 1 or claim 2, wherein the carbon concentration of the first buffer layer is lower than the carbon concentration of the second buffer layer.

6. The semiconductor device according to claim 1 or claim 2, wherein the gate length of the first gate electrode is smaller than the gate length of the second gate electrode.

7. The semiconductor device according to claim 1 or claim 2, wherein the first gate electrode overhangs at least toward the first drain electrode, the second gate electrode overhangs at least toward the second drain electrode, and the length of the overhang of the first gate electrode toward the first drain electrode is smaller than the length of the overhang of the second gate electrode toward the second drain electrode.

8. The first FET comprises a first field plate provided above the first nitride semiconductor layer between the first gate electrode and the first drain electrode, The second FET comprises a second field plate provided above the second nitride semiconductor layer between the second gate electrode and the second drain electrode, The semiconductor device according to claim 1 or claim 2, wherein the distance between the first nitride semiconductor layer and the first field plate in the thickness direction of the first nitride semiconductor layer is greater than the distance between the second nitride semiconductor layer and the second field plate in the thickness direction of the second nitride semiconductor layer.

9. The first FET comprises a first field plate provided above the first nitride semiconductor layer between the first gate electrode and the first drain electrode, The second FET comprises a second field plate provided above the second nitride semiconductor layer between the second gate electrode and the second drain electrode, The semiconductor device according to claim 1 or claim 2, wherein the distance between the end of the first gate electrode closest to the first drain electrode and the end of the first field plate closest to the first drain electrode is smaller than the distance between the end of the second gate electrode closest to the second drain electrode and the end of the second field plate closest to the second drain electrode.

10. A semiconductor device according to claim 1 or claim 2, A distributor that distributes the input signal into the first signal and the second signal, A combiner that combines the first signal amplified by the main amplifier and the second signal amplified by the peak amplifier, A Doherty amplifier equipped with this feature.

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