Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that enable more accurate measurement of the structure. [Solution] The semiconductor device according to this embodiment comprises a structure and a light-shielding portion. The light-shielding portion is provided at a measurement site for measuring the structure of the structure by irradiating it with measurement light, at a position on the side of the direction of propagation of the irradiated measurement light relative to the structure, and blocks the measurement light. The light-shielding portion has two or more first metal layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In the manufacturing process of semiconductor devices, as process quality control for film formation processes, CMP (Chemical Mechanical Polishing) processes, etching processes, etc., it is common to optically measure the film thickness of the insulating film and the thickness of the wiring layer at pre-installed measurement sites. However, in recent years, in semiconductor devices with complex structures typified by 3D flash memories, the spectrum may become complex due to an increase in spectral oscillation caused by interference of thick insulating films and reflected light from a large number of interface layers. The difficulty in creating measurement recipes and the increase in measurement time due to spectral complexity have become problems.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device and a method for manufacturing the same that can more appropriately measure the structure.

Means for Solving the Problems

[0005] The semiconductor device according to the present embodiment includes a structure and a light shielding portion. The light shielding portion is provided at a position on the traveling direction side of the measurement light to be irradiated, rather than the structure, at a measurement site for measuring the structure of the structure by irradiating the measurement light, and blocks the measurement light. The light shielding portion has two or more first metal layers.

Brief Description of the Drawings

[0006] [Figure 1] This is a cross-sectional view showing an example of the structure of a semiconductor device. [Figure 2] This is a cross-sectional view showing an example of the structure of a columnar section. [Figure 3] This is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 4A] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 4B] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 5A] This is a top view showing an example of the configuration of the light-shielding structure according to the first embodiment. [Figure 5B] This is a top view showing an example of the configuration of the light-shielding structure according to the first embodiment. [Figure 6] This is a top view showing an example of the configuration of the upper wiring according to the first embodiment. [Figure 7] This is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 8A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8B] This is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 8A. [Figure 9] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 10A] This is a top view showing an example of the configuration of the light-shielding structure according to the second embodiment. [Figure 10B] This is a top view showing an example of the configuration of the light-shielding structure according to the second embodiment. [Figure 10C] This is a top view showing an example of the configuration of the light-shielding structure according to the second embodiment. [Figure 11A] This is a top view showing an example of the configuration of a light-shielding structure according to the third embodiment. [Figure 11B] This is a top view showing an example of the configuration of a light-shielding structure according to the third embodiment. [Figure 11C] This is a top view showing an example of the configuration of a light-shielding structure according to the third embodiment. [Figure 12] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fourth embodiment. [Figure 13A] It is a cross-sectional view showing an example of the configuration of a light-shielding structure according to the fourth embodiment. [Figure 13B] It is a cross-sectional view showing an example of the configuration of a light-shielding structure according to the fourth embodiment. [Figure 14] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fifth embodiment. [Figure 15] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fifth embodiment. [Figure 16] It is a top view showing an example of the configuration of a light-shielding structure according to the seventh embodiment. [Figure 17] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the eighth embodiment. [Figure 18A] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment. [Figure 18B] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 18A. [Figure 19] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the tenth embodiment. [Figure 20] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to the eleventh embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with respect to the previous drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing an example of the structure of a semiconductor device. The semiconductor device in Figure 1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together. Array chip 1 is an example of a first chip, and circuit chip 2 is an example of a second chip.

[0009] The array chip 1 comprises a memory cell array 11 containing multiple memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films.

[0010] Circuit chip 2 is located beneath array chip 1. The symbol S indicates the bonding surface between array chip 1 and circuit chip 2. Bonding surface S is an example of a first bonding surface. Circuit chip 2 comprises an interlayer insulating film 14 and a substrate 15 beneath the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0011] Figure 1 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 15, and the Z direction, which is perpendicular to the surface of the substrate 15. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0012] The array chip 1 comprises multiple word lines WL and source lines SL as electrode layers within the memory cell array 11. Figure 1 shows the stepped structure 21 of the memory cell array 11. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 24 and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer and a second layer SL2 which is a metal layer.

[0013] The circuit chip 2 comprises a plurality of transistors 31. Each transistor 31 comprises a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 15. The circuit chip 2 also comprises a plurality of contact plugs 33 provided on the gate electrode 32, source diffusion layer, or drain diffusion layer of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and containing a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and containing a plurality of wires.

[0014] The circuit chip 2 further comprises a wiring layer 36 provided on the wiring layer 35 and containing multiple wirings, multiple via plugs 37 provided on the wiring layer 36, and multiple metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit is composed of transistors 31 and the like and is electrically connected to the metal pads 38.

[0015] The array chip 1 comprises a plurality of metal pads 41 provided on a metal pad 38, and a plurality of via plugs 42 provided on the metal pads 41. The array chip 1 also comprises a wiring layer 43 provided on these via plugs 42 and containing a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and containing a plurality of wirings. The metal pads 41 are, for example, a Cu layer or an Al layer.

[0016] The array chip 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on these via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer and function as external connection pads (bonding pads) of the semiconductor device shown in Figure 1. The passivation film 47 is, for example, an insulating film such as a silicon oxide film and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or other devices via this opening P using bonding wires, solder balls, metal bumps, etc.

[0017] Figure 2 is a cross-sectional view showing an example of the structure of the columnar section CL.

[0018] As shown in Figure 2, the memory cell array 11 comprises a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on an interlayer insulating film 13 (Figure 1). The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films.

[0019] The columnar portion CL includes, in order, a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, a silicon nitride film and is formed on the side surfaces of the word line WL and the insulating layer 51 via the block insulating film 52. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer and is formed on the side surfaces of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, a silicon oxide film or a metal insulating film.

[0020] Figure 3 is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. Figure 3 shows a portion of the wafer before the array chip 1 or circuit chip 2 is separated into individual chips. The dimensional values ​​such as height, thickness, and width described below are examples only.

[0021] The device region A1 shown in Figure 3 is provided with a configuration including semiconductor elements such as the memory cell array 11 and transistor 31, as shown in Figure 1. A measurement site ST is provided on the scribe line A2. The measurement site ST is the area where optical measurement techniques such as the OCD (Optical Critical Dimension) method, which will be explained later, are performed. The scribe line A2 is provided with a configuration similar to that provided on the device region A1.

[0022] The device region A1 is divided by a scribe line A2 with a width of 70 μm. A measurement site ST with sides of 50 μm is located within the scribe line A2. In this embodiment, the entire measurement site ST constitutes the measurement area. The measurement area is the area within the measurement site ST where measurements are actually taken, and may vary depending on the measurement conditions, etc.

[0023] In this embodiment, the measurement site ST is preferably located on the scribe line A2 in order to effectively utilize the device area A1. Even if the measurement site ST is located on the scribe line A2, by installing a light-shielding structure, a complex structure that mimics the device area A1 can be created as an underlying structure in the measurement area, thereby improving process control accuracy.

[0024] Figures 4A and 4B are cross-sectional views showing an example of the configuration of a semiconductor device according to the first embodiment.

[0025] Figure 4A shows a cross-sectional view of the semiconductor device at the measurement site ST.

[0026] A silicon oxide (SiO2) film is formed as an insulating film 62 on a substrate 61 (for example, a semiconductor substrate such as a silicon substrate). Multiple lower wiring layers 65 are formed inside the insulating film 62, each composed of a barrier metal film 63 containing titanium nitride (TiN) and a conductive member 64 containing tungsten (W). A first light-shielding layer 68 with a height of 100 nm is formed above the lower wiring layers 65, consisting of a barrier metal film 66 containing titanium nitride (TiN) and a wiring member 67 containing copper (Cu). A silicon carbide nitride (SiCN) film with a thickness of 50 nm is formed above the first light-shielding layer 68, as a first cap film 69. A silicon oxide (SiO2) film is formed above the first cap film 69, as an insulating film 70. A second light-shielding layer 73 with a height of 160 nm is formed inside the insulating film 70, consisting of a barrier metal film 71 containing titanium nitride (TiN) and a wiring member 72 containing copper (Cu). A light-shielding structure 74 is formed by a first light-shielding layer 68 and a second light-shielding layer 73, and is arranged so that either the first light-shielding layer 68 or the second light-shielding layer 73 is present across the entire measurement area when viewed from above. A silicon nitride (SiCN) film with a thickness of 50 nm is formed on the upper part of the second light-shielding layer 73 as a second cap film 75. A silicon oxide (SiO2) film with a thickness of 300 nm is formed on the upper part of the upper insulating film 76 as an upper insulating film 76. An upper wiring 79 with a height of 200 nm is formed inside the upper insulating film 76, consisting of a barrier metal film 77 containing titanium nitride (TiN) and a wiring member 78 containing copper (Cu). The upper insulating film 76 and the upper wiring 79 constitute the upper structure 80 to be measured.

[0027] Figure 4B shows a cross-sectional view of a semiconductor device in device region A1. Figure 4B shows, for example, a cross-sectional view of a circuit chip C2.

[0028] In the device region A1 shown in Figure 4B, a transistor 31, contact plugs, via plugs, etc., are further provided. The substrate 61 also has an element isolation region 611.

[0029] The lower layer wiring 65 may be provided in one layer or in three or more layers. Furthermore, the transistor 31 and the element isolation region 611 may be provided below the lower layer wiring 65.

[0030] As shown in Figures 4A and 4B, the height (position) and material of the lower wiring 65, first light-shielding layer 68, second light-shielding layer 73, and upper wiring 79 are the same between the device region A1 and the scribe line A2.

[0031] Figures 5A and 5B are top views showing an example of the configuration of the light-shielding structure 74 according to the first embodiment. Figures 5A and 5B show the layout of the first light-shielding layer 68 and the second light-shielding layer 73, respectively.

[0032] The first light-shielding layer 68 is composed of a 160 nm wide line pattern (line and space) installed in the X direction with a repeating pitch P1 of 240 nm, separated by a space of 80 nm width. Similarly, the second light-shielding layer 73 is composed of a 160 nm wide line pattern installed in the X direction with a repeating pitch P2 of 240 nm, separated by a space of 80 nm width. In order to block incident light with the light-shielding structure 74, the first light-shielding layer 68 or the second light-shielding layer 73 is arranged to cover the entire measurement area. That is, the first light-shielding layer 68 and the second light-shielding layer 73 are arranged alternately and without gaps when viewed from the Z direction.

[0033] Figure 6 is a top view showing an example of the configuration of the upper wiring 79 according to the first embodiment.

[0034] The upper layer wiring 79 consists of a 480nm wide line pattern installed in the X direction with a repeating pitch P3 of 960nm, separated by a 480nm wide space.

[0035] The first light-shielding layer 68, the second light-shielding layer 73, and the upper wiring 79 form a repeating structure in the X direction at a pitch of 960 nm, which is the least common multiple of the repeating pitches of each layer.

[0036] Figure 7 is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. Figure 7 shows a schematic diagram of the upper layer structure 80 of the measurement area when it is optically measured by the OCD method. In the OCD method, the spectrum of the reflected light of the irradiated light is acquired, and the wiring depth and structural pattern can be measured from the spectrum. The OCD method is performed at the measurement site ST.

[0037] Incident light (not shown) irradiated from above by the light source of the measuring instrument is reflected by each layer interface in the measurement area. The shape of the upper layer structure is measured by detecting the reflected spectrum with the sensor of the measuring instrument. The reflected light consists of a first reflected light RL1 reflected from the upper surface of the upper layer wiring 79, a second reflected light RL2 reflected from the upper surface of the second cap film 75, a third reflected light RL3 reflected from the upper surface of the second light-shielding layer 73, a fourth reflected light RL4 reflected from the upper surface of the first cap film 69, and a fifth reflected light RL5 reflected from the upper surface of the first light-shielding layer 68. The incident light is blocked by the light-shielding structure 74, which consists of the first light-shielding layer 68 and the second light-shielding layer 73, and does not reach the lower layer wiring 65 or the substrate 61. This prevents the reflection spectrum from becoming complicated due to reflection from the lower layer wiring 65 or the substrate 61, making it easier to create measurement recipes and shortening measurement time.

[0038] In other words, the light-shielding structure 74 (light-shielding portion) is positioned on the direction of propagation of the irradiated measurement light, rather than on the upper layer structure 80, at the measurement site ST for measuring the structure of the upper layer structure 80 (structure) by irradiation with measurement light. More specifically, the light-shielding structure 74 is positioned on the direction of propagation of the irradiated measurement light, rather than on the upper layer wiring 79, at the measurement site ST. Furthermore, the light-shielding structure 74 has two or more light-shielding layers (metal layers). More specifically, the first light-shielding layer 68 and the second light-shielding layer 73 are arranged alternately to block the measurement light and are arranged without gaps when viewed from the Z direction. As a result, the light-shielding structure 74 is positioned to cover the entire measurement site ST.

[0039] Furthermore, the light-shielding structure 74 has two or more light-shielding layers. This reduces the risk of dishing and film peeling. If the light-shielding structure 74 has one light-shielding layer covering the entire measurement area, a large metal area is formed, which increases the risk of dishing and film peeling. In contrast, if the light-shielding structure 74 has two or more light-shielding layers, the occupancy rate of the metal area for each layer can be reduced, thereby reducing the risk of dishing and film peeling.

[0040] Next, we will explain the manufacturing method for semiconductor devices.

[0041] Figures 8A and 8B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0042] Figure 8A is a cross-sectional view of the measurement area within the measurement site ST installed on the semiconductor device before the CMP process.

[0043] A wiring groove 76a with a depth of 250 nm is formed on the upper part of the upper insulating film 76. A barrier metal film 77 containing titanium nitride (TiN) is formed on the upper part of the upper insulating film 76 with a depth of 10 nm, and a wiring member 78 containing copper (Cu) is formed with a depth of 500 nm.

[0044] Figure 8B is a cross-sectional view of the measurement area of ​​the semiconductor device after the CMP process.

[0045] In the CMP process, a barrier metal film 77 containing titanium nitride (TiN) and a wiring member 78 containing copper (Cu), formed on the upper surface of the upper insulating film 76, are removed by polishing. Furthermore, a portion of the upper insulating film 76 is removed to form an upper wiring 79 with a height of 200 nm. To control the finished shape of the upper wiring 79 and the upper insulating film 76, the measurement area within the measurement site ST is measured optically using the OCD method.

[0046] By blocking reflected light from the lower layer wiring 65 and substrate 61 with the light-shielding structure 74, the complexity of the reflection spectrum can be prevented. This allows for more accurate measurement of the structure of the upper layer structure 80 used for post-CMP management. As a result, measurement recipe creation can be simplified and measurement time can be reduced.

[0047] The OCD method may be performed within the CMP apparatus using measuring devices installed within the apparatus, or it may be performed using different measuring devices. Furthermore, the OCD method has been described in the context of being performed after CMP. However, since the OCD method measures the shape before the CMP process, it may also be performed before the CMP process.

[0048] This section describes the use of the OCD method as an optical measurement technique. In addition to the OCD method, other optical measurement techniques such as optical interferometry or spectroscopic ellipsometry may also be used.

[0049] As described above, according to the first embodiment, the light-shielding structure 74 is provided at the measurement site ST at a position on the direction of propagation of the irradiated measurement light, relative to the upper layer structure 80, and blocks the measurement light. By installing a light-shielding layer formed of multiple patterned metal layers at the measurement site ST, it is possible to prevent light from penetrating to the layer below the light-shielding layer. This prevents spectral complexity caused by reflected light from the lower layer structure of the upper layer structure 80, such as the lower layer wiring 65, and makes it possible to simplify the creation of measurement recipes and shorten the measurement time.

[0050] Furthermore, the light-shielding structure 74 has two or more light-shielding layers. This reduces the risk of dishing and film peeling.

[0051] In order to block incident light with the light-shielding structure 74, it is desirable to design the light-shielding structure 74 such that a metal layer of 80 nm or more exists throughout the entire measurement area (light-shielding structure 74). That is, by making the total thickness of the metal layers included in the light-shielding structure 74 at any position in the measurement area 80 nm or more, incident light can be blocked. When viewed from the Z direction, the first light-shielding layer 68 and the second light-shielding layer 73 have overlapping and non-overlapping positions. Thus, at positions where the number of overlapping metal layers is small when viewed from the Z direction, the total thickness of the metal layers becomes smaller compared to positions where the number of overlapping layers is large. However, at any position in the measurement area, even at positions where the number of overlapping metal layers is small, the total thickness of the metal layers is 80 nm or more. The thickness of 80 nm is an example of a predetermined thickness and may be changed, for example, by the optical measurement method or its conditions.

[0052] The light-shielding structure 74 may be made of any metal, but in order to simplify the manufacturing process of semiconductor devices, it is preferable that the light-shielding structure 74 be made of a metal containing at least one of Cu, W, Mo, Co, Al, Ru, Ti, and Ta, which are used as wiring materials.

[0053] To measure more efficiently and simplify the measurement model, it is desirable that each layer of the metal layer pattern constituting the light-shielding structure 74 be formed with a repeating pattern. While each layer of the metal layer pattern constituting the light-shielding structure 74 may be composed of a shape pattern other than a line pattern, in that case, it is desirable that it be formed with a repeating pattern in both the X and Y directions. Each layer of the metal layer pattern constituting the light-shielding structure 74 may be formed with a different pattern, but it is desirable to design it so that the least common multiple of the pitches of the repeating patterns of each layer is small. More specifically, it is desirable that the least common multiple of the pitches of the repeating patterns of each layer is 4 times or less the largest pitch among the repeating patterns of each layer. Furthermore, it is desirable that the least common multiple of the pitches of the repeating patterns of each layer be 5 μm or less. Note that the value of the least common multiple may be changed according to the size of the irradiation range of the measurement light (e.g., 20 μm).

[0054] As will be described in later embodiments, the upper layer structure 80 may consist only of an upper insulating film 76 that does not include upper wiring 79. Alternatively, it may be formed of multiple stacked insulating films or multiple stacked upper wiring 79.

[0055] When forming upper wiring 79 on the upper structure 80, it is desirable that each layer forming the upper wiring 79 be formed with a repeating pattern in order to simplify the measurement model for more efficient measurement. Each layer forming the upper wiring 79 may be composed of a shape pattern other than a line pattern, but in that case, it is desirable that it be formed with a repeating pattern in both the X and Y directions. That is, it is desirable that each layer of the metal layer pattern constituting the light-shielding structure 74 and each layer of the metal layer pattern constituting the upper wiring 79 be formed with a repeating pattern. Each layer of the metal layer pattern constituting the upper wiring 79 may be formed with a different pattern, but it is desirable to design it so that the least common multiple of the pitches of the repeating patterns of each layer of the metal layer pattern constituting the upper wiring 79 and each layer of the metal layer pattern constituting the light-shielding structure 74 is small. More specifically, it is desirable that the least common multiple of the pitches of the repeating patterns of each layer be 4 times or less the largest pitch of the repeating patterns of each layer. Also, it is desirable that the least common multiple of the pitches of the repeating patterns of each layer be 5 μm or less. The least common multiple may be changed depending on the size of the irradiation area of ​​the measurement light (e.g., 20 μm).

[0056] The effect of the light-shielding structure 74 is particularly effective when the underlying structure has a complex reflection pattern. For example, when the underlying structure has a metal wiring structure such as the lower wiring 65, the reflected light tends to become complex due to reflection from the upper surface of the metal wiring. By installing the light-shielding structure 74, the complexity of the reflected light can be prevented.

[0057] The measurement sites ST are located at multiple positions on the wafer. As will be described in later embodiments, at least one configuration of the lower layer structure, light-shielding structure 74, and upper layer structure 80 may differ depending on the location of the measurement sites ST.

[0058] (Second Embodiment) Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the second embodiment. The second embodiment differs from the first embodiment in that the light-shielding structure 74 has a three-layer structure.

[0059] The light-shielding structure 74 is composed of a first light-shielding layer 68 with a height of 80 nm, a second light-shielding layer 73 with a height of 80 nm, and a third light-shielding layer 81 with a height of 80 nm, which is formed on top of the first light-shielding layer 74 and consists of a barrier metal film containing titanium nitride (TiN) and a wiring member containing copper (Cu). A silicon carbide nitride (SiCN) film with a thickness of 50 nm is formed on top of the third light-shielding layer 81 as a third cap film 82. The upper layer structure 80 to be measured is formed on top of the third cap film 82.

[0060] Figures 10A to 10C are top views showing an example of the configuration of the light-shielding structure 74 according to the second embodiment. Each of Figures 10A to 10C shows the layout of the first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81.

[0061] The first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81 are each formed of a 100 nm wide line pattern installed in the X direction at a repeating pitch of 240 nm, with a space of 140 nm width in between.

[0062] In order to block incident light with the light-shielding structure 74, the first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81 are arranged so that they are present throughout the entire measurement area. That is, the first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81 are arranged without any gaps when viewed from the Z direction.

[0063] The light-shielding structure 74 may have four or more light-shielding layers.

[0064] As in the second embodiment, the light-shielding structure 74 may have a three-layer structure. In this case as well, the same effects as in the first embodiment can be obtained.

[0065] (Third embodiment) Figures 11A to 11C are top views showing an example of the configuration of the light-shielding structure 74 according to the third embodiment. Each of Figures 11A to 11C shows the layout of the first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81. In the third embodiment, the pattern shape of the light-shielding layers is different from that of the second embodiment.

[0066] The first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81 are formed in a repeating pattern with a repeating pitch P4 of 240 nm in the X direction and a repeating pitch P5 of 240 nm in the Y direction.

[0067] In the third embodiment, as in the second embodiment, the first light-shielding layer 68, the second light-shielding layer 73, and the third light-shielding layer 81 are arranged to be present throughout the entire measurement area in order to block incident light with the light-shielding structure 74.

[0068] As in the third embodiment, the pattern shape of the light-shielding layer may be changed. In this case as well, the same effects as in the second embodiment can be obtained.

[0069] (Fourth Embodiment) Figure 12 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that the material of the first light-shielding layer 68 and the material of the second light-shielding layer 73 are different.

[0070] The light-shielding layers, consisting of two or more layers, include two or more different metal materials for each layer. The materials of the first light-shielding layer 68 and the second light-shielding layer 73 may be changed depending on the materials of the metal layers in the device region A1.

[0071] The light-shielding structure 74 is composed of a first light-shielding layer 68 with a height of 100 nm, formed from a barrier metal film 66a containing tungsten nitride (WN) and a wiring member 67a containing tungsten (W), and a second light-shielding layer 73 with a height of 160 nm, composed from a barrier metal film 71 containing titanium nitride (TiN) and a wiring member 72 containing copper (Cu). Depending on the material of the first light-shielding layer 68, a first cap film 69 to prevent the diffusion of copper (Cu) may not be provided.

[0072] Figures 13A and 13B are cross-sectional views showing an example of the configuration of the light-shielding structure 74 according to the fourth embodiment. Figures 13A and 13B show the layout of the first light-shielding layer 68 and the second light-shielding layer 73, respectively.

[0073] The first light-shielding layer 68 is formed with a line pattern 140 nm wide, arranged at a repeating pitch of 240 nm in the X direction with a space of 100 nm wide in between, and the second light-shielding layer 73 is formed with a line pattern 180 nm wide, arranged at a repeating pitch of 240 nm in the X direction with a space of 60 nm wide in between. In other words, the wiring width of the first light-shielding layer 68 and the wiring width of the second light-shielding layer 73 may be different.

[0074] As in the fourth embodiment, the material of the first light-shielding layer 68 and the material of the second light-shielding layer 73 may be different. In this case as well, the same effects as in the first embodiment can be obtained.

[0075] (Fifth embodiment) Figure 14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the fifth embodiment. The fifth embodiment differs from the first embodiment in that the upper layer wiring 79 is not provided.

[0076] The upper layer structure 80 consists only of an upper insulating film 76, which does not include the upper layer wiring 79.

[0077] As in the fifth embodiment, the upper wiring 79 does not need to be provided. In this case as well, the same effects as in the first embodiment can be obtained.

[0078] (Sixth Embodiment) Figure 15 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the sixth embodiment. In the sixth embodiment, the configuration of the upper layer structure 80 is different from that of the first embodiment.

[0079] The upper structure 80 consists of a first upper insulating film 83 formed of a silicon oxide (SiO2) film with a thickness of 140 nm, a first upper wiring 84 with a height of 50 nm composed of a barrier metal film containing titanium nitride (TiN) and a wiring member containing copper (Cu), a fourth cap film 85 formed of a silicon nitride (SiCN) film with a thickness of 50 nm, a second upper insulating film 86 formed of a silicon oxide (SiO2) film with a thickness of 110 nm, and a second upper wiring 87 with a height of 50 nm composed of a barrier metal film containing titanium nitride (TiN) and a wiring member containing copper (Cu).

[0080] As in the sixth embodiment, the configuration of the upper structure 80 may be changed. In this case as well, the same effects as in the first embodiment can be obtained.

[0081] (Seventh Embodiment) Figure 16 is a top view showing an example of the configuration of the light-shielding structure 74 according to the seventh embodiment. The fifth embodiment differs from the first embodiment in that the upper layer wiring 79 is arranged in a pad shape.

[0082] The upper layer wiring 79 consists of a 480nm wide square pattern installed with a repeating pitch P6 of 960nm in the X direction and a repeating pitch P7 of 960nm in the Y direction, separated by a 480nm wide space.

[0083] Note that the shape of the upper wiring 79 is not limited to a square.

[0084] As in the seventh embodiment, the upper wiring 79 may be arranged in a pad-like configuration. In this case as well, the same effects as in the first embodiment can be obtained.

[0085] (Eighth embodiment) Figure 17 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the eighth embodiment. The eighth embodiment differs from the first embodiment in that a laminate is provided below the light-shielding structure 74.

[0086] The stacked structure 90 is provided at the same height as the memory cell array 11 in the device region A1.

[0087] A laminate 90 is formed on a substrate 61, consisting of 64 alternating layers of insulating film 88 containing 20 nm silicon oxide (SiO2) and insulating film 89 containing 20 nm silicon nitride (Si3N4), for a total of 128 layers. A light-shielding structure 74 and an upper layer structure 80 are formed on top of the laminate 90.

[0088] The effect of the light-shielding structure 74 is particularly effective when the underlying structure has a complex reflection pattern. For example, in a structure with multiple light-transmitting films stacked on top of each other, the reflected light tends to become complex due to reflection from multiple stacking interfaces. By installing the light-shielding structure 74, the complexity of the reflected light can be prevented.

[0089] In the manufacturing process of three-dimensional flash memory, it is necessary to stack more than 50 layers of light-transmitting films to form a memory cell array 11. In addition, it is necessary to deposit a light-transmitting film of 2.5 μm or more in thickness to fill the spaces between the memory cell array 11 structures. 2.5 μm is an example of a predetermined thickness. The installation of a light-shielding structure 74 is particularly effective in these structures.

[0090] The light-shielding structure 74 prevents spectral complexity caused by reflected light from multiple interfaces in the lower layer structure of the upper layer structure 80, thereby simplifying the creation of measurement recipes and shortening measurement time.

[0091] As in the eighth embodiment, a laminate may be provided below the light-shielding structure 74. In this case as well, the same effects as in the first embodiment can be obtained.

[0092] (Ninth Embodiment) Figures 18A and 18B are cross-sectional views showing an example of a semiconductor device manufacturing method according to the ninth embodiment. The ninth embodiment differs from the eighth embodiment in that the upper layer wiring 79 is not provided.

[0093] Figure 18A is a cross-sectional view of the measurement area within the measurement site ST installed on the semiconductor device before the CMP process.

[0094] The number of layers in the stacked structure 90 is the same as the number of layers in the memory cell array of the 3D flash memory formed within the device region A1. The upper layer structure 80 to be measured does not have upper layer wiring 79 formed on it, and is composed only of an upper layer insulating film 76 with a thickness of 500 nm. To measure the thickness of the upper layer insulating film 76 before the CMP process, the measurement area within the measurement site ST is measured optically using the OCD method.

[0095] Figure 18B is a cross-sectional view of the measurement area of ​​the semiconductor device after the CMP process.

[0096] The upper insulating film 76 is polished using the CMP process until its thickness reaches 300 nm. To measure the thickness of the upper insulating film 76 after the CMP process, the measurement area within the measurement site ST is measured optically using the OCD method. From the thickness of the upper insulating film 76 before and after the CMP process, the amount of upper insulating film 76 removed per polishing time is calculated and managed as a process control item.

[0097] Furthermore, measurement of the measurement area within the measurement site ST before the CMP process is not necessarily required.

[0098] As in the ninth embodiment, the upper wiring 79 does not need to be provided. In this case as well, the same effects as in the eighth embodiment can be obtained.

[0099] (Tenth embodiment) Figure 19 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the tenth embodiment. The tenth embodiment differs from the first embodiment in that a light-transmitting film is provided below the light-shielding structure 74.

[0100] A 3.4 μm thick film 91 containing silicon dioxide (SiO2) is formed on the substrate 61. A light-shielding structure 74 and an upper layer structure 80 are formed on top of the film 91.

[0101] The film 91 is a light-transmitting film.

[0102] The effect of the light-shielding structure 74 is particularly effective when a thick light-transmitting film is present in the underlying structure. When a thick light-transmitting film is present in the underlying structure, numerous amplitude peaks are generated in the reflection spectrum, complicating spectral analysis and easily leading to increased measurement time and erroneous measurements. By installing the light-shielding structure 74, the generation of amplitude peaks can be reduced.

[0103] The light-shielding structure 74 prevents spectral complexity caused by interference from the underlying structure of the upper layer structure 80, such as a thick light-transmitting film, thereby simplifying the creation of measurement recipes and shortening measurement time.

[0104] As in the tenth embodiment, a light-transmitting film may be provided below the light-shielding structure 74. In this case as well, the same effects as in the first embodiment can be obtained.

[0105] (11th embodiment) Figure 20 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the 11th embodiment. The 11th embodiment differs from the first embodiment in that the first light-shielding layer 68 and the second light-shielding layer 73 are each divided into two layers and arranged accordingly.

[0106] A silicon oxide (SiO2) film is formed as an insulating film 62 on a substrate 61 (for example, a semiconductor substrate such as a silicon substrate). Multiple lower wiring layers 65 are formed inside the insulating film 62, each composed of a barrier metal film 63 containing titanium nitride (TiN) and a conductive member 64 containing tungsten (W). A first divided light-shielding layer 68a with a height of 50 nm is formed on the upper part of the lower wiring layers 65, composed of a barrier metal film 66 containing titanium nitride (TiN) and a wiring member 67 containing copper (Cu). A silicon carbide nitride (SiCN) film with a thickness of 50 nm is formed on the upper part of the first divided light-shielding layer 68a as a first cap film 69. A silicon oxide (SiO2) film is formed on the upper part of the first cap film 69 as an insulating film 70a. A second divided light-shielding layer 68b with a height of 50 nm is formed inside the insulating film 70a, composed of a barrier metal film 66 containing titanium nitride (TiN) and a wiring member 67 containing copper (Cu). A silicon nitride (SiCN) carbide film with a thickness of 50 nm is formed on the upper part of the second divided light-shielding layer 68b as the first cap film 69. A silicon oxide (SiO2) film is formed on the upper part of the first cap film 69 as the insulating film 70b. Inside the insulating film 70b, a third divided light-shielding layer 73a with a height of 50 nm is formed, composed of a barrier metal film 71 containing titanium nitride (TiN) and a wiring member 72 containing copper (Cu). A silicon nitride (SiCN) carbide film with a thickness of 50 nm is formed on the upper part of the third divided light-shielding layer 73a as the second cap film 75. A silicon oxide (SiO2) film is formed on the upper part of the second cap film 75 as the insulating film 70c. Inside the insulating film 70c, a fourth divided light-shielding layer 73b with a height of 50 nm is formed, composed of a barrier metal film 71 containing titanium nitride (TiN) and a wiring member 72 containing copper (Cu). The light-shielding structure 74 is composed of a first light-shielding layer 68a, a second light-shielding layer 68b, a third light-shielding layer 73a, and a fourth light-shielding layer 73b, and is arranged so that one of the first light-shielding layer 68a, the second light-shielding layer 68b, the third light-shielding layer 73a, or the fourth light-shielding layer 73b is present across the entire measurement area when viewed from above. A silicon carbide nitride (SiCN) film with a thickness of 50 nm is formed on the upper part of the fourth light-shielding layer 73b as a second cap film 75.A silicon oxide (SiO2) film with a thickness of 300 nm is formed on the upper part of the second cap film 75 as an upper insulating film 76. Inside the upper insulating film 76, an upper wiring 79 with a height of 200 nm is formed, consisting of a barrier metal film 77 containing titanium nitride (TiN) and a wiring member 78 containing copper (Cu). The upper insulating film 76 and the upper wiring 79 constitute the upper structure 80 to be measured.

[0107] The thicknesses of the first, second, third, and fourth light-shielding layers 68a, 68b, 73a, and 73b are all less than 80 nm. However, the sum of the thicknesses of the metal layers at any given position in the measurement area is 80 nm or more. This is because the minimum number of overlapping metal layers viewed from the Z direction is two. Thus, multiple relatively thin metal layers may be provided so that the sum of the thicknesses of the metal layers at any given position in the measurement area is 80 nm or more.

[0108] Note that the division of the first light-shielding layer 68 and the second light-shielding layer 73 into two parts is just one example, and the number of divisions is not limited to this. Also, the total number of metal layers is not limited to four.

[0109] As in the 11th embodiment, the first light-shielding layer 68 and the second light-shielding layer 73 may each be divided into two layers and arranged accordingly. In this case as well, the same effects as in the first embodiment can be obtained.

[0110] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0111] 11 Memory cell array, 51 Insulating layer, 61 Substrate, 65 Lower wiring, 68 First light-shielding layer, 73 Second light-shielding layer, 74 Light-shielding structure, 79 Upper wiring, 80 Upper structure, 81 Third light-shielding layer, 90 Laminate, 91 Film, A1 Device area, A2 Scribe line, CL Columnar section, WL Word line, ST Measurement site

Claims

1. Structures and In a measurement site for measuring the structure of the structure by irradiating it with measurement light, a light-shielding portion is provided at a position on the side of the direction of propagation of the irradiated measurement light relative to the structure, and blocks the measurement light. Equipped with, The light-shielding portion is a semiconductor device having two or more first metal layers.

2. The semiconductor device according to claim 1, wherein the total thickness of the two or more first metal layers is 80 nm or more over the entire area of ​​the light-shielding portion within the measurement site.

3. The semiconductor device according to claim 1, wherein the two or more first metal layers include at least one of Cu, W, Mo, Co, Al, Ru, Ti, and Ta.

4. The substrate further comprises the above structure and the light-shielding portion, The semiconductor device according to claim 1, wherein each of the two or more first metal layers has a repeating pattern in either or both of a first direction and a second direction that are substantially parallel to the substrate and perpendicular to each other.

5. The semiconductor device according to claim 4, wherein the least common multiple of the pitches of the repeating patterns of the two or more first metal layers is four times or less the largest pitch.

6. The semiconductor device according to claim 4, wherein the least common multiple of the pitches of the repeating patterns of the two or more first metal layers is 5 μm or less.

7. The aforementioned structure has a second metal layer having a predetermined pattern, The semiconductor device according to claim 1, wherein the light-shielding portion is provided at a position on the side of the direction of propagation of the irradiated measurement light, relative to the second metal layer.

8. The substrate further comprises the above structure and the light-shielding portion, The semiconductor device according to claim 7, wherein each of the two or more first metal layers and the second metal layer has a repeating pattern in either or both of a first direction and a second direction that are substantially parallel to the substrate and perpendicular to each other.

9. The semiconductor device according to claim 8, wherein the least common multiple of the pitches of the repeating patterns of each of the two or more first metal layers and the second metal layer is four times or less the largest pitch.

10. The semiconductor device according to claim 8, wherein the least common multiple of the pitches of the repeating patterns of each of the two or more first metal layers and the second metal layer is 5 μm or less.

11. A substrate on which the above structure and the light-shielding portion are provided, The semiconductor device according to claim 1, further comprising a film provided between the light-shielding portion and the substrate, having a thickness of 2.5 μm or more and being light-transmitting.

12. A substrate on which the above structure and the light-shielding portion are provided, The semiconductor device according to claim 1, further comprising a laminate provided between the light-shielding portion and the substrate, wherein 50 or more layers of light-transmitting films are stacked.

13. A substrate on which the above structure and the light-shielding portion are provided, The semiconductor device according to claim 1, further comprising at least one third metal layer provided between the light-shielding portion and the substrate.

14. The semiconductor device according to claim 1, wherein the measurement site is located on the scribe line.

15. The device further comprises a semiconductor element located in a device region different from the aforementioned measurement site, The aforementioned semiconductor device is A memory cell array comprising multiple conductive layers and multiple insulating layers stacked alternately, Multiple columnar portions penetrating the memory cell array, A semiconductor device according to claim 1, having the following features.

16. The semiconductor device according to claim 1, further comprising two or more metal layers in a device region different from the measurement site, each of which is the same height and material as the two or more first metal layers in the measurement site.

17. The semiconductor device according to claim 1, wherein the two or more first metal layers each contain two or more different metal materials.

18. A method for manufacturing a semiconductor device comprising: a structure; and a light-shielding portion having two or more first metal layers, provided at a measurement site for measuring the structure of the structure by irradiating it with measurement light, at a position on the side of the direction of propagation of the irradiated measurement light relative to the structure; The structure of the structure at the measurement site is measured. A method for manufacturing a semiconductor device, comprising the following:

19. The method for manufacturing a semiconductor device according to claim 18, wherein measuring the structure of the said structure includes measuring the structure of the said structure by optical interferometry, spectroscopic ellipsometry, or OCD (Optical Critical Dimension) method.

20. Before measuring the structure of the aforementioned structure, The aforementioned structure is polished. It further comprises, Before measuring the structure of the aforementioned structure, The structure of the aforementioned structure before polishing was measured, The aforementioned structure is polished. A method for manufacturing a semiconductor device according to claim 18, further comprising the above.

21. The semiconductor device further comprises a semiconductor element located in a device region different from the measurement site, The aforementioned semiconductor device is A memory cell array comprising multiple conductive layers and multiple insulating layers stacked alternately, Multiple columnar portions penetrating the memory cell array, A method for manufacturing a semiconductor device according to claim 18, comprising:

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