Photoelectric mixed galvanizing system

Abstract

To provide an optical-electric mixed-signal device having an optical connection structure with high connectivity reliability. [Solution] The optical-electric mixed-signal device comprises a first wiring board, a second wiring board facing a first region of the first wiring board and electrically connected to the first wiring board via a connecting member arranged in the first region, a semiconductor device mounted on the first wiring board or the second wiring board, a sealing resin filled between the first region of the first wiring board and the second wiring board and covering the connecting member and the semiconductor device, an optical integrated circuit mounted on the side of the second wiring board opposite to the first wiring board and electrically connected to the semiconductor device, and an optical component arranged adjacent to the optical integrated circuit via a first bonding material and enabling the transmission and reception of optical signals with the optical integrated circuit, wherein the optical component is fixed via a second bonding material to a second region of the first wiring board that does not face the second wiring board.

Description

Technical Field

[0001] The present invention relates to an optoelectronic hybrid device.

Background Art

[0002] In a data center or the like where various devices such as computers and data communication devices are installed, an optical connection structure for connecting an optical waveguide device and an optical fiber or the like may be used. As an example of such an optical connection structure, an optical connection component using a planar lightwave circuit is adhesively fixed to the end face of the input / output waveguide of an optical waveguide device, and the optical waveguide device and the optical fiber are optically connected via the planar lightwave circuit (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described optical connection structure, since the optical waveguide device and the optical connection component are adhesively fixed with a small adhesive area, the adhesive strength between the two is weak. Therefore, when stress is applied to the connection portion between the optical waveguide device and the optical connection component, there is a risk that the connection between the optical waveguide device and the optical connection component will break, and the connection reliability cannot be said to be high.

[0005] The present invention has been made in view of the above points, and an object thereof is to provide an optoelectronic hybrid device having an optical connection structure with high connection reliability.

Means for Solving the Problems

[0006] The optical-electric mixed-signal device comprises a first wiring board, a second wiring board facing a first region of the first wiring board and electrically connected to the first wiring board via a connecting member located in the first region, a semiconductor device mounted on the first or second wiring board, a sealing resin filled between the first region of the first wiring board and the second wiring board and covering the connecting member and the semiconductor device, an optical integrated circuit mounted on the side of the second wiring board opposite to the first wiring board and electrically connected to the semiconductor device, and an optical component arranged adjacent to the optical integrated circuit via a first bonding material and enabling the transmission and reception of optical signals with the optical integrated circuit, wherein the optical component is fixed to a second region of the first wiring board that does not face the second wiring board via a second bonding material. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to provide an optoelectronic hybrid device having an optical connection structure with high connectivity reliability. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view illustrating a photoelectric mixed-signal device according to the first embodiment. [Figure 2] This is a plan view illustrating a first wiring board that constitutes a photoelectric mixed-signal device according to the first embodiment. [Figure 3] This is a cross-sectional view showing an application example of the photoelectric mixed-signal device according to the first embodiment. [Figure 4] This is a diagram (part 1) illustrating the manufacturing process of a photoelectric mixed-signal device according to the first embodiment. [Figure 5] This is a diagram (part 2) illustrating the manufacturing process of a photoelectric mixed-signal device according to the first embodiment. [Figure 6] This is a diagram (part 3) illustrating the manufacturing process of a photoelectric mixed-signal device according to the first embodiment. [Figure 7] This is a cross-sectional view illustrating a photoelectric mixed-signal device according to Modification 1 of the First Embodiment. [Figure 8] This is a cross-sectional view illustrating a photoelectric mixed-loading apparatus according to a modified example 2 of the first embodiment. [Figure 9] This is a cross-sectional view illustrating a photoelectric mixed-loading device according to a modified example 3 of the first embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of a photoelectric mixed-signal device] Figure 1 is a cross-sectional view illustrating an optoelectronic mixed-signal device according to the first embodiment. Figure 2 is a plan view illustrating a first wiring board constituting the optoelectronic mixed-signal device according to the first embodiment. For convenience, the indicator lines and reference numerals for the first region R1 shown in Figure 2 are omitted in Figure 1.

[0011] Referring to Figures 1 and 2, the photoelectric mixed-signal device 1 includes a first wiring board 10, a connecting member 20, a second wiring board 30, a semiconductor device 40, an underfill resin 50, an optical integrated circuit 60, an underfill resin 70, a sealing resin 80, a fiber array 90, a first bonding material 110, and a second bonding material 120. The fiber array 90 is a typical example of an optical component according to the present invention.

[0012] In the photoelectric mixed-signal device 1, the first wiring board 10 comprises a first region R1 and a second region R2 that is continuous with the first region R1. The second wiring board 30 faces the first region R1 of the first wiring board 10 and is electrically connected to the first wiring board 10 via a connecting member 20 located in the first region R1. In other words, in the first wiring board 10, the region facing the second wiring board 30 is the first region R1, and the region not facing the second wiring board 30 is the second region R2.

[0013] For example, the first wiring board 10 is rectangular in plan view, and the first region R1 and the second region R2 can be arranged adjacent to each other in the longitudinal direction of the rectangle. However, the arrangement of the first region R1 and the second region R2 is not limited to the example of FIG. 2. For example, the second region R2 does not have to be arranged along the entire side of the first region R1, and may be arranged along only a part of one side of the first region R1.

[0014] In addition, in the present embodiment, for the sake of convenience, the side of the solder resist layer 37 in FIG. 1 is taken as the upper side or one side, and the side of the solder resist layer 13 is taken as the lower side or the other side. Also, the surface on the solder resist layer 37 side of each part is taken as one surface or the upper surface, and the surface on the solder resist layer 13 side is taken as the other surface or the lower surface. However, the optoelectronic hybrid mounting device 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, the plan view means viewing the object from the normal direction of one surface of the solder resist layer 37, and the planar shape means the shape of the object viewed from the normal direction of one surface of the solder resist layer 37.

[0015] The first wiring board 10 includes an insulating layer 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15.

[0016] In the first wiring board 10, as the insulating layer 11, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin can be used. As the insulating layer 11, a substrate obtained by impregnating a woven or non-woven fabric of glass fiber, carbon fiber, aramid fiber, etc. with an insulating resin such as an epoxy resin may also be used. The thickness of the insulating layer 11 can be, for example, about 60 to 200 μm. In each figure, the illustration of the glass cloth, etc. is omitted.

[0017] The wiring layer 12 is formed on the lower surface side of the insulating layer 11. The wiring layer 14 is formed on the upper surface of the insulating layer 11. In the insulating layer 11, a via hole 11x is formed which penetrates the insulating layer 11 and exposes the lower surface of the wiring layer 14. The via hole 11x is a frustum-shaped recess in which the diameter of the opening on the solder resist layer 13 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 14. The diameter of the opening of the via hole 11x can be, for example, about 50 μm.

[0018] The wiring layer 12 is composed of, for example, via wirings filled in the via hole 11x and wiring patterns formed on the lower surface of the insulating layer 11. The lower surface of the wiring layer 14 is in contact with the upper end portions of the via wirings filled in the via hole 11x of the wiring layer 12. That is, the wiring layer 12 is electrically connected to the wiring layer 14.

[0019] As the material of the wiring layer 12, for example, copper (Cu) or the like can be used. The thickness of the wiring pattern constituting the wiring layer 12 can be, for example, about 10 to 20 μm. The material of the wiring layer 14 can be, for example, the same as that of the wiring layer 12. The thickness of the wiring layer 14 can be, for example, the same as that of the wiring pattern constituting the wiring layer 12.

[0020] The solder resist layer 13 is formed on the lower surface of the insulating layer 11 so as to cover the wiring layer 12. The solder resist layer 13 can be formed from, for example, a photosensitive resin or the like. The thickness of the solder resist layer 13 can be, for example, about 15 to 35 μm. The solder resist layer 13 has an opening 13x, and a part of the wiring layer 12 is exposed in the opening 13x. The wiring layer 12 exposed in the opening 13x constitutes a pad 12p. The pad 12p functions as a pad that is electrically connected to a package substrate or the like.

[0021] The solder resist layer 13 may be provided so as to completely expose the pad 12p. In this case, the solder resist layer 13 may be provided so as to be in contact with the side surface of the pad 12p and the inner wall surface of the opening 13x, or the solder resist layer 13 may be provided so as to create a gap between the side surface of the pad 12p and the inner wall surface of the opening 13x.

[0022] If necessary, a metal layer may be formed on the underside of pad 12p, or an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment may be applied. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer formed by stacking Ni and Au layers in that order), and a Ni / Pd / Au layer (a metal layer formed by stacking Ni, Pd, and Au layers in that order). In addition, external connection terminals such as solder balls may be formed on the underside of pad 12p.

[0023] The solder resist layer 15 is formed on the upper surface of the insulating layer 11 so as to cover the wiring layer 14. The material and thickness of the solder resist layer 15 can be the same as, for example, the solder resist layer 13. The solder resist layer 15 has an opening 15x, and a portion of the wiring layer 14 is exposed within the opening 15x. The wiring layer 14 exposed within the opening 15x constitutes a pad 14p. The pad 14p functions as a pad that is electrically connected to the connecting member 20. If necessary, the aforementioned metal layer may be formed on the upper surface of the pad 14p, or an anti-oxidation treatment such as OSP treatment may be applied.

[0024] In the examples shown in Figures 1 and 2, in the second region R2, the lower surface of the insulating layer 11 is exposed from the solder resist layer 13, and the upper surface of the insulating layer 11 is exposed from the solder resist layer 15. However, the solder resist layers 13 and / or 15 may extend from the first region R1 to the second region R2, covering part or all of the lower and / or upper surfaces of the insulating layer 11.

[0025] The second wiring board 30 has an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, a solder resist layer 35, a wiring layer 36, and a solder resist layer 37.

[0026] In the second wiring board 30, the material and thickness of the insulating layer 31 can be, for example, the same as those of the insulating layer 11. The wiring layer 32 is formed on the lower surface of the insulating layer 31. The material of the wiring layer 32 can be, for example, the same as those of the wiring layer 12. The thickness of the wiring layer 32 can be, for example, the same as the wiring pattern that constitutes the wiring layer 12.

[0027] The insulating layer 33 is formed on the underside of the insulating layer 31 so as to cover the wiring layer 32. As the material for the insulating layer 33, for example, an insulating resin such as a thermosetting epoxy resin can be used. The insulating layer 33 may also contain fillers such as silica (SiO2). The thickness of the insulating layer 33 can be, for example, about 15 to 35 μm.

[0028] The wiring layer 34 is formed on the lower side of the insulating layer 33. The wiring layer 34 consists of via wiring filled in via holes 33x that penetrate the insulating layer 33 and expose the lower surface of the wiring layer 32, and a wiring pattern formed on the lower surface of the insulating layer 33.

[0029] The via hole 33x is a frustoconical recess that opens to the solder resist layer 35 and has its bottom surface formed by the lower surface of the wiring layer 32, with the area of ​​the opening being larger than the area of ​​the bottom surface. The material of the wiring layer 34 can be, for example, the same as that of the wiring layer 12. The thickness of the wiring layer 34 can be, for example, the same as that of the wiring pattern constituting the wiring layer 12.

[0030] The solder resist layer 35 is a protective insulating layer formed on the underside of the insulating layer 33, covering the wiring layer 34. The material and thickness of the solder resist layer 35 can be the same as, for example, the solder resist layer 13. The solder resist layer 35 has an opening 35x, in which a portion of the wiring layer 34 is exposed. The wiring layer 34 exposed in the opening 35x constitutes pads 34p and 34q.

[0031] Pad 34p is positioned opposite pad 14p of the first wiring board 10. Pad 34p functions as a pad that is joined to the connecting member 20. Pad 34q functions as a pad that is joined to the semiconductor device 40. Multiple pads 34q are formed on the first wiring board 10 side of the second wiring board 30. The opening diameters of pad 34p, which is electrically connected to the connecting member 20, and pad 34q, which is electrically connected to the semiconductor device 40, can be set independently. If necessary, the aforementioned metal layer may be formed on the lower surface of pads 34p and 34q, or an anti-oxidation treatment such as OSP treatment may be applied.

[0032] The wiring layer 36 is formed on the upper side of the insulating layer 31. The wiring layer 36 consists of via wiring filled in via holes 31x that penetrate the insulating layer 31 and expose the upper surface of the wiring layer 32, and a wiring pattern formed on the upper surface of the insulating layer 31.

[0033] The via hole 31x is an inverted frustoconical recess that opens towards the solder resist layer 37 and has its bottom surface formed by the upper surface of the wiring layer 32, with the area of ​​the opening being larger than the area of ​​the bottom surface. The lower end of the via wiring filled in the via hole 31x of the wiring layer 36 is in contact with the upper surface of the wiring layer 32. That is, the wiring layer 36 is electrically connected to the wiring layer 32. The material of the wiring layer 36 and the thickness of the wiring pattern constituting the wiring layer 36 can be the same as, for example, the same as that of the wiring layer 12.

[0034] The solder resist layer 37 is formed on the upper surface of the insulating layer 31 so as to cover the wiring layer 36. The material and thickness of the solder resist layer 37 can be the same as, for example, the solder resist layer 13. The solder resist layer 37 has an opening 37x, and a portion of the wiring layer 36 is exposed within the opening 37x. The wiring layer 36 exposed within the opening 37x constitutes a pad 36p. The pad 36p functions as a pad to be joined to the optical integrated circuit 60. A portion of the pad 36p may be used as a pad for external connection. If necessary, the aforementioned metal layer may be formed on the upper surface of the pad 36p, or an anti-oxidation treatment such as OSP treatment may be applied.

[0035] The semiconductor device 40 is mounted on the side of the first wiring board 10 facing the second wiring board 30, or on the side of the second wiring board 30 facing the first wiring board 10. In the example shown in Figure 1, the semiconductor device 40 is mounted on the side of the second wiring board 30 facing the first wiring board 10 and is electrically connected to the optical integrated circuit 60 via the second wiring board 30. Specifically, the semiconductor device 40 is flip-chip mounted face-down on the underside of the second wiring board 30. The semiconductor device 40 has a body 41 equipped with a semiconductor integrated circuit and electrodes 42 which are connection terminals, and the electrodes 42 of the semiconductor device 40 are electrically connected to the pads 34q of the second wiring board 30 via solder or the like. As the electrodes 42, for example, gold bumps, solder bumps, copper posts with solder at the tip, etc., can be used.

[0036] The semiconductor device 40 is, for example, a semiconductor chip. The semiconductor device 40 may also be a semiconductor package in which an insulating layer and redistribution are formed on the semiconductor chip. In addition to the semiconductor device 40, passive elements such as capacitors, inductors, and resistors may be mounted on the first wiring board 10 and / or the second wiring board 30.

[0037] The underfill resin 50 is filled between the semiconductor device 40 and the lower surface of the second wiring substrate 30. It is preferable to use a material with good fluidity for the underfill resin 50. For example, an insulating resin such as an epoxy resin can be used as the material for the underfill resin 50.

[0038] The optical integrated circuit 60 is mounted on the side of the second wiring board 30 opposite to the first wiring board 10 and is electrically connected to the semiconductor device 40. Specifically, the optical integrated circuit 60 is flip-chip mounted face-down on the upper surface of the second wiring board 30. The optical integrated circuit 60 has a main body 61 equipped with an optical waveguide and the like, and electrodes 62 which are connection terminals, and the electrodes 62 of the optical integrated circuit 60 are electrically connected to the pads 36p of the second wiring board 30 via solder or the like. For example, gold bumps, solder bumps, copper posts with solder at the tip can be used as electrodes 62.

[0039] The photonic integrated circuit 60 (PIC) is, for example, a substrate such as silicon on which optical waveguides, light-emitting elements, light-receiving elements, etc., are provided. The photonic integrated circuit 60 is sometimes referred to as silicon photonics. The photonic integrated circuit 60 can have the function of converting optical signals input from the fiber array 90 into electrical signals and outputting them to the semiconductor device 40, and / or converting electrical signals input from the semiconductor device 40 into optical signals and outputting them to the fiber array 90.

[0040] It is preferable that at least a portion of the optical integrated circuit 60 overlaps with the semiconductor device 40 in a plan view. This arrangement allows the optical integrated circuit 60 and the semiconductor device 40 to be connected by a short wiring path, enabling high-speed, high-capacity data transmission and reception between the optical integrated circuit 60 and the semiconductor device 40.

[0041] The semiconductor device 40 may have a function to amplify the electrical signal input from the optical integrated circuit 60. Since the electrical signal input from the optical integrated circuit 60 is fast and easily attenuated, the quality of the electrical signal output from the semiconductor device 40 can be improved by connecting the optical integrated circuit 60 and the semiconductor device 40 with short wiring and amplifying the attenuating electrical signal with the semiconductor device 40.

[0042] The underfill resin 70 is filled between the optical integrated circuit 60 and the upper surface of the second wiring board 30. For example, the same material as the underfill resin 50 can be used for the underfill resin 70.

[0043] The connecting member 20 is positioned between the pad 14p of the first wiring board 10 and the pad 34p of the second wiring board 30. The connecting member 20 electrically connects the first wiring board 10 and the second wiring board 30, and also has the function of ensuring a predetermined distance between the first wiring board 10 and the second wiring board 30.

[0044] In this embodiment, as an example, a solder ball with a core is used as the connecting member 20. The connecting member 20 comprises a substantially spherical core 21 and a conductive material 22 covering the outer circumferential surface of the core 21, and is arranged so that the core 21 is in contact with the pads 14p and 34p. The diameter of the core 21 before bonding to the first wiring board 10 and the second wiring board 30 can be, for example, about 100 μm to 300 μm, and is preferably about 200 μm. The overall diameter of the connecting member 20, including the conductive material 22 before bonding to the first wiring board 10 and the second wiring board 30, can be, for example, about 150 μm to 350 μm, and is preferably about 250 μm.

[0045] For the core 21, for example, a metal core made of a metal such as copper or a resin core made of resin can be used. For the conductive material 22, for example, solder materials such as alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Sb, alloys of Sn and Ag, or alloys of Sn, Ag, and Cu can be used. The diameter of the core 21 can be determined considering the height (thickness) of the semiconductor device 40.

[0046] Furthermore, the connecting member 20 is not limited to a solder ball with a core, which includes a core 21 and a conductive material 22 covering the outer surface of the core 21. For example, a solder ball without a core may be used. If a solder ball without a core is used, the distance between the first wiring board 10 and the second wiring board 30 can be controlled using a predetermined jig during the manufacturing of the photoelectric mixed-signal device 1. In addition, metal posts such as copper posts or metal bumps such as gold bumps may be used as the connecting member 20.

[0047] In Figure 1, the connecting members 20 are shown in a simplified manner, but in reality, multiple rows of connecting members 20 are arranged, for example, in a peripheral configuration. When the first wiring board 10 and the second wiring board 30 are rectangular in plan view, the connecting members 20 are provided around the periphery of the boards, for example, in a peripheral configuration. For example, if the diameter of the connecting members 20 is about 150 μm, the pitch of the connecting members 20 can be about 200 μm.

[0048] The sealing resin 80 is filled between the first wiring board 10 and the second wiring board 30, covering the connecting member 20 and the semiconductor device 40. As the material for the sealing resin 80, for example, a molding resin can be used. A molding resin is an insulating resin mainly composed of a non-photosensitive thermosetting resin that can be used in transfer molding, compression molding, injection molding, etc. The molding resin is, for example, an insulating resin such as a non-photosensitive thermosetting epoxy resin, and may contain fillers.

[0049] The fiber array 90 comprises, for example, a base 91, a plurality of optical fibers 92, and a lid 93. The base 91 and lid 93 can be formed from, for example, glass or resin. The fiber array 90 is positioned adjacent to the optical integrated circuit 60 via a first bonding material 110, enabling the transmission and reception of optical signals between the fiber array 90 and the optical integrated circuit 60.

[0050] The gap between the fiber array 90 and the optical integrated circuit 60 is, for example, about several tens of micrometers. The ends of each optical waveguide in the optical integrated circuit 60 face the ends of each optical fiber 92 via the first bonding material 110. Therefore, each optical waveguide in the optical integrated circuit 60 can transmit and receive optical signals with each optical fiber 92. The first bonding material 110 is, for example, an optical adhesive with good transmittance for the wavelength of the optical signals transmitted and received between the fiber array 90 and the optical integrated circuit 60.

[0051] The fiber array 90 is fixed to a second region R2 of the first wiring board 10 that does not face the second wiring board 30, via a second bonding material 120. The second bonding material 120 may be placed over the entire region where the fiber array 90 and the second region R2 of the first wiring board 10 face each other, or it may be placed only in a part of it. For example, the second bonding material 120 may be placed at the four corners of the region where the fiber array 90 and the second region R2 of the first wiring board 10 face each other. As the second bonding material 120, an ultraviolet-curing type or a thermosetting type epoxy resin can be used.

[0052] Thus, in the optical-electric mixed-signal device 1, the fiber array 90 is fixed to the optical integrated circuit 60 by the first bonding material 110, and also fixed to the second region R2 of the first wiring board 10 by the second bonding material 120. As a result, stress is less likely to concentrate at the connection point between the fiber array 90 and the optical integrated circuit 60, thereby reducing the risk of fracture at the connection point between the fiber array 90 and the optical integrated circuit 60. In other words, a highly reliable optical connection structure can be realized between the fiber array 90 and the optical integrated circuit 60.

[0053] Figure 3 is a cross-sectional view showing an application example of the photoelectric mixed-signal device according to the first embodiment. Referring to Figure 3, the photoelectric mixed-signal device 1 is mounted on a package substrate 200. Specifically, the package substrate 200 has a main body 210 and a pad 220 located on the upper surface of the main body 210. The pad 220 is electrically connected to the pad 12p of the photoelectric mixed-signal device 1 via a joint 300, which is a solder ball or the like.

[0054] The package substrate 200 can, for example, mount a processor. The processor can be electrically connected to the semiconductor device 40 of the photoelectric mixed-signal device 1 via the package substrate 200.

[0055] The lower side of the package substrate 200 is connected to a mounting board, such as a motherboard. In other words, the package substrate 200 is an interposer that relays the electrical connection between the optical-electrical mixed-signal device 1 and other mounting boards. The main body 210 of the package substrate 200 is, for example, a resin substrate or a silicon substrate with multilayer wiring formed on it. By using the package substrate 200, even if the pads of the optical-electrical mixed-signal device 1 have a narrow pitch, it is possible to enlarge the pitch, thus facilitating the electrical connection between the optical-electrical mixed-signal device 1 and other mounting boards.

[0056] Furthermore, the highly reliable optical connection structure between the fiber array 90 and the optical integrated circuit 60 is completed within the optoelectronic mixed-signal device 1 and does not depend on the package substrate 200. Therefore, the optoelectronic mixed-signal device 1 is easy to handle, and the design flexibility of the mounting structure using the optoelectronic mixed-signal device 1 can be improved.

[0057] [Manufacturing method for photoelectric mixed-loading devices] Next, a method for manufacturing the photoelectric mixed-signal device according to the first embodiment will be described. Figures 4 to 6 illustrate the manufacturing process of the photoelectric mixed-signal device according to the first embodiment.

[0058] First, in the process shown in Figure 4(a), the first wiring board 10 is manufactured. The first wiring board 10 has a first region R1 which faces the second wiring board 30 and a second region R2 which does not face the second wiring board 30.

[0059] The first wiring board 10 can be formed, for example, using a well-known build-up method. Specifically, an insulating layer 11 made of a so-called glass epoxy substrate is prepared. Then, a wiring layer 14 is formed on the upper surface of the insulating layer 11. Next, via holes 11x are formed in the insulating layer 11 to expose the lower surface of the wiring layer 14, and then a wiring layer 12 is formed on the lower surface of the insulating layer 11. The wiring layer 12 and the wiring layer 14 are electrically connected via the insulating layer 11.

[0060] After forming the via holes 11x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surface of the wiring layer 14 exposed at the bottom of the via holes 11x. The via holes 11x can be formed by a laser processing method, for example, using a CO2 laser. The wiring layers 12 and 14 can be formed using various wiring formation methods, such as the semi-additive method or the subtractive method. For example, the wiring layers 12 and 14 can be formed by copper plating.

[0061] Next, a solder resist layer 13 is formed on the lower surface of the insulating layer 11 to cover the wiring layer 12, and a solder resist layer 15 is formed on the upper surface of the insulating layer 11 to cover the wiring layer 14. The solder resist layer 13 can be formed, for example, by applying an insulating resin such as a liquid or paste-like photosensitive epoxy resin to the lower surface of the insulating layer 11 using a screen printing method, roll coating method, or spin coating method so as to cover the wiring layer 12.

[0062] Similarly, the solder resist layer 15 can be formed by applying an insulating resin, such as a liquid or paste-like photosensitive epoxy resin, to the upper surface of the insulating layer 11 in the same manner so as to cover the wiring layer 14. Alternatively, instead of applying a liquid or paste-like resin, an insulating resin, such as a film-like photosensitive epoxy resin, may be laminated.

[0063] Then, by exposing and developing the coated or laminated insulating resin, openings 13x and 15x are formed in the solder resist layers 13 and 15, and pads 12p and 14p are formed (photolithography method). This completes the first wiring board 10. The openings 13x and 15x may also be formed by laser processing or blasting. The planar shape of each of the openings 13x and 15x can be, for example, circular. The diameter of each of the openings 13x and 15x can be arbitrarily designed to suit the connection target.

[0064] Next, in the process shown in Figure 4(b), the connecting member 20 is placed on the pad 14p exposed within the opening 15x of the solder resist layer 15 of the first wiring board 10. Then, it is heated to a predetermined temperature to melt the conductive material 22 constituting the connecting member 20, and then hardened to bond it to the pad 14p. A portion of the core 21 constituting the connecting member 20 is in contact with the pad 14p. The connecting member 20 is arranged, for example, in a peripheral configuration.

[0065] Next, in the process shown in Figure 5(a), a second wiring board 30 is fabricated. The second wiring board 30 can be fabricated, for example, using a well-known build-up method. Specifically, an insulating layer 31 using a so-called glass epoxy substrate is prepared, and a wiring layer 32 is formed on the lower surface of the insulating layer 31. Next, via holes 31x are formed in the insulating layer 31 to expose the upper surface of the wiring layer 32, and then a wiring layer 36 is formed on the upper surface of the insulating layer 31. The wiring layer 32 and the wiring layer 36 are electrically connected via the insulating layer 31.

[0066] After forming the via holes 31x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 31x. The via holes 31x can be formed, for example, by a laser processing method using a CO2 laser. The wiring layers 32 and 36 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.

[0067] Next, an insulating resin film, such as a thermosetting epoxy resin, is laminated to the lower surface of the insulating layer 31 so as to cover the wiring layer 32, thereby forming an insulating layer 33. Alternatively, instead of laminating with an insulating resin film such as a thermosetting epoxy resin, a liquid or paste-like insulating resin, such as a thermosetting epoxy resin, may be applied and then cured to form the insulating layer 33.

[0068] Next, via holes 33x are formed in the insulating layer 33, penetrating the insulating layer 33 and exposing the lower surface of the wiring layer 32. The via holes 33x can be formed, for example, by a laser processing method using a CO2 laser. After forming the via holes 33x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 33x.

[0069] Next, a wiring layer 34 is formed on the lower side of the insulating layer 33. The wiring layer 34 consists of via wiring filled in via holes 33x and a wiring pattern formed on the lower surface of the insulating layer 33. The wiring layer 34 is electrically connected to the wiring layer 32 exposed at the bottom of the via holes 33x. The wiring layer 34 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.

[0070] Next, a solder resist layer 35 covering the wiring layer 34 is formed on the lower surface of the insulating layer 33, and a solder resist layer 37 covering the wiring layer 36 is formed on the upper surface of the insulating layer 31, similar to the solder resist layer 13 of the first wiring board 10. Then, openings 35x and 37x are formed in the solder resist layers 35 and 37, similar to the openings 13x of the first wiring board 10, and pads 34p and 36p are formed (photolithography). This completes the second wiring board 30. The second wiring board 30, for example, has a rectangular shape with a smaller area than the first wiring board 10 when viewed from above.

[0071] Next, in the process shown in Figure 5(b), a semiconductor device 40 having a main body 41 and electrodes 42 is prepared, and the semiconductor device 40 is mounted on the second wiring board 30 so that the electrodes 42 are joined to the pads 34q. Specifically, for example, a paste-like solder material is applied to the pads 34q. Then, the electrodes 42 of the semiconductor device 40 and the pads 34q are aligned, and the semiconductor device 40 is placed on the second wiring board 30. After that, the solder material is heated and melted by reflow or the like, and then solidified. As a result, the electrodes 42 of the semiconductor device 40 are electrically connected to the pads 34q of the second wiring board 30 via the solder material.

[0072] Next, the second wiring board 30 is stacked on the first wiring board 10 with the semiconductor device 40 sandwiched in between, so that the connecting member 20 is positioned to correspond to the pad 34p. Then, the conductive material 22 of the connecting member 20 is heated and melted using a heater or the like, and then solidified. As a result, the lower side of the core 21 constituting the connecting member 20 is joined to the pad 14p of the first wiring board 10, and the upper side is joined to the pad 34p of the second wiring board 30. In other words, the first wiring board 10 and the second wiring board 30 are electrically connected via the connecting member 20. In addition, the core 21 of the connecting member 20 ensures a predetermined gap between the first wiring board 10 and the second wiring board 30.

[0073] Next, in the process shown in Figure 6(a), an optical integrated circuit 60 having a main body 61 and electrodes 62 is prepared, and the optical integrated circuit 60 is mounted on the second wiring board 30 on the side opposite to the first wiring board 10 so that the electrodes 62 are joined to the pads 36p. Specifically, for example, a paste-like solder material is applied to the pads 36p. Then, the electrodes 62 of the optical integrated circuit 60 and the pads 36p are aligned, and the optical integrated circuit 60 is placed on the second wiring board 30 on the side opposite to the first wiring board 10. After that, the solder material is heated and melted by reflow or the like, and then solidified. As a result, the electrodes 62 of the optical integrated circuit 60 are electrically connected to the pads 36p of the second wiring board 30 via the solder material.

[0074] Next, a fiber array 90 is prepared, comprising a base 91, a plurality of optical fibers 92, and a lid 93. The fiber array 90 is then placed on the second region R2 of the first wiring board 10 with the lid 93 facing downwards, and the base 91 of the fiber array 90 is bonded to the optical integrated circuit 60 via the first bonding material 110 so that each optical fiber 92 makes optical connection to each optical waveguide of the optical integrated circuit 60. For example, the base 91 of the fiber array 90 and the optical integrated circuit 60 are temporarily fixed with the uncured first bonding material 110. Then, active alignment is performed to position each optical fiber 92 so that it makes optical connection to each optical waveguide of the optical integrated circuit 60, and the uncured first bonding material 110 is cured.

[0075] Next, in the process shown in Figure 6(b), the lid 93 of the fiber array 90 is fixed to the second region R2 of the first wiring board 10 via the second bonding material 120. For example, an uncured UV-curing or thermosetting epoxy resin is poured between the lid 93 and the second region R2 of the first wiring board 10 and cured.

[0076] The fiber array 90, which is fixed to the optical integrated circuit 60 via the first bonding material 110, is also fixed to the second region R2 of the first wiring substrate 10 by the second bonding material 120. This reduces stress concentration at the connection point between the fiber array 90 and the optical integrated circuit 60. Therefore, the risk of fracture at the connection point between the fiber array 90 and the optical integrated circuit 60 can be reduced. In other words, a highly reliable optical connection structure can be realized between the fiber array 90 and the optical integrated circuit 60.

[0077] Next, a sealing resin 80 is formed, which is filled between the first region R1 of the first wiring board 10 and the second wiring board 30, and covers the connecting member 20 and the semiconductor device 40. As the sealing resin 80, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. The sealing resin 80 can be formed, for example, by a transfer molding method using a sealing mold.

[0078] The steps of fixing the lid 93 of the fiber array 90 to the second region R2 of the first wiring board 10 via the second bonding material 120 and forming the sealing resin 80 between the first region R1 of the first wiring board 10 and the second wiring board 30 may be performed in reverse order.

[0079] The photoelectric mixed-signal device 1 is completed through the above process. If necessary, external connection terminals such as solder balls may be formed on the pads 12p of the first wiring board 10.

[0080] <Variation 1 of the First Embodiment> Modification 1 of the first embodiment differs from the first embodiment in that the second bonding material is a different material from the sealing resin, and instead shows an example in which the second bonding material is the same material as the sealing resin, that is, an example in which the sealing resin is also used as the second bonding material.

[0081] Figure 7 is a cross-sectional view illustrating a modified example of the first embodiment of the photoelectric mixed-signal device. Referring to Figure 7, in the photoelectric mixed-signal device 1A, the sealing resin 80 extends from the first region R1 to the second region R2 of the first wiring board 10 and enters between the second region R2 and the lid 93 of the fiber array 90, functioning as a second bonding material that fixes the fiber array 90 to the first wiring board 10.

[0082] In the process shown in Figure 6(b), the encapsulating resin 80 can be filled between the first region R1 of the first wiring board 10 and the second wiring board 30, and further extended from the first region R1 to the second region R2 of the first wiring board 10 so that it fits between the second region R2 and the lid 93 of the fiber array 90. The encapsulating resin 80 can be formed, for example, by a transfer molding method using an encapsulating mold.

[0083] In the optical-electric mixed-signal device 1A, the fiber array 90, which is fixed to the optical integrated circuit 60 via the first bonding material 110, is also fixed to the second region R2 of the first wiring board 10 by the sealing resin 80. This reduces stress concentration at the connection point between the fiber array 90 and the optical integrated circuit 60. Therefore, the risk of fracture at the connection point between the fiber array 90 and the optical integrated circuit 60 can be reduced. In other words, a highly reliable optical connection structure can be realized between the fiber array 90 and the optical integrated circuit 60.

[0084] <Modification 2 of the First Embodiment> Modification 2 of the first embodiment shows an example in which the fiber array is bonded to the sealing resin via a second bonding material.

[0085] Figure 8 is a cross-sectional view illustrating a modified photoelectric combined-signal device according to a second modification of the first embodiment. Referring to Figure 8, in the photoelectric combined-signal device 1B, the sealing resin 80 extends from the first region R1 to the second region R2 of the first wiring board 10. The sealing resin 80 can be provided, for example, over the entire second region R2. The sealing resin 80 can be provided, for example, over the entire upper surface of the insulating layer 11 located in the second region R2.

[0086] The fiber array 90 is fixed to the sealing resin 80 located in the second region R2 of the first wiring board 10 via a second bonding material 120. The second bonding material 120 may be placed over the entire region where the fiber array 90 and the sealing resin 80 face each other, or it may be placed over only a portion of that region. For example, the second bonding material 120 may be placed at the four corners of the region where the fiber array 90 and the sealing resin 80 face each other.

[0087] The thickness of the sealing resin 80 located in the second region R2 is preferably determined such that the thickness of the second bonding material 120 between the sealing resin 80 located in the second region R2 and the fiber array 90 is 10 μm or more and 50 μm or less. If the second bonding material 120 has such a thickness, thermal shrinkage when the second bonding material 120 is heated and cured can be reduced. As a result, tilting of the fiber array 90 due to thermal shrinkage of the second bonding material 120 is less likely to occur, and thus the optical axis misalignment between the optical waveguide of the optical integrated circuit 60 and the optical fiber 92 of the fiber array 90 can be suppressed.

[0088] To manufacture the photoelectric mixed-signal device 1B, for example, after the process shown in Figure 5(b), a sealing resin 80 is formed to fill the space between the first region R1 of the first wiring board 10 and the second wiring board 30, and further extend from the first region R1 to the second region R2 of the first wiring board 10. The sealing resin 80 can be formed, for example, by a transfer molding method using a sealing mold. By forming the sealing resin 80 in this way before placing the optical integrated circuit 60 and the fiber array 90, it is not necessary to place the optical integrated circuit 60 and the fiber array 90 into the sealing mold. Therefore, this is preferable in that it does not damage the optical integrated circuit 60 and the fiber array 90.

[0089] Next, after the sealing resin 80 has hardened, the optical integrated circuit 60 is mounted on the side of the second wiring board 30 opposite to the first wiring board 10. Then, with the lid 93 facing downwards, the fiber array 90 is placed on the second region R2 of the first wiring board 10, and the base 91 of the fiber array 90 is bonded to the optical integrated circuit 60 via the first bonding material 110 so that each optical fiber 92 is optically connected to each optical waveguide of the optical integrated circuit 60.

[0090] Next, an uncured UV-curable or thermosetting epoxy resin is poured between the lid 93 of the fiber array 90 and the sealing resin 80 located in the second region R2, and cured to form the second bonding material 120. This completes the photoelectric mixed-signal device 1B. Alternatively, an uncured epoxy resin may be applied onto the sealing resin 80 located in the second region R2 before optically connecting the fiber array 90 to the optical integrated circuit 60. In this case, the uncured epoxy resin is cured after optically connecting the fiber array 90 to the optical integrated circuit 60 to form the second bonding material 120.

[0091] In the optical-electric mixed-signal device 1B, the fiber array 90 is fixed to the optical integrated circuit 60 by a first bonding material 110, and also fixed to the sealing resin 80 located in the second region R2 of the first wiring board 10 by a second bonding material 120. This reduces stress concentration at the connection point between the fiber array 90 and the optical integrated circuit 60, thereby reducing the risk of fracture at the connection point between the fiber array 90 and the optical integrated circuit 60. In other words, a highly reliable optical connection structure can be realized between the fiber array 90 and the optical integrated circuit 60.

[0092] Furthermore, in the photoelectric mixed-signal device 1B, since the sealing resin 80 extends from the first region R1 to the second region R2 of the first wiring board 10, the rigidity of the second region R2 of the first wiring board 10 can be improved. As a result, warping and bending in the second region R2 of the first wiring board 10 can be suppressed. From the viewpoint of improving the rigidity of the second region R2, it is preferable that the thickness of the sealing resin 80 located in the second region R2 is 50 μm or more. The thickness of the sealing resin 80 located in the second region R2 may be the same as the thickness of the sealing resin 80 located in the first region R1. Also, from the viewpoint of improving the rigidity of the second region R2, it is preferable that the sealing resin 80 is provided over the entire second region R2.

[0093] <Modification 3 of the First Embodiment> Modification 3 of the first embodiment shows an example in which a connector 150 is placed instead of the fiber array 90.

[0094] Figure 9 is a cross-sectional view illustrating a modified example 3 of the first embodiment of the photoelectric mixed-signal device. Referring to Figure 9, in the photoelectric mixed-signal device 1C, the connector 150 is positioned adjacent to the optical integrated circuit 60 via the first bonding material 110. The connector 150 is also fixed to the second region R2 of the first wiring board 10 by the second bonding material 120.

[0095] The connector 150 is a female connector and can be formed from, for example, a transparent resin. Alternatively, the connector 150 may be formed from an opaque resin and have openings in the region facing each optical waveguide of the optical integrated circuit 60 that can transmit and receive optical signals.

[0096] The connector 150 has an insertion portion 150x that opens on the opposite side from the optical integrated circuit 60, and can be connected to a fiber array equipped with optical fibers. When the connector 150 and the fiber array are connected, the optical integrated circuit 60 can send and receive optical signals with the optical fibers. For example, by inserting a male connector connected to the fiber array into the insertion portion 150x from the direction of the arrow, each optical fiber of the fiber array and each optical waveguide of the optical integrated circuit 60 can be brought into opposition and optically connected to each other. Note that the connector 150 may be male and the connector connected to the fiber array may be female.

[0097] Thus, the optical component according to the present invention is not limited to the fiber array 90, but may be a connector 150 or the like, as long as it is a component that is arranged adjacent to the optical integrated circuit 60 via the first bonding material 110 and contributes to enabling the transmission and reception of optical signals with the optical integrated circuit 60.

[0098] If the optical component according to the present invention has a connector 150, repeated stress may be applied to the connection portion between the connector 150 and the optical integrated circuit 60 due to the attachment and detachment of fiber arrays, etc., to the connector 150. Therefore, there is great technical significance in fixing the connector 150 to the second region R2 of the first wiring board 10 with a second bonding material 120 to reduce the stress applied to the connection portion between the connector 150 and the optical integrated circuit 60. Of course, a sealing resin 80 that functions as the second bonding material 120 may be used to fix the connector 150 to the first wiring board 10. Alternatively, the sealing resin 80 may be extended from the first region R1 to the second region R2, and the connector 150 may be bonded to the sealing resin 80 located in the second region R2 via the second bonding material 120.

[0099] Although preferred embodiments and their variations have been described in detail above, the invention is not limited to the embodiments and their variations described above, and various modifications and substitutions can be made to the embodiments and their variations described above without departing from the scope of the claims. [Explanation of symbols]

[0100] 1,1A,1B,1C Photoelectric mixed-signal device 10. First wiring board 11, 31, 33 Insulating layer 11x, 31x, 33x Beer Hall 12, 14, 32, 34, 36 wiring layers 12p, 14p, 34p, 34q, 36p pads 13, 15, 35, 37 Solder resist layers 13x, 15x, 35x, 37x opening 20 Connecting Members 21 cores 22 Conductive materials 30 Second wiring board 40 Semiconductor Devices 41 Main unit 42 electrodes 50,70 Underfill resin 60 Optical Integrated Circuits 61 Main unit 62 electrodes 80 Sealing resin 90 Fiber Array 91 Bass 92 Optical Fiber 93 Lid 110 1st bonding material 120 Second bonding material 150 connectors 150x Insertion section 200 package substrates 210 Main Unit 220 pads 300 joint

Claims

1. First wiring board and A second wiring board is located opposite the first region of the first wiring board and is electrically connected to the first wiring board via a connecting member arranged in the first region, A semiconductor device mounted on the first wiring board or the second wiring board, A sealing resin is filled between the first region of the first wiring board and the second wiring board and covers the connecting member and the semiconductor device, An optical integrated circuit is mounted on the side of the second wiring board opposite to the first wiring board and electrically connected to the semiconductor device, It includes an optical component that is positioned adjacent to the optical integrated circuit via a first bonding material and enables the transmission and reception of optical signals with the optical integrated circuit, The optical component is fixed to a second region of the first wiring board that does not face the second wiring board via a second bonding material, in a photoelectric mixed-signal device.

2. The photoelectric mixed-loading apparatus according to claim 1, wherein the sealing resin extends from the first region to the second region and enters between the second region and the optical component, and functions as a second bonding material.

3. The photoelectric mixed-loading apparatus according to claim 1, wherein the second bonding material is a component separate from the sealing resin.

4. The sealing resin is stretched from the first region to the second region, The photoelectric mixed-loading apparatus according to claim 3, wherein the optical component is fixed to the sealing resin located in the second region via the second bonding material.

5. The photoelectric mixed loading apparatus according to claim 4, wherein the sealing resin is provided over the entire second region.

6. The optical component includes an optical fiber, The optical integrated circuit is capable of transmitting and receiving optical signals with the optical fiber, the optical-electric mixed-signal apparatus according to any one of claims 1 to 5.

7. The optical component is a connector that can be connected to a fiber array equipped with optical fibers. The optical integrated circuit becomes capable of transmitting and receiving optical signals with the optical fiber when the connector and the fiber array are connected, according to any one of claims 1 to 5.

8. The optical integrated circuit has the function of converting an optical signal input from the optical component into an electrical signal and outputting it to the semiconductor device, and / or the function of converting an electrical signal input from the semiconductor device into an optical signal and outputting it to the optical component, according to any one of claims 1 to 5.

9. The semiconductor device is mounted on the first wiring board side of the second wiring board and is electrically connected to the optical integrated circuit via the second wiring board. The photoelectric mixed-signal apparatus according to claim 8, wherein at least a portion of the optical integrated circuit overlaps with the semiconductor device in a plan view.

10. The photoelectric mixed-signal apparatus according to claim 9, wherein the semiconductor device has the function of amplifying the electrical signal input from the optical integrated circuit.

Images