Polishing pad for semiconductor hybrid bonding process and method for manufacturing semiconductor devices using the same

Abstract

This invention provides a polishing pad that generates a predetermined dishing on the surface of a film to be polished, which contains dissimilar materials with different coefficients of thermal expansion, thereby achieving an appropriate polishing rate, and a method for manufacturing a semiconductor device using the polishing pad. [Solution] The polishing pad 200 includes a polishing layer 250 having a predetermined range of polishing selectivity ratios according to the thermal expansion coefficient of the object to be polished. During the polishing process, the dishing of the semiconductor substrate is adjusted, reducing surface defects and bonding defects of the semiconductor element.

Description

[Technical Field]

[0001] The present invention relates to a polishing pad and a method for manufacturing a semiconductor device using the same. More specifically, the present invention relates to a polishing pad for a semiconductor hybrid bonding process and a method for manufacturing a semiconductor device using the same. [Background technology]

[0002] Chemical mechanical planarization (CMP) processes can be performed for various purposes in various technological fields. For example, CMP processes can be used to planarize the surfaces of materials and substrates used in semiconductor devices, electronic components, optical components, etc., for purposes such as removing aggregated material, eliminating crystal lattice damage, and removing surface defects and sources of contamination.

[0003] In the CMP process, polishing pads may be used to polish the surface of the workpiece. For example, in the semiconductor manufacturing process, the CMP process involves attaching a semiconductor substrate, such as a wafer or die, to a head, and polishing the surface of the semiconductor substrate by rotating the head and the platen relative to each other while the semiconductor substrate is in contact with the surface of a polishing pad placed on a platen.

[0004] Polishing pads are manufactured using polymers, such as polyurethane resins, and may have grooves on their surface to support large-scale slurry flow and pores to support fine-scale flow. The pores in the polishing pad may be formed using solid-phase foaming agents, gas-phase foaming agents, liquid-phase foaming agents, or by gas generation through chemical reactions.

[0005] Because polishing pads directly interact with the surface of the workpiece, they can affect the machining quality of the workpiece's surface. For example, the polishing rate of the CMP process can be sensitively affected by the components contained in the polishing pad, the physical properties of the polishing pad, or the size, distribution, and content of the pores.

[0006] Recently, as semiconductor devices have become more highly integrated, miniaturized, or multilayered, each layer constituting the semiconductor device contains complex and fine circuit patterns. Therefore, to improve the performance of semiconductor devices, it is necessary to ensure connectivity between the circuit patterns in each layer of the semiconductor device, as well as adhesion between layers, and to improve the surface characteristics of the circuit patterns.

[0007] Therefore, to improve the bonding stability between the layers constituting the semiconductor device, the connectivity between electrodes and wiring, and the uniformity at the bonding interface, more refined and reliable polishing quality is required. This necessitates adjusting the physical properties, composition, and pore shape of the polishing pad to an optimal range. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Korean Registered Patent No. 10-0418648 [Overview of the project] [Problems that the invention aims to solve]

[0009] The technical problem that the present invention aims to solve is to provide a polishing pad that has specific polishing properties for a film to be polished containing dissimilar materials with different coefficients of thermal expansion, and that can generate a predetermined dishing on the surface of the film to be polished.

[0010] Furthermore, the invention provides a method for manufacturing a useful semiconductor device on a target film (semiconductor substrate) by achieving an appropriate polishing ratio using the aforementioned polishing pad. [Means for solving the problem]

[0011] A polishing pad according to one embodiment of the present invention includes a polishing layer, and the dishing value may be 0.5 nm to 3.5 nm.

[0012] The aforementioned dishing value is 1.0 × 10 -7 mm / mm℃~3.5×10 -6 A first region having a thermal expansion coefficient of mm / mm℃, and 4.0 × 10 -6 mm / mm℃~3.0×10 -5 The measurement is the difference (nm) in thickness change between the first and second regions when a workpiece, including a second region having a thermal expansion coefficient of mm / mm℃, is polished with the polishing pad for 10 seconds under the conditions of a polishing pad rotation speed of 93 rpm, workpiece rotation speed of 87 rpm, and polishing load of 5.0 psi, while adding ceria slurry (ACS-580, manufactured by KC Tech) at a rate of 150 mL / min.

[0013] In a method for manufacturing a semiconductor device according to another embodiment of the present invention, the polishing pad described above can be attached to a platen. The semiconductor substrate can be attached to a head such that the surface of the semiconductor substrate to be polished contacts the polishing surface of the polishing pad. The surface of the semiconductor substrate to be polished can be polished by rotating the polishing pad and the semiconductor substrate relative to each other.

[0014] In a method for manufacturing a semiconductor device according to another embodiment of the present invention, the upper surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate can be polished with the polishing pad described above. The upper surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate can be placed facing each other and in contact. The first semiconductor substrate and the second semiconductor substrate can be heat-treated. [Effects of the Invention]

[0015] A polishing pad according to one embodiment of the present invention has a predetermined degree of polishing selectivity for each of dissimilar materials having different coefficients of thermal expansion, thereby allowing the dishing value to be adjusted within a predetermined range. Performing a CMP process using the polishing pad can improve the surface processing quality of semiconductor substrates such as wafers and the bonding quality of semiconductor elements.

[0016] For example, by adjusting the polishing amounts of metal and dielectric materials on the polished surface of a semiconductor substrate to a predetermined range, process defects in hybrid bonding can be prevented, and lifting and damage to the semiconductor substrate caused by differences in thermal expansion coefficients can be prevented. [Brief explanation of the drawing]

[0017] [Figure 1a] Figure 1a is a schematic diagram illustrating the dishing value of the present invention. [Figure 1b] Figure 1b is a schematic diagram illustrating the dishing values ​​of the present invention. [Figure 2a] Figure 2a is a diagram illustrating semiconductor substrate bonding defects caused by dishing values. [Figure 2b] Figure 2b is a diagram illustrating semiconductor substrate bonding defects caused by dishing values. [Figure 2c] Figure 2c is a diagram illustrating semiconductor substrate bonding defects caused by dishing values. [Figure 3a] Figure 3a is a diagram illustrating bonding defects in semiconductor substrates due to dishing values. [Figure 3b] Figure 3b is a diagram illustrating bonding defects in semiconductor substrates due to dishing values. [Figure 3c] Figure 3c is a diagram illustrating bonding defects in semiconductor substrates due to dishing values. [Figure 4] Figure 4 is a schematic cross-sectional view showing a polishing pad according to one embodiment of the present invention. [Figure 5] Figure 5 is a schematic process flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] Figure 6 is a schematic process flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] Figure 7 shows a cross-sectional image obtained by 3D-CT scanning the polishing pad of Example 1. [Modes for carrying out the invention]

[0018] The present invention will be described in detail below with reference to various implementation examples and embodiments. The implementation examples are not limited to those disclosed below and can be modified in various forms as long as the essence of the invention is not altered.

[0019] In this specification, terms used to refer to each component are used to distinguish them from other components and are not intended to limit the examples of implementation. Furthermore, in this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0020] In this specification, when a part "includes" a component, this means, unless otherwise stated, that it may include other components rather than excluding them.

[0021] In this specification, any description of one component being formed above / below another, or being connected or joined to one another, includes all instances of direct or indirect formation, connection, or joining between these components. Furthermore, the criteria for above / below each component should be understood to vary depending on the direction from which the object is observed.

[0022] All numerical ranges indicating physical properties, dimensions, etc., of the constituent components described herein should be understood to be modified by the term "approximately" in all cases, unless otherwise specified.

[0023] In the numerical ranges that limit the size, physical properties, etc., of the components described herein, if numerical ranges limited only by upper limits and numerical ranges limited only by lower limits are given as separate examples, it should be understood that the numerical ranges formed by combining these upper and lower limits are also included in the exemplary ranges.

[0024] In this specification, terms such as "first," "second," etc., are used to describe various components, and such components should not be limited by such terms. The terms are used for the purpose of distinguishing one component from another.

[0025] In the drawings of this specification, the shape, size, proportions, etc., of each component are exaggerated, omitted, or schematically illustrated for the sake of explanation, and the realization of the present invention is not limited to the shape, size, proportions, etc., of each component shown in the drawings.

[0026] [Polishing pad] The polishing pad according to an embodiment of the present invention includes a polishing layer, and the dishing value may be 0.5 nm to 3.5 nm.

[0027] The dishing value is the difference (nm) in thickness change between the first region and the second region measured when the surface of a workpiece, which includes a first region having a first coefficient of thermal expansion and a second region having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion, is polished with the polishing pad for 10 seconds.

[0028] For example, the dishing value can be expressed by the following formula 1. [Formula 1] Disping value (nm) = Thickness change of the second region (nm) - Thickness change of the first region (nm)

[0029] The polishing process for the workpiece can be carried out by polishing for 10 seconds while adding ceria slurry under the conditions of a polishing pad rotation speed of 93 rpm, a workpiece rotation speed of 87 rpm, and a polishing load of 5.0 psi.

[0030] ACS-580 (KC Tech) can be used as the ceria slurry, and the injection rate of the ceria slurry may be 150 mL / min. In one implementation example, the thickness change can be measured using a CMP system (POLI-400LM, G&P Technology). The measurement temperature may be 20°C, but is not limited to this.

[0031] In the polishing process, the first and second regions can be exposed from the surface (polished surface) of the workpiece toward the polishing pad. For example, the dishing value can be measured by polishing the polished surface using the polishing pad while the upper surfaces of the first and second regions are at the same height or level as the polished surface of the workpiece.

[0032] "Thickness change" can mean the difference in thickness between the thickness of the area to be polished before polishing and the thickness of the most polished portion of the area to be polished after polishing. For example, the thickness change can mean the reduction in thickness in the intermediate portion of the area to be removed by the polishing process when the intermediate portion is polished more than the edge portion, and it can also mean the reduction in thickness in the edge portion when the edge portion of the area to be removed is polished more than the intermediate portion.

[0033] In one implementation example, if the first and second regions have the same thickness before the polishing process, the difference in the thickness change of the first and second regions (dishing value) may be calculated as the difference between the minimum thickness of the first region and the minimum thickness of the second region measured after the polishing process.

[0034] "Dishing" refers to the phenomenon in which, after the CMP process on a semiconductor substrate, the upper surface of a metal layer on the semiconductor substrate is not at the same level as the upper surface of a dielectric material such as an oxide or nitride, resulting in the formation of a concave or convex recess. The aforementioned "dishing value" can numerically represent the aforementioned dishing, allowing for the quantitative evaluation of the degree of dishing caused by the CMP process, such as the deviation from flatness.

[0035] Figures 1a and 1b are schematic diagrams illustrating the dishing values. Specifically, Figure 1a is a schematic cross-sectional view of the workpiece before the polishing process, and Figure 1b is a schematic cross-sectional view of the workpiece after the polishing process.

[0036] Referring to Figure 1a, the workpiece 100 includes a base substrate 105 and may include a first region 110 having the first coefficient of thermal expansion and a second region 120 having the second coefficient of thermal expansion on the surface of the base substrate 105. The surface of the workpiece 100 can be polished by the polishing surface 205 of the polishing pad 200 contacting the surface of the workpiece 100 and rotating relative to it.

[0037] Referring to Figure 1b, the workpiece 100 may be polished and its thickness reduced during the polishing process. In Figure 1b, the dotted line (BP) indicates the height of the workpiece 100 before the polishing process. Due to the difference in polishing rates between the first region 110 and the second region 120, the upper surfaces of the first region 110 and the second region 120 may be at different levels after the polishing process, and a recess 125 may be formed in the second region 120. In Figure 1b, the second region 120 is shown to have a concave recess 125, but this is not the only option, and a convex recess 125 may also be formed depending on the physical properties of the polishing pad, the conditions of the polishing process, the materials or properties of the first and second regions, etc.

[0038] The dishing value can be calculated by the difference (Dv) between the thickness reduction in the second region 120 and the thickness reduction in the first region 110. The reduced thickness represents the change in thickness at the most polished portion in each region.

[0039] By adjusting the dishing value within the aforementioned range using the polishing pad, surface defects such as scratches and chatter marks appearing on the surface of the workpiece (e.g., a semiconductor substrate) can be suppressed. Furthermore, the defect rate in the semiconductor substrate bonding process and the semiconductor device packaging process can be reduced.

[0040] For example, in the manufacturing process of semiconductor devices, semiconductor substrates such as wafers and dies may contain different materials with different properties on the same surface. Therefore, hybrid bonding may be used to join two or more semiconductor substrates together. In hybrid bonding, materials with similar properties in each semiconductor substrate can be bonded together. Specifically, metallic materials in the upper substrate (e.g., circuit wiring) and metallic materials in the lower substrate can be bonded together, and dielectric materials in the upper substrate (e.g., insulating film) and dielectric materials in the lower substrate can be bonded together.

[0041] In one implementation example, in hybrid bonding, semiconductor substrates attached to each other can be joined together by heat treatment. For example, by heat treatment, the metallic material and dielectric material on the surfaces of the upper and lower substrates can expand and connect or integrate. In this case, since the metallic material and inorganic material have different coefficients of thermal expansion (CTE), lifting or bonding defects may occur at the bonding interface due to differences in the coefficients of thermal expansion between regions. According to an implementation example of the present invention, by adjusting the dishing value of the polishing pad to the aforementioned range, bonding defects due to differences in the coefficients of thermal expansion between regions can be prevented even if the semiconductor substrate includes different regions on the bonding surface, thereby improving the adhesion between semiconductor substrates and the connection quality between circuit wirings, and potentially improving the performance of the semiconductor device.

[0042] Figures 2a and 2c illustrate bonding defects in semiconductor substrates when the dishing value is less than 0.5 nm. Specifically, Figure 2a is a schematic cross-sectional view of the semiconductor substrate after the polishing process, Figure 2b is a schematic cross-sectional view of the semiconductor substrate after the bonding process, and Figure 2c is a schematic cross-sectional view of the semiconductor substrate after the heat treatment process.

[0043] Referring to Figures 2a to 2c, if the dishing value is less than 0.5 nm, during the polishing process, a recess 125 may not be sufficiently formed in the region 120 of the semiconductor substrate surface that has a high coefficient of thermal expansion (e.g., a second coefficient of thermal expansion), for example, in a metallic region (see Figure 2a). As a result, with the upper substrate (UB) and lower substrate (LB) bonded together, a sufficient separation space 130 to accommodate the expansion due to heat treatment may not be secured between the region 120 with a high coefficient of thermal expansion (see Figure 2b). Therefore, during the heat treatment process, the region 120 with a high coefficient of thermal expansion pushes out from each other due to the difference in coefficients of thermal expansion, forming a void between the region with a low coefficient of thermal expansion (e.g., a first coefficient of thermal expansion), which may cause lifting or damage between the substrates (see Figure 2c).

[0044] For example, if the polishing rate for a region having a second coefficient of thermal expansion (e.g., a metal) is substantially similar to or lower than the polishing rate for a region having a first coefficient of thermal expansion (e.g., a dielectric), the dishing value may be less than 0.5 nm.

[0045] Figures 3a to 3c illustrate the bonding defects of semiconductor devices when the dishing value exceeds 3.5 nm. Specifically, Figure 3a is a schematic cross-sectional view of the semiconductor substrate after the polishing process, Figure 3b is a schematic cross-sectional view of the semiconductor substrate after the deposition process, and Figure 3c is a schematic cross-sectional view of the semiconductor substrate after the heat treatment process.

[0046] Referring to Figures 3a to 3c, if the dishing value exceeds 3.5 nm, a relatively deep recess 125 may be formed in the region 120 having a high coefficient of thermal expansion on the surface of the semiconductor substrate after polishing (see Figure 3a). Therefore, when semiconductor substrates are joined together, an excessively large separation space 130 may be formed between the semiconductor substrates in the region 120 having a high coefficient of thermal expansion (see Figure 3b). In that case, even if the region 120 having a high coefficient of thermal expansion expands due to heat treatment, it may not come into contact with each other, which may result in a poor connection between the semiconductor substrates (see Figure 3c).

[0047] For example, when the polishing rate for a region having a first coefficient of thermal expansion (e.g., a dielectric, etc.) is too high compared to the polishing rate for a region having a second coefficient of thermal expansion (e.g., a metal, etc.), the dishing value may exceed 3.5 nm.

[0048] The first coefficient of thermal expansion is 1.0×10 -7 mm / mm·°C to 3.5×10 -6 mm / mm·°C, and the second coefficient of thermal expansion may be 4.0×10 -6 mm / mm·°C to 3.0×10 -5 mm / mm·°C. The dishing value for the region having a coefficient of thermal expansion within the above range is adjusted within the range, and the expanded volume of each region during the heat treatment process can appropriately fill the gap between the semiconductor substrates. Therefore, the bonding stability and connectivity between the semiconductor substrates can be further improved.

[0049] For example, the first coefficient of thermal expansion may be 3.5×10 -6 mm / mm·°C or less, 3.0×10 -6 mm / mm·°C or less, 1.0×10 -6 mm / mm·°C or less, 9.0×10 -7 mm / mm·°C or less, 8.0×10 -7 mm / mm·°C or less, or 7.0×10 -7 mm / mm·°C or less. For example, the first coefficient of thermal expansion may be 1.0×10 -7 mm / mm·°C or more, 1.5×10 -7 mm / mm·°C or more, 2.0×10 -7 mm / mm·°C or more, 3.0×10 -7 mm / mm·°C or more, or 4.0×10 -7 mm / mm·°C or more.

[0050] In one implementation example, the first coefficient of thermal expansion is 1.5×10 -7 mm / mm·°C to 3.0×10 -6 mm / mm·°C, 2.0×10 -7 mm / mm·°C to 1.0×10 -6 mm / mm·°C, 3.0×10 -7 mm / mm·°C to 9.0×10 -7 mm / mm·°C, 4.0×10-7 mm / mm℃~7.0×10 -7 It can be mm / mm℃.

[0051] In some realizations, the region having the first coefficient of thermal expansion may include a dielectric material. For example, the dielectric may include oxides, nitrides, and more specifically, silicon oxide (SiO2), silicon nitride (SiN x ) may include, etc.

[0052] For example, the second coefficient of thermal expansion is 4.0 × 10 -6 mm / mm℃ or higher, 5.0 × 10 -6 mm / mm℃ or higher, 1.0 × 10 -5 mm / mm℃ or higher, 1.5 × 10 -5 mm / mm℃ or higher, or 1.6 × 10 -5 It may be greater than or equal to mm / mm℃. For example, the second coefficient of thermal expansion is 3.0 × 10 -5 mm / mm℃ or less, 2.8×10 -5 mm / mm℃ or less, 2.5×10 -5 mm / mm℃ or less, 2.4×10 -5 mm / mm℃ or less, 2.2×10 -5 mm / mm℃ or less, or 2.1 × 10 -5 It may be less than mm / mm℃.

[0053] In one implementation example, the second thermal expansion coefficient is 5.0 × 10 -6 mm / mm℃~2.8×10 -5 mm / mm℃, 1.0 × 10 -5 mm / mm℃~2.5×10 -5 mm / mm℃, 1.5 × 10 -5 mm / mm℃~2.4×10 -5 mm / mm℃, 1.6 × 10 -5 mm / mm℃~2.1×10 -5 It can be mm / mm℃.

[0054] In some implementations, the region having the second coefficient of thermal expansion may include metal. For example, the metal may include copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), and the like.

[0055] The first and second thermal expansion coefficients may be measured using a thermomechanical analyzer (TMA) at a heating rate of 10°C / min. Specifically, the thermal expansion coefficients may be measured using the penetration method under conditions of a heating rate of 10°C / min, a load of 50g, and a pin wire of 0.5mmφ.

[0056] In one implementation example, the difference between the first thermal expansion coefficient and the second thermal expansion coefficient is 1.0 × 10⁻⁶. -6 mm / mm℃ or higher, 5.0 × 10 -6 mm / mm℃ or higher, 9.0 × 10 -6 mm / mm℃ or higher, 1.0 × 10 -5 mm / mm℃ or higher, 1.3 × 10 -5 mm / mm℃ or higher, or 1.5 × 10 -5 The temperature is above mm / mm℃ and 2.7 × 10 -5 mm / mm℃ or less, 2.5×10 -5 mm / mm℃ or less, 2.2×10 -5 mm / mm℃ or less, 2.0×10 -5 mm / mm℃ or less, or 1.8 × 10 -5 It may be less than mm / mm℃.

[0057] In some implementations, the dishing value may be 0.5 nm or more, 1.0 nm or more, 1.5 nm or more, 1.8 nm or more, 2.0 nm or more, or 2.1 nm or more. This reduces surface roughness in regions with a low coefficient of thermal expansion, and further improves surface flatness. In addition, sufficient recess space is secured in regions with a high coefficient of thermal expansion, allowing the volume expanded by heat treatment to be easily accommodated. Therefore, the bonding stability between semiconductor substrates can be further improved.

[0058] In some implementations, the dishing value may be 3.5 nm or less, 3.3 nm or less, 3.0 nm or less, 2.9 nm or less, 2.7 nm or less, or 2.5 nm or less. This prevents erosion during the polishing process and ensures that appropriate vertical separation spaces are formed between regions with high thermal expansion coefficients during the substrate bonding process, thereby further enhancing contact during the heat treatment process. Consequently, poor connections between circuit wirings on the semiconductor substrate can be prevented, and bonding stability can be further improved.

[0059] In one implementation example, the dishing value may be 0.5nm to 3.5nm, 1.0nm to 3.5nm, 1.0nm to 3.3nm, 1.0nm to 3.0nm, 1.5nm to 3.0nm, 1.8nm to 3.0nm, 1.8nm to 2.9nm, 2.0nm to 2.7nm, 2.0nm to 2.5nm, or 2.1nm to 2.5nm.

[0060] The polished layer may have a porous structure containing multiple pores. In some implementations, the average diameter (Dn) of the multiple pores is 50 ) can be 18 μm to 30 μm.

[0061] The average diameter of the aforementioned pores (Dn 50 The area can be obtained by 3D-CT scanning. For example, the area per unit area of ​​the polished layer (1 cm²) 2 Based on this, pores within the polished layer can be measured using 3D-CT scanning, and the diameter, area, volume, and number of pores can be calculated using CT data analysis and visualization software such as volume graphics. For example, the volume of a pore with diameter r is 4πr 3 The average diameter (Dn 50 ) can be defined as the diameter of a stoma at which the volume fraction reaches 50% in the volume distribution obtained by accumulating stomata in ascending order of diameter.

[0062] The average diameter of the pores can affect the surface condition of the polishing pad, the fluidity of the polishing slurry, and the polishing efficiency. For example, as the average diameter of the pores decreases, the depth, width, and roughness of the grooves formed on the surface of the polishing layer decrease, the spacing and number of grooves increase, and the real contact area between the polishing pad and the workpiece can increase. By adjusting the average diameter of the multiple pores contained in the polishing layer to within the range described above, the fluidity of the polishing slurry can be ensured and the occurrence of surface bonding can be suppressed, while the pressure applied to the workpiece can be distributed, making it easier to control the polishing rate and surface flatness for each workpiece within a desired range.

[0063] In one implementation example, the average diameter (Dn) of the plurality of pores 50 ) may be 18μm~29μm, 18μm~27μm, 18μm~26μm, 19μm~26μm, 19μm~25μm, 20μm~25μm, 21μm~25μm, 21μm~24μm, 22μm~24μm, or 22μm~23μm.

[0064] Dn of the plurality of pores 10 The size of the Dn can be 5μm-21μm, 10μm-20μm, 15μm-20μm, 15μm-19μm, 15μm-18μm, or 16μm-18μm. 10 This can be defined as the diameter of a stoma at a volume fraction of 10% in the volume distribution obtained by accumulating stomata in order of increasing diameter.

[0065] Dn of the plurality of pores 90 The size of Dn can be 20 μm to 45 μm, 23 μm to 45 μm, 23 μm to 40 μm, 25 μm to 40 μm, 27 μm to 40 μm, 27 μm to 35 μm, or 27 μm to 30 μm. 90 This can be defined as the diameter of a stoma at which the volume fraction reaches 90% in the volume distribution obtained by accumulating stomata in order of increasing diameter.

[0066] Dn of the plurality of pores 10 , Dn 50 and Dn 90The size and distribution of pores are controlled within a certain range, allowing for adjustment of polishing properties to a desired degree, for example, for metal and dielectric films, and making it easier to provide dishing values ​​within the aforementioned range.

[0067] In some implementations, the plurality of pores may include a first pore with a diameter of 16.9 μm or less, a second pore with a diameter of 27.4 μm or more, and a third pore with a diameter greater than 16.9 μm and less than 27.4 μm. Based on the total volume of the plurality of pores, the total volume of the first pore may be 10 volume% or less, and the total volume of the second pore may be 10 volume% or less. The volumes of the first pore and the second pore can be obtained by the pore volume distribution described above. Within the above range, the formation of pores with diameters that are too small or too large relative to the average diameter can be controlled, and the degree of polishing for each region can be controlled to be constant by having a relatively uniform size for the plurality of pores.

[0068] In one implementation example, based on the total volume of the plurality of pores, the total volume of the first pores may be 5% to 10% by volume, and the total volume of the second pores may be 5% to 10% by volume or less. Within this range, the pores are distributed more uniformly within the polishing layer, which improves polishing efficiency and makes it easier to control the dishing value.

[0069] The polishing layer of the polishing pad may contain a resin. For example, the polishing layer may contain a urethane-based resin.

[0070] In one embodiment, the polishing layer may include a cured product of a composition comprising a urethane-based prepolymer, a curing agent, and a foaming agent. The foaming agent may cause pores to form within the polishing layer.

[0071] By adjusting the composition, physical properties, and pore shape, size, distribution, and content of the polishing layer, the polishing selectivity ratio for dissimilar materials with different thermal expansion coefficients, such as metals and dielectrics, can be adjusted. This allows for appropriate adjustment of the surface flatness and recesses of the workpiece after the CMP process, and the dishing value can be easily controlled within the aforementioned range.

[0072] Figure 4 is a schematic cross-sectional view showing a polishing pad according to an embodiment of the present invention. Referring to Figure 4, the polishing pad 10 may include a polishing layer 12 as a top pad layer and a support layer 16 as a sub-pad layer below the polishing layer 12.

[0073] The thickness of the polishing layer 12 can be 0.5 mm to 5 mm. For example, the thickness of the polishing layer 12 can be 0.8 mm to 4 mm, 1 mm to 3 mm, 1.5 mm to 2.5 mm, 1.7 mm to 2.3 mm, or 2.0 mm to 2.2 mm. As the thickness of the polishing layer 12 increases, the size deviation of the pores in the upper and lower regions within the polishing layer 12 may increase, and as the thickness decreases, the physical properties of the polishing layer 12 may deteriorate. By satisfying the above range for the thickness of the polishing layer 12, it is possible to ensure the physical properties of the polishing pad 10 required for the CMP process while minimizing the particle size deviation of the pores.

[0074] The support layer 16 is positioned beneath the polishing layer 12 and stably supports the polishing layer 12, while also absorbing and / or dispersing impacts applied to the polishing layer 12. The support layer 16 may be manufactured using a nonwoven fabric, suede, or porous pad.

[0075] The thickness of the support layer 16 may be, for example, 0.5 mm to 4 mm, 0.6 mm to 3.5 mm, 0.8 mm to 3 mm, or 1 mm to 2 mm. Within this range, the polishing pad 10 can be made lighter, and the support layer 16 can stably support the polishing layer 12.

[0076] In some implementations, the polishing pad 10 may further include an adhesive layer 14 between the polishing layer 12 and the support layer 16. The adhesive layer 14 may contact the lower surface of the polishing layer 12 and the upper surface of the support layer 16 to bond the polishing layer 12 and the support layer 16. Furthermore, the adhesive layer 14 may also function as a barrier layer to prevent the polishing slurry supplied to the polishing layer 12 from flowing into the support layer 16. In one implementation, the adhesive layer 14 may be formed using a hot-melt adhesive composition.

[0077] The hot-melt adhesive composition may include commonly known hot-melt adhesives. In one example, the hot-melt adhesive may include polyurethane resins, polyester resins, ethylene-vinyl acetate resins, polyamide resins, and / or polyolefin resins. These may be used individually or in combination of two or more.

[0078] The thickness of the adhesive layer 14 may be, for example, 5 μm to 30 μm, 10 μm to 30 μm, 20 μm to 27 μm, or 23 μm to 25 μm. Within this range, the bonding force between the polishing layer 12 and the support layer 16 is further enhanced, and the polishing pad 10 can be made even lighter.

[0079] [Method for manufacturing polishing pads] In a method for manufacturing an abrasive pad according to an embodiment of the present invention, a raw material mixture can be produced by mixing a urethane-based prepolymer, a curing agent, and a foaming agent.

[0080] A "prepolymer" generally refers to a polymer with a relatively low molecular weight whose degree of polymerization has been stopped at an intermediate stage to facilitate molding in the production of a type of final molded product. Prepolymers can be molded on their own or after reacting with other polymerizable compounds. For example, a prepolymer can be produced by reacting an isocyanate compound with a polyol.

[0081] The aforementioned urethane-based prepolymer can be produced by reacting an isocyanate compound with a polyol.

[0082] The isocyanate compound may include, for example, one or more compounds selected from the group consisting of toluene diisocyanate (TDI), naphthalene-1,5-diisocyanate, p-phenylene diisocyanate, tolidine diisocyanate, 4,4'-diphenyl methane diisocyanate, hexamethylene diisocyanate, dicyclohexylmethane diisocyanate, and isophorone diisocyanate.

[0083] The polyol may include, for example, one or more compounds selected from the group consisting of polyether polyols, polyester polyols, polycarbonate polyols, and acrylic polyols.

[0084] In one implementation example, the polyol may have a weight-average molecular weight (Mw) of 300 g / mol to 3000 g / mol.

[0085] In one example, the urethane-based prepolymer may be a polymer prepared by reacting an isocyanate compound containing toluene diisocyanate with a polyol containing polytetramethylene ether glycol.

[0086] In some implementations, the urethane-based prepolymer may have a weight-average molecular weight of 500 g / mol to 3000 g / mol. Specifically, the urethane-based prepolymer may have a weight-average molecular weight of 600 g / mol to 2000 g / mol or 800 g / mol to 1000 g / mol.

[0087] In one implementation example, the isocyanate end group (terminal NCO) content (NCO%) of the urethane-based prepolymer can be 5% to 15% by weight based on the total weight of the urethane-based prepolymer. For example, the terminal NCO content (NCO%) of the urethane-based prepolymer can be 6% to 13% by weight, 7% to 12% by weight, 7.5% to 11% by weight, or 8% to 10% by weight. By satisfying the above ranges for the weight-average molecular weight and NCO% of the urethane-based prepolymer, the polishing rate according to the workpiece can be adjusted to a desired range in the CMP process, and the dishing value of the polishing pad can be appropriately adjusted.

[0088] The foaming agent may include a solid-phase foaming agent. For example, the multiple pores in the polishing pad may originate from the solid-phase foaming agent.

[0089] When using a solid-phase foaming agent, the shape, size, content, and distribution of pores can be controlled more precisely than when using a liquid-phase or gas-phase foaming agent. For example, the shape, size, content, and distribution of pores can vary depending on the particle size, distribution, shape, constituent materials, and elemental composition of the solid-phase foaming agent. Furthermore, since the solid-phase foaming agent has an outer wall and voids, it can maintain the shape of the micropores contained in the polished layer even during the CMP process, thus further improving polishing performance.

[0090] In some implementations, the solid-phase foaming agent may be purified by a purification system. This allows the solid-phase foaming agent to have a uniform density, average particle size, solvent resistance, or heat resistance.

[0091] In one implementation example, the average particle size (D) of the solid-phase foaming agent 50The particle size can be 1 μm to 20 μm. The average particle size can be defined as the particle size at a volume fraction of 50% in the volume particle size distribution obtained by accumulating particles in ascending order of particle size. For example, the D of the solid-phase foaming agent 50 The particle size can be 1 μm to 15 μm, 5 μm to 15 μm, 5 μm to 10 μm, or 6 μm to 9 μm. For example, the purification system can control the average particle size of the solid-phase foaming agent to fall within the range by removing particles that are too small or too large.

[0092] D of the solid-phase foaming agent 50 If the D of the solid-phase foaming agent is within the aforementioned range, the polishing rate and flatness can be more easily adjusted within the desired range. For example, the D of the solid-phase foaming agent 50 This can adjust the size, distribution, shape, or content of pores within the polishing layer, potentially affecting the dishing value of the workpiece.

[0093] In some implementations, the solid-phase foaming agent may contain thermally expanded particles. When the solid-phase foaming agent contains thermally expanded particles, the D of the solid-phase foaming agent 50 This may refer to the average particle size in a thermally expanded state. The thermally expanded particles may be obtained by heating and expanding thermally expandable particles.

[0094] The thermally expandable particles may include an outer shell containing a thermoplastic resin and a foaming agent encapsulated within the outer shell. The thermoplastic resin may include one or more copolymers selected from the group consisting of vinylidene chloride copolymers, acrylonitrile copolymers, methacrylonitrile copolymers, and acrylic copolymers.

[0095] In one embodiment, the foaming agent sealed inside may contain hydrocarbon compounds having 1 to 7 carbon atoms. For example, the foaming agent sealed inside may include ethane, ethylene, propane, propene, n-butane, isobutane, butene, isobutene, n-pentane, isopentane, neopentane, n-hexane, heptane, and petroleum ether. It may contain low molecular weight hydrocarbons such as ether; chlorofluoro hydrocarbons such as trichlorofluoromethane (CCl3F), dichlorodifluoromethane (CCl2F2), chlorotrifluoromethane (CClF3), and tetrafluoroethylene (CClF2-CClF2); and tetramethylsilane, trimethylethylsilane, trimethylisopropylsilane, trimethyl-n-propylsilane, etc. These may be included individually or in combination of two or more.

[0096] In some implementation examples, the density of the solid-phase foaming agent is 25 kg / m³. 3 The following is possible. This prevents pore aggregation and clumping during the mixing and curing processes of the raw material mixture, and allows for the formation of pores with uniform size and distribution within the polished layer. For example, the density of the solid-phase foaming agent is 0 kg / m³. 3 Over 25 kg / m 3 Below 5kg / m 3 ~25kg / m 3 , or 10 kg / m 3 ~25kg / m 3 The following are possible:

[0097] In some implementations, the thermal decomposition start temperature (Tstart) of the solid-phase foaming agent may be between 95°C and 110°C. This thermal decomposition start temperature is the temperature at which the weight of the solid-phase foaming agent begins to decrease when heated from 0°C at a heating rate of 10°C / min in a nitrogen gas atmosphere. For example, the thermal decomposition start temperature of the solid-phase foaming agent may be between 98°C and 110°C, 100°C and 110°C, or 100°C and 108°C.

[0098] In some implementations, the maximum thermal decomposition temperature (Tmax) of the solid-phase foaming agent may be between 130°C and 170°C. The maximum thermal decomposition temperature of the solid-phase foaming agent may be the temperature at which the solid-phase foaming agent completely dissolves when heated from 0°C at a heating rate of 10°C / min under a nitrogen gas atmosphere. For example, the maximum thermal decomposition temperature of the solid-phase foaming agent may be between 135°C and 170°C, 140°C and 165°C, or 143°C and 160°C.

[0099] If the thermal decomposition start temperature and maximum thermal decomposition temperature of the solid-phase foaming agent are within the aforementioned range, the pore characteristics, such as the size, distribution, and content of the pores formed in the polishing pad, can be more precisely controlled. Therefore, polishing pads that provide a desired range of polishing amount and dishing value can be easily manufactured.

[0100] The content of the solid-phase foaming agent may be 0.5 to 5.0 parts by weight based on 100 parts by weight of the raw material mixture. For example, the content of the solid-phase foaming agent may be 0.5 to 3.5 parts by weight, 0.5 to 3.0 parts by weight, 0.5 to 2.0 parts by weight, 0.5 to 1.5 parts by weight, or 0.8 to 1.4 parts by weight based on 100 parts by weight of the raw material mixture. Within this range, the hardness, tensile strength, and elongation of the polishing pad will not decrease, and the size, distribution, and content of pores in the polishing layer can be controlled to a desired range.

[0101] The curing agent may include amine compounds and / or alcohol compounds. For example, the curing agent may include one or more compounds selected from the group consisting of aromatic amines, aliphatic amines, aromatic alcohols, and aliphatic alcohols.

[0102] For example, the curing agent may be 4,4'-methylenebis(2-chloroaniline) (MOCA), diethyltoluenediamine, diaminodiphenylmethane, diaminodiphenyl sulfone, or m-xylylenediamine. It may contain one or more substances selected from the group consisting of diamine, isophoronediamine, ethylenediamine, diethylenetriamine, triethylenetetramine, polypropylenediamine, polypropylenetriamine, ethyleneglycol, diethyleneglycol, dipropyleneglycol, butanediol, hexanediol, glycerine, trimethylolpropane, and bis(4-amino-3-chlorophenyl)methane.

[0103] The content of the curing agent may be 3.0 to 40 parts by weight based on 100 parts by weight of the raw material mixture. For example, the content of the curing agent may be 5.0 to 35 parts by weight, or 7.0 to 30 parts by weight, based on 100 parts by weight of the raw material mixture. Within this range, the physical properties of the polishing pad can be further improved, and a polishing pad having, for example, the hardness, elongation, or modulus required in the CMP process can be provided.

[0104] The urethane-based prepolymer and curing agent can be mixed in a molar equivalent ratio of 1:0.8 to 1.2 or 1:0.9 to 1.1, based on the number of moles of reactive groups within each molecule. The "based on the number of moles of reactive groups" means, for example, using the number of moles of isocyanate groups in the urethane-based prepolymer and the number of moles of reactive groups (amine groups, alcohol groups, etc.) in the curing agent as the basis. The urethane-based prepolymer and curing agent can be added during the mixing process to satisfy the aforementioned molar equivalent ratio and react with each other. By performing the curing reaction at this reaction ratio, the curing reaction is optimized, and a polishing pad with the physical properties required in the CMP process can be provided.

[0105] In some implementations, the raw material mixture may contain, based on 100 parts by weight of the raw material mixture, 55 to 96.5 parts by weight of the urethane-based prepolymer, 0.5 to 5.0 parts by weight of the solid-phase foaming agent, and 3.0 to 40 parts by weight of the curing agent. For example, the raw material mixture may contain, based on 100 parts by weight of the raw material mixture, 66.5 to 96.5 parts by weight of the urethane-based prepolymer, 0.5 to 3.5 parts by weight of the solid-phase foaming agent, and 5.0 to 35 parts by weight of the curing agent.

[0106] In some implementations, the raw material mixture may further contain a surfactant. The overlapping and clumping of pores formed by the surfactant can be prevented. For example, a silicone-based nonionic surfactant can be used as the surfactant, and various other surfactants can be selected depending on the physical properties required for the polishing pad.

[0107] As the silicone-based nonionic surfactant, a silicone-based nonionic surfactant having a hydroxyl group may be used alone, or a silicone-based nonionic surfactant having a hydroxyl group and a silicone-based nonionic surfactant not having a hydroxyl group may be used together.

[0108] The hydroxyl group-containing silicone-based nonionic surfactant is not particularly limited as long as it has excellent compatibility with isocyanate-containing compounds and active hydrogen compounds and is widely used in the polyurethane technology field. In one example, a commercially available substance that is the hydroxyl group-containing silicone-based nonionic surfactant is, for example, Dow Corning's DOW CORNING 193 (silicone glycol copolymer, liquid phase; specific gravity at 25°C: 1.07; viscosity at 20°C: 465 mm²). 2 Examples include the DC-193 (flash point: 92°C).

[0109] Examples of commercially available silicone-based nonionic surfactants that do not have hydroxyl groups include, for example, Dow Corning's DOW CORNING 190 (silicone glycol copolymer, Gardner color number: 2; specific gravity at 25°C: 1.037; viscosity at 25°C: 2000 mm²). 2 Its characteristics include: flash point: 63°C or higher; inverse solubility point (1.0% aqueous solution): 36°C (hereinafter referred to as DC-190).

[0110] The amount of the surfactant may be 0.1 to 2 parts by weight, 0.2 to 1.8 parts by weight, 0.2 to 1.7 parts by weight, 0.2 to 1.6 parts by weight, or 0.2 to 1.5 parts by weight, based on 100 parts by weight of the raw material mixture. Within this range, pores derived from the foaming agent can be stably formed and maintained during the curing or molding process.

[0111] The raw material mixture can be reacted to form a solid-phase polyurethane. For example, in the reaction process, the isocyanate-terminated groups (NCO groups) of the urethane-based prepolymer can react with amine groups, alcohol groups, etc., of the curing agent. The solid-phase foaming agent can be uniformly dispersed within the solid-phase polyurethane without participating in the curing reaction, forming multiple pores.

[0112] In one implementation example, the solid-phase polyurethane can be manufactured in sheet form. In some implementations, the molding or curing process may be carried out using a mold. For example, the raw material mixture may be injected into a mold for molding. Specifically, the raw material mixture, stirred with a mixing head or the like, may be discharged into the mold to fill the inside of the mold.

[0113] In one implementation example, during the process of mixing and dispersing the urethane-based prepolymer, solid-phase foaming agent, and curing agent, the rotation speed of the mixing head can be 500 rpm to 10000 rpm, specifically 1000 rpm to 9000 rpm, 2000 rpm to 9000 rpm, 3000 to 8000 rpm, 4000 to 8000 rpm, or 5000 rpm to 7000 rpm. Within this range, the shape of the pores contained in the polishing pad can be more easily controlled within a desired range.

[0114] The reaction between the urethane-based prepolymer and the curing agent is completed within the mold, and a molded body solidified according to the shape of the mold can be obtained.

[0115] The molded body can be sliced ​​or cut to process it into sheets for the manufacture of polishing pads. For example, the raw material mixture can be molded in a mold with a height of 5 to 50 times the thickness of the polishing pad to be finally manufactured, and the molded body can be sliced ​​at intervals of the same thickness to simultaneously produce a large number of polishing pad sheets. In one implementation example, a reaction retarder may be further mixed in as a reaction rate modifier to ensure sufficient solidification time.

[0116] The reaction rate modifier may include one or more selected from the group consisting of triethylenediamine, dimethylethanolamine, tetramethylbutanediamine, 2-methyl-triethylenediamine, dimethylcyclohexylamine, triethylamine, triisopropanolamine, 1,4-diazabicyclo(2,2,2)octane, bis(2-methylaminoethyl) ether, trimethylaminoethylethanolamine, N,N,N',N'',N''-pentamethyldiethyldimethylaminoethylamine, dimethylaminopropylamine, benzyldimethylamine, N-ethylmorpholine, N,N-dimethylaminoethylmorpholine, N,N-dimethylcyclohexylamine, 2-methyl-2-azanorbornene, dibutyltin dilaurate, stanas octoate, dibutyltin diacetate, dioctyltin diacetate, dibutyltin malate, dibutyltin di-2-ethylhexanoate, and dibutyltin dimercaptide.

[0117] [Manufacturing method for semiconductor element] In a method for manufacturing a semiconductor device according to an embodiment of the present invention, the semiconductor substrate can be polished using the aforementioned polishing pad.

[0118] Figure 5 is a schematic process flowchart illustrating the manufacturing method of a semiconductor device.

[0119] Referring to Figure 5, the polishing pad including the polishing layer can be mounted on the platen (for example, in step S11). The semiconductor substrate can be positioned on the polishing pad such that the polishing surface of the polishing pad and the surface of the semiconductor substrate (the surface to be polished) are in contact (for example, in step S12). The surface of the semiconductor substrate can be in direct contact with the polishing surface of the polishing layer.

[0120] In one implementation example, polishing slurry can be sprayed onto the polishing pad for polishing. In one implementation example, the flow rate of the polishing slurry can be adjusted to within the range of 10 mL / min to 1000 mL / min, or 50 mL / min to 500 mL / min.

[0121] The polishing pad and the semiconductor substrate can be rotated relative to each other to polish the surface of the semiconductor substrate (for example, in step S13). In one implementation example, the rotation direction of the polishing pad and the rotation direction of the semiconductor substrate can be the same as each other. In one implementation example, the rotation direction of the polishing pad and the rotation direction of the semiconductor substrate can be opposite to each other.

[0122] In one implementation example, the rotation speed of the polishing pad and the rotation speed of the semiconductor substrate can be 10 rpm to 500 rpm, 30 rpm to 200 rpm, or 50 rpm to 150 rpm, respectively.

[0123] In one implementation example, the semiconductor substrate can be pressed against the polishing surface of the polishing pad with a predetermined load while being mounted on a polishing head. The load applied to the surface of the semiconductor substrate and the polishing surface of the polishing pad by the polishing head is 1 gf / cm 2 ~1000 gf / cm 2 or 10 gf / cm 2 ~800 gf / cm 2 and can be.

[0124] In one implementation example, in order to maintain the polishing surface of the polishing pad in a state suitable for polishing, the polishing surface of the polishing pad can be processed by a conditioner. The conditioning process for the polishing surface can be performed simultaneously with the polishing of the semiconductor substrate.

[0125] The semiconductor substrate may include a first region having the first coefficient of thermal expansion and a second region having the second coefficient of thermal expansion on its surface. By polishing the surface of the semiconductor substrate using the polishing pad, the polishing selection ratio of the first region and the second region calculated by the dishing value can be adjusted within a desired range on the surface of the semiconductor substrate after the polishing process.

[0126] In one implementation example, the first region may include a dielectric. For example, the first region may function as a dielectric layer or an insulating layer of a semiconductor substrate. The first region may include SiO2 or SiN x and can be.

[0127] In one implementation example, the second region may include a metal. For example, the second region may function as circuit wiring, contacts, etc., on a semiconductor substrate. The second region may include copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), etc.

[0128] Figure 6 is a schematic process flowchart illustrating the manufacturing method of a semiconductor device.

[0129] Referring to Figure 6, the surfaces of the first semiconductor substrate and the second semiconductor substrate can be polished using the polishing pad described in the aforementioned implementation example (for example, in step S21).

[0130] The polishing process for the first semiconductor substrate and the second semiconductor substrate may be the same as the process described in Figure 5. For example, the first semiconductor substrate may be mounted on the head so that its upper surface contacts the polishing surface of the polishing pad, and the upper surface of the first semiconductor substrate may be polished by rotating the first semiconductor substrate and the polishing pad relative to each other. For example, the second semiconductor substrate may be mounted on the head so that its bottom surface contacts the polishing surface of the polishing pad, and the bottom surface of the second semiconductor substrate may be polished by rotating the second semiconductor substrate and the polishing pad relative to each other.

[0131] In some implementations, the top surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate may each include a first region having a first coefficient of thermal expansion and a second region having a second coefficient of thermal expansion.

[0132] During the polishing process, recesses having a concave or convex shape may be formed in the second region. For example, the outermost surface of the first region and the outermost surface of the second region may be located at different levels or heights. By polishing with the polishing pad, the dishing value can be adjusted to a desired range on the top surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate after the polishing process.

[0133] The first semiconductor substrate and the second semiconductor substrate may be attached facing each other (for example, in step S22). For example, the first semiconductor substrate may be attached to the second semiconductor substrate such that the top surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate face each other.

[0134] In some implementations, the first semiconductor substrate and the second semiconductor substrate may be in contact with each other while the two semiconductor substrates are attached to each other. For example, the first region of the first semiconductor substrate may be adjacent vertically to the first region of the second semiconductor substrate, and the second region of the first semiconductor substrate may be adjacent vertically to the second region of the second semiconductor substrate.

[0135] In one implementation example, a predetermined pressure may be applied to the adhesion surface during the process of bonding the first semiconductor substrate and the second semiconductor substrate. This may form a chemical bond between the first regions. For example, a hydrogen bond may be formed between the first regions in contact with each other, thereby chemically linking the first region of the first semiconductor substrate and the first region of the second semiconductor substrate.

[0136] At least a portion of the second region of the first semiconductor substrate can be physically separated from the second region of the second semiconductor substrate. For example, since the second regions of the first and second semiconductor substrates each have a recess shape, a gap can be formed at the interface between the semiconductor substrates by the second region.

[0137] The first semiconductor substrate and the second semiconductor substrate can be heat-treated to bond them together (for example, in step S23). During the heat treatment process, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate expand relative to each other, filling the gap between the semiconductor substrates. For example, the second region has a high coefficient of thermal expansion and therefore may have a relatively higher coefficient of volume expansion compared to the first region. Thus, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate can come into contact with each other without bonding defects between the first regions. Furthermore, the heat treatment can cause mutual diffusion between the second regions, allowing them to bond or integrate with each other.

[0138] By polishing a semiconductor substrate using a polishing pad according to an embodiment of the present invention, a desired range of dishing values ​​can be obtained on the surface of each semiconductor substrate. This prevents bonding defects between semiconductor substrates, and the second regions can be closely joined vertically, potentially improving connectivity between circuit wiring, for example.

[0139] In some implementations, the heat treatment may be performed at a temperature of 100°C to 400°C. In one implementation, the heat treatment may be performed in steps. For example, the heat treatment may include a first heat treatment step performed at a temperature of 200°C or lower and a second heat treatment step performed at a temperature of 300°C or higher. For example, the first heat treatment may be performed at a temperature of 100°C to 200°C, followed by the second heat treatment at a temperature of 300°C to 400°C. Within this range, damage and delamination due to high temperatures can be prevented, and the contact between the second regions can be further improved. This further improves the bonding stability between semiconductor substrates, enabling the manufacture of high-quality semiconductor devices.

[0140] For example, in the first heat treatment process, the bonding force between the first regions may increase. In the first heat treatment temperature range, if covalent bonds and hydrogen bonds are formed between the first regions, stronger adhesion may be achieved. In the second heat treatment temperature range, interdiffusion is further promoted between the second regions, and the second regions may be connected more stably.

[0141] Furthermore, by adjusting the dishing value of the semiconductor substrate to the aforementioned range using the polishing pad, the thermal expansion amounts of the first region and the second region can be adjusted substantially similarly during the heat treatment process. The thermal expansion amount of each region can be calculated by multiplying the thermal expansion coefficient of each region (mm / mm°C) by the thickness of each region after polishing (nm) by the temperature change due to the heat treatment (°C).

[0142] In some implementation examples, the difference between the thermal expansion of the first region and the thermal expansion of the second region may be 1.0 nm or less, 0.8 nm or less, 0.6 nm or less, 0.5 nm or less, 0.3 nm or less, 0.2 nm or less, 0.1 nm or less, 0.01 nm or less, 0.005 nm or less, or 0.001 nm or less in absolute value.

[0143] As the difference between the thermal expansion of the first region and the thermal expansion of the second region decreases, the difference in thickness between the regions decreases, and after heat treatment, the upper surfaces of the first region and the upper surfaces of the second region may be at substantially the same level. For example, if the difference between the thermal expansion of the second region and the thermal expansion of the first region is greater than 1.0 nm, a void may occur at the joint surface of the first region, as explained in Figure 2c. For example, if the difference between the thermal expansion of the first region and the thermal expansion of the second region is greater than 1.0 nm, a void may occur at the joint surface of the second region, as explained in Figure 3c.

[0144] By adjusting the difference between the thermal expansion of the first region and the thermal expansion of the second region to the aforementioned range, even when the semiconductor substrate is heat-treated while bonded, the first and second regions may be located at substantially the same height or level, and no voids may be generated at the bonding surface.

[0145] (Examples) The present invention will be described in more detail below with reference to the following examples. However, the following examples are for illustrative purposes only, and the scope of the present invention is not limited to these examples.

[0146] (Example 1) The aforementioned urethane-based prepolymer was used, along with triethylenediamine (Dow) as a curing agent and microcapsules (Expancel 044DU20, Noutyon) as a solid-phase foaming agent.

[0147] Average particle size of solid-phase foaming agent (D 50 The particle size is 6 μm to 9 μm, the thermal decomposition start temperature (Tstart) is 100°C to 108°C, the maximum thermal decomposition temperature (Tmax) is 143°C to 160°C, and the density is 25 kg / m³. 3 The following measurements were obtained. In addition, the elemental content of the solid-phase foaming agent was measured using an Inductively Coupled Plasma Emission Spectrometer (Agilent 5110 ICP-OES, Agilent). The elemental composition ratio of the solid-phase foaming agent, measured by weight, was Ca:Fe:Mg:Na:Si:Zn = 38:128:76:242:39267:32.

[0148] In a casting apparatus equipped with the aforementioned urethane-based prepolymer, curing agent, inert gas injection line, and solid-phase foaming agent injection line, the urethane-based prepolymer obtained in the above production example was filled, the triethylenediamine curing agent was filled into the curing agent tank, and at the same time, the purified solid-phase foaming agent was quantified to 2.0 parts by weight per 100 parts by weight of the raw material mixture and injected into the prepolymer tank.

[0149] The urethane prepolymer, curing agent, and solid-phase foaming agent were added to the mixing head and stirred at a rotational speed of 6000 rpm. The molar equivalents of the NCO groups in the urethane prepolymer and the reactive groups in the curing agent were matched in a 1:1 ratio, and the total amount added was maintained at a rate of 10 kg / min.

[0150] The stirred raw materials (raw material mixture) were extruded into a mold (1000mm x 1000mm x 3mm) to complete the reaction and obtain a solid-phase cake-like molded body. The upper and lower ends of the molded body were each cut by a thickness of 0.5mm to obtain an upper pad with a thickness of 2mm.

[0151] The upper pad was subjected to surface milling and groove forming processes, and then laminated with the lower pad using a hot melt adhesive to manufacture a polishing pad.

[0152] (Example 2) In Example 1, a polishing pad was manufactured in the same manner as in Example 1, except that the elemental composition ratio of the solid-phase foaming agent was changed by weight to Ca:Fe:Mg:Na:Si:Zn=21:64:27:189:27500:5.

[0153] (Example 3) In Example 1, a polishing pad was manufactured in the same manner as in Example 1, except that the elemental composition ratio of the solid-phase foaming agent was changed by weight to Ca:Fe:Mg:Na:Si:Zn = 111:2:50:383:43917:15.

[0154] (Comparative Example 1) In Example 1, a polishing pad was manufactured in the same manner as in Example 1, except that the elemental composition ratio of the solid-phase foaming agent was changed by weight to Ca:Fe:Mg:Na:Si:Zn = 45:65:38:184:27020:19.

[0155] (Comparative Example 2) In Example 1, a polishing pad was manufactured in the same manner as in Example 1, except that the elemental composition ratio of the solid-phase foaming agent was changed by weight to Ca:Fe:Mg:Na:Si:Zn = 35:3:63:354:38558:3.

[0156] (Experimental Example 1: Measurement of the diameter distribution of multiple stomata) For each of the polishing pads manufactured in the examples and comparative examples, the polishing pad was cut into a 1cm x 1cm square (thickness: 2mm), and then 3D-CT scanned (GE). The diameter of multiple pores within the polishing pad was measured by the 3D-CT scan, and the volume of each pore was calculated accordingly.

[0157] The volume distribution of stomata was obtained by arranging them in ascending order of stomatal diameter. From the volume distribution of stomata, Dn was calculated based on the diameter of the stomata at a volume fraction of 50%.50 was measured, and Dn is the pore diameter at a volume fraction of 10%. 10 was measured, and Dn is the pore diameter at a volume fraction of 90%. 90 was measured.

[0158] Figure 7 is a cross-sectional image obtained by 3D-CT scanning of the polishing pad of Example 1. Referring to Figure 7, in Example 1, it can be confirmed that a plurality of pores have a uniform diameter and the pores are uniformly distributed in the polishing pad.

[0159] (Experimental Example 2: Measurement of Polishing Amount and Dishing Value) Cu was deposited on the upper surface of the patterned SiO2 wafer, and the upper surface of the wafer was polished to prepare a semiconductor substrate in which Cu pads were patterned on the SiO2 film. The thermal expansion coefficient of the SiO2 film is 5.7×10 -7 mm / mm·°C, and the thermal expansion coefficient of the Cu pad is 2.0×10 -5 mm / mm·°C. At this time, polishing was performed until the upper surface of the SiO2 film and the upper surface of the Cu pad were located at the same level on the polishing surface of the semiconductor substrate and the SiO2 film was exposed.

[0160] Thereafter, the polishing surface of the semiconductor substrate was further polished for 10 seconds to perform an additional polishing process, and the dishing value due to the additional polishing process was measured.

[0161] The polishing process and the additional polishing process were carried out using a CMP system (POLI-400LM, G&P Technology) under the conditions of 20°C, a polishing pad rotation speed of 93 rpm, a workpiece rotation speed of 87 rpm, and a polishing load of 5.0 psi while introducing a ceria slurry (ACS-580, KC Tech).

[0162] The dishing value was calculated by determining the difference in thickness changes between the SiO2 film and the Cu pad before and after the additional polishing process. Since the SiO2 film and Cu pad had the same thickness before the additional polishing process, the difference in thickness changes was calculated by measuring the minimum thickness of the SiO2 film and Cu pad after the additional polishing process, and subtracting the minimum thickness of the Cu pad from the minimum thickness of the SiO2 film. The thickness measurements were performed using an atomic force microscope (AFM), and the minimum thickness after the additional polishing process was measured at the thickness of the most polished portion.

[0163] [Table 1]

[0164] (Manufacturing of semiconductor devices) The semiconductor substrates manufactured as described above were prepared as the upper and lower substrates. The upper and lower substrates were attached to each other so that their polished surfaces were in contact, and then pressed with a pressure of 15N. At this time, the upper and lower substrates were attached in an aligned manner so that the Cu pads faced each other and the SiO2 films faced each other. With the upper and lower substrates attached, the temperature was raised from 20°C to 150°C and heat-treated at 150°C for 1 hour, and then the temperature was raised to 350°C and heat-treated at 350°C for 1 hour to manufacture a semiconductor device.

[0165] (Experimental Example 3: Evaluation of bonding properties) In the examples and comparative examples, the bonding performance between the upper and lower substrates was evaluated. Specifically, the thermal expansion of the SiO2 film (first thermal expansion) and the thermal expansion of the Cu pad (second thermal expansion) were calculated, and the difference in thermal expansion was calculated by subtracting the first thermal expansion from the second thermal expansion to evaluate the bonding performance. The smaller the difference between the first and second thermal expansions, the more likely it is that the upper surface of the SiO2 film and the upper surface of the Cu pad after heat treatment can be at substantially the same level, and the bonding performance between the upper and lower substrates can be improved.

[0166] The first thermal expansion was calculated using the thermal expansion coefficient of the SiO2 film × the thickness of the SiO2 film after the additional polishing process × the temperature difference before and after heat treatment, and the second thermal expansion was calculated using the thermal expansion coefficient of Cu × the thickness of the Cu pad after the additional polishing process × the temperature difference before and after heat treatment.

[0167] The temperature difference before and after the heat treatment is 330°C, which is the difference between the final heat treatment temperature and the initial temperature before the heat treatment. The thermal expansion coefficient of the SiO2 film is 5.7 × 10⁻⁶. -7 At mm / mm°C, the thermal expansion coefficient of Cu is 2.0 × 10⁻⁶. -5 At mm / mm°C, the thickness of the SiO2 film after the additional polishing step was set to 2.2954 nm. The thickness of the Cu pad after the additional polishing step was calculated by subtracting the dishing value from the thickness of the SiO2 film. The unit of the thermal expansion difference in Table 2 is (×10 -2 It is (nm).

[0168] [Table 2]

[0169] Referring to Table 2 above, in the example, the dishing value by the polishing pad is 3.5 nm or less, and in the semiconductor substrate bonding process, the difference in thermal expansion between the Cu pad and the SiO2 film is 1.0 × 10⁻⁶ in absolute value. -2 The wavelength was adjusted to below nm. Therefore, it was confirmed that the bonding quality of the semiconductor substrate and the connectivity between Cu pads were improved in the semiconductor substrate manufactured in the example compared to the comparative example.

[0170] In Example 1, the thermal expansion of the Cu pad and the thermal expansion of the SiO2 film were substantially the same. In Example 2, the dishing value increased compared to Example 1, and the difference in thermal expansion was negative, meaning that the thermal expansion of the Cu pad was smaller than that of the SiO2 film. In Example 3, the dishing value decreased compared to Example 1, and the difference in thermal expansion was positive. [Explanation of symbols]

[0171] 100: Semiconductor substrate 105: Base board 110:First area 120:Second area 125: Recess 130: Separate space 10, 200: Polishing pads 12, 250: Polishing layer 14: Adhesive layer 16:Support layer

Claims

1. Includes an abrasive layer, Polishing pads with a dishing value of 0.5 nm to 3.5 nm: The aforementioned dishing value is 1.0 × 10 －７ mm / mm℃~3.5×10 －６ A first region having a thermal expansion coefficient of mm / mm°C, and 4.0 × 10 －６ mm / mm℃~3.0×10 －５ The measurement is the difference (nm) in thickness change between the first and second regions when the surface of a workpiece, which includes a second region having a thermal expansion coefficient of mm / mm°C, is polished with the polishing pad for 10 seconds under the conditions of a polishing pad rotation speed of 93 rpm, workpiece rotation speed of 87 rpm, and polishing load of 5.0 psi, while adding ceria slurry (ACS-580, manufactured by KC Tech Co., Ltd.) at a rate of 150 mL / min.

2. The polishing pad according to claim 1, wherein the first region includes a dielectric and the second region includes a metal.

3. The first region is silicon dioxide (SiO ２ The polishing pad according to claim 1, wherein the second region is a copper (Cu) film.

4. The polished layer contains multiple pores, The average diameter (Dn) of the plurality of pores ５０ ) is 18 μm to 30 μm, The plurality of pores include first pores having a diameter of 16.9 μm or less and second pores having a diameter of 27.4 μm or more. The polishing pad according to claim 1, wherein, based on the total volume of the plurality of pores, the total volume of the first pore is 10% by volume or less, and the total volume of the second pore is 10% by volume or less.

5. The polishing layer comprises a cured product of a raw material mixture containing a urethane-based prepolymer, a solid-phase foaming agent, and a curing agent. The polishing pad according to claim 4, wherein the plurality of pores are derived from the solid-phase foaming agent.

6. The step of attaching the polishing pad described in claim 1 to the platen, The steps include: mounting the semiconductor substrate to the head so that the surface of the semiconductor substrate to be polished contacts the polishing surface of the polishing pad; A method for manufacturing a semiconductor device, comprising the step of rotating the polishing pad and the semiconductor substrate relative to each other to polish the surface of the semiconductor substrate.

7. The steps include polishing the upper surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate with the polishing pad described in claim 1, The steps include: attaching the upper surface of the first semiconductor substrate and the lower surface of the second semiconductor substrate facing each other; The step includes heat treatment of the first semiconductor substrate and the second semiconductor substrate, A method for manufacturing semiconductor devices.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the upper surface of the first semiconductor substrate and the bottom surface of the second semiconductor substrate each include a first region and a second region.

9. The aforementioned adhesion step is, A method for manufacturing a semiconductor device according to claim 8, comprising the first region of the first semiconductor substrate and the first region of the second semiconductor substrate being in contact with each other.

10. In the aforementioned adhesion step, The method for manufacturing a semiconductor device according to claim 8, wherein at least a portion of the second region of the first semiconductor substrate is physically separated from the second region of the second semiconductor substrate.

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