Semiconductor device and method for manufacturing a semiconductor device

Abstract

We provide a semiconductor device that can reduce its size. [Solution] According to one embodiment, the semiconductor device 1 comprises a semiconductor substrate 100 having an upper surface 101 and a lower surface 102, and in a plan view, includes an element region A10 containing a semiconductor element and a peripheral region B10 surrounding the element region A10, wherein the semiconductor substrate 100 of the peripheral region B10 includes an N-type drift layer 10, an N++-type channel stop layer 11 disposed on the upper surface 101 side of the N-type drift layer 10, which comprises at least one annular N++-type channel stop layer 11 surrounding the element region A10, and an N-type guard ring layer 12 disposed on the upper surface 101 side of the N-type drift layer 10, which comprises at least one annular N-type guard ring layer 12 disposed between the outermost outermost structure inside the area surrounded by the N++-type channel stop layer 11 and the N++-type channel stop layer 11.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 describes a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is desired to reduce the size of a semiconductor device. For example, it is desired to reduce the size of a semiconductor device without increasing the process cost of an IGBT and without impairing the negative charge tolerance of the IGBT. In this specification, the negative charge tolerance means the limit of the amount of negative charge such that when a large amount of negative charge reaches the surface of the semiconductor device during use of the semiconductor device, the predetermined breakdown voltage can be maintained without being lost due to the negative charge.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, the semiconductor device comprises a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and in a plan view from the first main surface side, the semiconductor substrate includes an element region containing a semiconductor element and a peripheral region surrounding the element region, and the semiconductor substrate in the peripheral region includes a drift layer of a first conductivity type and a channel stop layer of a first conductivity type disposed on the first main surface side of the drift layer, wherein at least one annular channel stop layer surrounding the element region and a guard ring layer of a first conductivity type disposed on the first main surface side of the drift layer, and in the plan view the channel stop The outermost structure is enclosed by layers and includes at least one annular guard ring layer disposed between the outermost structure and the channel stop layer, wherein the outermost structure includes at least one annular semiconductor layer of a second conductivity type disposed on the first main surface side of the semiconductor substrate than the drift layer, and an annular field plate containing a conductive material disposed on the first main surface side of the semiconductor substrate, wherein the concentration of the first conductivity type impurity in the guard ring layer is greater than the concentration of the first conductivity type impurity in the drift layer and less than the concentration of the first conductivity type impurity in the channel stop layer.

[0007] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of: setting an element region including a semiconductor element and a peripheral region surrounding the element region on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, in a plan view from the first main surface side; forming a drift layer of a first conductivity type and a channel stop layer of a first conductivity type disposed on the first main surface side of the drift layer, wherein at least one annular channel stop layer surrounds the element region; and forming a guard ring layer of a first conductivity type disposed on the first main surface side of the drift layer, wherein the outermost outermost structure is located inside the channel stop layer. The method comprises the steps of forming at least one annular guard ring layer disposed between the channel stop layer and the guard ring layer, wherein the outermost structure includes at least one annular semiconductor layer of a second conductivity type disposed on the first main surface side of the semiconductor substrate than the drift layer, and an annular field plate containing a conductive material disposed on the first main surface side of the semiconductor substrate, wherein the concentration of the first conductivity type impurity in the guard ring layer is greater than the concentration of the first conductivity type impurity in the drift layer and less than the concentration of the first conductivity type impurity in the channel stop layer. [Effects of the Invention]

[0008] According to the above embodiment, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce the size. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view illustrating a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view illustrating a peripheral region in the semiconductor device according to Embodiment 1, showing the cross-section along line II-II in Figure 1. [Figure 3] This is an enlarged cross-sectional view illustrating a peripheral region in the semiconductor device according to Embodiment 1, showing a cross-section of surface III in Figure 2. [Figure 4] This is a cross-sectional view illustrating an element region in a semiconductor device according to Embodiment 1, showing the cross-section along line IV-IV in Figure 1. [Figure 5] This is a cross-sectional view illustrating the manufacturing process of a peripheral region in the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view illustrating the manufacturing process of an element region in a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view illustrating the manufacturing process of an element region in a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view illustrating the manufacturing process of an element region in a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 9] This is a cross-sectional view illustrating the manufacturing process of an element region in a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 10] This is a cross-sectional view illustrating the manufacturing process of an element region in a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 11] This is a cross-sectional view illustrating a peripheral region in the semiconductor device according to Comparative Example 1. [Figure 12] This is a cross-sectional view illustrating a peripheral region in the semiconductor device according to Comparative Example 2. [Figure 13] This is a cross-sectional view illustrating a peripheral region in the semiconductor device according to Comparative Example 3. [Modes for carrying out the invention]

[0010] For clarity of explanation, the following descriptions and drawings have been omitted and simplified as appropriate. Furthermore, in drawings, hatching and other markings may be omitted, even in cross-sections, if they would make the drawing more complex or if the distinction from voids is clear. In each drawing, the same elements are assigned the same reference numeral, and redundant explanations have been omitted where necessary. Reference numerals have also been omitted as appropriate to avoid making the drawings more complex.

[0011] In this specification, the N-type conductivity of a semiconductor means that electrons alone are charge carriers, or that both electrons and holes may be charge carriers, but the concentration of electrons is higher than the concentration of holes, and electrons are the primary charge carriers. In this specification, the P-type conductivity of a semiconductor means that holes alone are charge carriers, or that both electrons and holes may be charge carriers, but the concentration of holes is higher than the concentration of electrons, and holes are the primary charge carriers.

[0012] Note that N++ and P++ types represent low-resistance N and P conductive types, respectively. N+ and P+ types represent N and P conductive types that have higher resistance than N++ and P++ types, but lower resistance than N and P types, respectively. P- and N- types represent N and P conductive types with higher resistance than N and P types, respectively. Therefore, N and P types represent N and P conductive types with resistances between N+ and P+ types and P- and N- types, respectively. N+ and P+ types represent N and P conductive types with resistances between N++ and P++ types and P and N types, respectively. The same meaning is used below unless otherwise specified.

[0013] The N-type conductivity is sometimes referred to as the first conductivity type, and the P-type conductivity is sometimes referred to as the second conductivity type. On the other hand, the N-type conductivity may be referred to as the second conductivity type, and the P-type conductivity may be referred to as the first conductivity type. Furthermore, semiconductor devices in which the conductivity types of each configuration of this disclosure are reversed are also included within the scope of the technical concept of this disclosure. In addition, the resistances of the N++-type, N+-type, N-type, and N-type semiconductor layers are illustrative. Unless otherwise specified, they may be greater than or less than the resistances shown in this disclosure. The relative magnitudes of the resistances of the N++-type, N+-type, N-type, and N-type semiconductor layers may be reversed in some cases. Similarly, the resistances of the P++-type, P+-type, P-type, and P-type semiconductor layers are illustrative. Unless otherwise specified, they may be greater than or less than the resistances shown in this disclosure. The relative magnitudes of the resistances of the P++-type, P+-type, P-type, and P-type semiconductor layers may be reversed in some cases.

[0014] <Embodiment 1> A semiconductor device according to Embodiment 1 will be described. FIG. 1 is a plan view illustrating the semiconductor device 1 according to Embodiment 1. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, in the shape of a rectangular plate. The two plate surfaces of the semiconductor substrate 100 are referred to as the first main surface and the second main surface. The second main surface is the surface on the opposite side of the first main surface. Therefore, the semiconductor substrate 100 has the first main surface and the second main surface on the opposite side of the first main surface. For convenience of explanation, the first main surface may be referred to as the upper surface 101, and the second main surface may be referred to as the lower surface 102.

[0015] Here, for convenience of explanation of the semiconductor device 1 and the like, an XYZ orthogonal coordinate system is introduced. The direction perpendicular to the upper surface 101 is defined as the Z-axis direction, and the two directions perpendicular to the Z-axis direction are defined as the X-axis direction and the Y-axis direction. The direction from the lower surface 102 toward the upper surface 101 is defined as the +Z-axis direction. The first main surface side is the +Z-axis direction side and the upper surface 101 side. The second main surface side is the -Z-axis direction side and the lower surface 102 side. For convenience, the +Z-axis direction is regarded as the upward direction. The -Z-axis direction is regarded as the downward direction. Note that the upward and downward directions are for convenience of explanation and do not indicate the directions when the actual semiconductor device 1 is used.

[0016] In this specification, "in plan view" means the case when viewed from a direction perpendicular to the upper surface 101 of the semiconductor substrate 100. That is, "in plan view" means the case when the semiconductor substrate 100 is viewed from the +Z-axis direction side of the semiconductor substrate 100 in the -Z-axis direction.

[0017] In a plan view, the semiconductor device 1 and the semiconductor substrate 100 include an element region A10 and a peripheral region B10. The element region A10 includes a semiconductor element. The peripheral region B10 is arranged to surround the element region A10. The peripheral region B10 may include a first peripheral region B11, a second peripheral region B12, and a third peripheral region B13. The third peripheral region B13 is arranged to surround the element region A10. The second peripheral region B12 is arranged to surround the element region A10 and the third peripheral region B13. Therefore, the third peripheral region B13 is located between the element region A10 and the second peripheral region B12. The first peripheral region B11 is arranged to surround the element region A10, the third peripheral region B13, and the second peripheral region B12. Therefore, the second peripheral region B12 is located between the third peripheral region B13 and the first peripheral region B11.

[0018] The direction from element region A10 toward the third peripheral region B13 is called the outer direction, and the direction from the third peripheral region B13 toward element region A10 is called the inner direction. Peripheral region B10 is located outside element region A10. Element region A10 is located inside peripheral region B10. Below, we will explain the <peripheral region> and <element region> separately.

[0019] <Related areas> Figure 2 is a cross-sectional view illustrating the peripheral region B10 in the semiconductor device 1 according to Embodiment 1, showing the cross-section along line II-II in Figure 1. Figure 3 is an enlarged cross-sectional view illustrating the peripheral region B10 in the semiconductor device 1 according to Embodiment 1, showing the cross-section of plane III in Figure 2. As shown in Figures 2 and 3, in the peripheral region B10, the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 are arranged in a unidirectional direction from the element region A10 toward the third peripheral region B13. In Figures 2 and 3, the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 are arranged in the X-axis direction as an example. The first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 may also be arranged in the Y-axis direction, or in a direction inclined from the X-axis and Y-axis directions.

[0020] The semiconductor substrate 100 in peripheral region B10 includes an N-type drift layer 10, an N++-type channel stop layer 11, and an N-type guard ring layer 12. The semiconductor substrate 100 in peripheral region B10 may also include a P-type semiconductor layer 13. Furthermore, the semiconductor substrate 100 in peripheral region B10 may further include other semiconductor layers not shown.

[0021] The N-type drift layer 10 is included in the semiconductor substrate 100 in peripheral region B10. Specifically, the N-type drift layer 10 is formed across the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13. The N-type drift layer 10 is also formed in the device region A10.

[0022] <First peripheral region> In the first peripheral region B11, the semiconductor device 1 comprises a semiconductor substrate 100 including an N-type drift layer 10. The N++-type channel stop layer 11 is located on the +Z axis side of the semiconductor substrate 100 in the first peripheral region B11 compared to the N-type drift layer 10. The N++-type channel stop layer 11 has at least one annular shape surrounding the device region A10. Therefore, in a plan view, the device region A10 is located inside the area surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the device region A10 is located inside the N++-type channel stop layer 11.

[0023] In the first peripheral region B11, the semiconductor device 1 may further include a first interlayer insulating film 21 and an equipotential ring 31 in addition to the semiconductor substrate 100. The first interlayer insulating film 21 is provided on the +Z axis side of the semiconductor substrate 100 on which the N++ type channel stop layer 11 is located. The equipotential ring 31 is provided on the +Z axis side of the first interlayer insulating film 21. The equipotential ring 31 contains a conductive material. For example, the equipotential ring 31 contains aluminum. The equipotential ring 31 is connected to the N++ type channel stop layer 11 via a contact groove 26 formed in the first interlayer insulating film 21. The equipotential ring 31 may have a portion that protrudes inward from the N++ type channel stop layer 11. In the direction shown in the figure, the equipotential ring 31 may have a portion that protrudes in the -X axis side from the N++ type channel stop layer 11.

[0024] <Second peripheral area> In the second peripheral region B12, the semiconductor device 1 comprises a semiconductor substrate 100 including an N-type drift layer 10. The N-type guard ring layer 12 is located on the +Z axis side of the N-type drift layer 10 in the semiconductor substrate 100 in the second peripheral region B12. The N-type guard ring layer 12 is located inside the N++-type channel stop layer 11. In other words, in a plan view, the N-type guard ring layer 12 is located inside the N++-type channel stop layer 11. The N-type guard ring layer 12 has at least one annular shape so as to surround the device region A10.

[0025] The semiconductor substrate 100 in the peripheral region B12 may include a plurality of N-type guard ring layers 12. The plurality of N-type guard ring layers 12 are arranged inside the area surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the plurality of N-type guard ring layers 12 are arranged inside the N++-type channel stop layer 11. The plurality of N-type guard ring layers 12 are arranged in a ring shape so as to surround the device region A10. The plurality of N-type guard ring layers 12 are spaced apart from each other. The N-type guard ring layers 12 are also spaced apart from the N++-type channel stop layer 11. Furthermore, the N-type guard ring layers 12 may be spaced apart from the equipotential ring 31 in a plan view. The N-type guard ring layers 12 may also be spaced apart from the P-type semiconductor layer 13.

[0026] The concentration of N-type impurities in the N-type guard ring layer 12 is greater than the concentration of N-type impurities in the N-type drift layer 10, and less than the concentration of N-type impurities in the N++-type channel stop layer 11. Furthermore, if the semiconductor device 1 includes an IGBT as a semiconductor element in element region A10, the N-type guard ring layer 12 may contain the same type of impurities as the N-type barrier layer in the IGBT. Moreover, the N-type guard ring layer 12 may contain the same concentration of impurities as the N-type barrier layer. As will be described later, the N-type barrier layer is the portion located below (on the collector side of) the P-type body layer (P-type channel layer) in contact with the trench gate electrode.

[0027] In the second peripheral region B12, the semiconductor device 1 may further include a second interlayer insulating film 22 in addition to the semiconductor substrate 100. The second interlayer insulating film 22 is provided on the +Z axis side of the semiconductor substrate 100 on which the N-type guard ring layer 12 is located. The thickness of the second interlayer insulating film 22 is greater than the thickness of the first interlayer insulating film 21. For example, the second interlayer insulating film 22 may include an insulating material such as LOCOS (Local Oxidation of Silicon). The N-type guard ring layer 12 may be covered with LOCOS. In contrast, the first interlayer insulating film 21 may be formed by a different process than the second interlayer insulating film 22.

[0028] <Third peripheral area> In the third peripheral region B13, the semiconductor device 1 comprises a semiconductor substrate 100 including an N-type drift layer 10. In the third peripheral region B13, the semiconductor substrate 100 may also include at least one P-type semiconductor layer 13. The P-type semiconductor layer 13 is located on the +Z axis side of the N-type drift layer 10 in the semiconductor substrate 100 in the third peripheral region B13. In a plan view, the P-type semiconductor layer 13 is located inside the area surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the P-type semiconductor layer 13 is located inside the N++-type channel stop layer 11. The P-type semiconductor layer 13 may be arranged in a ring shape surrounding the device region A10.

[0029] In the third peripheral region B13, the semiconductor device 1 may further include a third interlayer insulating film 23 and at least one field plate 33, in addition to the semiconductor substrate 100. The third interlayer insulating film 23 is provided on the +Z axis side of the semiconductor substrate 100 on which the P-type semiconductor layer 13 is arranged. The thickness of the third interlayer insulating film 23 may be greater than the thickness of the first interlayer insulating film 21.

[0030] The field plate 33 is positioned on the +Z axis side of the third interlayer insulating film 23. The field plate 33 contains a conductive material. For example, the conductive material contains aluminum. In a plan view, the field plate 33 is positioned inside the area surrounded by the N++ type channel stop layer 11. That is, in a plan view, the field plate 33 is positioned inside the N++ type channel stop layer 11. The field plate 33 is arranged in an annular shape so as to surround the device region A10. The field plate 33 may be connected to the P-type semiconductor layer 13 via a contact groove 26 formed in the third interlayer insulating film 23. The field plate 33 may have a portion that protrudes outward from the P-type semiconductor layer 13. In the direction shown in the figure, the field plate 33 may have a portion that protrudes on the +X axis side of the P-type semiconductor layer 13.

[0031] The semiconductor device 1 may include an outermost structure. In a plan view, the outermost structure includes at least one of a P-type semiconductor layer 13 and a field plate 33, which are located on the outermost side within the interior surrounded by the N++-type channel stop layer 11. In this case, the N-type guard ring layer 12 is located between the outermost structure within the interior surrounded by the N++-type channel stop layer 11 and the N++-type channel stop layer 11, in a plan view.

[0032] The semiconductor substrate 100 may include a plurality of field-limiting ring layers 13a as the P-type semiconductor layer 13. The plurality of field-limiting ring layers 13a are located on the +Z axis side of the N-type drift layer 10. In a plan view, the plurality of field-limiting ring layers 13a are located inside the area surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the plurality of field-limiting ring layers 13a are located inside the N++-type channel stop layer 11. The plurality of field-limiting ring layers 13a are arranged in a ring shape so as to surround the device region A10. The plurality of field-limiting ring layers 13a are arranged spaced apart from each other.

[0033] The semiconductor device 1 may include a plurality of field plates 33 to correspond to a plurality of field limiting ring layers 13a. The plurality of field plates 33 may each be connected to the plurality of field limiting ring layers 13a via a plurality of contact grooves 26 formed in the third interlayer insulating film 23. In this case, the outermost structure includes either the field limiting ring layer 13a or the field plate 33 located on the outermost periphery from the plurality of field limiting ring layers 13a and the plurality of field plates 33. Therefore, in a plan view, the N-type guard ring layer 12 is located between the N++-type channel stop layer 11 and either the field limiting ring layer 13a or the field plate 33 located on the outermost periphery within the interior surrounded by the N++-type channel stop layer 11.

[0034] Furthermore, if the semiconductor element in element region A10 includes a P-type semiconductor layer 13, such as a P-type floating layer, which is positioned on the +Z axis side of the N-type drift layer 10, the P-type semiconductor layer 13 may function as the outermost structure. In that case, the semiconductor substrate 100 of peripheral region B10, which includes the third peripheral region B13, does not need to have a P-type semiconductor layer 13. The N-type guard ring layer 12 is positioned between the P-type semiconductor layer 13 and the N++-type channel stop layer 11 in element region A10.

[0035] Furthermore, for example, in a JTE (Junction Termination Extension) structure, the semiconductor substrate 100 in the peripheral region B10 may include a P-type semiconductor layer 13 that functions as a termination structure positioned on the +Z axis side of the N-type drift layer 10. The P-type semiconductor layer 13 may be located inside an area surrounded by an N++-type channel stop layer 11 in a plan view. In this case, the outermost structure includes the P-type semiconductor layer 13.

[0036] In the peripheral region B10, the interlayer insulating film, including the first interlayer insulating film 21, the second interlayer insulating film 22, and the third interlayer insulating film 23, is provided on the +Z axis side of the semiconductor substrate 100 in the peripheral region B10. At least one of the first interlayer insulating film 21, the second interlayer insulating film 22, and the third interlayer insulating film 23 may have a fixed positive charge. Thus, the interlayer insulating film in the peripheral region B10 may have a fixed positive charge. For example, at least one of the first interlayer insulating film 21, the second interlayer insulating film 22, and the third interlayer insulating film 23 may be formed using P-TEOS deposited by a plasma CVD method with TEOS (Tetra Ethoxy Silane) as the main raw material. In this case, the charge generated in the P-TEOS may be fixed by RTA (Rapid Thermal Annealing).

[0037] <Element Area> Figure 4 is a cross-sectional view illustrating the element region A10 in the semiconductor device 1 according to Embodiment 1, showing the cross-section along line IV-IV in Figure 1. As shown in Figure 4, in the element region A10, the semiconductor device 1 may further include, in addition to the semiconductor substrate 100, an insulating film 24a, an interlayer insulating film 25, an emitter wiring 34, and a collector wiring 35. Multiple semiconductor elements may be formed in the element region A10. The semiconductor elements may include, for example, IGBTs. The semiconductor elements may also include at least one of MOSFETs and diodes.

[0038] The semiconductor substrate 100 in device region A10 includes, as part of the IGBT configuration, an N-type drift layer 10, an N-type barrier layer 14, P-type body layers 15a and 15i, an N+-type emitter layer 16, a P+-type latch-up prevention layer 17, and a P+-type body contact layer 18. The semiconductor substrate 100 in device region A10 also includes a trench gate electrode 41, a trench emitter electrode 42, a P-type floating layer 43, a P+-type collector layer 44, an N-type field stop layer 45, a trench insulating film 46, and a trench insulating film 47. The emitter wiring 34 is connected to the N+-type emitter layer 16, the P-type body layer 15a, the P+-type body contact layer 18, and the trench emitter electrode 42 via contact grooves 26 formed in the insulating film 24a and the interlayer insulating film 25. The collector wiring 35 is connected to the P+-type collector layer 44.

[0039] The N-type drift layer 10 is continuously arranged across the device region A10 and the surrounding region B10. In the device region A10, the N-type drift layer 10 is positioned on the +Z axis side of the N-type field stop layer 45 in the semiconductor substrate 100.

[0040] The N-type barrier layer 14 is positioned on the +Z axis side of the N-type drift layer 10. In a plan view, the N-type barrier layer 14 extends, for example, in the Y axis direction. The N-type barrier layer 14 is sandwiched on both sides in the X axis direction by the trench gate electrode 41 and the trench emitter electrode 42. That is, the N-type barrier layer 14 is positioned inside the space sandwiched between the trench gate electrode 41 and the trench emitter electrode 42.

[0041] The portion of the P-type body layer 15a located in the active cell region 40a is positioned on the +Z axis side of the N-type barrier layer 14. The P-type body layer 15a is sandwiched on both sides in the X axis direction by the trench gate electrode 41 and the trench emitter electrode 42. The P-type body layer 15a is connected to the emitter wiring 34 filled in the contact groove 26 that penetrates the interlayer insulating film 25, the insulating film 24a, and the N+-type emitter layer 16.

[0042] The N+ type emitter layer 16 is positioned on the +Z axis side of the P type body layer 15a. The N+ type emitter layer 16 is located inside the trench gate electrode 41 and the trench emitter electrode 42. The N+ type emitter layer 16 is connected to the emitter wiring 34 which is filled in the contact groove 26 that penetrates the insulating film 24a and the interlayer insulating film 25.

[0043] The trench gate electrode 41 and trench emitter electrode 42 are provided so as to sandwich the N-type barrier layer 14, the P-type body layer 15a, and the N+-type emitter layer 16 from both sides in the X-axis direction. In a plan view, the trench gate electrode 41 and trench emitter electrode 42 include portions that extend, for example, in the Y-axis direction. For example, the trench gate electrode 41 is positioned on the +X-axis side of the trench emitter electrode 42. The trench emitter electrode 42 is positioned on the -X-axis side of the trench gate electrode 41.

[0044] The trench gate electrode 41 is connected, for example, to the gate wiring. The trench emitter electrode 42 is connected to the emitter wiring 34, which is filled in a contact groove 26 that penetrates the insulating film 24a and the interlayer insulating film 25. Thus, the N+ type emitter layer 16, the P type body layer 15a, and the trench gate electrode 41 are connected to the emitter wiring 34. The structure between the trench gate electrode 41 and the trench emitter electrode 42 is called the inter-trench structure. For example, the inter-trench structure of an IGBT includes an N type barrier layer 14, a P type body layer 15a, and an N+ type emitter layer 16. The inter-trench structure of an IGBT may further include a P+ type latch-up prevention layer 17 and a P+ type body contact layer 18. for example,

[0045] The P-type floating layer 43 is provided between adjacent IGBTs in a plurality of IGBTs. For example, the P-type floating layer 43 is provided between the trench gate electrode 41 of the IGBT on the -X axis side and the trench emitter electrode 42 of the IGBT on the +X axis side among adjacent IGBTs. The P-type floating layer 43 is provided on the opposite side of the N-type barrier layer 14, P-type body layer 15a, and N+-type emitter layer 16, with the trench gate electrode 41 or trench emitter electrode 42 in between.

[0046] The P-type floating layer 43 is positioned on the +Z axis side of the N-type drift layer 10. The P-type body layer 15i is positioned on the +Z axis side of the P-type floating layer 43. Therefore, on the +Z axis side of the N-type drift layer 10, from the -X axis side along the X axis, the following are arranged: a stack of the P-type floating layer 43 and the P-type body layer 15i, a trench emitter electrode 42 (covered with a trench insulating film 47), an inter-trench structure, a trench gate electrode 41 (covered with a trench insulating film 46), and a stack of the P-type floating layer 43 and the P-type body layer 15i. In the device region A10, this configuration is arranged to be repeated in the X axis direction.

[0047] Multiple IGBTs are formed in element region A10. Except for the IGBTs at the +X-axis end and the IGBTs at the -X-axis end of element region A10, the P-type floating layer 43 is in contact with the trench gate electrode 41 and the trench emitter electrode 42. In other words, the P-type floating layer 43 is formed between adjacent IGBTs, excluding those at the X-axis end of element region A10.

[0048] If the third peripheral region B13 in peripheral region B10 does not have a P-type semiconductor layer 13 such as a field limiting ring layer 13a, the P-type floating layer 43 of device region A10 may function as the outermost P-type semiconductor layer 13. In other words, the outermost structure includes the P-type floating layer 43. Therefore, the P-type floating layer 43 of the IGBT located on the outermost edge of device region A10 may also be the outermost annular P-type semiconductor layer 13 located on the +Z axis side of the N-type drift layer 10 within the interior surrounded by the N++-type channel stop layer 11. Thus, the N-type guard ring layer 12 may be located between the outermost annular P-type floating layer 43 and the N++-type channel stop layer 11. In this way, the P-type semiconductor layer 13 may include the P-type floating layer 43.

[0049] The trench insulating film 46 is provided between the trench emitter electrode 42 and the semiconductor substrate 100. Specifically, the trench insulating film 46 is provided between the trench emitter electrode 42 and the N-type drift layer 10, the N-type barrier layer 14, the P-type body layer 15a, the N+-type emitter layer 16, the P-type body layer 15i, and the P-type floating layer 43. The trench insulating film 47 is provided between the trench gate electrode 41 and the semiconductor substrate 100. Specifically, the trench insulating film 47 is provided between the trench gate electrode 41 and the N-type drift layer 10, the N-type barrier layer 14, the P-type body layer 15a, the P-type body layer 15i, and the P-type floating layer 43.

[0050] The N-type field stop layer 45 is located on the -Z axis side of the N-type drift layer 10. The P+-type collector layer 44 is located on the -Z axis side of the N-type field stop layer 45. The P+-type collector layer 44 is connected to the collector wiring 35.

[0051] The element region A10 may include a plurality of active cell regions 40a and a plurality of inactive cell regions 40i. The plurality of active cell regions 40a extend in the Y-axis direction and are arranged periodically in the X-axis direction in a plan view. In other words, the active cell regions 40a are formed in a vertical stripe pattern.

[0052] Furthermore, the multiple inactive cell regions 40i extend in the Y-axis direction and are arranged periodically in the X-axis direction in a plan view. The active cell regions 40a and the inactive cell regions 40i are arranged alternately in the X-axis direction. A unit cell region 40 is composed of one active cell region 40a, half of the inactive cell region 40i adjacent to the active cell region 40a on the +X-axis side, and half of the inactive cell region 40i adjacent to the active cell region 40a on the -X-axis side. Therefore, the element region A10 includes multiple unit cell regions 40. The unit cell region 40 includes, for example, an IGBT as a semiconductor element. Therefore, the element region A10 may include multiple IGBTs.

[0053] In the active cell region 40a, above the N-type drift layer 10, in order from bottom to top, there may be an N-type barrier layer 14, a P-type body layer 15a, and an N+-type emitter layer 16, as well as a P+-type latch-up prevention layer 17 and a P+-type body contact layer 18. The N+-type emitter layer 16 may be provided only on the trench gate electrode 41 side. An insulating film 24a and an interlayer insulating film 25 are formed on the +Z axis side of the trench gate electrode 41, trench emitter electrode 42, P-type body layer 15a, and N+-type emitter layer 16. Contact grooves 26 that reach the trench emitter electrode 42 and the inside of the semiconductor substrate 100 are formed in a part of the insulating film 24a and interlayer insulating film 25 in the active cell region 40a. The semiconductor substrate 100 at the bottom of these contact grooves 26 is provided with a P+-type body contact layer 18 and a P+-type latch-up prevention layer 17. Through this contact groove 26, the P-type body layer 15a and the N+-type emitter layer 16 are connected to the emitter wiring 34 provided on the insulating film 24a and the interlayer insulating film 25.

[0054] Here, the N-type barrier layer 14 is a barrier region that prevents holes from flowing into the passage from the N-type drift layer 10 to the N+-type emitter layer 16. The impurity concentration of the N-type barrier layer 14 is lower than that of the N+-type emitter layer 16 and higher than that of the N-type drift layer 10. The presence of this N-type barrier layer 14 effectively prevents holes accumulated in the N-type drift layer 10 from entering the emitter passage of the active cell region 40a (the passage from the N-type drift layer 10 to the P+-type body contact layer 18).

[0055] In contrast, the N-type drift layer 10 in the inactive cell region 40i has a P-type floating layer 43 and a P-type body layer 15i arranged from bottom to top. The depth of the P-type floating layer 43 is greater than the depth of the trench gate electrode 41 and the trench emitter electrode 42. Furthermore, the P-type floating layer 43 is distributed to cover the lower ends of the trench gate electrode 41 and the trench emitter electrode 42.

[0056] <Manufacturing method for semiconductor devices> Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described. First, a semiconductor substrate 100 containing a silicon single crystal into which N-type impurities such as phosphorus have been introduced is prepared. The semiconductor substrate 100 has an upper surface 101 as a first main surface and a lower surface 102 as a second main surface on the opposite side of the upper surface 101. Then, in a plan view, an element region A10 and a peripheral region B10 surrounding the element region A10 are set on the semiconductor substrate 100. In the step of setting the element region A10 and the peripheral region B10, the peripheral region B10 may include a third peripheral region B13 surrounding the element region A10, a second peripheral region B12 surrounding the element region A10 and the third peripheral region B13, and a first peripheral region B11 surrounding the element region A10, the third peripheral region B13, and the second peripheral region B12.

[0057] An element isolation member such as LOCOS may be formed on the semiconductor substrate 100. For example, LOCOS may be formed as the second interlayer insulating film 22 or as part thereof on the +Z axis side of the semiconductor substrate 100 in the second peripheral region B12. The <method for manufacturing the peripheral region> and the <method for manufacturing the element region> will be described below.

[0058] <Manufacturing method for peripheral areas> Figure 5 is a cross-sectional view illustrating the manufacturing process of the peripheral region B10 in the manufacturing method of the semiconductor device 1 according to Embodiment 1. As shown in Figure 5, an N-type drift layer 10 and an N++-type channel stop layer 11 are formed on the semiconductor substrate 100 of the first peripheral region B11, and the N++-type channel stop layer 11 is positioned on the +Z axis side of the N-type drift layer 10. The N++-type channel stop layer 11 is formed in a ring shape so as to surround the device region A10. For example, the N++-type channel stop layer 11 is formed on the N-type drift layer 10 by introducing a higher concentration of N-type impurities than that of the N-type drift layer 10 into the semiconductor substrate 100.

[0059] Furthermore, an N-type drift layer 10 and an N-type guard ring layer 12 positioned on the +Z axis side of the N-type drift layer 10 are formed on the semiconductor substrate 100 in the second peripheral region B12. The N-type guard ring layer 12 is formed to have at least one annular structure positioned between the outermost outermost structure within the interior surrounded by the N++-type channel stop layer 11 and the N++-type channel stop layer 11. For example, the N-type guard ring layer 12 is formed on the N-type drift layer 10 by introducing a higher concentration of N-type impurities than that of the N-type drift layer 10 into the semiconductor substrate 100.

[0060] In the process of forming the N-type guard ring layer 12, the concentration of N-type impurities in the N-type guard ring layer 12 is made greater than the concentration of N-type impurities in the N-type drift layer 10. Furthermore, the concentration of N-type impurities in the N-type guard ring layer 12 is made less than the concentration of N-type impurities in the N++-type channel stop layer 11. In addition, the process of forming the N-type guard ring layer 12 may involve introducing N-type impurities into the semiconductor substrate 100 via a second interlayer insulating film 22 such as LOCOS or a part thereof. For example, N-type impurities may be introduced into the semiconductor substrate 100 by ion implantation.

[0061] Furthermore, an outermost structure may be formed in the third peripheral region B13. The outermost structure includes at least one of a field plate 33 containing an annular conductive material positioned on the +Z axis side of the semiconductor substrate 100, and a P-type semiconductor layer 13 positioned on the +Z axis side of the N-type drift layer 10 in the semiconductor substrate 100.

[0062] A first interlayer insulating film 21 is formed in the first peripheral region B11 on the +Z axis side of the semiconductor substrate 100. As described above, a second interlayer insulating film 22 is formed in the second peripheral region B12 on the +Z axis side of the semiconductor substrate 100. In the step of forming the first interlayer insulating film 21 or the step of forming the second interlayer insulating film 22, the thickness of the second interlayer insulating film 22 is made greater than the thickness of the first interlayer insulating film 21. For example, the portion of the second interlayer insulating film 22 that is on the semiconductor substrate 100 side is formed by LOCOS, and after ion implantation to form the N-type guard ring layer 12 and the N++-type channel stop layer 11, the remaining portion of the second interlayer insulating film 22 and the first interlayer insulating film 21 are formed by P-TEOS in the same process. A third interlayer insulating film 23 is formed in the third peripheral region B13 on the +Z axis side of the semiconductor substrate 100. The portion of the third interlayer insulating film 23 that is on the semiconductor substrate 100 side may be formed by LOCOS in the same process as the similar portion of the second interlayer insulating film 22. The remaining portion of the third interlayer insulating film 23 may be formed by P-TEOS in the same process as the first interlayer insulating film 21. Alternatively, the entire third interlayer insulating film 23 may be formed by P-TEOS in the same process as the first interlayer insulating film 21. Contact grooves 26 are formed in the first interlayer insulating film 21 and the third interlayer insulating film 23.

[0063] Then, as shown in Figures 2 and 3, the contact grooves 26 in the first peripheral region B11 are filled, and an equipotential ring 31 is formed on the first interlayer insulating film 21 in the first peripheral region B11. In addition, the contact grooves 26 in the third peripheral region B12 are filled, and a field plate 33 is formed on the third interlayer insulating film 23 in the third peripheral region B13. In this way, the peripheral region B10 of the semiconductor device 1 can be formed.

[0064] <Manufacturing method for element regions> Next, the manufacturing method for element region A10 will be described. The manufacturing method for element region A10 includes the step of forming an IGBT as a semiconductor element in element region A10. The manufacturing method for element region A10 and the manufacturing method for peripheral region B10 may include manufacturing steps that are performed simultaneously. Figures 6 to 10 are cross-sectional views illustrating the manufacturing steps for element region A10 in the manufacturing method of semiconductor device 1 according to Embodiment 1.

[0065] As shown in Figure 6, for example, an N-type barrier layer 14 is formed by introducing N-type impurities to the upper surface 101 of the semiconductor substrate 100 using an ion implantation method with a resist pattern as a mask. The N-type barrier layer 14 is formed in the active cell region 40a. As mentioned above, the device region A10 has a plurality of active cell regions 40a and a plurality of inactive cell regions 40i. In the process of forming the N-type guard ring layer 12 in the manufacturing method of the peripheral region B10 described above, the N-type guard ring layer 12 may be formed simultaneously with the N-type barrier layer 14 in the process of forming the IGBT.

[0066] Next, a p-type floating layer 43 is formed by introducing p-type impurities to the upper surface 101 of the semiconductor substrate 100, for example, by an ion implantation method using a resist pattern as a mask. The p-type floating layer 43 is formed in the inactive cell region 40i. In the process of forming the p-type semiconductor layer 13 in the manufacturing method of the peripheral region B10 described above, the p-type semiconductor layer 13 may be formed simultaneously with the p-type floating layer 43 in the process of forming the IGBT.

[0067] Next, as shown in Figure 7, for example, a hard mask made of a silicon oxide film is used to form a plurality of trenches 27 and a plurality of trenches 28 on the upper surface 101 of the semiconductor substrate 100 by an anisotropic dry etching method.

[0068] Next, as shown in Figure 8, stretching diffusion is performed on the P-type floating layer 43 and the N-type barrier layer 14. At this time, stretching diffusion is performed so that the -Z-axis side end of the P-type floating layer 43 is positioned at the -Z-axis side end of the plurality of trenches 27 and plurality of trenches 28 in the Z-axis direction. Next, an insulating film 24 made of a silicon oxide film is formed on the upper surface 101 of the semiconductor substrate 100, for example by thermal oxidation. In addition, a trench insulating film 46 made of a silicon oxide film is formed on the inner wall of the trench 27. Furthermore, a trench insulating film 47 made of a silicon oxide film is formed on the inner wall of the trench 28. The insulating films 24, 46, and 47 may be formed simultaneously.

[0069] Through the stretching diffusion described above, a P-type floating layer 43 is formed on the +X-axis side of trench 27 and the -X-axis side of trench 28. Preferably, the P-type floating layer 43 is in contact with the trench insulating film 46 formed on the inner wall of trench 27 and the trench insulating film 47 formed on the inner wall of trench 28. In addition, an N-type barrier layer 14 is formed between the -X-axis side of trench 27 and the +X-axis side of trench 28. Preferably, the N-type barrier layer 14 is in contact with the trench insulating film 46 formed on the inner wall of trench 27 and the trench insulating film 47 formed on the inner wall of trench 28. Furthermore, during stretching diffusion, the region of the N-type semiconductor substrate 100 where the P-type floating layer 43 and the N-type barrier layer 14 are not formed becomes an N-type drift layer 10.

[0070] Next, a conductive film 29, composed of a phosphorus-doped polycrystalline silicon film, is formed on the upper surface 101 of the semiconductor substrate 100, and inside the trenches 27 and 28, for example, by a CVD (Chemical Vapor Deposition) method.

[0071] Next, as shown in Figure 9, the conductive film 29 is etched back, for example, by a dry etching method. This forms a trench gate electrode 41 consisting of the conductive film 29 embedded in the trench 27 via the trench insulating film 46. Also, a trench emitter electrode 42 consisting of the conductive film 29 embedded in the trench 28 via the trench insulating film 47 is formed.

[0072] Next, for example, the insulating film 24 outside the interiors of trenches 27 and 28 is removed by a dry etching method. Then, for example, a thermal oxidation method or a CVD method is used to form an insulating film 24a on the upper surface 101 of the semiconductor substrate 100, which consists of a relatively thin silicon oxide film for subsequent ion implantation. The insulating film 24a is used as a through-film for ion implantation, and is therefore also called an ion implantation through-film. Next, P-type body layers 15a and 15i are formed by introducing P-type impurities into the entire surface of the device region A10 and other necessary parts using an ion implantation method with a resist pattern as a mask.

[0073] Specifically, in the active cell region 40a, a P-type body layer 15a is formed between the trench 27 and the trench 28, in contact with the trench insulating film 46 formed on the inner wall of the trench 27 and the trench insulating film 47 formed on the inner wall of the trench 28. This P-type body layer 15a is formed on the N-type barrier layer 14. In the inactive cell region 40i, this P-type body layer 15i is formed on the P-type floating layer 43.

[0074] Furthermore, for example, an N+ type emitter layer 16 is formed in the active cell region 40a by introducing an N-type impurity into the upper layer of the P-type body layer 15a using an ion implantation method with a resist pattern as a mask. Note that in the process of forming the N++ type channel stop layer 11 in the manufacturing method of the peripheral region B10 described above, the N++ type channel stop layer 11 may be formed simultaneously with the N+ type emitter layer 16 in the process of forming the IGBT. Next, an interlayer insulating film 25, including, for example, a PSG (Phosphorous silicate Glass) film, is formed on the upper surface 101 of the semiconductor substrate 100 by, for example, a CVD method. The interlayer insulating film 25 is formed in each of the active cell region 40a and the inactive cell region 40i, for example, to cover the P-type body layers 15a and 15i via an insulating film 24a. Suitable materials for the interlayer insulating film 25 include, in addition to PSG films, BPSG (Borophosphosilicate Glass) films, NSG (Non-doped Silicate Glass) films, SOG (Spin-On-Glass) films, P-TEOS films, or composite films thereof. Furthermore, in the step of forming the first interlayer insulating film 21 in the manufacturing method of the peripheral region B10 described above, the first interlayer insulating film 21 may be formed simultaneously with the interlayer insulating film 25 in the step of forming the IGBT.

[0075] Next, as shown in Figure 10, contact grooves 26 are formed in the interlayer insulating film 25 and insulating film 24a by an anisotropic dry etching method using a resist pattern as a mask. Subsequently, the contact grooves 26 are extended into the semiconductor substrate 100 by the anisotropic dry etching method. As a result, in the active cell region 40a, contact grooves 26 are formed as openings that penetrate the interlayer insulating film 25, insulating film 24a and N+ type emitter layer 16 and reach partway through the P type body layer 15a and trench 28. In the active cell region 40a, the contact grooves 26 are formed continuously along the Y-axis in a plan view.

[0076] Next, a P+ type body contact layer 18 is formed by ion implanting P-type impurities through the contact groove 26, for example. Then, a P+ type latch-up prevention layer 17 is formed by ion implanting P-type impurities through the contact groove 26, for example. The concentration of P-type impurities in the P+ type body contact layer 18 is higher than the concentration of P-type impurities in the P+ type latch-up prevention layer 17.

[0077] Thus, in the active cell region 40a, a P+ type body contact layer 18 and a P+ type latch-up prevention layer 17 are formed on the portion of the P-type body layer 15a exposed to the contact groove 26. In the active cell region 40a, the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 are formed continuously along the Y-axis in a plan view. That is, the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 that are in contact with the P-type body layer 15a are formed in the portion located between the trenches 27 and 28. In the active cell region 40a, the concentration of P-type impurities in the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 is higher than the concentration of P-type impurities in the P-type body layer 15a.

[0078] Next, as shown in Figure 4, emitter wiring 34 is formed. Specifically, for example, a titanium-tungsten film is formed as a barrier metal film on the upper surface 101 of the semiconductor substrate 100 by sputtering. Then, an aluminum metal film is formed on the entire surface of the barrier metal film, for example, by sputtering, so as to fill the contact grooves 26. As a result, emitter wiring 34 is formed inside the contact grooves 26 and on the interlayer insulating film 25 in the active cell region 40a. The emitter wiring 34 electrically connects the multiple N+ type emitter layers 16, multiple P+ type body contact layers 18, and multiple P+ type latch-up prevention layers 17 formed in the active cell region 40a.

[0079] Next, the lower surface 102 of the semiconductor substrate 100 is subjected to back grinding. This thins the semiconductor substrate 100. Next, an N-type field stop layer 45 is formed on the lower surface 102 of the semiconductor substrate 100 by introducing N-type impurities, for example, by ion implantation. Next, a P+-type collector layer 44 is formed on the lower surface 102 of the semiconductor substrate 100 by introducing P-type impurities, for example, by ion implantation. Next, collector wiring 35, electrically connected to the P+-type collector layer 44, is formed on the lower surface 102 of the semiconductor substrate 100 by, for example, sputtering. In this way, the device region A10 can be formed.

[0080] Subsequently, the semiconductor substrate 100 is divided into chip regions by dicing or other methods, and the semiconductor device 1 is largely completed by sealing it in a package as needed.

[0081] Next, the effects of this embodiment will be described. The semiconductor device 1 of this embodiment includes at least one annular N-type guard ring layer 12 between the outermost structure and the N++-type channel stop layer 11, within the interior surrounded by the N++-type channel stop layer 11. This makes it possible to reduce the size of the peripheral breakdown voltage structure in the semiconductor device 1 without impairing the negative charge withstand capability.

[0082] For example, during use of the semiconductor device 1, a large amount of negative charge may reach the upper surface 101 of the semiconductor substrate 100. In such cases, the area near the upper surface 101 directly beneath the second interlayer insulating film 22 in the second peripheral region B12 may invert or nearly invert, making it difficult to maintain the breakdown voltage. However, the semiconductor device 1 of this embodiment has an N-type guard ring layer 12 on the upper surface 101 directly beneath the second interlayer insulating film 22. Therefore, it is possible to suppress the inversion of the area near the upper surface 101 directly beneath the second interlayer insulating film 22.

[0083] Thus, to suppress inversion due to negative charge on the upper surface 101 of the semiconductor substrate 100, it is effective to increase the donor density on the upper surface 101 of the semiconductor substrate 100. One reason for this is that the negative charge on the upper surface 101 of the semiconductor substrate 100 can be canceled out by the positive charge of ionized donors. Here, it is important that the concentration of N-type impurities in the N-type guard ring layer 12 is greater than the concentration of N-type impurities in the N-type drift layer 10, and less than the concentration of N-type impurities in the N++-type channel stop layer 11. With an N-type guard ring layer 12 having such a concentration of N-type impurities, the donor density on the upper surface 101 of the semiconductor substrate 100 in the second peripheral region B12 can be increased. Therefore, inversion near the upper surface 101 can be suppressed.

[0084] Figure 11 is a cross-sectional view illustrating the peripheral region B10 in semiconductor device 1a according to Comparative Example 1. Figure 12 is a cross-sectional view illustrating the peripheral region B10 in semiconductor device 1b according to Comparative Example 2. Figure 13 is a cross-sectional view illustrating the peripheral region B10 in semiconductor device 1c according to Comparative Example 3.

[0085] As shown in Figure 11, the semiconductor device 1a of Comparative Example 1 does not have an N-type guard ring layer 12 on the N-type drift layer 10 in the second peripheral region B12. In this case, if a large amount of negative charge reaches the upper surface 101 of the semiconductor substrate 100 while the semiconductor device 1a is in use, the area near the upper surface 101 directly below the second interlayer insulating film 22 will be inverted or nearly inverted, making it difficult to maintain breakdown voltage.

[0086] As shown in Figure 12, the semiconductor device 1b of Comparative Example 2 has a semiconductor layer 12b on the N-type drift layer 10 in the second peripheral region B12 that contains N++-type impurities at the same concentration as the N++-type channel stop layer 11. In this case, the donor density does not cause continuous depletion from the semiconductor layer 12b to the N++-type channel stop layer 11. As a result, the potential is the same as the equipotential ring 31 up to the -X-axis side end of the semiconductor layer 12b. In other words, it is equivalent to simply extending the N++-type channel stop layer 11 in the -X-axis direction. Therefore, the breakdown voltage of the peripheral region B10 cannot be improved.

[0087] As shown in Figure 13, the semiconductor device 1c of Comparative Example 3 has a semiconductor layer 12c containing N-type impurities at the same concentration as the N-type drift layer 10 on the N-type drift layer 10 in the second peripheral region B12. In this case, the portion of the semiconductor layer 12c also has a donor density that leads to depletion. In other words, it is essentially the same structure as Comparative Example 1. Consequently, the ionization donors contained in the depletion layer extending from the P-type semiconductor layer 13 side, such as the field limiting ring layer 13a, cancel out with the ionization acceptors of the P-type semiconductor layer 13, making it impossible to suppress the inversion on the upper surface 101 side of the semiconductor substrate 100.

[0088] Unlike Comparative Examples 1 to 3, this embodiment includes an N-type guard ring layer 12 that has a different potential from the N++-type channel stop layer 11 and the N-type drift layer 10, so as not to completely deplete the upper surface 101 of the semiconductor substrate 100. Therefore, it is possible to suppress the inversion of the upper surface 101 of the semiconductor substrate 100 and improve the breakdown voltage.

[0089] Furthermore, the N-type guard ring layer 12 is positioned so as to be spaced apart from the N++-type channel stop layer 11. This configuration ensures that the spaced-away portion between the N-type guard ring layer 12 and the N++-type channel stop layer 11 becomes depleted. When multiple N-type guard ring layers 12 are arranged, each N-type guard ring layer 12 may be at a different potential. This configuration improves the breakdown voltage.

[0090] Specifically, the depletion layer wraps around the underside of the N-type guard ring layer 12, depleting it up to the upper surface 101 of the separated portion (excluding the inversion channel). However, the configuration is such that avalanche failure does not occur at the -X-axis side end of the N-type guard ring layer 12 before this happens, nor does the entire N-type guard ring layer 12 become depleted. Therefore, it is desirable to adjust the N-type guard ring layer 12 to have an appropriate width in the X-axis direction.

[0091] For example, the lower limit of the width of the N-type guard ring layers 12 is that none of the multiple N-type guard ring layers 12 become depleted. In other words, if the width of the multiple N-type guard ring layers 12 is narrow, all of the N-type guard ring layers 12 will become depleted. Therefore, the width should be greater than the lower limit.

[0092] On the other hand, while the depletion layer spreads below the N-type guard ring layer 12, the electric field at the -X-axis side end of the N-type guard ring layer 12 continues to rise. Therefore, the upper limit of the width of the N-type guard ring layer 12 is such that it does not undergo avalanche breakdown. In other words, if the width of multiple N-type guard ring layers 12 is wide, avalanche breakdown will occur at the -X-axis side end before the depletion layer reaches the +X-axis side end. Therefore, the width should be smaller than the upper limit.

[0093] Although a single N-type guard ring layer 12 can function, it is preferable to arrange multiple N-type guard ring layers 12 according to the breakdown voltage that should be borne outside the outermost structure when a negative charge reaches the upper surface 101. With only one N-type guard ring layer 12, the breakdown voltage can only be improved by adding a voltage of +α to the voltage required for depletion of the upper surface 101 (excluding the inversion channel) of the separated portion outside the N-type guard ring layer 12. The breakdown voltage can be improved to some extent by widening the width of a single N-type guard ring layer 12 in the X-axis direction. However, if the width is made too wide, the electric field at the inner corner of the N-type guard ring layer 12 becomes too high, leading to avalanche failure and actually reducing the breakdown voltage. For this reason, there is a limit to the width of the N-type guard ring layer 12.

[0094] By providing an equipotential ring 31 in the first peripheral region B11, the breakdown voltage of the semiconductor device 1 can be improved. However, if an N-type guard ring layer 12 is present, the equipotential ring 31 may be unnecessary from the viewpoint of negative charge tolerance.

[0095] If the N-type guard ring layer 12 is not present, the equipotential ring 31 is extended from the N++-type channel stop layer 11 onto the semiconductor substrate 100 to act as an inverse field plate in terms of negative charge withstand capability. On the other hand, if the N-type guard ring layer 12 is present, when a negative charge reaches the upper surface 101, the portion below the extended portion of the equipotential ring 31 where the negative charge does not reach will support the withstand voltage. As a result, the electric field becomes high at the end of the extended portion of the equipotential ring 31. Therefore, for example, the equipotential ring 31 is placed directly above the N++-type channel stop layer 11, so that the equipotential ring 31 does not extend inward from the N++-type channel stop layer 11. In other words, the inner end of the equipotential ring 31 is made to coincide with the inner end of the N++-type channel stop layer 11. Alternatively, the inner end of the equipotential ring 31 may be placed outside the inner end of the N++-type channel stop layer 11. With this configuration, the N-type guard ring layer 12 can support the voltage when a negative charge reaches the upper surface 101. Therefore, it is possible to suppress the application of a large electric field to the inner end of the equipotential ring 31.

[0096] Furthermore, if the positive charge reaches the upper surface 101, the depletion layer does not extend in the direction of the first peripheral region B11 or the second peripheral region B12, so there is no need for the first peripheral region B11 or the second peripheral region B12 to share the breakdown voltage. As its name suggests, the equipotential ring 31 is primarily intended to prevent the potential around the outer periphery of the element region A10 from becoming uneven along the outer edge. Therefore, it is acceptable to narrow the width of the equipotential ring 31 to an extent that does not impair its function. Also, if the effect of uneven potential around the outer periphery of the element region A10 is small, it may even be possible to omit the equipotential ring 31 altogether.

[0097] If the semiconductor device in device region A10 is an IGBT having an N-type barrier layer 14, and the ion implantation energy used to form the N-type barrier layer 14 is sufficiently high to penetrate the already existing second interlayer insulating film 22 or a part of it (e.g., LOCOS) during the manufacturing process, then the N-type guard ring layer 12 may be formed in the same manufacturing process as the N-type barrier layer 14. This can reduce manufacturing costs.

[0098] Because the N++ type channel stop layer 11 requires high-dose ion implantation, it is difficult to introduce N-type impurities through a thick interlayer insulating film such as LOCOS. On the other hand, when forming the first interlayer insulating film 21, providing a special step to remove the material for forming the first interlayer insulating film 21 in the area where the second interlayer insulating film 22 already exists would lead to an increase in manufacturing costs. Therefore, the thickness of the first interlayer insulating film 21 is made smaller than the thickness of the second interlayer insulating film 22. For example, by forming the portion of the second interlayer insulating film 22 that is on the semiconductor substrate 100 side, and then forming the remaining portion of the second interlayer insulating film 22 and the first interlayer insulating film 21 in the same process, the thickness of the first interlayer insulating film 21 becomes smaller than the thickness of the second interlayer insulating film 22.

[0099] The interlayer insulating film in the peripheral region B10 may have a fixed positive charge. The fixed positive charge in the interlayer insulating film suppresses the elongation of the depletion layer, thus narrowing the gap between the outermost structure and the N++ type channel stop layer 11, and reducing the size of the semiconductor device 1. For example, the interlayer insulating film can be formed using P-TEOS, and the positive charge generated within the P-TEOS can be fixed by RTA.

[0100] The present inventors' disclosures have been described in detail above based on embodiments. However, it goes without saying that this disclosure is not limited to the embodiments and modifications described above, and can be modified in various ways without departing from its essence. For example, any combination of the components of Embodiment 1 is also within the scope of the technical concept of the embodiment. Furthermore, the following configurations are also within the scope of the technical concept of the embodiment.

[0101] (Note 1) A semiconductor substrate having a first main surface and a second main surface opposite the first main surface, comprising the steps of defining an element region containing a semiconductor element and a peripheral region surrounding the element region in a plan view from the first main surface side, On the semiconductor substrate in the peripheral region, A first conductive drift layer, A first conductivity type channel stop layer disposed on the first main surface side of the drift layer, comprising the step of forming at least one annular channel stop layer surrounding the element region, A first conductive type guard ring layer disposed on the first main surface side of the drift layer, comprising the step of forming at least one annular guard ring layer disposed between the outermost outermost structure inside the channel stop layer and the channel stop layer, Equipped with, In the step of forming the guard ring layer, The outermost structure includes at least one of an annular second conductivity type semiconductor layer disposed on the first main surface side of the drift layer in the semiconductor substrate, and an annular field plate containing a conductive material disposed on the first main surface side of the semiconductor substrate. The concentration of the first conductivity type impurity in the guard ring layer is greater than the concentration of the first conductivity type impurity in the drift layer, and less than the concentration of the first conductivity type impurity in the channel stop layer. A method for manufacturing a semiconductor device. (Note 2) In the step of forming the guard ring layer, The guard ring layer is spaced apart from the channel stop layer. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 3) In the step of forming the guard ring layer, The semiconductor substrate in the peripheral region includes a plurality of guard ring layers. Multiple guard ring layers are arranged to be spaced apart from each other. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 4) The steps include forming a first interlayer insulating film on the first main surface side of the semiconductor substrate in the peripheral region, The steps include forming a contact groove in the first interlayer insulating film, The steps include forming the equipotential ring containing the conductive material on the first main surface side of the first interlayer insulating film, Furthermore, In the step of forming the equipotential ring, The equipotential ring is formed so as to be connected to the channel stop layer via the contact groove. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 5) In the step of forming the equipotential ring, The guard ring layer is formed such that it is spaced apart from the equipotential ring in a plan view, The method for manufacturing a semiconductor device as described in Appendix 4. (Note 6) In the step of defining the element region including the semiconductor element and the peripheral region surrounding the element region, The aforementioned peripheral region is A third peripheral region surrounding the aforementioned element region, The element region and the second peripheral region surrounding the third peripheral region, The element region, the third peripheral region and the second peripheral region are surrounded by a first peripheral region, Make sure to include, The steps include forming a first interlayer insulating film on the first main surface side of the semiconductor substrate in the first peripheral region, The steps include forming a second interlayer insulating film on the first main surface side of the semiconductor substrate in the second peripheral region, Furthermore, In the step of forming the two-layer insulating film, The thickness of the second interlayer insulating film is made greater than the thickness of the first interlayer insulating film. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 7) In the step of forming the two-layer insulating film, The second interlayer insulating film contains LOCOS, The guard ring layer is to be covered by the LOCOS. The method for manufacturing a semiconductor device as described in Appendix 6. (Note 8) The steps include forming a plurality of field limiting ring layers within the area surrounded by the channel stop layer on the first main surface side of the drift layer in the semiconductor substrate in the peripheral region, The steps include forming a third interlayer insulating film on the first main surface side of the semiconductor substrate, The steps include forming a plurality of contact grooves in the third interlayer insulating film, The steps include forming a plurality of field plates on the first main surface side of the third interlayer insulating film, Furthermore, In the step of forming the field plate, Multiple field plates are connected to multiple field limiting ring layers via multiple contact grooves, The outermost structure includes, among the plurality of field limiting ring layers and the plurality of field plates, any of the field limiting ring layers and the field plates arranged on the outermost periphery. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 9) The step further comprises forming a second conductivity type semiconductor layer on the semiconductor substrate in the peripheral region, which functions as a termination structure located on the first main surface side of the drift layer, within the space surrounded by the channel stop layer. In the step of forming the semiconductor layer, The outermost structure includes the semiconductor layer. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 10) The step of forming the semiconductor element further comprises, The aforementioned semiconductor device is The drift layer and, A second conductive floating layer is disposed on the first main surface side of the drift layer, Make sure to include, In the step of forming the semiconductor element, The outermost structure includes the floating layer. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 11) The step further comprises forming an interlayer insulating film on the first main surface side of the semiconductor substrate in the peripheral region, In the step of forming the interlayer insulating film, The interlayer insulating film is designed to fix positive charges. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 12) In the step of defining the element region including the semiconductor element and the peripheral region surrounding the element region, The aforementioned peripheral region is A third peripheral region surrounding the aforementioned element region, The element region and the second peripheral region surrounding the third peripheral region, The element region, the third peripheral region and the second peripheral region are surrounded by a first peripheral region, Make sure to include, In the aforementioned third peripheral region, The drift layer and, A second conductive field limiting ring layer is disposed on the first main surface side of the drift layer, A third interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the field limiting ring layer is arranged, The field plate provided on the first main surface side of the third interlayer insulating film, The steps of forming, In the second peripheral region, The drift layer and, The guard ring layer and, A second interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the guard ring layer is arranged, The steps of forming, In the first peripheral region, The drift layer and, The channel stop layer, A first interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the channel stop layer is arranged, An equipotential ring provided on the first main surface side of the first interlayer insulating film, the equipotential ring containing a conductive material, The steps of forming, Furthermore, it is equipped with A method for manufacturing a semiconductor device as described in Appendix 1. (Note 13) The step further comprises forming an IGBT as the semiconductor element in the element region, The aforementioned IGBT is The drift layer and, A first conductive barrier layer is disposed on the first main surface side of the drift layer, A second conductive body layer is disposed on the first main surface side of the barrier layer, A first conductive emitter layer is disposed on the first main surface side of the body layer, The barrier layer, the body layer, and the emitter layer are sandwiched from both sides by a trench gate electrode and a trench emitter electrode, which are provided so as to sandwich the barrier layer, the body layer, and the emitter layer from both sides in one direction in a plane parallel to the first main surface. A trench insulating film is provided between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate. The second conductive floating layer is provided on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench gate electrode in between, and on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench emitter electrode in between, To have, In the step of forming the guard ring layer, The guard ring layer is formed simultaneously with the barrier layer in the step of forming the IGBT. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 14) In the step of forming the guard ring layer, The guard ring layer contains the same type of impurities as the impurities in the barrier layer. The method for manufacturing a semiconductor device as described in Appendix 13. (Note 15) In the step of forming the guard ring layer, The guard ring layer contains the same concentration of impurities as the barrier layer. The method for manufacturing a semiconductor device as described in Appendix 13. (Note 16) The semiconductor device includes at least one of a MOSFET and a diode. A method for manufacturing a semiconductor device as described in Appendix 1. (Note 17) The step further comprises forming a second interlayer insulating film on the first main surface side of the semiconductor substrate, The step of forming the guard ring layer involves introducing an impurity of the first conductivity type into the semiconductor substrate via the second interlayer insulating film. A method for manufacturing a semiconductor device as described in Appendix 1. [Explanation of Symbols]

[0102] 1, 1a, 1b, 1c Semiconductor device 10 N-type drift layer 11. N++ type channel stop layer 12 N-type guard ring layer 12b, 12c semiconductor layer 13 P-type semiconductor layer 13a Field limiting ring layer 14. N-type barrier layer 15a, 15i P-type body layer 16 N+ type emitter layer 17 P+ type latch-up prevention layer 18 P+ type body contact layer 21 First interlayer insulating film 22 Second interlayer insulating film 23 Third Interlayer Insulating Film 24, 24a insulating film 25 Interlayer insulating film 26 Contact grooves 27, 28 Trench 29 Conductive film 31 Equipotential rings 33 Field Plate 34 Emitter Wiring 35 Collector Wiring 40 unit cell area 40a Active cell area 40i Inactive Cell Area 41 Trench Gates 42 Trench Emitter Electrode 43 P-type floating layer 44 P+ type collector layer 45 N-type field stop layer 46, 47 Trench insulating film 100 semiconductor substrates 101 Top surface 102 Bottom surface A10 Element Region B10 Peripheral Area B11 First Peripheral Area B12 Second Peripheral Area B13 Third Peripheral Area

Claims

1. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, In a plan view from the first main surface side, the semiconductor substrate is, A device region including a semiconductor element, The peripheral region surrounding the aforementioned element region, Includes, The semiconductor substrate in the peripheral region is A first conductive drift layer, A first conductivity type channel stop layer disposed on the first main surface side of the drift layer, comprising at least one annular channel stop layer surrounding the element region, A first conductive type guard ring layer disposed on the first main surface side of the drift layer, comprising at least one annular guard ring layer disposed between the outermost outermost structure inside the channel stop layer surrounded by the channel stop layer in the plan view, Includes, The outermost structure includes at least one of an annular second conductivity type semiconductor layer disposed on the first main surface side of the drift layer in the semiconductor substrate, and a field plate containing an annular conductive material disposed on the first main surface side of the semiconductor substrate. The concentration of the first conductivity type impurity in the guard ring layer is greater than the concentration of the first conductivity type impurity in the drift layer, and less than the concentration of the first conductivity type impurity in the channel stop layer. Semiconductor equipment.

2. The guard ring layer is spaced apart from the channel stop layer. The semiconductor device according to claim 1.

3. The semiconductor substrate in the peripheral region includes a plurality of guard ring layers, Multiple guard ring layers are spaced apart from each other. The semiconductor device according to claim 1.

4. A first interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the channel stop layer is arranged, An equipotential ring provided on the first main surface side of the first interlayer insulating film, comprising the equipotential ring containing the conductive material, Furthermore, The equipotential ring is connected to the channel stop layer via a contact groove formed in the first interlayer insulating film. The semiconductor device according to claim 1.

5. The guard ring layer is spaced apart from the equipotential ring in a plan view. The semiconductor device according to claim 4.

6. A first interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the channel stop layer is arranged, A second interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the guard ring layer is arranged, Furthermore, The thickness of the second interlayer insulating film is greater than the thickness of the first interlayer insulating film. The semiconductor device according to claim 1.

7. The second interlayer insulating film contains LOCOS, The guard ring layer is covered with the LOCOS, The semiconductor device according to claim 6.

8. The semiconductor substrate in the peripheral region comprises a plurality of annular field-limiting ring layers of a second conductivity type, arranged on the first main surface side of the drift layer, and including a plurality of field-limiting ring layers arranged inside the area surrounded by the channel stop layer. The semiconductor substrate on which the field limiting ring layer is arranged is further provided with a third interlayer insulating film located on the first main surface side, Each of the field plates is connected to each of the field limiting ring layers via a plurality of contact grooves formed in the third interlayer insulating film. The outermost structure includes, among the plurality of field limiting ring layers and the plurality of field plates, any of the field limiting ring layers and the field plates arranged on the outermost periphery. The semiconductor device according to claim 1.

9. The semiconductor substrate in the peripheral region includes a second conductivity type semiconductor layer that functions as a termination structure located on the first main surface side of the drift layer, and comprises the semiconductor layer located inside the channel stop layer. The outermost structure includes the semiconductor layer, The semiconductor device according to claim 1.

10. The aforementioned semiconductor device is The drift layer and, A second conductive floating layer is disposed on the first main surface side of the drift layer, Includes, The outermost structure includes the floating layer, The semiconductor device according to claim 1.

11. The peripheral region further comprises an interlayer insulating film provided on the first main surface side of the semiconductor substrate, The interlayer insulating film has a fixed positive charge, The semiconductor device according to claim 1.

12. The aforementioned peripheral region is A third peripheral region surrounding the element region, The element region and the second peripheral region surrounding the third peripheral region, The element region, the third peripheral region, and the second peripheral region are surrounded by a first peripheral region, Includes, The third peripheral region described above is The drift layer and, A second conductive field limiting ring layer is disposed on the first main surface side of the drift layer, A third interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the field limiting ring layer is arranged, The field plate provided on the first main surface side of the third interlayer insulating film, Includes, The aforementioned second peripheral region is, The drift layer and, The guard ring layer and, A second interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the guard ring layer is arranged, Includes, The first peripheral region is, The drift layer and, The channel stop layer, A first interlayer insulating film is provided on the first main surface side of the semiconductor substrate on which the channel stop layer is arranged, An equipotential ring provided on the first main surface side of the first interlayer insulating film, the equipotential ring containing a conductive material, including, The semiconductor device according to claim 1.

13. The semiconductor device includes an IGBT, The aforementioned IGBT is, The drift layer and, A first conductive barrier layer is disposed on the first main surface side of the drift layer, A second conductive body layer is disposed on the first main surface side of the barrier layer, A first conductive emitter layer is disposed on the first main surface side of the body layer, The barrier layer, the body layer, and the emitter layer are sandwiched from both sides in one direction in a plane parallel to the first main surface by a trench gate electrode and a trench emitter electrode, A trench insulating film is provided between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate. A second conductive floating layer is provided on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench gate electrode in between, and on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench emitter electrode in between. Having, The semiconductor device according to claim 1.

14. The guard ring layer contains the same type of impurities as the impurities in the barrier layer. The semiconductor device according to claim 13.

15. The guard ring layer contains the same concentration of impurities as the barrier layer. The semiconductor device according to claim 13.

16. The semiconductor device includes at least one of a MOSFET and a diode. The semiconductor device according to claim 1.

17. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, comprising the steps of setting an element region containing a semiconductor element and a peripheral region surrounding the element region in a plan view from the first main surface side, On the semiconductor substrate in the peripheral region, A first conductive drift layer, A first conductivity type channel stop layer disposed on the first main surface side of the drift layer, comprising the step of forming at least one annular channel stop layer surrounding the element region, A first conductive type guard ring layer disposed on the first main surface side of the drift layer, comprising the step of forming at least one annular guard ring layer disposed between the outermost outermost structure inside the channel stop layer and the channel stop layer, Equipped with, In the step of forming the guard ring layer, The outermost structure includes at least one of an annular second conductivity type semiconductor layer disposed on the first main surface side of the drift layer in the semiconductor substrate, and an annular field plate containing a conductive material disposed on the first main surface side of the semiconductor substrate. The concentration of the first conductivity type impurity in the guard ring layer is greater than the concentration of the first conductivity type impurity in the drift layer, and less than the concentration of the first conductivity type impurity in the channel stop layer. A method for manufacturing a semiconductor device.

18. The step of forming an IGBT as the semiconductor element in the element region further comprises The aforementioned IGBT is, The drift layer and, A first conductive barrier layer is disposed on the first main surface side of the drift layer, A second conductive body layer is disposed on the first main surface side of the barrier layer, A first conductive emitter layer is disposed on the first main surface side of the body layer, The barrier layer, the body layer, and the emitter layer are sandwiched from both sides in one direction in a plane parallel to the first main surface by a trench gate electrode and a trench emitter electrode, A trench insulating film is provided between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate. The second conductive floating layer is provided on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench gate electrode in between, and on the opposite side of the barrier layer, the body layer, and the emitter layer, with the trench emitter electrode in between, To have, In the step of forming the guard ring layer, The guard ring layer is formed simultaneously with the barrier layer in the step of forming the IGBT. The method for manufacturing a semiconductor device according to claim 17.

19. In the step of defining the element region including the semiconductor element and the peripheral region surrounding the element region, The aforementioned peripheral region is A third peripheral region surrounding the element region, The element region and the second peripheral region surrounding the third peripheral region, The element region, the third peripheral region, and the second peripheral region are surrounded by a first peripheral region, Make sure to include, The steps include forming a first interlayer insulating film on the first main surface side of the semiconductor substrate in the first peripheral region, The steps include forming a second interlayer insulating film on the first main surface side of the semiconductor substrate in the second peripheral region, Furthermore, In the step of forming the two-layer insulating film, The thickness of the second interlayer insulating film is made greater than the thickness of the first interlayer insulating film. The method for manufacturing a semiconductor device according to claim 17.

20. The step further comprises forming a second interlayer insulating film on the first main surface side of the semiconductor substrate, The step of forming the guard ring layer involves introducing an impurity of a first conductivity type into the semiconductor substrate via the second interlayer insulating film. The method for manufacturing a semiconductor device according to claim 17.

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