Power management circuit

Abstract

This provides a power management circuit that can reduce noise in the power supply voltage. [Solution] The power management circuit 1 includes a clock signal generation unit 166 that generates a first clock signal for the first switching element of the first DC / DC converter and a second clock signal for the second switching element of the second DC / DC converter, and a delay amount determination unit 164 that determines the delay amount for the rising edge of the second clock signal relative to the rising edge of the first clock signal, based on the first duty cycle of the first switching element and the second duty cycle of the second switching element, such that the rising edge of the first clock signal does not overlap with the falling edge of the second clock signal, or the falling edge of the first clock signal does not overlap with the rising edge or falling edge of the second clock signal. The clock signal generation unit generates a second clock signal whose rising edge is delayed relative to the first clock signal by the delay amount determined by the delay amount determination unit.

Description

[Technical Field]

[0001] This disclosure relates to a power management circuit. [Background technology]

[0002] Patent Document 1 discloses a Power Management Integrated Circuit (PMIC) equipped with multiple DC / DC converters. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-120947

[0004] [overview] The inventors have come to recognize the following problem: A DC / DC converter generates a desired output voltage by driving internal transistor elements in response to a clock signal. When the transistor elements switch, the circuit current in the control circuit and drive circuit of the DC / DC converter increases or decreases rapidly, generating noise in the power supply voltage inside the PMIC. In particular, when the switching elements of multiple DC / DC converters switch simultaneously, even greater noise is generated in the power supply voltage, affecting the operation of the DC / DC converter.

[0005] This disclosure has been made in view of these circumstances, and one of its exemplary objectives is to provide a power management circuit that can reduce noise in the power supply voltage.

[0006] A power management circuit in one aspect of the present disclosure includes: a clock signal generation unit that generates a first clock signal for driving a first switching element of a first DC / DC converter and a second clock signal for driving a second switching element of a second DC / DC converter; and a delay amount determination unit that determines the amount of delay for the rising edge of the second clock signal relative to the rising edge of the first clock signal, based on the first duty cycle of the first switching element and the second duty cycle of the second switching element, such that the rising edge of the first clock signal does not overlap with the falling edge of the second clock signal, or the falling edge of the first clock signal does not overlap with the rising or falling edge of the second clock signal. The first clock signal and the second clock signal each have the same period. The clock signal generation unit generates a second clock signal whose rising edge is delayed relative to the first clock signal by the amount of delay determined by the delay amount determination unit.

[0007] Furthermore, any combination of the above components, as well as any conversion of the expressions of this disclosure between methods, apparatus, systems, etc., are also valid as aspects of this disclosure. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram of the power management circuit related to the reference technology. [Figure 2] Figure 2 shows the power supply voltage and clock signal timing chart related to the reference technology. [Figure 3] Figure 3 shows the timing charts for the three clock signals and power supply voltages related to the reference technology. [Figure 4] Figure 4 shows the timing charts of the clock signal and power supply voltage when the duty cycle of the high-side transistor related to the reference technology is different. [Figure 5] Figure 5 is a block diagram of the power management circuit according to the first embodiment. [Figure 6] Figure 6 shows an example configuration of a DC / DC converter according to the same embodiment. [Figure 7]FIG. 7 is a block diagram of the controller according to this embodiment. [Figure 8] FIG. 8 is a block diagram of the clock signal generation device according to this embodiment. [Figure 9] FIG. 9 is a timing chart of an example of the first clock signal and the second clock signal according to this embodiment. [Figure 10] FIG. 10 is a timing chart showing an example of the first clock signal, the second clock signal, and the third clock signal generated by the clock signal generation unit according to this embodiment. [Figure 11] FIG. 11 is a flowchart showing an example of the operation of the clock signal generation device according to this embodiment. [Figure 12] FIG. 12 is a flowchart showing an example of the flow of the delay amount determination process according to this embodiment. [Figure 13] FIG. 13 is a block diagram of the clock signal generation device according to the second embodiment. <S [Figure 14] FIG. 14 is a timing chart showing an example of the first clock signal, the sixth clock signal, and the seventh clock signal according to this embodiment. [Figure 15] [[ID=?]]FIG. 15 is a block diagram of the clock signal generation device according to the third embodiment. [Figure 16] FIG. 16 is a block diagram of the first clock signal generation block according to this embodiment. [Figure 17] FIG. 17 is a block diagram showing a configuration example of the overlap condition determination unit according to this embodiment. [Figure 18] FIG. 18 is a block diagram showing a configuration example of the first delay amount determination unit according to this embodiment. [Figure 19] FIG. 19 is a block diagram showing a configuration example of the first clock signal generation unit according to this embodiment. [Figure 20] FIG. 20 is a block diagram of the second clock signal generation block according to this embodiment. [Figure 21] FIG. 21 is a block diagram showing a configuration example of the second clock signal generation unit according to this embodiment. It seems there is a formatting issue in the original text where "図15は、第3実施形態に係るクロック信号生成装置のブロック図である。" has a "?" in the English translation placeholder. I've left it as it is for now based on the instructions to preserve the original text structure. You may want to double-check the original content for accuracy. [Figure 22] Figure 22 is a timing chart showing an example of various signals in the clock signal generation device according to the same embodiment.

[0009] [Detailed explanation] (overview) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow later. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify the essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one embodiment (example or variation) or more embodiments (example or variation) disclosed herein.

[0010] A power management circuit according to one embodiment includes a clock signal generation unit that generates a first clock signal for driving a first switching element of a first DC / DC converter and a second clock signal for driving a second switching element of a second DC / DC converter, and a delay amount determination unit that determines the amount of delay for the rising edge of the second clock signal relative to the rising edge of the first clock signal, based on the first duty cycle of the first switching element and the second duty cycle of the second switching element, such that the rising edge of the first clock signal does not overlap with the falling edge of the second clock signal, or the falling edge of the first clock signal does not overlap with the rising or falling edge of the second clock signal. The first clock signal and the second clock signal each have the same period. The clock signal generation unit generates a second clock signal whose rising edge is delayed relative to the first clock signal by the amount of delay determined by the delay amount determination unit.

[0011] This configuration eliminates the overlap of rising edges between the first and second clock signals, and also suppresses the overlap of the falling edges of one clock signal with the rising or falling edges of the other clock signal. This makes it possible to reduce noise in the power supply voltage.

[0012] In one embodiment, the power management circuit may further include a duty cycle calculation unit that calculates a first duty cycle of a first switching element based on input voltage data and output voltage data of a first DC / DC converter, and calculates a second duty cycle of the first switching element based on input voltage data and output voltage data of a second DC / DC converter. The delay amount determination unit may determine the delay amount based on the first duty cycle and the second duty cycle calculated by the duty cycle calculation unit, respectively.

[0013] In one embodiment, the delay amount determination unit may determine whether a first overlap condition, a second overlap condition, or a third overlap condition is met when the rising edge of the second clock signal is delayed relative to the rising edge of the first clock signal, and determine the amount of delay of the rising edge of the second clock signal relative to the rising edge of the first clock signal based on the determination result. The first overlap condition may be that the rising edge of the first clock signal and the falling edge of the second clock signal coincide. The second overlap condition may be that the falling edge of the first clock signal and the rising edge of the second clock signal coincide. The third overlap condition may be that the falling edge of the first clock signal and the falling edge of the second clock signal coincide.

[0014] In one embodiment, the delay amount determination unit may determine the delay amount such that both the first overlap condition and the second overlap condition are not satisfied.

[0015] In one embodiment, the delay amount determination unit may determine the delay amount such that the first overlap condition, the second overlap condition, and the third overlap condition are all satisfied.

[0016] In one embodiment, the delay amount determination unit has a period T which is 1 / m (m is an integer of 2 or more) times the period T of the first clock signal. REF Based on a reference clock signal having the period T, for each of a plurality of different delay amounts Δ (0 < Δ < T), it may be determined whether the first overlap condition, the second overlap condition, or the third overlap condition is satisfied. REF

[0017] In one embodiment, the delay amount determination unit may determine the smallest delay amount Δ among the delay amounts Δ for which all of the first overlap condition, the second overlap condition, and the third overlap condition are not satisfied as the delay amount of the second clock signal with respect to the first clock signal.

[0018] In one embodiment, the clock signal generation unit may further generate a third clock signal for the third DC / DC converter. The delay amount determination unit may determine the delay amount of the second clock signal with respect to the rising edge of the first clock signal and the delay amount of the rising edge of the third clock signal with respect to the rising edge of the second clock signal such that the rising edge of the first clock signal does not overlap the falling edge of the third clock signal, or such that the falling edge of the first clock signal does not overlap the rising edge or the falling edge of the third clock signal.

[0019] In one embodiment, the clock signal generation unit may generate first to p clock signals, each having the same period, for driving each switching element of the first to p DC / DC converters (where p is an integer of 3 or more). The delay amount determination unit may determine the k-th delay amount for the rising edge of the (k+1) clock signal relative to the rising edge of the (k+1) clock signal for each pair of the k-th clock signal and the (k+1) clock signal, based on the k-th duty cycle of the k-th clock signal and the (k+1) duty cycle of the (k+1) clock signal, such that the rising edge of the k-th clock signal does not overlap with the falling edge of the (k+1) clock signal, or the falling edge of the k-th clock signal does not overlap with the rising or falling edge of the (k+1) clock signal. The first to p clock signals may be arranged in descending order of duty cycle. The clock signal generation unit may generate a (k+1) clock signal for each pair of the k-th clock signal and the (k+1)-th clock signal, with the rising edge of the (k+1)-th clock signal delayed by the k-th delay amount determined by the delay amount determination unit.

[0020] In one embodiment, the delay amount determination unit may determine the delay amount of the (k+1) clock signal for each pair of the k-th clock signal and the (k+1)-th clock signal, starting with the pair of clock signals with the largest duty cycle, for each pair where all of the first, second, and third overlap conditions are not met. The first overlap condition may be that the rising edge of the k-th clock signal and the falling edge of the (k+1)-th clock signal coincide. The second overlap condition may be that the falling edge of the k-th clock signal and the rising edge of the (k+1)-th clock signal coincide. The third overlap condition may be that the falling edge of the k-th clock signal and the falling edge of the (k+1)-th clock signal coincide.

[0021] In one embodiment, the delay amount determination unit determines a period T that is 1 / m (where m is an integer of 2 or more) times the same period T. REFBased on a reference clock signal having, an initial value of the delay amount Δ (0 < Δ < T) of the (k + 1)-th clock signal with respect to the k-th clock signal is Δ INIT Let it be, and the delay amount is Δ INIT From to T REF While changing by each, it may be determined whether all of the first overlapping condition, the second overlapping condition, and the third overlapping condition are satisfied, and the delay amount may be determined based on the determination result. The initial value Δ INIT May be a value obtained by multiplying the integer part of m / (p - 1) by the period T REF That is.

[0022] In one embodiment, the clock signal generation unit generates first to p-th clock signals each having the same period for driving first to p-th switching elements respectively included in first to p DC / DC converters (p is an integer of 4 or more). When the delay amount determination unit divides the first to p-th clock signals into first to x-th clock signals (x is an integer greater than or equal to 2 and less than p - 1) and (x + 1)-th to p-th clock signals, it may include a first delay amount determination unit that determines the delay amount regarding the first to x-th clock signals, and a second delay amount determination unit that determines the delay amount regarding the (x + 1)-th to p-th clock signals. The first delay amount determination unit is for the k x (k x Is an integer from 1 to x - 1.) So that the rise of the k-th x Duty of the switching element and the (k x + 1) The (k x + 1) duty, so that the rise of the k-th x Clock signal does not overlap with the fall of the (k x + 1) clock signal, or the fall of the k x Clock signal does not overlap with the rise or fall of the (k x + 1) clock signal, for the rise of the k x Clock signal with respect to the (k x+1) The delay amount of the rising edge of the clock signal may be determined. The second delay amount determination unit determines the delay amount of the rising edge of the (x+1) clock signal relative to the rising edge of the first clock signal, based on the first duty cycle and the (x+1) duty cycle of the (x+1) switching element, such that the falling edge of the (x+1) clock signal is delayed by one period from the rising edge of the first clock signal, and the k y (k y (where x is an integer between x+1 and p-1.) The kth of the switching element y Duty and (k y +1) After the switching element (k y +1) Based on the duty cycle, the k y The falling edge of the clock signal is the (k y +1) So that it does not overlap with the rising edge of the clock signal, or the kth y The rising edge of the clock signal is (k y +1) The (k) y +1) kth relative to the falling edge of the clock signal y The amount of delay in the falling edge of the clock signal may be determined.

[0023] In one embodiment, the clock signal generation unit may include a cyclic counter, a first rising trigger circuit for generating a first rising signal, a first falling trigger circuit for generating a first falling signal, a second rising trigger circuit for generating a second rising signal, a second falling trigger circuit for generating a second falling signal, a first JK flip-flop for generating a first clock signal, and a second JK flip-flop for generating a second clock signal. The cyclic counter has a period T of the first clock signal that is 1 / m (where m is an integer of 2 or more) times the period T. REF Based on a reference clock signal having one period T REFThe counter value may be incremented by one each time, starting from 0, and reset to 0 when the counter value reaches m. The first rising edge trigger circuit may set the first rising edge signal high when the counter value is 0, and low when the counter value is not 0. The first falling edge trigger circuit may set the first duty cycle to D DUTY1 The counter value is m × D DUTY1 When this is the case, the first falling edge signal is set to high, and the counter value is m × D DUTY1 When this is different, the first falling edge signal may be set to low. The second rising edge trigger circuit sets the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal to D. DLY1 The counter value is D DLY1 / T REF When this is the case, the second rising edge signal is set to high, and the counter value is D DLY1 / T REF When it is different, the second rising edge signal may be set to low. The second falling edge trigger circuit sets the duty cycle of the second clock signal to D DUTY2 The counter value is (D DLY1 / T REF +m×D DUTY2 When ), the second falling edge signal is set to high, and the counter value is (D DLY1 / T REF +m×D DUTY2 The second falling edge signal may be set to low when it is different from the first falling edge signal. The first rising edge signal may be input to the J terminal of the first JK flip-flop. The first falling edge signal may be input to the K terminal of the first JK flip-flop. The second rising edge signal may be input to the J terminal of the second JK flip-flop. The second falling edge signal may be input to the K terminal of the second JK flip-flop. The first JK flip-flop may generate a first clock signal in accordance with a reference clock signal input to the clock signal terminal. The second JK flip-flop may generate a second clock signal in accordance with a reference clock signal input to the clock signal terminal.

[0024] In one embodiment, the power management circuit may further include a first DC / DC converter and a second DC / DC converter.

[0025] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Also, the embodiments are illustrative and not restrictive of the disclosure and the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and the invention.

[0026] In this specification, "member A is connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0027] Similarly, "member C is connected (provided) between member A and member B" includes not only the case where member A and member C or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0028] Also in this specification, the reference numerals assigned to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors represent their respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductance), as appropriate.

[0029] Also in this specification, "integrated integration" includes the case where all components of a circuit are formed on a semiconductor substrate, or the case where the main components of a circuit are integrally integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting circuit constants.

[0030] (Related Art and Its Problems) Figure 1 is a block diagram of the power management circuit 9 relating to the reference technology. The power management circuit 9 relating to the reference technology comprises an internal power supply 90, a first DC / DC converter 92_1, a second DC / DC converter 92_2, a third DC / DC converter 92_3, and a system circuit block 94.

[0031] The internal power supply 90 supplies power supply voltage V to each of the following: the first DC / DC converter 92_1, the second DC / DC converter 92_2, the third DC / DC converter 92_3, and the system circuit block 94. DD The system circuit block 94 supplies the clock signal CLK. 91 CLK 92 CLK 93 Generates.

[0032] The first DC / DC converter 92_1, the second DC / DC converter 92_2, and the third DC / DC converter 92_3 each have an output stage composed of a high-side transistor and a low-side transistor. The output voltage is generated when these transistors are driven in response to a clock signal.

[0033] The first DC / DC converter 92_1 receives the clock signal CLK 91 Output voltage V OUT91 The second DC / DC converter 92_2 generates the clock signal CLK. 92 Output voltage V OUT92 The third DC / DC converter 92_3 generates the clock signal CLK. 93 Output voltage V OUT93 Generates.

[0034] Figure 2 shows the power supply voltage V related to the reference technology. DD , clock signal CLK 91 CLK 92 This is the timing chart. The high-side transistor of the first DC / DC converter 92_1 receives the clock signal CLK. 91 The high-side transistor of the first DC / DC converter 92_2 switches accordingly, and the clock signal CLK 92Switching shall be performed accordingly. Here, the duty cycles of both high-side transistors are the same, and the clock signal CLK 91 CLK 92 Assume that the period is also the same.

[0035] Clock signal CLK 91 CLK 92 When a rising or falling edge occurs, a sudden change occurs in the circuit current inside the first DC / DC converter 92_1 and the second DC / DC converter 92_2, causing the power supply voltage V DD Noise is generated at timing t. As shown in Figure 2, 91 In this case, the clock signal CLK 91 CLK 92 They start up simultaneously, timing t 92 In this case, the clock signal CLK 91 CLK 92 They fall down simultaneously. Therefore, timing t 91 ,t 92 In this case, the noise from the two DC / DC converters reinforces each other, and the power supply voltage V DD A large amount of noise is generated.

[0036] Therefore, to prevent the rising and falling edges of the clock signal from overlapping, the clock signal CLK 91 For the clock signal CLK 92 Delay the clock signal CLK 92 For the clock signal CLK 93 Further delays are being considered.

[0037] Figure 3 shows the three clock signals CLK related to the reference technology. 91 CLK 92 CLK 93 and power supply voltage V DD This is a timing chart. In this example, the clock signal CLK 92 is the clock signal CLK 91 It is delayed by ΔT9, and the clock signal CLK 93 is the clock signal CLK 92It is delayed by ΔT9 with respect to

[0038] In the example shown in FIG. 3, the rising and falling edges of the clock signal CLK 91 do not overlap with either the rising or falling edge of the clock signal CLK 92 ,CLK 93 . Also, the rising and falling edges of the clock signal CLK 92 do not overlap with either the rising or falling edge of the clock signal CLK 93 . As a result, the timings at which noise is generated due to the rising and falling edges of the clock signal CLK 91 ,CLK 92 ,CLK 93 are dispersed, and an increase in noise is suppressed. However, in reality, the duty of each high-side transistor may be different.

[0039] FIG. 4 is a timing chart of the clock signals CLK 91 ,CLK 92 ,CLK 93 and the power supply voltage V DD in the case where the duty of the high-side transistor according to the related art is different. As shown in FIG. 4, when the duty of the high-side transistor is different, the falling edge timings (t 91 ,CLK 92 ,CLK 93 ) of the clock signals CLK 93 coincide, and large noise may be generated in the power supply voltage V DD .

[0040] (First Embodiment) FIG. 5 is a block diagram of the power management circuit 1 according to the first embodiment. The power management circuit 1 according to the present embodiment includes an internal power supply 10, a first DC / DC converter 12_1, a second DC / DC converter 12_2, a third DC / DC converter 12_3, and a controller 14. The power management circuit 1 may be integrally integrated on one semiconductor chip.

[0041] The first DC / DC converter 12_1, the second DC / DC converter 12_2, and the third DC / DC converter 12_3 may be, for example, a boost type, a buck type, and a buck-boost type. In this embodiment, an example in which the first DC / DC converter 12_1, the second DC / DC converter 12_2, and the third DC / DC converter 12_3 are all buck types will be described.

[0042] The first DC / DC converter 12_1, the second DC / DC converter 12_2, and the third DC / DC converter 12_3 each have high-side and low-side switching elements. These switching elements may be composed of, for example, MOS (Metal Oxide Semiconductor) transistors. In this embodiment, an example is described in which the power management circuit 1 has three DC / DC converters, but the number of DC / DC converters may be two, four or more.

[0043] The internal power supply 10 supplies a power supply voltage V to each of the following: the first DC / DC converter 12_1, the second DC / DC converter 12_2, the third DC / DC converter 12_3, and the controller 14. DD The controller 14 supplies the first clock signal CLK. 11 , second clock signal CLK 12 and the third clock signal CLK 13 Generates.

[0044] First clock signal CLK 11 This is a signal for driving the first switching element of the first DC / DC converter 12_1. Also, the second clock signal CLK 12 This is a signal for driving the second switching element of the second DC / DC converter 12_2. Furthermore, the third clock signal CLK 13 This is a signal for driving the third switching element of the third DC / DC converter 12_3. These switching elements may be, for example, high-side transistors and low-side transistors.

[0045] The first DC / DC converter 12_1 receives the first clock signal CLK 11 The first switching element is driven accordingly, and the input voltage V IN Output voltage V corresponding to the corresponding value OUT11 The second DC / DC converter 12_2 generates the second clock signal CLK. 12 The second switching element is driven accordingly, and the input voltage V IN Output voltage V corresponding to the corresponding value OUT12 The third DC / DC converter 12_3 generates the third clock signal CLK. 13 In response, the third switching element is driven, and the input voltage V IN Output voltage V corresponding to the corresponding value OUT13 Generates.

[0046] Figure 6 shows an example configuration of the DC / DC converter 12 according to the first embodiment. The first DC / DC converter 12_1, the second DC / DC converter 12_2, and the third DC / DC converter 12_3 may each have the same configuration as the DC / DC converter 12 shown in Figure 6.

[0047] The DC / DC converter 12 receives an input voltage V IN Output voltage V corresponding to the corresponding value OUT It generates the output voltage V. OUT V OUT11 ~V OUT13 This may be the case. As shown in Figure 6, the DC / DC converter 12 includes a high-side transistor MH, a low-side transistor ML, and an inductor L. The high-side transistor MH and the low-side transistor ML may each be composed of an N-channel MOS transistor. One end of the inductor L is connected between the high-side transistor MH and the low-side transistor ML, and the other end of the inductor L is connected to one end of the output capacitor C. The high-side transistor MH and the low-side transistor ML are driven in accordance with the clock signal generated by the controller 14.

[0048] Figure 7 is a block diagram of the controller 14 according to the first embodiment. The controller 14 according to this embodiment includes an A / D converter 140, an input voltage register 142, an output voltage register 144, and a clock signal generator 150.

[0049] The A / D converter 140 receives the input voltage V IN Digital input voltage data D VIN Convert to input voltage data D VIN This is transmitted to the input voltage register 142. The input voltage register 142 receives the input voltage data D VIN It retains the retained input voltage data D. VIN This is referenced by the clock signal generator 150 as needed. The input voltage data D to the input voltage register 142 is also referenced. VIN The transmission may be carried out by external communication. The communication method may be any method, such as I2C (Inter-Integrated Circuit).

[0050] The output voltage register 144 contains output voltage data D which specifies the output voltage that the first DC / DC converter 12_1 should generate. VOUT11 Output voltage data D that specifies the output voltage that the second DC / DC converter 12_2 should generate. VOUT12 and output voltage data D which specifies the output voltage that the third DC / DC converter 12_3 should generate. VOUT13 It holds the output voltage data D. VOUT11 ~D VOUT13 This is referenced by the clock signal generator 150 as needed.

[0051] The clock signal generator 150 generates first to p clock signals, each having the same period T, for driving the switching elements of the first to p DC / DC converters (where p is an integer of 3 or more; in this embodiment, p is 3). In this embodiment, the clock signal generator 150 generates first clock signals CLK, each having the same period T. 11 , second clock signal CLK 12 and the third clock signal CLK13 The clock signal generator 150 generates a clock signal. The clock signal generator 150 may include a CPU (Central Processing Unit), RAM (Random Access Memory), and ROM (Read Only Memory) as needed.

[0052] Figure 8 is a block diagram of the clock signal generation device 150 according to the first embodiment. The clock signal generation device 150 according to this embodiment includes a processing unit 160 and a storage unit 170.

[0053] The storage unit 170 stores various types of information. The storage unit 170 may store, for example, data generated by processing by the processing unit 160 (for example, data related to duty cycles and delay amounts) and programs for the processing unit 160 to execute various processes.

[0054] The processing unit 160 performs various processes. In this embodiment, the processing unit 160 processes the input voltage data D VIN and output voltage data D VOUT1 Based on this, the first clock signal CLK 11 , second clock signal CLK 12 and the third clock signal CLK 13 Generates output voltage data D. VOUT1 This is the output voltage data D VOUT11 ~D VOUT13 This includes the processing performed by the processing unit 160, which may be executed by, for example, a CPU. The processing unit 160 according to this embodiment includes a duty cycle calculation unit 162, a delay amount determination unit 164, and a clock signal generation unit 166.

[0055] The duty cycle calculation unit 162 calculates the input voltage data D VIN and output voltage data D VOUT1 Based on this, the duty cycle of the switching element is calculated. For example, the duty cycle calculation unit 162 calculates D VOUT1 / D VINThe duty cycle is calculated by performing a division. Here, the duty cycle is the proportion of time during the period T of the clock signal when the switching element (e.g., a high-side transistor) is turned on.

[0056] The duty cycle calculation unit 162 calculates the input voltage data D VIN and output voltage data D VOUT1 Based on this, the first duty cycle D of the first switching element DUTY11 The duty cycle calculation unit 162 calculates the input voltage data D. VIN and output voltage data D VOUT12 Based on this, the second duty cycle D of the second switching element DUTY12 The duty cycle calculation unit 162 calculates the input voltage data D. VIN and output voltage data D VOUT13 Based on this, the third duty cycle D of the third switching element DUTY13 Calculate.

[0057] Duty D DUTY11 , 2nd Duty D DUTY12 and the 3rd duty D DUTY13 is, 0 <D DUTY11 <1, 0 <D DUTY12 <1, 0 <D DUTY13 The condition <1 is satisfied. The calculated first duty cycle D DUTY11 , 2nd Duty D DUTY12 and the 3rd duty D DUTY13 This may be transmitted to the delay amount determination unit 164 or stored in the storage unit 170.

[0058] The delay amount determination unit 164 can determine the delay amount for any pair of clock signals from the first to the p-th clock signals based on the duty cycle calculated by the duty cycle calculation unit 162. In this embodiment, the first to the p-th clock signals are arranged in descending order of duty cycle, with the duty cycle of the first switching element being the largest and the duty cycle of the p-th switching element being the smallest. In this embodiment, D DUTY11 >D DUTY12 >D DUTY13 Let it be so.

[0059] The delay amount determination unit 164 determines the delay amount for the rising edge of the r clock signal relative to the rising edge of the q clock signal, such that the rising edge of the q clock signal (where q is an integer from 1 to p) does not coincide with the falling edge of the r clock signal (where r is an integer from 2 to p that is greater than q), or that the falling edge of the q clock signal does not coincide with the rising or falling edge of the r clock signal.

[0060] Specifically, the delay amount determination unit 164 determines whether the first, second, or third overlap condition is met for the pair of the q-th clock signal and the r-th clock signal. Based on the determination result, the delay amount determination unit 164 determines the delay amount between the rising edge of the r-th clock signal and the rising edge of the q-th clock signal.

[0061] The first overlap condition is that the rising edge of the q-th clock signal coincides with the falling edge of the r-th clock signal. The second overlap condition is that the falling edge of the q-th clock signal coincides with the rising edge of the r-th clock signal. The third overlap condition is that the falling edge of the q-th clock signal coincides with the falling edge of the r-th clock signal.

[0062] The delay amount determination unit 164 may determine one of the first to third overlap conditions, two of the overlap conditions, or all three of the overlap conditions. For example, the delay amount determination unit 164 may determine the delay amount such that both the first and second overlap conditions are not satisfied. Alternatively, the delay amount determination unit 164 may determine the delay amount such that all of the first to third overlap conditions are not satisfied.

[0063] For example, the delay amount determination unit 164 determines whether the first overlap condition, the second overlap condition, or the third overlap condition is met when the rising edge of the second clock signal is delayed by a certain amount relative to the rising edge of the first clock signal. Based on the determination result, the delay amount determination unit 164 determines the first delay amount D of the rising edge of the second clock signal relative to the rising edge of the first clock signal. DLY11 You may decide that.

[0064] In this case, the first overlap condition is that the rising edge of the first clock signal coincides with the falling edge of the second clock signal. The second overlap condition is that the falling edge of the first clock signal coincides with the rising edge of the second clock signal. Furthermore, the third overlap condition is that the falling edge of the first clock signal coincides with the falling edge of the second clock signal.

[0065] For example, the delay amount determination unit 164 determines the first delay amount D such that both the first overlap condition and the second overlap condition are not met. DLY11 The delay amount determination unit 164 may determine the first delay amount D such that the first overlap condition, the second overlap condition, and the third overlap condition are all satisfied. DLY11 The delay amount determination unit 164 determines the second delay amount D of the rising edge of the third clock signal relative to the rising edge of the second clock signal. DLY12 You may decide that.

[0066] Furthermore, the delay amount determination unit 164 determines the first delay amount D such that the rising edge of the first clock signal does not overlap with the falling edge of the third clock signal, or the falling edge of the first clock signal does not overlap with the rising or falling edge of the third clock signal. DLY11 and the second delay amount D DLY12 You may decide that.

[0067] Here, the number of possible pairs of q and r is expressed by the following equation (1). p C2=(p-1)+(p-1)(p-2) / 2···(1) In equation (1), the first term on the right-hand side is the number of cases where q and r are adjacent (r=q+1), and the second term on the right-hand side is the number of cases where p and q are not adjacent (r≠q+1).

[0068] If the delay amount determination unit 164 determines whether the first to third overlap conditions are met for all the clock signal pairs represented by equation (1), the amount of determination processing required can become enormous as the number of p increases.

[0069] The delay amount determination unit 164 may determine the delay amount (the kth delay amount) for each pair of the kth clock signal (where k is an integer from 1 to p-1) and the (k+1) clock signal, based on the kth duty cycle and the (k+1) duty cycle. Specifically, the delay amount determination unit 164 may determine the kth delay amount such that the rising edge of the kth clock signal does not coincide with the falling edge of the (k+1) clock signal, or the falling edge of the kth clock signal does not coincide with the rising or falling edge of the (k+1) clock signal.

[0070] The delay amount determination unit 164 may determine the kth delay amount for each pair of the kth clock signal and the (k+1)th clock signal, starting with the pair of clock signals with the largest duty cycle, such that all of the first, second, and third overlap conditions are not met. Here, the first overlap condition is that the rising edge of the kth clock signal and the falling edge of the (k+1)th clock signal coincide. The second overlap condition is that the falling edge of the kth clock signal and the rising edge of the (k+1)th clock signal coincide. Furthermore, the third overlap condition is that the falling edge of the kth clock signal and the falling edge of the (k+1)th clock signal coincide.

[0071] Two adjacent clock signals are more likely to have their rising or falling edges overlap with the other's compared to two non-adjacent clock signals. Therefore, by determining the delay amount so that the falling edges (or rising and falling edges) of two adjacent clock signals do not overlap, it is possible to more efficiently suppress the overlap of the rising edges (or rising and falling edges) of the two clock signals.

[0072] For example, the delay amount determination unit 164 may determine the k-th delay amount for each of the (p-1) adjacent clock signal pairs, starting with the pairs with the largest duty cycles, such that all of the first, second, and third overlap conditions are not met. That is, the delay amount determination unit 164 may determine the delay amount for the pair of the (p-1) clock signal and the p-th clock signal, starting with the pair of the first clock signal and the second clock signal. Even by determining the delay amount for just (p-1) clock signal pairs in this way, the power supply voltage V can be effectively controlled. DD It is possible to reduce noise in this context.

[0073] The delay amount determination unit 164 according to this embodiment has a first duty cycle D DUTY1 and the second duty D DUTY2 Based on this, the first delay amount D of the rising edge of the second clock signal relative to the rising edge of the first clock signal is set such that the rising edge of the first clock signal does not coincide with the falling edge of the second clock signal, or the falling edge of the first clock signal does not coincide with the rising or falling edge of the second clock signal. DLY11 To decide.

[0074] Furthermore, the delay amount determination unit 164 determines the second duty cycle D DUTY2 and the 3rd duty D DUTY3Based on this, the second delay amount D of the rising edge of the third clock signal with respect to the rising edge of the second clock signal is determined such that the rising edge of the second clock signal does not overlap with the falling edge of the third clock signal, or the falling edge of the second clock signal does not overlap with the rising edge or the falling edge of the third clock signal. DLY12 Determine.

[0075] Here, the reference clock signal CLK REF is a clock signal having a period T that is 1 / m (m is an integer greater than or equal to 2) times the period T of each clock signal. The delay amount determination unit 164 according to the present embodiment, for any pair of clock signals, based on the reference clock signal CLK REF determines whether the first overlap condition, the second overlap condition, or the third overlap condition is satisfied for each of a plurality of different delay amounts Δ (0 < Δ < T) that are different by T in period. The delay amount determination unit 164 determines the delay amount of the rising edge of the r-th clock signal with respect to the rising edge of the q-th clock signal based on the determination result. The delay amount Δ can take a total of (m - 1) values of T / m, 2×T / m, ···, (m - 1)×T / m. The value of m can be appropriately set based on parameters such as duty. REF Based on REF each different by T

[0076] In the present embodiment, the delay amount determination unit 164 can set the length of the high period in one period T of each clock signal, the length of the low period in one period T of each clock signal, and the delay amount, respectively, in units of the period T REF of the reference clock signal CLK REF Hereinafter, the high period in one period T and the low period in one period T will be simply referred to as the high period and the low period, respectively.

[0077] The delay amount determination unit 164 may determine the delay amount such that the length of the high period of each clock signal is s times (s is an integer satisfying 0 < s < m) the period T REF of the reference clock signal CLK REF For example, the delay amount determination unit 164 sets the length of the high period of the clock signal to s×T REFYou can use the value closest to the value obtained by multiplying the duty cycle by the period T.

[0078] The delay amount determination unit 164 determines the initial value of the delay amount Δ Δ INIT Let T / m be the time interval, and let the delay amount Δ be T REF The delay amount determination unit 164 may determine whether the first to third overlap conditions are met for each pair of clock signals while gradually changing the value. If none of the first to third overlap conditions are met, the delay amount determination unit 164 sets the initial value Δ INIT This can be determined as the delay amount between the rising edge of the r clock signal and the rising edge of the q clock signal.

[0079] On the other hand, if any of the first to third overlap conditions are met, the delay amount determination unit 164 determines whether the first to third overlap conditions are met while changing the delay amount Δ by T / m. For example, the delay amount determination unit 164 may determine whether the first to third overlap conditions are met while increasing the delay amount Δ by T / m or decreasing the delay amount Δ by T / m. If the delay amount determination unit 164 finds a delay amount Δ in which all of the first to third overlap conditions are not met, it may use that delay amount Δ as the delay amount between the rising edge of the r clock signal and the rising edge of the q clock signal.

[0080] The delay amount determination unit 164 may determine the smallest delay amount Δ among the delay amounts Δ for which all of the first, second, and third overlap conditions are not satisfied as the delay amount between the rising edge of the r clock signal and the rising edge of the q clock signal. For example, the delay amount determination unit 164 may determine whether the first to third overlap conditions are satisfied for all possible values ​​of the delay amount Δ (T / m, 2×T / m, ...(m-1)×T / m), and select the smallest delay amount Δ among the delay amounts Δ for which all of the first to third overlap conditions are not satisfied.

[0081] The delay amount determination unit 164 determines the initial value of the delay amount Δ Δ INIT The integer part of m / (p-1) is T REF It can be taken as the value obtained by multiplying by Δ. For example, when m=50 and p=4, the initial value ΔINIT is 16×T REF This may be the case. In this case, the delay amount determination unit 164 may search for a delay amount Δ in which all of the first to third overlap conditions are not satisfied, by raising or lowering the delay amount Δ by, for example, T / m.

[0082] Thus, the initial value of the delay amount Δ is Δ INIT By using the integer part of m / (p-1), it becomes possible to evenly distribute the timing difference between the falling edges (or rising and falling edges) of each pair of clock signals within the period T. In other words, it is possible to suppress the occurrence of some pairs of clock signals having close timing differences between their falling edges (or rising and falling edges), and some pairs of clock signals having large timing differences between their falling edges (or rising and falling edges). By suppressing the occurrence of pairs of clock signals with close timing differences between their falling edges (or rising and falling edges), the power supply voltage V can be more reliably maintained. DD This makes it possible to reduce noise in the system.

[0083] Referring to Figure 9, the first, second, and third overlap conditions will be explained in more detail for the case where k=1 (q=1, r=2). Figure 9 shows the first clock signal CLK according to the first embodiment. 11 and the second clock signal CLK 12 An example timing chart is shown. The first clock signal CLK 11 and the second clock signal CLK 12 Each of them has the same period T.

[0084] First clock signal CLK 11 The high period is T×D DUTY11 The first clock signal CLK 11 The low period is T × (1-D DUTY1 ) is also the second clock signal CLK. 12 The high period is T×D DUTY2 The second clock signal CLK 12 The low period is T × (1-D DUTY12) is. The rising edge of the second clock signal CLK 12 is delayed by Δ (0 < Δ < T) with respect to the rising edge of the first clock signal CLK 11 .

[0085] The first overlap condition will be described. If the timing of the rising edge of the first clock signal CLK 11 is t1, the timing of the rising edge of the first clock signal CLK 11 is t1 + n1 × T (n1 is an integer). From the rising edge of the first clock signal CLK 11 to the rising edge of the second clock signal CLK 12 , if the delay amount is Δ, the timing of the falling edge of the second clock signal CLK 12 is t1 + (Δ + T × D DUTY12 ). Therefore, the first overlap condition is expressed by the following equation (2). t1 + n1 × T = t1 + (Δ + T × D DUTY12 ) + n2 × T n1 × T = (Δ + T × D DUTY12 ) + n2 × T (n1 - n2) × T = Δ + T × D DUTY12 ···(2)

[0086] Considering the range of the right side of equation (2) here, since 0 < Δ < T and 0 < T × D DUTY12 < T, then 0 < Δ + T × D DUTY12 < 2T. Therefore, when the right side of equation (2) is (n1 - n2) × T, it is only when the right side of equation (2) is T. In this case, n1 - n2 = 1 and Δ + T × D DUTY12 = T holds, and n1 = n2 + 1, Δ = T × (1 - D DUTY12 ). From the above, when Δ = T × (1 - D DUTY12 ), the first overlap condition is satisfied.

[0087] The second overlap condition will be described. The timing when the first clock signal CLK 11 falls is t1 + n1 × T + T × D DUTY11 . Also, the second clock signal CLK 12The rising timing is t1 + Δ + n2×T. Therefore, the second overlapping condition is expressed by the following equation (3). t1 + n1×T + T×D DUTY11 = t1 + Δ + n2×T n1×T + T×D DUTY11 = Δ + n2×T (n1 - n2)×T = Δ - T×D DUTY11 ···(3)

[0088] Here, considering the range of the right side of equation (3), 0 < Δ < T, and -T < -T×D DUTY11 <Since it is 0, -T < Δ - T×D DUTY11 <T. Therefore, when the right side of equation (3) is (m - n)×T, it is only when the right side of equation (3) is 0. In this case, n1 - n2 = 0, Δ - T×D DUTY11 = 0 holds, and n1 = n2, Δ = T×D DUTY11 Thus, from the above, Δ = T×D DUTY11 When, the second overlapping condition is satisfied.

[0089] The third overlapping condition will be described. The falling timing of the first clock signal CLK 11 is t1 + n1×T + T×D DUTY11 Let's set it. The falling timing of the second clock signal CLK 12 is t1 + (Δ + T×D DUTY12 ) + n2×T. Therefore, the third overlapping condition is expressed by the following equation (4). t1 + n1×T + T×D DUTY11 = t1 + (Δ + T×D DUTY12 ) + n2×T n1×T + T×D DUTY11 =(Δ + T×D DUTY12 ) + n2×T (n1 - n2)×T = Δ + T×(D DUTY12 - D DUTY11 )···(4)

[0090] Here, 0 < Δ < T, and also, D DUTY11 > D DUTY12 Therefore, -T < T×(D DUTY12 - D DUTY11) is less than 0. Considering the range of the right side of Equation (4), -T < Δ + T×(D DUTY12 -D DUTY11 ) < T. Therefore, when the right side of Equation (4) becomes (n1 - n2)×T, it is only when the right side of Equation (4) is 0. In this case, n1 - n2 = 0, Δ + T×(D DUTY12 -D DUTY11 ) = 0 holds, n1 = n2, and Δ = T×(D DUTY11 -D DUTY12 ). From the above, when Δ = T×(D DUTY11 -D DUTY12 ), the third overlapping condition is satisfied.

[0091] Note that here, it has been described assuming D DUTY11 > D DUTY12 , but the case of D DUTY11 < D DUTY12 is also considered. For the case of D DUTY11 < D DUTY12 , the condition that the falling edge of the first clock signal CLK 11 overlaps with the falling edge of the second clock signal CLK 12 is defined as the fourth overlapping condition. In this case, considering the range of the right side of Equation (4), 0 < T×(D DUTY12 -D DUTY11 ) < T, so 0 < Δ + T×(D DUTY12 -D DUTY11 ) < 2T. Therefore, when the right side of Equation (4) becomes (n1 - n2)×T, it is only when the right side of Equation (4) is T. In this case, n1 - n2 = 1, Δ + T×(D [[ID=ZZZ]] DUTY12 [[ID=YYY]] DUTY11 ) = T holds, n1 = n2 + 1, and Δ = T×(1 + D DUTY12 -D DUTY11 ) = T holds, n1 = n2 + 1, and Δ = T×(1 + D DUTY11 -D DUTY12 [[ID=ZZZ]] DUTY11 [[ID=YYY]] DUTY12 ). From the above, when Δ = T×(1 + D DUTY11 -D DUTY12 ), the fourth overlapping condition is satisfied.

[0092] Summarizing the above, the first to fourth overlapping conditions are represented by the following Equations (5) to (8), respectively. First overlapping condition: Δ = T×(1 - D DUTY12 ) ··· (5) Second overlapping condition: Δ = T×DDUTY11 ...(6) Third overlap condition: Δ = T × (D DUTY11 -D DUTY12 )(However, D DUTY11 >D DUTY12 )···(7) Fourth overlap condition: Δ = T × (1 + D) DUTY11 -D DUTY12 )(However, D DUTY11 <D DUTY12 )···(8)

[0093] The first to fourth overlap conditions for pairs of the k-th clock signal and the (k+1)-th clock signal are expressed by the following equations. First overlap condition: Δ = T × (1 - D) DUTY(k+1) ) Second overlap condition: Δ = T × D DUTYk Third overlap condition: Δ = T × (D DUTYk -D DUTY(k+1) )(However, D DUTYk >D DUTY(k+1) ) Fourth overlap condition: Δ = T × (1 + D) DUTYk -D DUTY(k+1) )(However, D DUTYk <D DUTY(k+1) ) Here, D DUTYk This is the duty cycle of the k-th clock signal, and D DUTY(k+1) This is the duty cycle of the (k+1)th clock signal.

[0094] Returning to Figure 8, the clock signal generation unit 166 will be described. The clock signal generation unit 166 in this embodiment generates a clock signal for driving the switching elements of the DC / DC converter. The clock signal generation unit 166 generates the first to p clock signals. For each pair of the k-th clock signal and the (k+1)-th clock signal, the clock signal generation unit 166 may generate the (k+1)-th clock signal whose rising edge is delayed relative to the k-th clock signal by the k-th delay amount determined by the delay amount determination unit 164.

[0095] The clock signal generation unit 166 according to this embodiment generates a first clock signal CLK 11 , second clock signal CLK 12 and the third clock signal CLK 13 For example, the clock signal generation unit 166 generates the first delay amount D determined by the delay amount determination unit 164. DLY11 For that amount, the first clock signal CLK 11 The second clock signal CLK has a delayed rise time. 12 The clock signal generation unit 166 generates the second delay amount D determined by the delay amount determination unit 164. DLY12 The second clock signal CLK 12 The third clock signal CLK has a delayed rise time. 13 Generates.

[0096] The high period of each clock signal is the length corresponding to the duty cycle calculated by the duty cycle calculation unit 162. For example, the first clock signal CLK 11 The high period is T×D DUTY11 This may be the case, and the second clock signal CLK 12 The high period is T×D DUTY12 This may be the case, and the third clock signal CLK 13 The high period is T×D DUTY13 That's fine.

[0097] Figure 10 shows the first clock signal CLK generated by the clock signal generation unit 166 according to the first embodiment. 11 , second clock signal CLK 12 and the third clock signal CLK 13 This is a timing chart illustrating an example. These clock signals may be used to switch the high-side transistors of the corresponding DC / DC converters.

[0098] In the example shown in Figure 10, the reference clock signal CLK REF Period T REF This is the first clock signal CLK 11 The period T is 1 / 8 times (m=8). The first clock signal CLK. 11 Length of the high period T × DDUTY11 is T REF It is 6 times that of the second clock signal CLK 12 Length of the high period T × D DUTY12 is T REF It is 5 times that of the third clock signal CLK 13 Length of the high period T × D DUTY13 is T REF It is twice as much as the first delay amount D. DLY11 is, T REF It is twice as much as the second delay amount D DLY12 is, T REF It is identical to [the other one].

[0099] Note: T×D DUTY11 , T×D DUTY12 Or T×D DUTY13 is T REF If the length of the high period is not an integer multiple of T, then the length of the high period is T REF The length of the high period may be adjusted as appropriate so that it is an integer multiple of T × D. For example, T × D DUTY11 The closest T REF The first clock signal CLK is an integer multiple of the first clock signal CLK 11 This can be considered a period of high.

[0100] As shown in Figure 10, the first clock signal CLK 11 The rising edge (timing t1), the second clock signal CLK 12 The rising edge (timing t2) and the third clock signal CLK 13 The timing t3 occurs at different times. That is, the first clock signal CLK 11 , second clock signal CLK 12 and the third clock signal CLK 13 The startups do not overlap.

[0101] First clock signal CLK 11 The falling edge (timing t5) corresponds to the second clock signal CLK. 12 It does not overlap with either the rising or falling edge (timing t6) of the signal. Furthermore, it does not overlap with the second clock signal CLK. 12 The falling edge corresponds to the third clock signal CLK. 13It does not overlap with either the rising or falling edge (timing t4) of the signal. Furthermore, it does not overlap with the first clock signal CLK. 11 The falling edge corresponds to the third clock signal CLK. 13 It does not overlap with either the rising or falling edge.

[0102] In this way, by ensuring that the rising and falling edges of the clock signal do not overlap with the rising and falling edges of other clock signals, the power supply voltage V can be reliably maintained. DD This can reduce noise in the signal. Note that some of the rising and falling edges of the three clock signals may overlap with the rising or falling edges of other clock signals. For example, the first clock signal CLK 11 The falling edge corresponds to the second clock signal CLK. 12 It is acceptable for this to overlap with the falling edge.

[0103] Figure 11 is a flowchart showing an example of the operation of the clock signal generation device 150 according to the first embodiment. The operation flow of the clock signal generation device 150 will be explained below in accordance with the flowchart shown in Figure 11.

[0104] First, the duty cycle calculation unit 162 calculates the input voltage data D VIN and output voltage data D VOUT1 Based on this, the duty cycle is calculated (S101). Here, the duty cycle calculation unit 162 calculates the first duty cycle D DUTY11 , 2nd Duty D DUTY12 and the 3rd duty D DUTY13 Calculate.

[0105] Next, the delay amount determination unit 164 determines the order of the pairs of clock signals whose delay amounts are determined (S103). Here, the delay amount determination unit 164 determines the delay amount for each of the two pairs: the first pair of the first clock signal and the second clock signal, and the second pair of the second clock signal and the third clock signal. The delay amount determination unit 164 determines the delay amounts for the first pair, then the second pair.

[0106] Next, the delay amount determination unit 164 selects a pair of clock signals for which the delay amount has not been determined, based on the order of the clock signals determined in S103 (S105). Then, the delay amount determination unit 164 performs a delay amount determination process on the pair of clock signals selected in S105 (S107). The specific processing flow of S107 will be described later with reference to Figure 12.

[0107] Next, the delay amount determination unit 164 determines whether or not the delay amount has been determined for all pairs of clock signals (S109). For example, if the delay amount has been determined for both the first pair and the second pair, the delay amount determination unit 164 may determine that the delay amount has been determined for all pairs of clock signals. Also, if the delay amount has not been determined for at least one of the first pair and the second pair, the delay amount determination unit 164 determines that the delay amount has not been determined for all pairs of clock signals. If it is determined that the delay amount has not been determined for all pairs of clock signals (S109: NO), the process returns to S105.

[0108] If it is determined in S109 that the delay amount has been determined for all pairs of clock signals (S109: YES), the clock signal generation unit 166 generates a clock signal based on the determined delay amount (S111). Here, the clock signal generation unit 166 generates the first clock signal CLK 11 , second clock signal CLK 12 and the third clock signal CLK 13 Generates.

[0109] Figure 12 is a flowchart showing an example of the delay amount determination process (S107) according to the first embodiment. The flow of the delay amount determination process will be explained below in accordance with the flowchart shown in Figure 12. Here, as an example, we will explain an example in which the delay amount of the first pair is determined.

[0110] First, the delay amount determination unit 164 determines whether the duty cycles of the two clock signals in the pair are different (S121). For example, the delay amount determination unit 164 determines whether the first duty cycle D DUTY11 2nd Duty D DUTY12 Determine whether the duty cycles are different or not. If the duty cycles are different (S121: YES), proceed to process S123. On the other hand, if the duty cycles are the same (S121: NO), proceed to process S135.

[0111] If it is determined in S121 that the duty cycle is different, the delay amount determination unit 164 determines the initial value of the delay amount Δ Δ INIT The delay amount determination unit 164 sets the reference clock signal CLK. REF 1 period T REF Initial value Δ INIT This may be done. Alternatively, the delay amount determination unit 164 may use the period T in the integer part of m / (p-1). REF It may be the value obtained by multiplying by Δ. For example, when m=8 and p=3, the delay amount determination unit 164 determines the initial value Δ INIT 4×T REF (=T / 2) is acceptable.

[0112] Next, the delay amount determination unit 164 determines whether or not the first overlap condition is not met (S125). For example, the delay amount determination unit 164 determines Δ = T × (1 - D DUTY12 The process determines whether the first overlap condition is not met (S125:YES). If it is determined that the first overlap condition is met (S125:NO), the process proceeds to S127.

[0113] If it is determined in S125 that the first overlap condition is not met, the delay amount determination unit 164 determines whether or not the second overlap condition is not met (S127). For example, the delay amount determination unit 164 determines Δ = T × D DUTY11 The process determines whether the second overlap condition is not met. If it is determined that the second overlap condition is not met (S127: YES), the process proceeds to S129. On the other hand, if it is determined that the second overlap condition is met (S127: NO), the process proceeds to S133.

[0114] If it is determined in S127 that the second overlap condition is not met, the delay amount determination unit 164 determines whether or not the third overlap condition is not met (S129). For example, the delay amount determination unit 164 determines Δ = T × (D DUTY11 -D DUTY12 The system determines whether the third overlap condition is not met (S129: YES). If it is determined that the third overlap condition is met (S129: NO), the system proceeds to process S131.

[0115] If it is determined in S129 that the third overlap condition is not met, the delay amount determination unit 164 determines the delay amount (S131). For example, the delay amount determination unit 164 may determine the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal to a set delay amount Δ.

[0116] If it is determined in S125 that the first overlap condition is met, if it is determined in S127 that the second overlap condition is met, or if it is determined in S129 that the third overlap condition is met, the delay amount determination unit 133 determines whether or not to end the search for the delay amount (S133). For example, if the set delay amount Δ has reached its maximum value T×(m-1) / m, the delay amount determination unit 133 may decide to end the search for the delay amount. Alternatively, if the set delay amount Δ has not reached T×(m-1) / m, the delay amount determination unit 133 may decide to continue the search for the delay amount.

[0117] If it is determined in S133 that the search for the delay amount is complete (S133:YES), the process proceeds to S135. On the other hand, if it is determined in S133 that the search for the delay amount will continue (S133:NO), the delay amount determination unit 164 updates the delay amount Δ (S137). The delay amount determination unit 164 may update the delay amount Δ by adding T / m and set the delay amount Δ. Once the delay amount Δ is updated, the process returns to S125.

[0118] If it is determined in S121 that the duty cycles are the same, or if it is determined in S133 that the search for the delay amount is complete, the delay amount determination unit 164 sets the delay amount to the initial value Δ INIT This is determined (S135). As a result, at least the first clock signal CLK 11 The rising edge and the second clock signal CLK 12 The start of the next phase will no longer overlap.

[0119] In S131, the delay amount is determined, or in S135, the delay amount is set to the initial value Δ INIT Once this is determined, the delay amount determination process ends.

[0120] The configuration and operation examples of the power management circuit 1 and its clock signal generation device 150 according to this embodiment have been described above. The clock signal generation device 150 according to this embodiment includes a delay amount determination unit 164 and a clock signal generation unit 166.

[0121] The clock signal generation unit 166 generates a first clock signal CLK for driving the first switching element of the first DC / DC converter 12_1. 11 And, a second clock signal CLK for driving the second switching element of the second DC / DC converter 12_2. 12 It generates the first clock signal CLK. 11 and the second clock signal CLK 12 Each of them has the same period T.

[0122] The delay amount determination unit 164 determines the first duty cycle D DUTY11 and the second duty D DUTY12 Based on this, the first delay amount D is set such that the rising edge of the first clock signal does not coincide with the falling edge of the second clock signal, or the falling edge of the first clock signal does not coincide with the rising or falling edge of the second clock signal. DLY1 The clock signal generation unit 166 determines the first delay amount D determined by the delay amount determination unit 164. DLY1 For that amount, the first clock signal CLK 11 The second clock signal CLK has a delayed rise time.12 Generates.

[0123] According to this embodiment, the first clock signal CLK 11 and the second clock signal CLK 12 This eliminates the overlap of rising edges and suppresses the overlap of the falling edge of one clock signal with the rising or falling edge of the other clock signal. As a result, the power supply voltage V DD This makes it possible to reduce noise in the system.

[0124] (Second Embodiment) Figure 13 is a block diagram of the clock signal generation device 250 according to the second embodiment. The clock signal generation device 250 according to the second embodiment differs from the clock signal generation device 150 according to the first embodiment mainly in the function of the delay amount determination unit 264. The clock signal generation device 250 according to the second embodiment includes a processing unit 180 and a storage unit 270.

[0125] The processing unit 180 according to the second embodiment generates a clock signal CLK2 for driving the switching elements of each of the first to pDC / DC converters. In this embodiment, p is an integer of 4 or more. The clock signal CLK2 is the first clock signal CLK 21 ~p clock signal CLK 2p Includes the first clock signal CLK. 21 ~p clock signal CLK 2p Each of them has the same period T.

[0126] The duty cycle calculation unit 262 calculates the input voltage data D VIN and output voltage data D VOUT2 Based on, Duty D DUTY2 Calculate the output voltage data D. VOUT2 This is the output voltage data D of the first to second pDC / DC converters. VOUT21 ~D VOUT2p This includes the duty cycle D calculated by the duty calculation unit 262. DUTY2 This is the first duty D DUTY21 ~Prior Duty D DUTY2pIncludes.

[0127] The delay amount determination unit 264 determines the duty cycle D DUTY2 Based on this, delay amount D DLY_X ,D DLY_Y The delay amount determination unit 264 includes a first delay amount determination unit 268 and a second delay amount determination unit 269. The first clock signal CLK 21 ~p clock signal CLK 2p This can be divided into the 1st to xth clock signals (where x is an integer greater than or equal to 2 and less than p-1) and the (x+1)th to pth clock signals. In this embodiment, we will describe an example where p=10, x=5, and y=5.

[0128] The first delay amount determination unit 268 determines the delay amount for the first to xth clock signals. x (k x k is an integer between 1 and x-1. x Duty and (k x +1) After the switching element (k x +1) Based on the duty cycle, the k x The rising edge of the clock signal is the (k x +1) So that it does not overlap with the falling edge of the clock signal, or the kth x The falling edge of the clock signal is the (k x +1) The kth such that it does not overlap with the rising or falling edge of the clock signal. x The (k)th rising edge of the clock signal x +1) Delay amount of the rising edge of the clock signal (kth x Determine the amount of delay.

[0129] The first delay amount determination unit 268 determines the first delay amount D in the same manner as the delay amount determination unit 164 in the first embodiment. DLY21 ~xth delay amount D DLY2x The first delay amount D may be determined. DLY21 ~xth delay amount D DLY2x Delay amount D including DLY_X This signal is transmitted to the clock signal generation unit 266.

[0130] The second delay amount determination unit 169 determines the delay amount for the (x+1) to p clock signals. Based on the first duty cycle of the first switching element and the (x+1) duty cycle of the (x+1) switching element, the second delay amount determination unit 169 determines the delay amount for the rising edge of the (x+1) clock signal relative to the rising edge of the first clock signal, such that the falling edge of the (x+1) clock signal is delayed by 1 period T from the rising edge of the first clock signal.

[0131] The second delay amount determination unit 169 determines the k y (k y (where x is an integer between x+1 and p-1.) The kth of the switching element y Duty and (k y +1) After the switching element (k y +1) Based on the duty cycle, the k y The falling edge of the clock signal is the (k y +1) So that it does not overlap with the rising edge of the clock signal, or the kth y The rising edge of the clock signal is (k y +1) The (k) y +1) kth relative to the falling edge of the clock signal y Determine the amount of delay in the falling edge of the clock signal.

[0132] The second delay amount determination unit 169 in this embodiment determines the sixth clock signal CLK 26 The falling edge of the first clock signal CLK 21 The first clock signal CLK is delayed by one cycle T from its rising edge. 21 The sixth clock signal CLK for the rising edge 26 The rise time delay D DLY2X To decide.

[0133] The second delay amount determination unit 169 determines the sixth clock signal CLK 26 The falling edge is the 7th clock signal CLK 27 To avoid overlapping with the rising edge, or with the sixth clock signal CLK 26The rising edge is the 7th clock signal CLK 27 The seventh clock signal CL is designed so as not to overlap with the rising or falling edge of the signal. 27 The sixth clock signal CLK for the falling edge of the signal. 26 The falling edge delay amount D DLY26 To decide.

[0134] The second delay amount determination unit 169 similarly determines the eighth clock signal CLK 28 The seventh clock signal CLK for the falling edge 27 Delay amount D DLY27 , 9th clock signal CLK 29 The eighth clock signal CLK for the falling edge 28 Delay amount D DLY28 , and the 10th clock signal CLK 210 The 9th clock signal CLK for the falling edge 29 Delay amount D DLY29 The determined delay amount D can be determined. DLY2X and delay amount D DLY26 ~D DLY29 Delay amount D including DLY_Y This signal is transmitted to the clock signal generation unit 266.

[0135] The clock signal generation unit 266 determines the delay amount D determined by the first delay amount determination unit 268. DLY_X and the delay amount D determined by the second delay amount determination unit 269 DLY_Y Based on this, the clock signal CLK2 is generated.

[0136] Figure 14 shows the first clock signal CLK according to the second embodiment. 21 , the sixth clock signal CLK 26 and the seventh clock signal CLK 27 This is a timing chart illustrating one example.

[0137] As shown in Figure 14, the sixth clock signal CLK 26 rising time (timing t) 13 ) is the first clock signal CLK 21 rising time (timing t) 11 ) with respect to delay amount DDLY2X This results in a delay of that amount. As a result, the 6th clock signal CLK 26 Falling edge (timing t) 15 ) is the first clock signal CLK 21 The rise time is delayed by 1 period T.

[0138] 6th clock signal CLK 26 The falling edge is the falling edge of the 7th clock signal (timing t 14 ) with respect to delay amount D DLY26 This results in a delay of that amount. As a result, the 6th clock signal CLK 26 The falling edge corresponds to the 7th clock signal CLK. 27 rising time (timing t) 16 It does not overlap with the sixth clock signal CLK. 26 The rising edge is the 7th clock signal CLK 27 rising time (timing t) 12 ) and does not overlap with either the falling edge.

[0139] According to the delay amount determination unit 264 of this embodiment, the first delay amount determination unit 268 determines the delay amount so as to delay each clock signal sequentially from the beginning of one period T. In contrast, the second delay amount determination unit 269 determines the delay amount so as to advance each clock signal sequentially from the end of one period T. This makes it possible to generate the rising and falling edges of each clock signal more evenly throughout one period T, and to more reliably maintain the power supply voltage V DD This makes it possible to reduce the amount of noise in the system.

[0140] (Third embodiment) Figure 15 is a block diagram of the clock signal generation device 350 according to the third embodiment. In the third embodiment, the clock signal generation device 350 generates a first clock signal CLK to drive the switching elements of three DC / DC converters (first DC / DC converter, second DC / DC converter, and third DC / DC converter). 31 , second clock signal CLK 32 and the third clock signal CLK 33The clock signal generation device 350 according to the third embodiment includes a duty cycle calculation unit 360, a first clock signal generation block 370, and a second clock signal generation block 380.

[0141] The duty cycle calculation unit 360 calculates the input voltage data D IN and output voltage data D OUT3 Based on, the first duty D DUTY31 , 2nd Duty D DUTY32 and the 3rd duty D DUTY33 Calculate the output voltage data D. OUT3 This includes the output voltage data for each of the three DC / DC converters. Here, D DUTY31 >D DUTY32 >D DUTY33 Let it be so.

[0142] Duty D DUTY31 and the second duty D DUTY32 This is transmitted to the first clock signal generation block 370, and the second duty cycle D DUTY32 and the 3rd duty D DUTY33 This signal is transmitted to the second clock signal generation block 380.

[0143] The first clock signal generation block 370 has a first duty cycle D DUTY31 and the second duty D DUTY32 Based on this, the first clock signal CLK 31 and the second clock signal CLK 32 The second clock signal generation block 380 generates the second duty cycle D DUTY32 and the 3rd duty D DUTY33 Based on this, the third clock signal CLK 33 Generates.

[0144] Figure 16 is a block diagram of the first clock signal generation block 370 according to the third embodiment. The first clock signal generation block 370 includes a first overlap condition determination unit 371, a second overlap condition determination unit 372, a third overlap condition determination unit 373, a subtraction unit 374, a first delay amount determination unit 376, and a first clock signal generation unit 378.

[0145] The first overlap condition determination unit 371 determines whether the first overlap condition is satisfied for the first clock signal and the second clock signal based on the second duty D DUTY32 . Specifically, the first overlap condition determination unit 371 determines whether the first overlap condition is satisfied by using the expression (5) with D DUTY12 replaced by D DUTY32 . The first determination result D DET1 is transmitted to the first delay amount determination unit 376.

[0146] In this embodiment, the period T REF of the reference clock signal CLK REF is set to be 1 / 8 (m = 8) of the periods T of the first to third clock signals. The first overlap condition determination unit 371 sets s as an integer satisfying 0 < s < m, sets Δ = T × s / m, and determines whether the first overlap condition is satisfied for all s. That is, the first overlap condition determination unit 371 determines whether the first overlap condition is satisfied for all Δ of Δ = T × 1 / 8, T × 2 / < / 8, ···, T × 7 / 8.

[0147] The second overlap condition determination unit 372 determines whether the second overlap condition is satisfied for the first clock signal and the second clock signal based on the first duty D DUTY31 . Specifically, the second overlap condition determination unit 372 determines whether the second overlap condition is satisfied by using the expression (6) with D DUTY11 replaced by D DUTY31 . Similar to the first overlap condition determination unit 371, the second overlap condition determination unit 372 determines whether the second overlap condition is satisfied for all s. The second determination result D DET2 is transmitted to the first delay amount determination unit 376.

[0148] The subtraction unit 374 calculates a value obtained by subtracting the second duty D DUTY31 from the first duty D DUTY32 . The calculation result D DIF1 (= D DUTY31 - D DUTY32This information is transmitted to the third overlap condition determination unit 373.

[0149] The third overlap condition determination unit 373 determines the calculation result D of the subtraction unit 374. DIF1 Based on this, it is determined whether the third overlap condition is met with respect to the first clock signal and the second clock signal. Specifically, the third overlap condition determination unit 373 determines whether (D DUTY11 -D DUTY12 ) to (D DUTY31 -D DUTY32 Using equation (7) with the substitution ), it is determined whether the third overlap condition is met. The third overlap condition determination unit 373 determines whether the third overlap condition is met for all s, similar to the first overlap condition determination unit 371. Third determination result D DET3 This is transmitted to the first delay amount determination unit 376.

[0150] The first delay amount determination unit 376 determines the first determination result D DET1 , second judgment result D DET2 and the third judgment result D DET3 Based on this, the first delay amount D of the rising edge of the second clock signal relative to the rising edge of the first clock signal. DLY31 To decide.

[0151] The first delay amount determination unit 376 in this embodiment determines the first delay amount D such that all of the first overlap condition, second overlap condition, and third overlap condition are not met. DLY31 The first delay amount determination unit 376 determines the first delay amount D if there is no delay amount that does not satisfy all of the first overlap conditions, second overlap conditions and third overlap conditions. DLY31 The reference clock signal CLK REF 1 period T REF It can be considered a portion.

[0152] The first clock signal generation unit 378 determines the first delay amount D determined by the first delay amount determination unit 376. DLY31 Based on this, the first clock signal CLK 31 and the second clock signal CLK 32Specifically, the first clock signal generation unit 378 generates the first delay amount D DLY31 For that amount, the first clock signal CLK 31 The second clock signal CLK has a delayed rise time in comparison. 32 The first clock signal generation unit 378 generates the first clock signal CLK. 31 The high period of T×D DUTY31 The second clock signal CLK 32 The high period of T×D DUTY32 Let's assume that.

[0153] Figure 17 is a block diagram showing an example configuration of the overlap condition determination unit 400 according to the third embodiment. The first overlap condition determination unit 371, the second overlap condition determination unit 372, and the third overlap condition determination unit 373 may be configured in the same way as the overlap condition determination unit 400. The overlap condition determination unit 400 uses a value D related to duty cycle. DUTY3 Based on this, the judgment result is D DET Generates.

[0154] D DUTY3 In the case of the first overlap condition determination unit 371, the second duty cycle D DUTY32 In the case of the second overlap condition determination unit 372, the first duty cycle D DUTY31 Therefore, in the case of the third overlap condition determination unit 372, the calculation result D DIF1 That is the case. Also, the judgment result is D DET In the case of the first overlap condition determination unit 371, the first determination result D DET1 In the case of the second overlap condition determination unit 372, the second determination result D DET2 In the case of the third overlap condition determination unit 372, the third determination result D DET3 That is the case.

[0155] The overlap condition determination unit 400 includes the first comparison circuit 401 to the seventh comparison circuit 407. Each of the first comparison circuit 401 to the seventh comparison circuit 407 calculates the first input value by m × D DUTY3 The second input value is compared with values ​​1 to 7, and the signal S is generated based on the comparison result. COMP1 ~S COMP7 Generates signal S. COMP1 ~S COMP7In the corresponding comparator circuit, this signal becomes low when the first input value and the second input value match, and high when the first input value and the second input value do not match. COMP1 ~S COMP7 Judgment result D including DET This is transmitted to the first delay amount determination unit 376.

[0156] Here, signal S COMP1 ~S COMP7 In the case of the first overlap condition determination unit 371, signal S COMP11 ~S COMP17 Therefore, in the case of the second overlap condition determination unit 372, signal S COMP21 ~S COMP27 Therefore, in the case of the third overlap condition determination unit 372, signal S COMP31 ~S COMP37 That is the case.

[0157] Figure 18 is a block diagram showing an example configuration of the first delay amount determination unit 376 according to the third embodiment. The first delay amount determination unit 376 includes first AND circuits 421 to seventh AND circuits 427, each with 3 inputs, a selection circuit 430, a seven-input AND circuit 432, and a two-input multiplexer 434.

[0158] The first AND gate 421 to the seventh AND gate 427 each handle the signal S COMP11 ~S COMP7 The first input signal, signal S COMP21 ~S COMP27 The second input signal, signal S COMP31 ~S COMP37 This is the third input signal. The first AND gates 421 to 427 each, when all input signals (first input signal, second input signal, and third input signal) are high, will output a high signal S. AND1 ~Signal S AND7 It generates a signal S, and if it is anything else, a low signal S AND1 ~Signal S AND7 Generates.

[0159] The selection circuit 430 receives the signal S AND1 ~S AND7 Based on the signal S SELIt generates the signal S. Specifically, the selection circuit 430 generates the signal S. AND1 ~S AND7 Assign numerical values ​​1 to 7 to each of them in order, and signal S AND1 ~S AND7 A signal that indicates the numerical value corresponding to the high signal among them. SEL This generates the signal S. AND1 ~S AND7 If multiple of these signals are high, the selection circuit 430 selects the signal S that represents the smallest number among the numbers associated with those signals. SEL The following may be generated. The selection circuit 430 may, for example, generate the signal S AND2 and signal S AND4 If it is high, then signal S AND2 Signal S, which corresponds to 2. SEL The following may be generated. Also, the selection circuit 430 generates the signal S AND1 ~S AND7 If there is no high signal in the set, then the signal S indicates 1. SEL You may generate this.

[0160] The AND gate 432 uses seven signals S AND1 ~Signal S AND7 If all of the values ​​are 0, then the signal S is high. AND It generates a signal S that is low otherwise. AND Generates.

[0161] The multiplexer 434 receives the signal S generated by the selection circuit 430. SEL Let be the first input signal and 1 be the second input signal. Select either input signal and set a first delay amount D according to the selected signal. DLY31 This generates the first delay amount D. DLY31 The value indicated by the selected signal is set to the reference clock signal CLK. REF Period T REF It is the value obtained by multiplying by .

[0162] The signal selected by the multiplexer 434 is the signal S generated by the AND gate 432. AND Determined by the signal S. Multiplexer 434 is determined by the signal S. AND If it is low, the signal S generated by the selection circuit 430SEL Select signal S AND If the signal is high, select the signal that indicates 1.

[0163] Figure 19 is a block diagram showing an example configuration of the first clock signal generation unit 378 according to the third embodiment. The first clock signal generation unit 378 according to this embodiment includes a cyclic counter 440, an adder circuit 442, a first rising edge trigger circuit 451, a first falling edge trigger circuit 452, a second rising edge trigger circuit 453, a second falling edge trigger circuit 454, and a first clock signal CLK 31 The first JK flip-flop 471 generates the signal, and the second clock signal CLK is generated. 32 Includes a second JK flip-flop 472 that generates [something].

[0164] The cyclic counter 440 receives a signal S indicating the counter value. CNT The cyclic counter 440 according to this embodiment generates the reference clock signal CLK. REF Based on this, 1 period T REF Each time, the counter value is incremented by one, starting from 0. When the counter value reaches 7 (=m-1), it is reset to 0.

[0165] The adder circuit 442 controls the first delay amount D DLY31 and the second duty D DUTY32 Based on this, the signal S indicates the summation value. SUM1 This generates the following: Here, the added value is D DLY31 / T REF +m×D DUTY32 It is represented as follows.

[0166] The first rising edge trigger circuit 451 generates the first rising edge signal S when the counter value is 0. RISE1 When this is set to high and the counter value is different from 0, the first rising edge signal S RISE1 Set this to low. First rising edge signal S RISE1 This is input to the J terminal of the first JK flip-flop 471.

[0167] The first rising edge trigger circuit 451 receives the comparison signal S COMP41The system includes a comparator circuit 461 and a NOT gate 465 that generate the comparison signal S when the counter value is 0. COMP41 When the value is low and the counter value is different from 0, the comparison signal S COMP41 The NOT circuit 465 is set to high. COMP41 Inverting this signal gives the first rising edge signal S RISE1 Generates.

[0168] The first falling-edge trigger circuit 452 is activated when the counter value is m × D DUTY31 When this is the case, the first falling edge signal S FALL1 Set to high, and the counter value is m × D DUTY31 When it is different, the first falling edge signal S FALL1 Set this to low. First falling edge signal S FALL1 This is input to the K terminal of the first JK flip-flop 471.

[0169] The first falling-edge trigger circuit 452 receives the comparison signal S. COMP42 The system includes a comparator circuit 462 and a NOT gate 466 that generate a counter value of m × D. DUTY31 When this is the case, the comparison signal S COMP42 Set this to low, and the counter value is m × D DUTY31 When it is different, the comparison signal S COMP42 The NOT circuit 466 is set to high when the comparison signal S COMP42 Inverting this signal gives the first falling edge signal S FALL1 Generates.

[0170] The second rising edge trigger circuit 453 is activated when the counter value is D DLY31 / T REF In this case, the second rising edge signal S RISE2 Set to High, and the counter value is D DLY31 / T REF When it is different, the second rising edge signal S RISE2 Set this to low. Second rising edge signal S RISE2 This is input to the J terminal of the second JK flip-flop 472.

[0171] The second rising edge trigger circuit 453 receives the comparison signal SCOMP43 The system includes a comparator circuit 463 and a NOT gate 467 that generate a counter value D DLY31 / T REF When this is the case, the comparison signal S COMP43 Set to low, and the counter value is D DLY1 / T REF When it is different, the comparison signal S COMP43 The NOT circuit 467 is set to high. COMP43 Inverting this creates the second rising edge signal S RISE2 Generates.

[0172] The second falling-edge trigger circuit 454 is activated when the counter value is (D DLY31 / T REF +m×D DUTY32 When ), the second falling edge signal S FALL2 Set to high, and the counter value is (D DLY31 / T REF +m×D DUTY32 When it is different from ), the second falling edge signal S FALL2 Set this to low. Second falling edge signal S FALL2 This is input to the K terminal of the second JK flip-flop 472.

[0173] The second falling-edge trigger circuit 454 receives the comparison signal S. COMP44 The system includes comparator circuit 464 and NOT gate 468 that generate a counter value (D DLY31 / T REF +m×D DUTY32 When the comparison signal S is COMP44 Set to low, and the counter value is (D DLY1 / T REF +m×D DUTY2 When it is different from ), the comparison signal S COMP44 Set to high. NOT circuit 468 receives comparison signal S COMP44 Inverting this creates the second falling edge signal S FALL2 Generates.

[0174] The first JK flip-flop 471 receives the reference clock signal CLK input to the clock signal terminal. REF The first clock signal CLK 31The second JK flip-flop 472 receives the reference clock signal CLK input to the clock signal terminal. REF The second clock signal CLK 32 Generates.

[0175] Figure 20 is a block diagram of the second clock signal generation block 380 according to the third embodiment. The second clock signal generation block 380 includes a first overlap condition determination unit 381, a second overlap condition determination unit 382, ​​a third overlap condition determination unit 383, a subtraction unit 384, a second delay amount determination unit 386, and a second clock signal generation unit 388.

[0176] The first overlap condition determination unit 381 of the second clock signal generation block 380 determines if the duty cycle used is the second duty cycle D DUTY32 From the 3rd Duty D DUTY33 Aside from being replaced by the first overlap condition determination unit 371 of the first clock signal generation block 370, it functions similarly. Fourth determination result D DET4 This is transmitted to the second delay amount determination unit 386.

[0177] The second overlap condition determination unit 382 of the second clock signal generation block 380 determines if the duty cycle used is the first duty cycle D DUTY31 From the 3rd Duty D DUTY32 Aside from being replaced by the second overlap condition determination unit 372 of the first clock signal generation block 370, it functions similarly. Fifth determination result D DET5 This is transmitted to the second delay amount determination unit 386.

[0178] The subtraction unit 374 is the second duty cycle D DUTY32 From the 3rd Duty D DUTY33 Write the value after subtracting [the specified value]. Calculation result D DIF2 (=D DUTY32 -D DUTY33 The result is transmitted to the third overlap condition determination unit 383. The third overlap condition determination unit 383 of the second clock signal generation block 380 determines the calculation result to be used. DIF1 From D DIF2Aside from the replacement, it functions similarly to the third overlap condition determination unit 373 of the first clock signal generation block. Sixth determination result D DET6 This is transmitted to the second delay amount determination unit 386.

[0179] The second delay amount determination unit 386 determines the fourth determination result D DET4 , 5th judgment result D DET5 and the 6th judgment result D DET6 Based on this, the second delay amount D of the rising edge of the third clock signal relative to the rising edge of the second clock signal. DLY32 The second delay amount determination unit 386 may be configured in the same way as the first delay amount determination unit 376. The determined second delay amount D DLY32 This signal is transmitted to the second clock signal generation unit 388.

[0180] The second clock signal generation unit 388 determines the first delay amount D determined by the first delay amount determination unit 376. DLY31 The second delay amount D determined by the second delay amount determination unit 386 DLY32 , signal S indicating the counter value CNT , reference clock signal CLK REF and the 3rd duty D DUTY33 Based on this, the third clock signal CLK 33 Generates.

[0181] Figure 21 is a block diagram showing an example configuration of the second clock signal generation unit 388 according to the third embodiment. The second clock signal generation unit 388 includes a first adder circuit 480, a second adder circuit 482, and a third rising edge signal S RISE3 A third rising edge trigger circuit 491 generates a third falling edge signal S. FALL3 Includes a third falling-fall trigger circuit 492 and a third JK flip-flop 510 that generate [the specified frequency].

[0182] The first adder circuit 480 controls the first delay amount D DLY31 and the second delay amount D DLY32 Adding the two, the added delay amount D SUM2 (=D DLY31 +D DLY32 The second adder circuit 482 calculates the added delay amount D.SUM2 and the 3rd duty D DUTY33 Based on this, the added value D SUM3 Calculate the sum D. SUM3 D SUM3 =D SUM2 +T×D DUTY33 That is the case.

[0183] The third rising edge trigger circuit 491 is activated when the counter value is D SUM2 / T REF In this case, the third rising edge signal S RISE3 Set to High, and the counter value is D SUM2 / T REF When it is different, the third rising edge signal S RISE3 Set this to low. Third rising edge signal S RISE3 This is input to the J terminal of the 3rd JK flip-flop 510.

[0184] The third rising edge trigger circuit 491 receives the comparison signal S COMP51 The system includes a comparator circuit 501 and a NOT gate 503 that generate a counter value D SUM2 / T REF When this is the case, the comparison signal S COMP51 Set to low, and the counter value is D SUM2 / T REF When it is different, the comparison signal S COMP51 The NOT circuit 503 is set to high when the comparison signal S COMP51 Inverting this creates the third rising edge signal S RISE3 Generates.

[0185] The third falling-edge trigger circuit 492 is activated when the counter value is D SUM2 / T REF In this case, the third falling-edge signal S FALL3 Set to High, and the counter value is D SUM2 / T REF When it is different, the third falling edge signal S FALL3 Set this to low. Third falling edge signal S FALL3 This is input to the K terminal of the third JK flip-flop 510.

[0186] The third falling-edge trigger circuit 492 receives the comparison signal S. COMP52 The system includes a comparator circuit 502 and a NOT gate 504 that generate a counter value D SUM2 / T REF When this is the case, the comparison signal S COMP52 Set to low, and the counter value is D SUM2 / T REF When it is different, the comparison signal S COMP52 The NOT circuit 504 is set to high when the comparison signal S COMP52 Inverting this creates the third falling edge signal S FALL3 Generates.

[0187] Figure 22 is a timing chart showing an example of various signals in the clock signal generation device 350 according to the third embodiment. In the example shown in Figure 22, T×D DUTY31 The reference clock signal CLK REF This is equivalent to 6 cycles, and T×D DUTY32 The reference clock signal CLK REF This is equivalent to 5 cycles. Figure 22 shows D A mD DUTY2 That is the case.

[0188] First clock signal CLK 31 The second clock signal CLK corresponds to the rising edge of the signal. 32 The rise time delay (first delay D) DLY31 ) is the reference clock signal CLK REF This corresponds to two cycles. As a result, as shown in Figure 22, the first clock signal CLK 31 The rising edge is the second clock signal CLK 32 It does not coincide with the falling edge of the first clock signal CLK. 31 The falling edge corresponds to the second clock signal CLK. 32 It does not overlap with either the falling or rising edge of the signal.

[0189] (First variation) In the first embodiment described above, if there is no delay amount that does not satisfy all of the first to third overlapping conditions, the delay amount is set to the initial value Δ INITAn example of determining the delay amount (S135) has been explained. However, if there is a delay amount Δ in which some of the overlap conditions among the first to third overlap conditions are not met, the delay amount Δ may be determined to be the delay amount Δ for the rising edge of one clock signal relative to the rising edge of another clock signal. For example, if there is a delay amount Δ in which the first and second overlap conditions are not met, but the third overlap condition is met, the delay amount Δ may be determined to be the delay amount Δ for the rising edge of the second clock signal relative to the rising edge of the first clock signal.

[0190] (Second variation) In the third embodiment described above, an example was described in which the first clock signal generation block 370 and the second clock signal generation block 380 each include a first to third overlap condition determination unit. However, the invention is not limited to this example, and the first clock signal generation block 370 and the second clock signal generation block 380 do not necessarily have to include a part of the first to third overlap condition determination unit.

[0191] For example, the first clock signal generation block 370 and the second clock signal generation block 380 do not need to include a third overlap condition determination unit. In this case, the first clock signal CLK 31 The falling edge and the second clock signal CLK 32 The falling edge may coincide with this. However, in this case, the first clock signal CLK may occur. 31 The rising edge is the second clock signal CLK 32 It does not coincide with the falling edge of the first clock signal CLK. 31 The falling edge corresponds to the second clock signal CLK. 32 This makes it possible to avoid overlapping with the falling edge of the signal. Furthermore, it allows for the second clock signal CLK to be avoided. 32 The rising edge is the third clock signal CLK 33 It does not coincide with the falling edge of the second clock signal CLK. 32 The falling edge corresponds to the third clock signal CLK. 33 This makes it possible to avoid overlapping with the falling edge.

[0192] (supplement) While the embodiments described herein have been explained using specific terminology, this explanation is merely illustrative to aid understanding and does not limit the scope of this disclosure or the claims. The scope of the present invention is defined by the claims. Furthermore, not only embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention. It is also possible to combine one or more elements of one embodiment with one or more elements of another embodiment.

[0193] (Note) The technology disclosed herein can be understood in one respect as follows:

[0194] (Item 1) A clock signal generation unit that generates a first clock signal for driving a first switching element in a first DC / DC converter and a second clock signal for driving a second switching element in a second DC / DC converter, The system includes a delay amount determination unit that determines the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal, based on the first duty cycle of the first switching element and the second duty cycle of the second switching element, such that the rising edge of the first clock signal does not overlap with the falling edge of the second clock signal, or the falling edge of the first clock signal does not overlap with the rising or falling edge of the second clock signal. The first clock signal and the second clock signal each have the same period, The clock signal generation unit generates a second clock signal whose rising edge is delayed relative to the first clock signal by the amount of delay determined by the delay amount determination unit. Power management circuit.

[0195] (Item 2) The system further includes a duty cycle calculation unit that calculates a first duty cycle of the first switching element based on the input voltage data and output voltage data of the first DC / DC converter, and calculates a second duty cycle of the first switching element based on the input voltage data and output voltage data of the second DC / DC converter. The delay amount determination unit determines the delay amount based on the first duty cycle and the second duty cycle calculated by the duty cycle calculation unit, respectively. The power management circuit described in item 1.

[0196] (Item 3) The delay amount determination unit determines whether the first, second, or third overlap condition is met when the rising edge of the second clock signal is delayed relative to the rising edge of the first clock signal, and determines the amount of delay of the rising edge of the second clock signal relative to the rising edge of the first clock signal based on the determination result. The first overlap condition is that the rising edge of the first clock signal and the falling edge of the second clock signal coincide. The second overlap condition is that the falling edge of the first clock signal and the rising edge of the second clock signal coincide. The third overlapping condition is that the falling edge of the first clock signal and the falling edge of the second clock signal coincide. The power management circuit described in item 1 or 2.

[0197] (Item 4) The delay amount determination unit determines the delay amount such that both the first overlap condition and the second overlap condition are not satisfied. The power management circuit described in item 3.

[0198] (Item 5) The delay amount determination unit determines the delay amount such that the first overlap condition, the second overlap condition, and the third overlap condition are all satisfied. The power management circuit described in item 4.

[0199] (Item 6) The delay amount determination unit determines the period T which is 1 / m (m is an integer of 2 or more) times the period T of the first clock signal REF Based on a reference clock signal having a period T, for each of a plurality of different delay amounts Δ (0 < Δ < T) that are different by T REF Determines whether the first overlap condition, the second overlap condition, or the third overlap condition is satisfied The power management circuit according to Item 3

[0200] (Item 7) The delay amount determination unit determines the smallest delay amount Δ among the delay amounts Δ for which all of the first overlap condition, the second overlap condition, and the third overlap condition are not satisfied as the delay amount of the second clock signal with respect to the first clock signal The power management circuit according to Item 6

[0201] (Item 8) The clock signal generation unit further generates a third clock signal for a third DC / DC converter The delay amount determination unit determines the delay amount of the second clock signal with respect to the rising edge of the first clock signal and the delay amount of the rising edge of the third clock signal with respect to the rising edge of the second clock signal so that the rising edge of the first clock signal does not overlap the falling edge of the third clock signal, or so that the falling edge of the first clock signal does not overlap the rising edge or the falling edge of the third clock signal The power management circuit according to any one of Items 1 to 7

[0202] (Item 9) The clock signal generation unit generates first to p clock signals (p is an integer of 3 or more) each having the same period for driving the switching elements of the first to p DC / DC converters The delay amount determination unit determines the k-th delay amount for the rising edge of the (k+1) clock signal relative to the rising edge of the (k+1) clock signal for each pair of the k-th clock signal and the (k+1) clock signal, based on the k-th duty cycle of the k-th clock signal and the (k+1) duty cycle of the (k+1) clock signal, such that the rising edge of the k-th clock signal does not overlap with the falling edge of the (k+1) clock signal, or the falling edge of the k-th clock signal does not overlap with the rising or falling edge of the (k+1) clock signal. The aforementioned 1st to p-th clock signals are arranged in descending order of duty cycle, The clock signal generation unit generates the (k+1) clock signal for each pair of the k-th clock signal and the (k+1)-th clock signal, with the rising edge of the (k+1)-th clock signal delayed by the k-th delay amount determined by the delay amount determination unit. The power management circuit described in item 1.

[0203] (Item 10) The delay amount determination unit determines the delay amount of the (k+1) clock signal for each pair of the k clock signal and the (k+1) clock signal, starting with the pair of clock signals with the largest duty cycle, for the k clock signal for which all of the first, second, and third overlap conditions are not met. The first overlap condition is that the rising edge of the k clock signal and the falling edge of the (k+1) clock signal coincide. The second overlap condition is that the falling edge of the k clock signal and the rising edge of the (k+1) clock signal coincide. The third overlap condition is that the falling edge of the k clock signal and the falling edge of the (k+1) clock signal coincide. The power management circuit described in item 9.

[0204] (Item 11) The delay amount determination unit uses a reference clock signal having a period of T / m (m is an integer of 2 or more) times the same period T REF to determine an initial value Δ (0 < Δ < T) of the delay amount of the (k + 1)-th clock signal with respect to the k-th clock signal based on the reference clock signal, and sets the delay amount as Δ INIT and determines whether all of the first overlap condition, the second overlap condition, and the third overlap condition are satisfied while changing the delay amount by Δ INIT to T REF one by one, and determines the delay amount based on the determination result. The initial value Δ INIT is a value obtained by multiplying the integer part of m / (p - 1) by the period T REF . The power management circuit according to item 10.

[0205] (Item 12) The clock signal generation unit generates first to p-th clock signals each having the same period for driving first to p-th switching elements respectively included in first to p DC / DC converters (p is an integer of 4 or more). When the delay amount determination unit divides the first to p-th clock signals into first to x-th clock signals (x is an integer of 2 or more and less than p - 1) and (x + 1)-th to p-th clock signals, the delay amount determination unit includes a first delay amount determination unit that determines the delay amount for the first to x-th clock signals, and a second delay amount determination unit that determines the delay amount for the (x + 1)-th to p-th clock signals. The first delay amount determination unit is based on the duty of the k-th x (k x is an integer from 1 to x - 1) switching element and the (k x + 1) duty of the (k x + 1) switching element, such that the rising edge of the k-th x clock signal does not overlap the falling edge of the (k x + 1) clock signal, or the falling edge of the k-th x clock signal does not overlap the rising edge of the (k x + 1) clock signal, or the falling edge of the k-th x+1) The kth such that it does not overlap with the rising or falling edge of the clock signal. x The (k)th rising edge of the clock signal x +1) Determine the amount of delay in the rising edge of the clock signal, The second delay amount determination unit determines the delay amount of the rising edge of the (x+1) clock signal relative to the rising edge of the first clock signal, based on the first duty cycle and the (x+1) duty cycle of the (x+1) switching element, such that the falling edge of the (x+1) clock signal is delayed by one period from the rising edge of the first clock signal, and then the k y (k y (where x is an integer between x+1 and p-1.) The kth of the switching element y Duty and (k y +1) After the switching element (k y +1) Based on duty, the aforementioned k y The falling edge of the clock signal is the (k y +1) So that it does not overlap with the rising edge of the clock signal, or the aforementioned k y The rising edge of the clock signal is the aforementioned (k y +1) The (k) y +1) kth relative to the falling edge of the clock signal y Determines the amount of delay in the falling edge of the clock signal. The power management circuit described in item 1.

[0206] (Item 13) The clock signal generation unit includes a cyclic counter, a first rising trigger circuit for generating a first rising signal, a first falling trigger circuit for generating a first falling signal, a second rising trigger circuit for generating a second rising signal, a second falling trigger circuit for generating a second falling signal, a first JK flip-flop for generating the first clock signal, and a second JK flip-flop for generating the second clock signal. The cyclic counter has a period T that is 1 / m (where m is an integer of 2 or more) times the period T of the first clock signal. REFBased on a reference clock signal having one period T REF Each time, the counter value is incremented by one, starting from 0, and when the counter value reaches m, it is reset to 0. The first rising edge trigger circuit sets the first rising edge signal high when the counter value is 0, and sets the first rising edge signal low when the counter value is different from 0. The first falling-edge trigger circuit sets the first duty cycle to D DUTY1 The counter value is m × D DUTY1 When this is the case, the first falling edge signal is set to high, and the counter value is m × D DUTY1 When it is different, the first falling edge signal is set to low. The second rising edge trigger circuit sets the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal to D DLY1 The counter value is D DLY1 / T REF When this is the case, the second rising edge signal is set to high, and the counter value is D DLY1 / T REF When it is different, the second rising edge signal is set to low. The second falling-edge trigger circuit sets the duty cycle of the second clock signal to D DUTY2 As the counter value is (D DLY1 / T REF +m×D DUTY2 When the second falling edge signal is high, the counter value is (D DLY1 / T REF +m×D DUTY2 When it is different from ), the second falling edge signal is set to low. The first rising edge signal is input to the J terminal of the first JK flip-flop. The first falling edge signal is input to the K terminal of the first JK flip-flop. The second rising edge signal is input to the J terminal of the second JK flip-flop. The second falling edge signal is input to the K terminal of the second JK flip-flop. The first JK flip-flop generates the first clock signal in accordance with the reference clock signal input to the clock signal terminal, The second JK flip-flop generates the second clock signal in accordance with the reference clock signal input to the clock signal terminal. A power management circuit as described in any one of items 1 through 12.

[0207] (Item 14) Further comprising the first DC / DC converter and the second DC / DC converter, A power management circuit as described in any one of items 1 through 13. [Explanation of symbols]

[0208] 1 Power management circuit, 10 Internal power supply, 12_1 First DC / DC converter, 12_2 Second DC / DC converter, 12 DC / DC converter, 12_3 Third DC / DC converter, 14 Controller, 140 A / D converter, 142 Input voltage register, 144 Output voltage register, 150, 250, 350 Clock signal generator, 160, 180 Processing unit, 162, 262, 360 Duty cycle calculation unit, 164, 264 Delay amount determination unit, 166, 266 Clock signal generation unit, 170, 270 Memory unit, 268 First delay amount determination unit, 269 Second delay amount determination unit, 370 First clock signal generation block, 371, 381 First overlap condition determination unit, 372, 382 Second overlap condition determination unit, 373, 383 Third overlap condition determination unit, 374, 384 Subtraction unit, 376 First delay amount determination unit, 378 First clock signal generation unit, 380 Second clock signal generation block, 386 Second delay amount determination unit, 388 Second clock signal generation unit, 400 Overlap condition determination unit, 401-407 First-to-seventh comparison circuits, 421-427 First-to-seventh AND circuits, 430 Selection circuit, 432 AND circuit, 434 Multiplexer, 440 Cyclic counter, 442 Adder circuit, 451 First rising edge trigger circuit, 452 First falling edge trigger circuit, 453 Second rising edge trigger circuit, 454 Second falling edge trigger circuit, 461-464, 501, 502 Comparison circuits, 465-468, 503, 504 NOT circuit, 471 First JK flip-flop, 472 Second JK flip-flop, 480 First adder circuit, 482 Second adder circuit, 491; third rising edge trigger circuit, 492; third falling edge trigger circuit, 510; third JK flip-flop, MH high-side transistor, ML low-side transistor, L inductor, C output capacitor.

Claims

1. A clock signal generation unit that generates a first clock signal for driving a first switching element in a first DC / DC converter and a second clock signal for driving a second switching element in a second DC / DC converter, The system includes a delay amount determination unit that determines the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal, based on the first duty cycle of the first switching element and the second duty cycle of the second switching element, such that the rising edge of the first clock signal does not overlap with the falling edge of the second clock signal, or the falling edge of the first clock signal does not overlap with the rising or falling edge of the second clock signal. The first clock signal and the second clock signal each have the same period, The clock signal generation unit generates a second clock signal whose rising edge is delayed relative to the first clock signal by the amount of delay determined by the delay amount determination unit. Power management circuit.

2. The system further includes a duty cycle calculation unit that calculates a first duty cycle of the first switching element based on the input voltage data and output voltage data of the first DC / DC converter, and calculates a second duty cycle of the first switching element based on the input voltage data and output voltage data of the second DC / DC converter. The delay amount determination unit determines the delay amount based on the first duty cycle and the second duty cycle calculated by the duty cycle calculation unit, respectively. The power management circuit according to claim 1.

3. The delay amount determination unit determines whether the first overlap condition, the second overlap condition, or the third overlap condition is met when the rising edge of the second clock signal is delayed relative to the rising edge of the first clock signal, and determines the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal based on the determination result. The first overlap condition is that the rising edge of the first clock signal and the falling edge of the second clock signal coincide. The second overlap condition is that the falling edge of the first clock signal and the rising edge of the second clock signal coincide. The third overlapping condition is that the falling edge of the first clock signal and the falling edge of the second clock signal coincide. The power management circuit according to claim 1.

4. The delay amount determination unit determines the delay amount such that both the first overlap condition and the second overlap condition are not satisfied. The power management circuit according to claim 3.

5. The delay amount determination unit determines the delay amount such that the first overlap condition, the second overlap condition, and the third overlap condition are all satisfied. The power management circuit according to claim 4.

6. The delay amount determination unit determines the period T of the first clock signal to be 1 / m (where m is an integer of 2 or more) times the period T. ＲＥＦ Based on a reference clock signal having the period T ＲＥＦ For each of several different delay amounts Δ (0 < Δ < T), it is determined whether the first overlap condition, the second overlap condition, or the third overlap condition is met. The power management circuit according to claim 3.

7. The delay amount determination unit determines the smallest delay amount Δ among the delay amounts Δ in which all of the first overlap condition, the second overlap condition, and the third overlap condition are not satisfied as the delay amount of the second clock signal relative to the first clock signal. The power management circuit according to claim 6.

8. The clock signal generation unit further generates a third clock signal for the third DC / DC converter, The delay amount determination unit determines the delay amount of the second clock signal relative to the rising edge of the first clock signal and the delay amount of the rising edge of the third clock signal relative to the rising edge of the second clock signal, such that the rising edge of the first clock signal does not coincide with the falling edge of the third clock signal, or the falling edge of the first clock signal does not coincide with the rising edge or falling edge of the third clock signal. The power management circuit according to claim 1.

9. The clock signal generation unit generates first to p clock signals, each having the same period, for driving the switching elements of the first to p DC / DC converters (where p is an integer of 3 or more). The delay amount determination unit determines the k-th delay amount for the rising edge of the (k+1) clock signal relative to the rising edge of the (k+1) clock signal for each pair of the k-th clock signal and the (k+1) clock signal, based on the k-th duty cycle of the k-th clock signal and the (k+1) duty cycle of the (k+1) clock signal, such that the rising edge of the k-th clock signal does not overlap with the falling edge of the (k+1) clock signal, or the falling edge of the k-th clock signal does not overlap with the rising or falling edge of the (k+1) clock signal. The aforementioned first to p-th clock signals are arranged in descending order of duty cycle. The clock signal generation unit generates the (k+1) clock signal for each pair of the k clock signal and the (k+1) clock signal, with the rising edge of the (k+1) clock signal delayed by the k delay amount determined by the delay amount determination unit. The power management circuit according to claim 1.

10. The delay amount determination unit determines the delay amount of the (k+1) clock signal for each pair of the k clock signal and the (k+1) clock signal, starting with the pair of clock signals with the largest duty cycle, for the k clock signal for which all of the first, second, and third overlap conditions are not met. The first overlap condition is that the rising edge of the k clock signal and the falling edge of the (k+1) clock signal coincide. The second overlap condition is that the falling edge of the k clock signal and the rising edge of the (k+1) clock signal coincide. The third overlapping condition is that the falling edge of the k clock signal and the falling edge of the (k+1) clock signal coincide. The power management circuit according to claim 9.

11. The delay amount determination unit determines a period T that is 1 / m (where m is an integer of 2 or more) times the same period T. ＲＥＦ Based on a reference clock signal having the following, the initial value of the delay amount Δ(0 < Δ < T) of the (k+1) clock signal relative to the k clock signal is set to Δ ＩＮＩＴ Let the delay amount be Δ ＩＮＩＴ From T ＲＥＦ The system determines whether all of the first, second, and third overlap conditions are met while gradually changing the values, and then determines the delay amount based on the result of that determination. The initial value Δ ＩＮＩＴ The period T is the integer part of m / (p-1). ＲＥＦ It is the value obtained by multiplying by, The power management circuit according to claim 10.

12. The clock signal generation unit generates first to p clock signals, each having the same period, for driving the first to p switching elements of each of the first to p DC / DC converters (where p is an integer of 4 or more). The delay amount determination unit includes a first delay amount determination unit that determines the delay amount for the first to x clock signals when the first to p clock signals are divided into the first to x clock signals (where x is an integer of 2 or more and less than p-1) and the (x+1) to p clock signals, and a second delay amount determination unit that determines the delay amount for the (x+1) to p clock signals. The first delay amount determination unit determines the k ｘ (k ｘ is an integer from 1 to x - 1).) The duty of the k ｘ th switching element and the (k ｘ + 1)th duty of the (k ｘ + 1)th switching element, based on which the rising edge of the k ｘ th clock signal does not overlap with the falling edge of the (k ｘ + 1)th clock signal, or the falling edge of the k ｘ th clock signal does not overlap with the rising edge or the falling edge of the (k ｘ + 1)th clock signal, and determines the delay amount of the rising edge of the (k ｘ + 1)th clock signal with respect to the rising edge of the k ｘ th clock signal, The second delay amount determination unit determines the delay amount of the rising edge of the (x+1) clock signal relative to the rising edge of the first clock signal, based on the first duty cycle and the (x+1) duty cycle of the (x+1) switching element, such that the falling edge of the (x+1) clock signal is delayed by one cycle from the rising edge of the first clock signal, and then k ｙ (k ｙ (x+1 to p-1 is an integer.) The kth of the switching element ｙ Duty and (k) ｙ +1) The (k) of the switching element ｙ +1) Based on the duty cycle, the k ｙ The falling edge of the clock signal is the (k) ｙ +1) So as not to overlap with the rising edge of the clock signal, or the above k ｙ The rising edge of the clock signal is the (k ｙ +1) The (k) such that it does not overlap with the rising or falling edge of the clock signal. ｙ +1) k-th term relative to the falling edge of the clock signal ｙ Determines the amount of delay in the falling edge of the clock signal. The power management circuit according to claim 1.

13. The clock signal generation unit includes a cyclic counter, a first rising trigger circuit for generating a first rising signal, a first falling trigger circuit for generating a first falling signal, a second rising trigger circuit for generating a second rising signal, a second falling trigger circuit for generating a second falling signal, a first JK flip-flop for generating the first clock signal, and a second JK flip-flop for generating the second clock signal. The cyclic counter has a period T that is 1 / m (where m is an integer of 2 or more) times the period T of the first clock signal. ＲＥＦ Based on a reference clock signal having one period T ＲＥＦ Each time, the counter value is incremented by one, starting from 0, and when the counter value reaches m, it is reset to 0. The first rising edge trigger circuit sets the first rising edge signal high when the counter value is 0, and sets the first rising edge signal low when the counter value is different from 0. The first falling-edge trigger circuit sets the first duty cycle to D ＤＵＴＹ１ The counter value is m × D ＤＵＴＹ１ When this is the case, the first falling edge signal is set to high, and the counter value is m × D ＤＵＴＹ１ When it is different, the first falling edge signal is set to low. The second rising edge trigger circuit sets the delay amount of the rising edge of the second clock signal relative to the rising edge of the first clock signal to D ＤＬＹ１ The counter value is D ＤＬＹ１ / T ＲＥＦ When this is the case, the second rising edge signal is set to high, and the counter value is D ＤＬＹ１ / T ＲＥＦ When it is different, the second rising edge signal is set to low. The second falling-edge trigger circuit sets the duty cycle of the second clock signal to D ＤＵＴＹ２ The counter value is (D ＤＬＹ１ / T ＲＥＦ +m × D ＤＵＴＹ２ When the second falling edge signal is high, the counter value is (D ＤＬＹ１ / T ＲＥＦ +m × D ＤＵＴＹ２ When it is different from the above, the second falling edge signal is set to low. The first rising edge signal is input to the J terminal of the first JK flip-flop. The first falling edge signal is input to the K terminal of the first JK flip-flop. The second rising edge signal is input to the J terminal of the second JK flip-flop. The second falling edge signal is input to the K terminal of the second JK flip-flop. The first JK flip-flop generates the first clock signal in accordance with the reference clock signal input to the clock signal terminal, The second JK flip-flop generates the second clock signal in accordance with the reference clock signal input to the clock signal terminal. The power management circuit according to claim 1.

14. Further comprising the first DC / DC converter and the second DC / DC converter, A power management circuit according to any one of claims 1 to 13.

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