Semiconductor package and method for manufacturing the same

Abstract

The present invention provides a semiconductor package and a method for manufacturing the same, which uses a thermally conductive material to bond the die to a substrate and effectively dissipate the heat generated by the operation of the die. [Solution] The semiconductor package of the present invention includes a substrate having an upper surface and a lower surface; a first die placed on the upper surface of the substrate; a thermally conductive material placed between the first die and the substrate and used to attach the first die to the upper surface of the substrate; a plurality of bonding wires, each with one end connected to the first die and the other end connected to the upper surface of the substrate; a sealing material formed on the upper surface of the substrate and covering the first die and the bonding wires; and a heat dissipation frame placed on the upper surface of the substrate and surrounding the sealing material. The present invention further provides a method for manufacturing the above semiconductor package.

Description

Technical Field

[0004] , ,

[0005] ,

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and particularly to a semiconductor package containing a thermally conductive material and a manufacturing method thereof.

Background Art

[0002] Currently, for products using wire bonding technology, when there is a heat dissipation requirement, usually a heat sink is attached to the encapsulant. However, with this method, the amount of heat generated by the operation of the die cannot be effectively dissipated.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In view of this, the present invention provides a semiconductor package and a manufacturing method thereof that use a thermally conductive material to adhere a die to a substrate and can effectively dissipate the heat generated by the operation of the die.

Means for Solving the Problems

[0004] To achieve the above object, the semiconductor package of the present invention includes a substrate having an upper surface and a bottom surface, a first die installed on the upper surface of the substrate, a thermally conductive material installed between the first die and the substrate and used to attach the first die to the upper surface of the substrate, a plurality of bonding wires each having one end connected to the first die and the other end connected to the upper surface of the substrate, an encapsulant formed on the upper surface of the substrate to cover the first die and the bonding wires, and a heat dissipation frame installed on the upper surface of the substrate to surround the encapsulant.

[0005] The present invention provides a method for manufacturing a semiconductor package, comprising the steps of: preparing a substrate having an upper surface and a lower surface; preparing a first die; placing a thermally conductive material between the first die and the substrate and attaching the first die to the upper surface of the substrate; placing a plurality of bonding wires, connecting one end of each bonding wire to the first die and the other end to the upper surface of the substrate; forming a sealing material on the upper surface of the substrate to cover the first die and the bonding wires; and installing a heat dissipation frame on the upper surface of the substrate and surrounding the sealing material. [Effects of the Invention]

[0006] According to the semiconductor package of the present invention, a die is bonded to a substrate using a thermally conductive material, and the heat generated by the operation of the die is effectively dissipated, resulting in a better heat dissipation effect. [Brief explanation of the drawing]

[0007] [Figure 1] This is an explanatory diagram of a first embodiment of the semiconductor package of the present invention. [Figure 2] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 3] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 4] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 5] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 6] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 7] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 8] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 9] Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Figure 10]Figure 1 is an explanatory diagram of the method for manufacturing the semiconductor package of the present invention. [Modes for carrying out the invention]

[0008] To further clarify the above and other objectives, features, and advantages of the present invention, embodiments of the present invention will be described in detail below, accompanied by the drawings.

[0009] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to a constant scale. In fact, for the sake of clarity in the description, the dimensions of various components may be arbitrarily enlarged or reduced.

[0010] The following disclosure provides many different embodiments or examples for carrying out different features of this disclosure. For the sake of brevity of this disclosure, specific examples of members and configurations are described below. Naturally, these members and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first member above or on top of a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which an additional member is formed between the first member and the first member so that the first member and the second member are not in direct contact. Also, in various examples of this disclosure, reference numbers and / or letters may be repeated. This repetition is for simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations being discussed.

[0011] Furthermore, for the sake of clarity, the text may use spatially relative terms such as "below," "downward," "bottom," "above," and "top" to describe the relationship between one member or component shown in the diagram and one or more other members or components. Beyond the orientations shown in the diagrams, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (90-degree rotation or other orientations), and the spatially relative descriptions used in the text shall be interpreted accordingly.

[0012] Referring to Figure 1, the semiconductor package of the present invention includes a substrate 110 having opposing first surfaces 111 and second surfaces 112, wherein the first surface 111 and the second surface 112 are located on different planes, for example, the first surface 111 is the top surface and the second surface 112 is the bottom surface. Conductive wires 113 and 114 are formed on the first surface 111 and the second surface 112 of the substrate 110, respectively, and the conductive wires 113 and 114 are electrically connected by a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the substrate 110. A plurality of passive members 180 may be further installed on the first surface 111 of the substrate 110 as needed.

[0013] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.

[0014] At least one, for example, a plurality of dies are mounted on the first surface 111 of the substrate 110, and the die includes at least a first die 130 and a second die 140. The first die 130 and the second die 140 are mounted in parallel. The first die 130 and the second die 140 each have an active surface and a back surface opposite to the active surface.

[0015] The back surface of the first die 130 is attached to the first surface 111 of the substrate 110 using a thermally conductive material 120, i.e., the thermally conductive material 120 is used as an adhesive for attaching the first die 130 to the substrate 110. The first die 130 is electrically connected to the first surface 111 of the substrate 110 using a plurality of bonding wires 132, i.e., both ends of each of the bonding wires 132 are connected to the active surface of the first die 130 and the first surface 111 of the substrate 110.

[0016] The second die 140 can be attached to the first surface 111 of the substrate 110 using flip chip technology and is electrically connected to the substrate 110. A plurality of conductive blocks 142 are provided on the active surface of the second die 140 and are sandwiched between the second die 140 and the substrate 110. The second die 140 is electrically connected to the substrate 110 via the conductive blocks 142. In another embodiment, the second die 140 can be electrically connected to the substrate 110 using bonding wires.

[0017] On the first surface 111 of the substrate 110, a sealing material 150 is formed to cover the first die 130, the second die 140, the passive member 180, and the bonding wires 132.

[0018] The sealing material 150 has a first surface 151, a second surface 152, and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located on different planes from each other, and the third surfaces 153 are connected to the first surface 151 and the second surface 152. In one embodiment, the first surface 151 is the upper surface, the second surface 152 is the bottom surface, and the third surfaces 153 are the side surfaces, but it is not limited thereto. The second surface 152 of the sealing material 150 contacts the first surface 111 of the substrate 110.

[0019] On the first surface 111 of the substrate 110, a heat dissipation frame 160 surrounding the encapsulant 150, the first die 130, the second die 140, the passive member 180, and the bonding wire 132 is further provided. The heat dissipation frame 160 has a first surface 161, a second surface 162, a plurality of third surfaces 163, and a plurality of fourth surfaces 164. The first surface 161 and the second surface 162 are located in different planes from each other, and the third surfaces 163 and the fourth surfaces 164 are connected to the first surface 161 and the second surface 162.

[0020] In one embodiment, the first surface 161 is the upper surface, the second surface 162 is the bottom surface, the third surfaces 163 are the outer surfaces, the fourth surfaces 164 are the inner surfaces, and the third surfaces 163 surround the fourth surfaces 164. The fourth surfaces 164 of the heat dissipation frame 160 respectively contact the third surfaces 153 of the encapsulant 150. The first surface 161 of the heat dissipation frame 160 is not covered by the encapsulant 150.

[0021] A heat sink 170 is provided on the first surface 151 of the encapsulant 150, and the heat sink 170 contacts the first surface 161 of the heat dissipation frame 160.

[0022] On the second surface 112 of the substrate 110, a plurality of solder balls 190 electrically connected to the substrate 110 are provided. The solder balls 190 are electrically connected to the bonding wire 132 through the conductive lines 113, 114 and the conductive plated-through holes 115 on the substrate 110, whereby the first die 130 can pass through the bonding wire 132, and the substrate 110 can be electrically connected to an external circuit using the solder balls 190. Similarly, the second die 140 can be electrically connected to an external circuit using the solder balls 190 through the substrate 110.

[0023] According to the semiconductor package of the present invention, the amount of heat generated by the operation of the first die 130 can be conducted to the substrate 110 via the thermally conductive material 120 and dissipated to the outside through the heat dissipation frame 160 and the heat sink 170.

[0024] Referring to Figures 2 to 10, Figures 2 to 10 illustrate the manufacturing method of the semiconductor package shown in Figure 1. As shown in Figure 2, a substrate 110 having opposing first surfaces 111 and second surfaces 112 is prepared, and the first surface 111 and the second surface 112 are located on different planes, for example, the first surface 111 is the top surface. The second surface 112 is the bottom surface, but is not limited to this. Conductive wires 113 and 114 are formed on the first surface 111 and the second surface 112 of the substrate 110, respectively, and the conductive wires 113 and 114 are electrically connected via a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the substrate 110.

[0025] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.

[0026] As shown in Figure 3, a plurality of passive members 180 are then placed on the first surface 111 of the substrate 110.

[0027] As shown in Figure 4, next, at least one, for example, multiple dies are placed on the first surface 111 of the substrate 110, and the die includes at least a first die 130 and a second die 140. The first die 130 and the second die 140 are placed in parallel. The first die 130 and the second die 140 each have an active surface and a back surface opposite to the active surface.

[0028] The back surface of the first die 130 is attached to the first surface 111 of the substrate 110 using a thermally conductive material 120. The second die 140 is attached to the first surface 111 of the substrate 110 using flip-chip technology and is electrically connected to the substrate 110.

[0029] As shown in Figure 5, the first die 130 is then electrically connected to the substrate 110 using a plurality of bonding wires 132. Each end of the bonding wire 132 is connected to the active surface of the first die 130 and the first surface 111 of the substrate 110, respectively. The second die 140 can also be electrically connected to the substrate 110 using bonding wires.

[0030] As shown in Figure 6, the heat dissipation frame 160 is then placed on the first surface 111 of the substrate 110, surrounding the first die 130, the second die 140, the passive member 180, and the bonding wire 132. The heat dissipation frame 160 has a first surface 161, a second surface 162, a third surface 163, and a fourth surface 164. The first surface 161 and the second surface 162 are located in different planes from each other, and the third surface 163 and the fourth surface 164 connect the first surface 161 and the second surface 162.

[0031] In one embodiment, the first surface 161 is the top surface, the second surface 162 is the bottom surface, the third surface 163 is the outer surface, the fourth surface 164 is the inner surface, and the third surface 163 surrounds the fourth surface 164.

[0032] As shown in Figure 7, the sealing material 150 is then formed on the first surface 111 of the substrate 110, covering the first die 130, the second die 140, the passive member 180, and the bonding wire 132.

[0033] As shown in Figure 8, next, a portion of the sealing material 150 is ground off to expose the first surface 161 of the heat dissipation frame 160.

[0034] The sealing material 150, after a portion is removed, has a first surface 151, a second surface 152, and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located on different planes, and the third surface 153 is connected to the first surface 151 and the second surface 152. In one embodiment, the first surface 151 is the top surface, the second surface 152 is the bottom surface, and the third surface 153 is the side surface, but is not limited thereto.

[0035] The second surface 152 of the sealing material 150 is in contact with the first surface 111 of the substrate 110, and the heat dissipation frame 160 surrounds the sealing material 150 and is in contact with the third surface 153 of the sealing material 150.

[0036] In another embodiment, after performing the steps shown in Figure 6, an exposed mold is attached to expose the first surface 161 of the heat dissipation frame 160 from the mold (not shown), and then the sealant 150 is formed on the first surface 111 of the substrate 110. Since the sealant 150 formed in this way does not cover the first surface 161 of the heat dissipation frame 160, there is no need to grind the sealant 150.

[0037] As shown in Figure 9, the heat sink 170 is then placed on the first surface 151 of the sealing material 150 and brought into contact with the first surface 161 of the heat dissipation frame 160.

[0038] As shown in Figure 10, a plurality of solder balls 190 are then formed on the second surface 112 of the substrate 110, and the solder balls 190 are electrically connected to the substrate 110 to form a semiconductor package as shown in Figure 1.

[0039] The solder ball 190 is electrically connected to the bonding wire 132 via the conductive wires 113 and 114 and the conductive plated through-hole 115 on the substrate 110, thereby allowing the first die 130 to be electrically connected to an external circuit using the solder ball 190 via the bonding wire 132 and the substrate 110. Similarly, the second die 140 can be electrically connected to an external circuit using the solder ball 190 via the substrate 110.

[0040] According to the semiconductor package of the present invention, a die is bonded to a substrate using a thermally conductive material, and the heat generated by the operation of the die is effectively dissipated, resulting in a better heat dissipation effect.

[0041] Although the present invention is disclosed in the embodiments described above, this does not limit the invention, and those skilled in the art can make various changes and modifications without departing from the spirit of the invention. Accordingly, the scope of protection of the present invention shall be as defined in the claims described below. [Explanation of symbols]

[0042] 110 circuit boards 111 Page 1 112 Side 2 113 Conductive wire 114 Conductive wire 115 Conductive plated through-holes 120 Thermally conductive materials 130 First Die 132 Bonding Wire 140 Second Die 142 Conductive Block 150 sealing material 151 Page 1 152 2nd page 153 Page 3 160 Heat Dissipation Frame 161 Page 1 162 2nd page 163 3rd page 164 Page 4 170 Heatsink 180 Passive member 190 solder balls

Claims

1. A substrate having a top surface and a bottom surface, A first die is installed on the upper surface of the substrate, A thermally conductive material is placed between the first die and the substrate and used to attach the first die to the upper surface of the substrate, A plurality of bonding wires, each having one end connected to the first die and the other end connected to the upper surface of the substrate, A sealing material formed on the upper surface of the substrate and covering the first die and the bonding wire, A heat dissipation frame is installed on the upper surface of the substrate and surrounds the sealing material, A semiconductor package that includes this.

2. The semiconductor package according to claim 1, further comprising a heat sink installed on the sealing material and in contact with the heat dissipation frame.

3. The semiconductor package according to claim 1, wherein the substrate is one of a circuit board, a redistribution layer substrate, or a glass substrate.

4. A second die is installed on the upper surface of the substrate, A plurality of conductive blocks are sandwiched between the second die and the substrate and electrically connected to the second die and the substrate, It further includes, The semiconductor package according to claim 1, wherein the sealing material further covers the second die.

5. A step of preparing a substrate having a top surface and a bottom surface, The process of preparing the first die, A step of placing a thermally conductive material between the first die and the substrate, and attaching the first die to the upper surface of the substrate, The process involves installing multiple bonding wires, connecting one end of each bonding wire to the first die, and connecting the other end to the upper surface of the substrate, A step of forming a sealing material on the upper surface of the substrate to cover the first die and bonding wire, The process involves installing the heat dissipation frame on the upper surface of the substrate and surrounding the sealing material, A method for manufacturing semiconductor packages, including the method described above.

6. A method for manufacturing a semiconductor package according to claim 5, further comprising the step of placing a heat sink on the sealing material and bringing it into contact with a heat sink frame.

7. A method for manufacturing a semiconductor package according to claim 5, further comprising the step of removing a portion of the sealing material by grinding to expose the heat dissipation frame.

8. The method for manufacturing a semiconductor package according to claim 5, further comprising the step of attaching an exposed mold and exposing the heat dissipation frame before forming the sealing material.

9. The method for manufacturing a semiconductor package according to claim 5, wherein the substrate is one of a circuit board, a redistribution layer substrate, or a glass substrate.

10. A step of installing multiple conductive blocks on a second chip, The steps include: placing the second die on the substrate and sandwiching the conductive block between the second die and the substrate; A method for manufacturing a semiconductor package according to claim 5, further comprising:

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