Wiring board, and method for manufacturing a wiring board

Abstract

To provide a wiring board having via conductors with good connection reliability. [Solution] The wiring board 1 of the embodiment comprises a first conductor layer 12F, an insulating layer 11 covering the first conductor layer 12F, a second conductor layer 12S formed on the surface of the insulating layer 11, and a via conductor 12V formed on the inner wall surface of a through hole 11c penetrating the insulating layer 11 to connect the first conductor layer 12F and the second conductor layer 12S. The via conductor 12V includes at least a first seed layer 121 and a plating layer 124 covering the inner wall surface of the through hole 11c, and the second conductor layer 12S is formed by a second seed layer 122 and a plating layer 124 covering the surface of the insulating layer 11, the first seed layer 121 and the plating layer 124 being made of different materials, and the second seed layer 122 and the plating layer being made of the same material.

Description

Technical Field

[0005] ,

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board. An opening for a via conductor is formed in an insulating layer laminated on a conductor layer. A seed layer is formed on the insulating layer and in the opening, and by electrolytic plating, a metal material is filled in the opening using the seed layer as a power supply layer to form a via conductor, and a plating layer for a conductor pattern is formed on the seed layer.

Prior Art Document

Patent Document

[0006] The present invention provides a method for manufacturing a wiring board, comprising: forming an insulating layer on a first conductor layer; forming through holes in the insulating layer that expose a portion of the upper surface of the first conductor layer; forming a first seed layer on the inner wall surface of the through holes and the upper surface of the first conductor layer exposed within the through holes; forming a second seed layer on the surface of the insulating layer; and forming a plating layer on the second seed layer using a material different from that of the first seed layer but of the same material as that of the second seed layer, thereby forming a via conductor and a second conductor layer.

[0007] According to embodiments of the present invention, it is possible to reduce peeling of via conductors and poor conductivity with the conductor layer by forming a highly adhesive metal film layer within the via conductor opening, and to improve the accuracy of conductor pattern formation and the efficiency of plating layer formation by forming an easily etchable metal film layer on the insulating layer. [Brief explanation of the drawing]

[0008] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2] An enlarged view of region II of the wiring board shown in Figure 1. [Figure 3A] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3B] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3C] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3D] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3E] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3F] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3G] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3H] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3I] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3J] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3K] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 3L] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Modes for carrying out the invention]

[0009] The wiring board of the embodiment will be described with reference to the drawings. Figure 1 shows a cross-sectional view of wiring board 1, which is an example of the wiring board of the embodiment. Note that wiring board 1 is merely an example of the wiring board of the embodiment. Wiring board 1 is formed of alternatingly stacked insulating layers 11 and conductive layers 12, and a part of it is shown in Figure 1. The stacked structure of the wiring board of the embodiment, as well as the number of conductive layers and insulating layers, are not limited to the stacked structure of wiring board 1 in Figure 1, as well as the number of insulating layers 11 and conductive layers 12. Also, the referenced drawings are drawn to facilitate understanding of the features of the present invention, and the size and proportions of each component may not be accurate.

[0010] In the following explanation, the side of the wiring board 1 where the component mounting surface U is formed will be referred to as "top," "upper side," or "upward direction," and the surface facing upward will be referred to as the "top surface." The side opposite to the U side will be referred to as "bottom," "lower side," or "downward direction," and the surface facing downward will be referred to as the "bottom surface."

[0011] The wiring board 1 shown in Figure 1 has multiple insulating layers 11 and conductor layers 12 that are stacked alternately. In Figure 1, one side of the wiring board 1 is formed as a component mounting surface U on which external electronic components such as semiconductor elements are mounted. Figure 1 shows the portion of the stacked multiple insulating layers 11 and conductor layers 12 that corresponds to three layers of insulating layers 11 on the component mounting surface U side. Conductor layers 12 that are facing each other above and below with one insulating layer 11 in between are connected by via conductors 12V. In the illustrated example, the conductor layers 12 that constitute a part of the component mounting surface U include multiple conductor pads 12P.

[0012] The insulating layer 11 can be formed using an insulating resin such as epoxy resin, polyimide resin, BT resin (bismaleimide-triazine resin), polyphenylene ether resin, or phenolic resin. The insulating layer 11 may also contain any of the following: fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI). The insulating layer 11 may also contain inorganic fillers such as fine particles made of silica (SiO2), alumina, or mullite. The insulating layer 11 may also contain a core material (reinforcement material) made of glass fiber or aramid fiber. In the wiring board 1, the thickness of each insulating layer 11 is, for example, 5 μm to 15 μm.

[0013] The conductor layer 12 can be formed on the upper or lower surface of the insulating layer 11, or between two insulating layers 11, using any material with appropriate conductivity. In Figure 1, the conductor layer 12 has a two-layer structure in which a plating layer 124 is laminated on a second seed layer 122, which is a metal film layer, but it is not limited to this and may have a structure with three or more layers. The second seed layer 122 is preferably a sputtering film layer. The plating layer 124 is preferably an electroplating layer with the second seed layer 122 as the power supply layer. The second seed layer 122 and the plating layer 124 are formed using the same type of conductive material. By forming the second seed layer 122 and the plating layer 124 with the same type of conductive material, the efficiency of forming the plating layer 124 by electroplating with the second seed layer 122 as the power supply layer may be increased. The second seed layer 122 and the plating layer 124 are more preferably formed using a conductive material containing copper or a copper alloy. By forming the second seed layer 122 and the plating layer 124 with a conductive material containing copper or a copper alloy, appropriate adhesion to the insulating layer 11 can be ensured while suppressing the generation of etching residue during conductor pattern formation, improving the accuracy of pattern formation and suppressing defects such as short circuits.

[0014] The via conductor 12V is formed by forming a metal film layer on the inner wall surface of the through hole 11c that penetrates the insulating layer 11 in the thickness direction, and further filling the inside of the through hole 11c with a conductive material. The metal film layer laminated on the inner wall surface of the through hole 11c includes at least a first seed layer 121. The first seed layer 121 is preferably a sputtering film layer. The first seed layer 121 is formed of a conductive material different from the second seed layer 122, and is preferably formed using a conductive material that easily adheres to the inner wall surface of the through hole 11c. Although the sputtering film layer is as thin as about 50 to 150 nm, since the first seed layer 121 is formed of a conductive material that easily adheres to the inner wall surface of the through hole 11c, the via conductor 12V firmly adheres and is fixed to the inner wall surface of the through hole 11c, and peeling of the via conductor 12V and conduction failure between conductor layers through the via conductor 12V can be avoided. The first seed layer 121 is more preferably formed using a conductive material containing titanium, a titanium alloy, nickel, or a nickel alloy. By forming the first seed layer 121 of a conductive material containing titanium, a titanium alloy, nickel, or a nickel alloy, the adhesion to the inner wall surface of the through hole 11c is improved, and peeling of the via conductor 12V and the like can be further reduced.

[0015] More preferably, a second seed layer 122 is also formed on the first seed layer 121, and the first seed layer 121 is covered by the second seed layer 122. By covering the first seed layer 121 with the second seed layer 122, the degree of freedom in selecting a conductive material that easily adheres to the inner wall surface of the through hole 11c as the first seed layer 121 increases, and peeling of the via conductor 12V and the like can be more reliably avoided.

[0016] Further, since the first seed layer 121 is covered by the second seed layer 122, the conductive material of the second seed layer 122 can be appropriately selected regardless of the adhesion to the inner wall surface of the through hole 11c. As described above, preferably, the second seed layer 122 is a sputtering film layer, and the plating layer 124 is an electrolytic plating layer using the second seed layer 122 as a power feeding layer. Also, the second seed layer 122 and the plating layer 124 are preferably formed using the same kind of conductive material, and more preferably, a conductive material containing copper or a copper alloy is used. When both the second seed layer 122 and the plating layer 124 are formed of a conductive material containing copper or a copper alloy, the formation efficiency of the plating layer 124 may be enhanced. Further, since a two-layer metal film layer of the first seed layer 121 and the second seed layer 122 is formed in the through hole 11c, the overall layer thickness increases and the conductor resistance is reduced, the current during electrolytic plating increases, and the plating formation speed in the through hole 11c may be increased.

[0017] In the wiring substrate 1, the first seed layer 121 and the second seed layer 122 are formed on the inner wall surface of the through hole 11c, and the second seed layer 122 is formed on the upper surface 11a of the insulating layer 11. Therefore, the number of stacked seed layers formed on the inner wall surface of the through hole 11c is larger than the number of stacked seed layers formed on the upper surface 11a of the insulating layer 11. As in the prior art document, when a plating seed layer composed of a sputtering film layer is continuously formed on the inner surface of the via hole and the surface of the interlayer insulating layer, the thickness of the sputtering film layer on the inner surface of the via hole may be about 15 to 30% thinner than the thickness of the sputtering film layer on the surface of the interlayer insulating layer. In the wiring substrate 1, by making the number of stacked sputtering film layers formed on the inner wall surface of the through hole 11c larger than the number of stacked sputtering film layers formed on the upper surface 11a of the insulating layer 11, the thickness difference between the seed layers formed on the inner wall surface of the through hole 11c and the upper surface 11a of the insulating layer 11 can be reduced.

[0018] The wiring board 1 comprises a solder resist layer 13 on top of an uppermost insulating layer 11 and a conductor layer 12. The solder resist layer 13 is formed using, for example, a photosensitive polyimide resin or epoxy resin. An opening 13c is formed in the solder resist layer 13, and the uppermost conductor pad 12P is exposed through the opening 13c.

[0019] In the wiring board 1, the thickness of the conductor layer 12 is, for example, 2 μm to 8 μm. The conductor layer 12 included in the wiring board 1 is patterned to have a predetermined conductor pattern, and can form a dense circuit wiring with fine wires. When the conductor layer 12 includes a fine wire conductor pattern, the diameter of the via conductor 12V connecting the conductor layers 12 may also be formed to be small. Specifically, the diameter of the through hole 11c or via conductor 12V formed in the insulating layer 11 may be, for example, 5 μm or more and 30 μm or less. When the diameter of the via conductor 12V is reduced, the contact area between the via conductor 12V and the conductor layer 12 and / or conductor pad 12P formed beneath the via conductor 12V decreases, making it easier for problems such as poor conductivity to occur. As described above, in the wiring board 1, a conductive material that has high adhesion to the inner wall surface of the through hole 11c without worrying about etching properties on the insulating layer surface can be selected as the material for the first seed layer 121 formed on the inner wall surface of the through hole 11c. Therefore, peeling of the via conductor 12V becomes less likely, and problems such as poor conductivity can be resolved. Note that the planar shape of the through hole 11c and / or via conductor 12V is not necessarily limited to a circle. The term "diameter" used in relation to the through hole 11c and / or via conductor 12V refers to the distance between the two longest points on the outer circumference of the through hole 11c and / or via conductor 12V on the upper surface of the insulating layer 11 through which the through hole 11c and / or via conductor 12V penetrate.

[0020] Figure 2 shows an enlarged view of region II of the wiring board 1 shown in Figure 1. Using Figure 2, the configuration of the insulating layer 11, the conductor layer 12, and the via conductor 12V included in the wiring board 1 will be described in detail. In the following description, the conductor layer 12 formed below the uppermost insulating layer 11 shown in Figure 2 will also be referred to as the "first conductor layer 12F," and the uppermost conductor layer 12 formed above the uppermost insulating layer 11 will also be referred to as the "second conductor layer 12S." The through-hole 11c penetrates the insulating layer 11 in the thickness direction, and is formed such that a part of the upper surface 12a of the first conductor layer 12F is exposed at the bottom surface of the through-hole 11c. The via conductor 12V is formed by sequentially sputtering a first seed layer 121 and a second seed layer 122 onto the inner wall surface of the through hole 11c and a portion of the upper surface 12a of the exposed first conductor layer 12F, and then filling the inside of the through hole 11c with a plating layer 124. As described above, as the conductor pattern becomes denser and thinner, the via conductor 12V becomes smaller in diameter, which inevitably leads to a smaller diameter for the through hole 11c, and the area of ​​the upper surface 12a of the first conductor layer 12F exposed at the bottom of the through hole 11c becomes smaller. When the area of ​​the upper surface 12a of the first conductor layer 12F exposed at the bottom of the through hole 11c becomes smaller, the contact area between the metal film layer formed on the inner wall surface of the through hole 11c and the first conductor layer 12F decreases, making it easier for problems such as poor conductivity to occur. In the wiring board 1 of Figure 2, the via conductor 12V has a first seed layer 121 made of a conductive material containing titanium or the like that has high adhesion to the inner wall surface of the through hole 11c. Therefore, it is firmly fixed in contact with the inner wall of the through hole 11c, and problems such as peeling can be suppressed. As a result, the via conductor 12V is securely fixed and in contact with the first conductor layer 12F, and poor conductivity between the via conductor 12V and the first conductor layer 12F can also be suppressed.

[0021] In the example shown in Figure 2, the second seed layer 122 constituting the second conductor layer 12S is made of copper or the like. Therefore, in the process of forming the conductor pattern of the second conductor layer 12S, it is easy to use a general etching agent, which suppresses the generation of etching residue and can prevent defects such as short circuits.

[0022] As described above, in the wiring board 1 of the embodiment, the first seed layer 121 formed in the through hole 11c and the second seed layer 122 formed on the upper surface 11a of the insulating layer 11 are formed using different conductive materials, and the second seed layer 122 is formed using the same conductive material as the plating layer 124. This makes it possible to achieve both the strong adhesion required for the metal film layer on the inner wall surface of the through hole 11c and the ease of etching and the formation efficiency of the plating layer 124 required for the metal film layer on the insulating layer 11. In particular, by configuring the second seed layer 122 to cover the first seed layer 121 in the through hole 11c, the materials of each metal film layer can be selected flexibly and appropriately. As a result, it is possible to simultaneously prevent peeling of the via conductor 12V, suppress etching residue during conductor pattern formation, and achieve high formation efficiency of the plating layer.

[0023] The manufacturing method of the wiring board according to the embodiment will be described below, with reference to Figures 3A to 3L, using the wiring board 1 shown in Figure 1 as an example. Unless otherwise specified, each component formed in the manufacturing method described below may be formed using the materials exemplified as the materials for the corresponding components in the description of the wiring board 1 in Figures 1 and 2. In Figures 3A to 3L, similar to Figure 1, the entire wiring board 1 is not shown; only the portion corresponding to the three insulating layers on the component mounting surface U side of the multiple stacked insulating layers 11 and conductor layers 12 is shown. Also, similar to the description of Figure 2, in the description of Figures 3A to 3L, the conductor layer 12 formed below the uppermost insulating layer 11 is also referred to as the first conductor layer 12F, and in the description of Figures 3K and 3L, the uppermost conductor layer 12 formed above the uppermost insulating layer 11 is also referred to as the second conductor layer 12S.

[0024] First, multiple insulating layers 11 and conductor layers 12 are formed, for example, using a build-up method for manufacturing a wiring board and a method for forming the conductor layer 12 described later. Figure 3A shows a wiring board 1p in which three insulating layers 11 and two conductor layers 12 have been stacked, and the stacking of the top insulating layer 11 has been completed.

[0025] The insulating layer 11 is formed using any insulating resin material. Examples of insulating resins that can be used for the insulating layer 11 include epoxy resin, polyimide resin, BT resin, polyphenylene ether resin, and phenolic resin. The insulating layer 11 may also contain any of the following: fluororesin, liquid crystal polymer, fluoroethylene resin, polyester resin, or modified polyimide resin. Furthermore, the insulating layer 11 may contain inorganic fillers such as silica or alumina. The insulating layer 11 may also contain a core material such as glass fiber or aramid fiber, if necessary. The inclusion of a core material improves the strength of the wiring board 1. Multiple insulating layers 11 may be composed of different materials, or they may all be formed from the same material. The insulating layer 11 may also be formed by heat-pressing these resins, which have been molded into film.

[0026] Next, as shown in Figure 3B, a protective film 14 is formed on the uppermost insulating layer 11. The protective film 14 completely covers the upper surface 11a of the uppermost insulating layer 11. For example, polyethylene terephthalate (PET) film or polyethylene naphthalate (PEN) film may be used as the protective film 14. A release agent may be formed between the protective film 14 and the insulating layer 11. The protective film 14 may be formed at the same time as the insulating layer 11, or it may be present in the insulating layer 11 beforehand. Furthermore, the protective film 14 may be an insulating layer made of the same or different insulating resin material as the insulating layer 11.

[0027] Next, with the protective film 14 still attached, a through-hole 11c is formed in the uppermost insulating layer 11 by irradiating the surface of the protective film 14 with, for example, UV (ultraviolet) laser light, as shown in Figure 3C. The through-hole 11c is formed at a position corresponding to the location where the via conductor 12V is formed in Figure 1. Due to the formation of the through-hole 11c, a portion of the upper surface 12a of the first conductor layer 12F below the uppermost insulating layer 11 is exposed within the bottom surface of the through-hole 11c. As the UV laser light, for example, a laser light with a wavelength of 100 nm or more and 500 nm or less, such as a YAG laser light, can be used. The through-hole 11c may be formed such that its diameter on the upper surface 11a of the uppermost insulating layer 11 is, for example, 5 μm or more and 30 μm or less.

[0028] Next, as shown in Figure 3D, cleaning is performed to remove the processing-modified material (smear) that has formed inside the through-hole 11c during its formation. Plasma etching is preferably used for cleaning.

[0029] Next, as shown in Figure 3E, a first seed layer 121 is formed by sputtering on the inner wall surface of the through hole 11c, the upper surface 12a of the first conductor layer 12F exposed on the bottom surface of the through hole 11c, and on the protective film 14. In forming the first seed layer 121, titanium, titanium alloy, nickel, or nickel alloy that easily adheres to the inner wall surface of the through hole 11c is used as the sputtering target, and the first seed layer 121 can be formed as a sputtered film containing titanium, titanium alloy, nickel, or nickel alloy. As a result, the first seed layer 121 adheres firmly to the inner wall of the through hole 11c, and problems such as peeling of the via conductor 12V can be suppressed. In addition, as a result of the via conductor 12V being firmly fixed, the contact between the via conductor 12V and the first conductor layer 12F can be improved.

[0030] Next, as shown in Figure 3F, the protective film 14 is removed, which removes the first seed layer 121 that was formed on the protective film 14, exposing the upper surface 11a of the uppermost insulating layer 11. As a result, the first seed layer 121 remains only on the inner wall surface and bottom surface of the through hole 11c.

[0031] Next, as shown in Figure 3G, a second seed layer 122 is formed by sputtering on the upper surface 11a of the uppermost insulating layer 11 and on the first seed layer 121b inside the through hole 11c. In forming the second seed layer 122, copper or a copper alloy is used as the sputtering target, and the second seed layer 122 may be formed as a sputtered film containing copper or a copper alloy. As a result, the second seed layer 122 adheres appropriately to the upper surface 11a of the insulating layer 11 and forms a metal film layer that is easy to etch. In addition, a two-layer metal film layer consisting of the first seed layer 121 and the second seed layer 122 is formed on the inner wall and bottom surfaces of the through hole 11c. As a result, the number of sputtered film layers formed on the inner wall surface of the through hole 11c is greater than the number of sputtered film layers formed on the upper surface 11a of the insulating layer 11, thus reducing the thickness difference of the seed layer formed on the inner wall surface of the through hole 11c and the upper surface 11a of the insulating layer 11.

[0032] Next, as shown in Figure 3H, a resist layer 15 is formed on the upper surface 122a of the second seed layer 122. The resist layer 15 is formed by bonding a dry film resist containing, for example, a photosensitive epoxy resin, polyhydroxy ether resin, phenol resin, or polyimide resin to form a resin layer, followed by exposure and development using a mask with an appropriate aperture pattern. The resist layer 15 has an aperture 15b corresponding to the conductive pad 12P (see Figure 1) formed on the component mounting surface U.

[0033] Next, as shown in Figure 3I, a plating layer 124 is formed within the opening 15b of the resist layer 15 by electroplating with the second seed layer 122 as the power supply layer. The inside of the through hole 11c is filled with the plating layer 124, forming a via conductor 12V. The plating layer 124 is formed on the insulating layer 11 to form the second conductor layer 12S. The plating layer 124, like the second seed layer 122, can be formed using a conductive material containing copper or the like. That is, both the second seed layer 122 and the plating layer 124 constituting the second conductor layer 12S are formed from a conductive material containing copper or the like. Furthermore, as described above, a two-layer metal film layer consisting of the first seed layer 121 and the second seed layer 122 is formed on the inner wall and bottom surfaces of the through hole 11c. As a result, the conductor resistance of the power supply layer during electroplating is reduced and the current increases, which can improve the efficiency of the formation of the plating layer 124 inside the through hole 11c.

[0034] Next, as shown in Figure 3J, the resist layer 15 is removed using a stripping solution. Removal of the resist layer 15 exposes the portion 122d of the second seed layer 122 that is not covered by the plating layer 124.

[0035] Next, as shown in Figure 3K, the exposed portion 122d of the second seed layer 122 is removed by etching. As a result, a second conductor layer 12S is formed on the upper surface 11a of the uppermost insulating layer 11, having a two-layer structure of the second seed layer 122 and the plating layer 124, and containing individually separated conductor patterns. As described above, since a conductive material such as copper can be selected for the second seed layer 122, etching is easier compared to the first seed layer 121 which is made of titanium or nickel, and less residue of the second seed layer 122 remains after etching, thus suppressing the occurrence of short-circuit defects and other problems.

[0036] Next, as shown in Figure 3L, a solder resist layer 13 is formed on the surface of the uppermost insulating layer 11 and the second conductor layer 12S using a photosensitive epoxy resin or polyimide resin, and an opening 13c defining the conductor pad 12P is formed by photolithography.

[0037] As described above, in the manufacturing method of the wiring board of this embodiment, a conductive material such as titanium or nickel that adheres well to the inner wall surface of the through hole 11c may be selected as the first seed layer 121. As a result, the via conductor 12V adheres firmly to the inner wall surface of the through hole 11c, suppressing defects such as peeling, and the via conductor 12V is firmly fixed, thereby improving contact with the first conductor layer 12F. This improves the electrical coupling between conductor layers via the via conductor, even when the via conductor diameter decreases due to an increase in the mounting density of the wiring board 1. Furthermore, a conductive material such as copper that is easily etched may be selected as the second seed layer 122. This reduces the likelihood of etching residue remaining during conductor pattern formation, thus suppressing short-circuit defects. In addition, the formation efficiency of the plating layer 124 using the second seed layer 122 as a power supply layer can be improved.

[0038] The wiring board of the embodiment is not limited to the structure shown in Figures 1 and 2, and the number, size, and material of its constituent members can be changed as appropriate. For example, the first seed layer 121 may be a conductive material other than titanium or nickel, and the second seed layer 122 may be a conductive material other than copper. The first seed layer 121 and the second seed layer 122 may be electroless plating layers. In addition, depending on the required characteristics and functions, some members of the wiring board may be omitted, or other members may be added.

[0039] The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to Figures 3A to 3L, and the conditions and sequence may be changed as appropriate. For example, the first seed layer 121 and the second seed layer 122 may be formed by electroless plating. The first seed layer 121 may be selectively formed only on the inner wall surface of the through hole 11c. Furthermore, depending on the structure of the wiring board to be manufactured, some steps may be omitted or other steps may be added in the method for manufacturing the wiring board. [Explanation of symbols]

[0040] 1 Wiring board 11 Insulating layer 11c through hole 12 Conductor Layers 12F First Conductor Layer 12S Second Conductor Layer 12P Conductor Pad 12V via conductor 121 First Seed Tier 122 Second Seed Layer 124 Plating layer 13 Solder Resist Layer 14 Protective film 15 Resist Layers

Claims

1. The first conductor layer, An insulating layer covering the above first conductor layer, A second conductive layer formed on the surface of the insulating layer, A via conductor formed on the inner wall surface of a through-hole penetrating the insulating layer, connecting the first conductor layer and the second conductor layer, A wiring board comprising, The via conductor includes at least a first seed layer covering the inner wall surface of the through hole, and a plating layer. The second conductor layer is formed by a second seed layer covering the surface of the insulating layer and the plating layer. The first seed layer and the plating layer are made of different materials. The second seed layer and the plating layer are made of the same material.

2. A wiring board according to claim 1, The second seed layer covers the first seed layer.

3. A wiring board according to claim 2, The second seed layer is integrally formed across the inner wall surface of the through hole and the surface of the insulating layer.

4. A wiring board according to claim 3, The number of stacked seed layers, including the first seed layer and the second seed layer, formed on the inner wall surface of the through hole is greater than the number of stacked seed layers, including the second seed layer, formed on the surface of the insulating layer.

5. A wiring board according to claim 1, The first seed layer contains titanium, a titanium alloy, nickel, or a nickel alloy.

6. A wiring board according to claim 1, The second seed layer and the plating layer contain copper or a copper alloy.

7. A wiring board according to claim 1, The first seed layer and / or the second seed layer are sputtering film layers.

8. A wiring board according to claim 1, The diameter of the through-hole is 5 μm or more and 30 μm or less.

9. Forming an insulating layer on the first conductor layer, The insulating layer is provided with through holes that expose a portion of the upper surface of the first conductor layer, A first seed layer is formed on the inner wall surface of the through hole and on the upper surface of the first conductor layer that is exposed within the through hole. A second seed layer is formed on the surface of the insulating layer, A method for manufacturing a wiring board, comprising forming a plating layer on the second seed layer using a material different from the first seed layer but of the same type as the second seed layer, thereby forming a via conductor and a second conductor layer.

10. A method for manufacturing a wiring board according to claim 9, The first seed layer and / or the second seed layer are formed by sputtering.

11. A method for manufacturing a wiring board according to claim 9, The second seed layer is formed integrally across the surface of the first seed layer and the surface of the insulating layer so as to cover the first seed layer.

12. A method for manufacturing a wiring board according to claim 9, Forming the via conductor and the second conductor layer is A resist pattern having an opening is formed on the second seed layer, The plating layer is formed on the second seed layer exposed within the opening of the resist pattern, Removing the resist pattern to expose the second seed layer not covered by the plating layer, This includes removing the exposed second seed layer.

13. A method for manufacturing a wiring board according to claim 9, Forming the first seed layer means A metal film layer is formed on the inner wall surface of the through-hole, the upper surface of the first conductor layer exposed within the through-hole, and above the insulating layer. This includes removing the metal film layer formed above the insulating layer.

14. A method for manufacturing a wiring board according to claim 13, Furthermore, the process includes forming a protective film on the surface of the insulating layer. Forming the first seed layer means The metal film layer is formed on the surface of the protective film, This includes removing the protective film together with the metal film layer on the protective film.

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