Semiconductor memory device and method for manufacturing the same

Abstract

The present invention provides a semiconductor memory device and a method for manufacturing the same, which can be configured more appropriately. [Solution] The semiconductor memory device according to this embodiment comprises a laminate and a contact plug. The laminate has a plurality of conductive layers and insulating layers stacked alternately in a first direction, and includes a stepped structure having a stepped shape at its end. The contact plug is electrically connected to the conductive layer at the stepped surface of the stepped structure and extends along the first direction, penetrating the laminate from the stepped surface and passing through the laminate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device and a method for manufacturing the same that can obtain a more appropriate configuration.

Means for Solving the Problems

[0005] The semiconductor memory device according to the present embodiment includes a laminate and a contact plug. The laminate has a plurality of conductive layers and insulating layers alternately laminated in a first direction, and includes a stepped structure portion having a stepped shape at an end portion. The contact plug is electrically connected to the conductive layer on the step surface of the stepped structure portion and extends through the laminate from the step surface along the first direction so as to penetrate the laminate.

Brief Description of the Drawings

[0006] [Figure 1] A perspective view illustrating a semiconductor memory device according to the first embodiment. [Figure 2] A plan view showing the laminate. [Figure 3] A cross-sectional view showing an example of a three-dimensional structure memory cell. [Figure 4]A cross-sectional view showing an example of a three-dimensional memory cell structure. [Figure 5] A plan view showing an example of a semiconductor memory device according to the first embodiment. [Figure 6] A schematic plan view showing the layout of the connection area and memory cell area. [Figure 7A] A perspective view showing a schematic of the connection area of ​​block BLK. [Figure 7B] A perspective view showing a schematic of the connection area of ​​block BLK. [Figure 8A] A plan view showing several conductive layers in the connection area in more detail. [Figure 8B] A plan view showing several conductive layers in the connection area in more detail. [Figure 9] This is a cross-sectional view showing an example of the structure of a semiconductor memory device according to the first embodiment. [Figure 10] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. [Figure 11] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. [Figure 12A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 12B] Figure 12A is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12C] Figure 12B is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12D] Figure 12C is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12E] Figure 12D is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12F] Figure 12E is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12G] Figure 12F is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12H] Figure 12G is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12I]It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12H. [Figure 12J] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12I. [Figure 12K] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12J. [Figure 12L] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12K. [Figure 12M] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12L. [Figure 12N] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12M. [Figure 13] It is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first comparative example. [Figure 14A] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first modification of the first embodiment. [Figure 14B] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12A. [Figure 14C] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12B. [Figure 14D] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12C. [Figure 14E] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12D. [Figure 14F] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12E. [Figure 14G] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12F. [Figure 14H] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12G. [Figure 14I] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12H. [Figure 14J] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 12I. [Figure 15] This figure shows an example of the configuration of a semiconductor memory device according to the second embodiment. [Figure 16] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second embodiment. [Figure 17A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 17B] This is a cross-sectional view showing an example of a semiconductor memory device manufacturing method, following Figure 17A. [Figure 17C] Figure 17B is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17D] Figure 17C is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17E] Figure 17D is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17F] Figure 17E is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17G] Figure 17F is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17H] Figure 17G is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17I] Figure 17H ​​is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17J] Figure 17I is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17K] Figure 17J is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17L] Figure 17K is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17M] Figure 17L is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17N] Figure 17M is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17O] Figure 17N is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17P] Figure 17O is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17Q] Figure 17P is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17R] Figure 17Q is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17S] Figure 17R is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 18] This is a plan view showing an example of an embedding pattern for an insulating member according to the second embodiment. [Figure 19] This figure shows an example of the configuration of a semiconductor memory device according to the second embodiment and the second comparative example. [Figure 20] This figure shows an example of the configuration of a semiconductor memory device according to the first modification of the second embodiment. [Figure 21] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a second modification of the second embodiment. [Figure 22] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a third modification of the second embodiment. [Figure 23] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a third modification of the second embodiment. [Figure 24] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a fourth modification of the second embodiment. [Figure 25] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a fifth modification of the second embodiment. [Figure 26] This is a plan view showing an example of the configuration of an insulating member according to a fifth modification of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) [First example configuration of a semiconductor memory device] Figure 1 is a perspective view illustrating a semiconductor memory device 100 according to the first embodiment. Figure 2 is a plan view showing a stacked body 2. In this specification, the stacking direction of the stacked body 2 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the Y-axis direction. The directions perpendicular to both the Z and Y-axis directions are defined as the X-axis direction. Figures 3 and 4 are cross-sectional views showing an example of a three-dimensional memory cell structure. Figure 5 is a plan view showing an example of a semiconductor memory device 100 according to the first embodiment. As shown in Figures 1 to 5, the semiconductor memory device 100 according to the first embodiment is a non-volatile memory having a three-dimensional memory cell array.

[0009] The semiconductor memory device 100 includes a substrate 1, a laminate 2, a plate-shaped portion 3, a plurality of columnar portions CL, and a plurality of insulating columns CLHR.

[0010] The substrate 1 includes a semiconductor wafer (substrate) 10, an insulating film 11, a conductive film 12, and a semiconductor portion 13. The insulating film 11 is provided on the semiconductor wafer 10. The conductive film 12 is provided on the insulating film 11. The semiconductor portion 13 is provided on the conductive film 12. The semiconductor wafer 10 is, for example, a silicon wafer. The conductivity type of the semiconductor wafer 10 is, for example, p-type. The surface region of the semiconductor wafer 10 is provided with, for example, an element isolation region 10i. The element isolation region 10i is, for example, an insulating region including a silicon oxide film, and defines an active area AA on the surface region of the semiconductor wafer 10. The source and drain regions of a transistor Tr are provided in the active area AA. The transistor Tr constitutes a CMOS (Complementary Metal Oxide Semiconductor) circuit as a control circuit for non-volatile memory. The insulating film 11 includes, for example, a silicon oxide film and insulates the transistor Tr. Wiring 11a is provided within the insulating film 11. Wiring 11a is electrically connected to the transistor Tr. The conductive film 12 contains a conductive metal, for example, tungsten (W). The semiconductor portion 13 contains, for example, n-type silicon. A portion of the semiconductor portion 13 may contain undoped silicon.

[0011] The laminate 2 is located above the semiconductor portion 13 in the Z-axis direction. The laminate 2 is constructed by alternately stacking a plurality of conductive layers 21 as first conductive layers and a plurality of insulating layers 22 as first insulating layers in the Z-axis direction. The plurality of conductive layers 21 are stacked with an insulating layer 22 in between, leaving a gap between them. The conductive layers 21 include a conductive metal, for example, tungsten. The insulating layers 22 include, for example, silicon oxide. The insulating layers 22 insulate the conductive layers 21 from each other. The number of stacks of each conductive layer 21 and insulating layer 22 is arbitrary. The insulating layers 22 may be, for example, gaps. An insulating film 2g is provided between the laminate 2 and the semiconductor portion 13. The insulating film 2g includes, for example, a silicon oxide film. The insulating film 2g may include a high dielectric material with a higher dielectric constant than silicon oxide. The high dielectric material may be an oxide such as a hafnium oxide film.

[0012] The conductive layer 21 includes at least one source-side selection gate SGS, a plurality of word lines WL, and at least one drain-side selection gate SGD. The source-side selection gate SGS is the gate electrode of the source-side selection transistor STS. The word lines WL are the gate electrodes of the memory cell MC. The drain-side selection gate SGD is the gate electrode of the drain-side selection transistor STD. The source-side selection gate SGS is located in the lower region of the stack 2. The drain-side selection gate SGD is located in the upper region of the stack 2. The lower region refers to the region of the stack 2 closer to the substrate 1, and the upper region refers to the region of the stack 2 further from the substrate 1. The word lines WL are located between the source-side selection gate SGS and the drain-side selection gate SGD.

[0013] Of the multiple insulating layers 22, the thickness in the Z-axis direction of the insulating layer 22 that insulates the source-side selection gate SGS and the word line WL may be thicker in the Z-axis direction than, for example, the thickness in the Z-axis direction of the insulating layer 22 that insulates the word line WL from other word line WL. Furthermore, a cover insulating film may be provided on the uppermost insulating layer 22 that is furthest from the substrate 1. The cover insulating film may contain, for example, silicon oxide.

[0014] The semiconductor memory device 100 has a plurality of memory cells MC connected in series between a source-side selection transistor STS and a drain-side selection transistor STD. The structure in which the source-side selection transistor STS, memory cells MC, and drain-side selection transistor STD are connected in series is called a “memory string” or “NAND string”. The memory string is connected to a bit line BL via, for example, a contact Cb. The bit line BL is located above the stack 2 and extends in the Y-axis direction.

[0015] The laminate 2 is provided with multiple deep slits ST and multiple shallow slits SHE. As shown in Figure 2, the slits ST extend in the X-axis direction in the planar layout. In the cross-section in the Z direction (lamination direction), the slits ST penetrate the laminate 2 from the upper end to the base portion 1 and are provided within the laminate 2. The plate-like portion 3 in Figure 2 is provided within the slits ST. The plate-like portion 3 uses an insulating film, such as a silicon oxide film. Alternatively, the plate-like portion 3 may be made of a conductive metal such as a conductor (e.g., tungsten, copper) that is electrically connected to the semiconductor portion 13, and may be electrically insulated from the laminate 2 by an insulating film. The slits SHE extend in the X-axis direction substantially parallel to the slits ST in the planar layout. In the cross-section in the Z direction, the slits SHE are provided from the upper end to partway through the laminate 2. Insulators 4 are provided within the slits SHE. Insulators 4 use insulating films, such as silicon oxide films.

[0016] As shown in Figure 2, the stacked structure 2 includes a stepped portion 2s and a memory cell array MCA. The stepped portion 2s is provided at the edge of the stacked structure 2. The memory cell array MCA is sandwiched or surrounded by the stepped portion 2s. The slit ST is provided from the stepped portion 2s at one end of the stacked structure 2, through the memory cell array MCA, to the stepped portion 2s at the other end of the stacked structure 2. The slit SHE is provided at least in the memory cell array MCA.

[0017] The portion of the laminate 2 sandwiched between the two slits ST (plate-shaped portions 3) is called a block BLK. A block constitutes, for example, the smallest unit for data erasure. Slits SHE (insulators 4) are provided within the block. The laminate 2 between slits ST and Slits SHE is called a finger. A drain-side selection gate SGD is separated for each finger. Therefore, during data writing and reading, one finger within the block can be selected by the drain-side selection gate SGD.

[0018] The memory cell array MCA includes a cell region (Cell) and other regions, as shown in Figure 5. The cell region (Cell) has multiple columnar sections (CL) within the memory holes (MH). The regions other than the cell region (Cell) are provided with a tap region (Tap), a stepped region (SSA), and a bridge region (BRA). The tap region (Tap) is located in a block (BLK) adjacent to the stepped region (SSA) and bridge region (BRA) in the Y direction, separated by a slit (ST). The tap region (Tap) may also be located between cell regions in the X direction, as shown in Figure 6. The stepped region (SSA) and bridge region (BRA) may also be located between cell regions in the X direction. The stepped region (SSA) is a region where multiple contact plugs (CC) are provided. The bridge region (BRA), as shown in Figure 6, is provided to electrically connect each wiring layer of the word lines (WL) of a block (BLK) adjacent to the stepped region (SSA) in the X direction. The tap region (Tap) is a region where a contact plug (C4) is provided. Each of the contact plugs (CC) and (C4) extends, for example, in the Z-axis direction. Each contact plug CC is electrically connected to, for example, the conductive layer 21. Contact plug C4 is electrically connected to, for example, the wiring 11a for power supply to the transistor Tr. Low-resistance metals such as copper and tungsten are used for contact plugs CC and C4.

[0019] An insulating film (not shown) is provided around each of the contact plugs CC and C4. This electrically insulates the contact plugs CC and C4 from the laminate 2. As a result, the contact plugs CC and C4 remain insulated from the laminate 2, while electrically connecting wiring above the laminate 2 to wiring below the laminate 2. For example, an insulating film such as a silicon oxide film can be used as the insulating film.

[0020] Each of the multiple columnar portions CL is located within a memory hole MH provided in the laminate 2. The memory hole MH extends from the upper end of the laminate 2 through the laminate 2 along the stacking direction (Z-axis direction) of the laminate 2, and extends into the laminate 2 and into the semiconductor portion 13. As shown in Figures 3 and 4, each of the multiple columnar portions CL includes a semiconductor body 210 as a semiconductor column, a memory film 220, and a core layer 230. The semiconductor body 210 extends in its stacking direction (Z-direction) within the laminate 2. It is electrically connected to the semiconductor portion 13. The memory film 220 has a charge trapping portion between the semiconductor body 210 and the conductive layer 21. The multiple columnar portions CL, one selected from each finger, are commonly connected to a single bit line BL via a contact Cb. Each of the columnar portions CL is located, for example, in the cell region (Cell) shown in Figure 5.

[0021] As shown in Figures 3 and 4, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A block insulating film 21a, which constitutes part of the memory film 220, may be provided between the conductive layer 21 and the insulating layer 22. The block insulating film 21a is, for example, a silicon oxide film or a metal oxide film. One example of a metal oxide is aluminum oxide. A barrier film 21b may be provided between the conductive layer 21 and the insulating layer 22, and between the conductive layer 21 and the memory film 220. For example, if the conductive layer 21 is tungsten, the barrier film 21b may be a laminated structure film of titanium nitride and titanium. The block insulating film 21a suppresses back tunneling of charge from the conductive layer 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the conductive layer 21 and the block insulating film 21a.

[0022] The semiconductor body 210 has a shape, for example, that is cylindrical. The semiconductor body 210 contains, for example, silicon. The silicon is, for example, polysilicon obtained by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor STD, the memory cell MC, and the source-side selection transistor STS, respectively.

[0023] The memory film 220, except for the block insulating film 21a, is provided between the inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is, for example, cylindrical. Multiple memory cells MC have a storage area between the semiconductor body 210 and a conductive layer 21 which becomes a word line WL, and are stacked in the Z-axis direction. The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. Each of the semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 extends in the Z-axis direction.

[0024] The cover insulating film 221 is provided between the insulating layer 22 and the charge trapping film 222. For example, silicon oxide is used for the cover insulating film 221. The cover insulating film 221 is provided to protect the charge trapping film 222 from etching when the sacrificial film provided between the insulating layers 22 is replaced with the conductive layer 21 during the manufacturing process. The cover insulating film 221 may be removed from between the conductive layer 21 and the memory film 220 during the replacement process. In this case, as shown in Figures 3 and 4, for example, a block insulating film 21a is provided between the conductive layer 21 and the charge trapping film 222. Also, if the replacement process is not used to form the conductive layer 21, the cover insulating film 221 may not be provided.

[0025] The charge trapping film 222 is provided between the block insulating film 21a and the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride and has trapping sites that trap charges within the film. Of the charge trapping film 222, the portion sandwiched between the conductive layer 21, which becomes the word line WL, and the semiconductor body 210 constitutes the memory area of ​​the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trapping section, or the amount of charge trapped in the charge trapping section. As a result, the memory cell MC can retain information.

[0026] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. For example, silicon oxide, or silicon oxide and silicon nitride can be used for the tunnel insulating film 223. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping portion (writing operation), and when holes are injected from the semiconductor body 210 to the charge trapping portion (erasing operation), the electrons and holes pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0027] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. An insulating film, such as a silicon oxide film, is used for the core layer 230.

[0028] Each of the multiple insulating columns CLHR shown in Figure 5 is provided within a hole HR provided within the laminate 2. The hole HR extends from the upper end of the laminate 2 along the Z-axis direction, penetrating the laminate 2 and extending into the laminate 2 and the semiconductor portion 13. The insulating columns CLHR use an insulating material such as a silicon oxide film. Furthermore, each insulating column CLHR may have the same structure as the columnar portion CL. Each insulating column CLHR is provided, for example, in the tap region, the step region SSA, and the bridge region BRA. The insulating columns CLHR function as support members for holding the gaps formed in the step region and the tap region when the sacrificial film (not shown) is replaced with the conductive layer 21 (replacement process). The holes HR of the insulating columns CLHR have a larger diameter (width in the X or Y direction) than the columnar portion CL.

[0029] As shown in Figure 1, the semiconductor memory device 100 further includes a semiconductor portion 14. The semiconductor portion 14 is located between the laminate 2 and the semiconductor portion 13. The semiconductor portion 14 is provided between the insulating layer 22 closest to the semiconductor portion 13 and the insulating film 2g. The conductivity type of the semiconductor portion 14 is, for example, n-type. The semiconductor portion 14 functions, for example, as a source-side selection gate SGS.

[0030] Figure 6 is a schematic plan view showing the layout of the connection region 101 and the memory cell region 100a. The memory cell region 100a includes a first memory cell region 100a_1 and a second memory cell region 100a_2 that are adjacent to each other. The first memory cell region 100a_1 and the second memory cell region 100a_2 each contain multiple blocks BLK. In the Y direction, the multiple blocks BLK are separated by slits ST that extend in the X direction.

[0031] The first memory cell region 100a_1 and the second memory cell region 100a_2 both have the above-mentioned plurality of columnar portions CL (memory holes MH) and have a plurality of memory cells arranged in three dimensions. Memory cells are formed at the intersections of a plurality of word lines WL and columnar portions CL.

[0032] For convenience, the block BLK belonging to the first memory cell region 100a_1 will be denoted as block BLK_1. Similarly, the block BLK belonging to the second memory cell region 100a_2 will be denoted as block BLK_2.

[0033] The connection region 101 is provided between the first memory cell region 100a_1 and the second memory cell region 100a_2 in the X direction intersecting the Z direction, and each block BLK is provided with a tap region, a step region SSA, and a bridge region BRA. The step region SSA and bridge region BRA are hereinafter also referred to as the step region SSA, etc.

[0034] As described above, the tap region (Tap) and the stair region (SSA), etc., are adjacent in the Y direction via the slit (ST). As shown in Figure 6, the tap region (Tap) and the stair region (SSA), etc., are arranged alternately in the Y direction. Although not shown, the tap region (Tap) and the stair region (SSA), etc., are also arranged alternately in the X direction. That is, the tap region (Tap) and the stair region (SSA), etc., are arranged alternately in the Y direction with the slit (ST) in between, and alternately in the X direction with the memory region (Cell, block BLK) in between.

[0035] In the stepped region SSA, the ends of the selected gate line (source-side selected gate) SGS and the multiple word lines WL are stepped in the X direction sequentially from the lower layer, forming a stepped structure. In other words, in the stepped region SSA, each of the selected gate line SGS and the multiple word lines WL has a terrace portion (also called a staircase, stair section, or lead-out section) at its end that does not overlap with the lower wiring layer (conductive layer). A contact plug CC, as shown in Figure 5, is formed on each terrace portion. Voltage can be applied separately to the selected gate line SGS and the multiple word lines WL via the contact plug CC. Thus, the stepped region SSA is provided as a terrace region for connecting multiple contacts to each of the multiple conductive layers connected to the selected gate line SGS and the multiple word lines WL.

[0036] Furthermore, contact plug CC is electrically connected to contact plug C4 in the tap region of Figure 5 via upper layer wiring (not shown), and is electrically connected to a row decoder located beneath the memory cell array via contact plug C4. This allows the row decoder to control the voltage of each conductive layer 21 (word line WL) via contact plug CC. The diameters of contact plugs CC and C4 are larger than the diameter of the insulator column CLHR.

[0037] In the bridge region BRA, multiple third conductive layers corresponding to the selection gate line SGS and multiple word lines WL are stacked in the Z direction, spaced apart from each other. The third conductive layers electrically connect the conductive layer 21 (selection gate line SGS and multiple word lines WL) of the first memory cell region 100a_1 and the conductive layer 21 (selection gate line SGS and multiple word lines WL) of the second memory cell region 100a_2, respectively. Thus, the first and second memory cell regions 100a_1 and 100a_2 can function as a single memory cell array MCA.

[0038] Thus, by positioning the connection region 101 in the middle of the memory cell array MCA, the contact plug CC is positioned in the middle of the word line WL wiring, shortening the distance from the contact plug CCa to the end of the word line WL. This allows the semiconductor memory device 100 to quickly supply power to the end of the word line WL via the contact plug CC, facilitating voltage control of the word line WL. Furthermore, since memory cell regions 100a_1 and 100a_2 can be placed on both sides of a single connection region 101, the size (storage capacity) of the memory cell array MCA can be increased while maintaining the operating speed.

[0039] The bridge region BRA has the same laminate structure as the first and second memory cell regions 100a_1 and 100a_2. Therefore, the laminate of the bridge region BRA is constructed by alternately stacking a plurality of conductive layers 21 and a plurality of insulating layers 22 in the Z-axis direction. That is, the plurality of conductive layers 21, which serve as the plurality of third conductive layers, are stacked with an insulating layer 22 in between, spaced apart from each other. As described above, the insulating layer 22 may be an air gap.

[0040] Figures 7A and 7B are perspective views showing a schematic of a connection region 101 of a certain block BLK. The stepped region SSA of the connection region 101 is provided in a stepped manner to connect multiple contact plugs CC to each of the multiple conductive layers 21 (word lines WL). The bridge region BRA electrically connects the multiple conductive layers 21 between the conductive layers 21 (word lines WL) of the first and second memory cell regions 100a_1 and 100a_2.

[0041] The bridge region BRA is provided in the connection region 101 adjacent to the step region SSA in the Y direction (approximately perpendicular to the extension direction of the slit ST), and is not carved in a step shape. Therefore, the bridge region BRA has the same number of conductive layers 21 and insulating layers 22 as the stacked bodies 2 of the first and second memory cell regions 100a_1 and 100a_2.

[0042] Figures 8A and 8B are plan views showing some of the conductive layers 21 of the connection region 101 in more detail. Figure 8A shows the conductive layers 21 stacked, and Figure 8B shows each of the conductive layers 21 separately. Figures 8A and 8B show five conductive layers 21. Of course, there may be four or fewer conductive layers 21, or six or more. Note that Figures 8A and 8B show one block BLK section, and the columnar section CL (memory hole MH), insulator column CLHR, and slit SHE shown in Figure 5 are omitted.

[0043] As shown in Figure 8A, the stepped region SSA of the connection region 101 is formed in a stepped shape so that the surface (tread) of each conductive layer 21 is visible from the Z direction. Each surface (tread) of the conductive layer 21 has a width (area) that allows the contact plug CC to be connected from the Z direction. In Figure 8A, the stepped sections of the stepped region SSA are provided facing each other on both sides in the X direction of the connection region 101. As shown in Figures 8A and 8B, one contact plug CC is provided on each conductive layer 21 of the stepped region SSA and is connected to the tread of the conductive layer 21. For example, in the example shown in Figure 8, the contact plug CC is alternately connected to the left and right stepped sections of the stepped region SSA. More specifically, in the uppermost conductive layer 21, the contact plug CC is connected to the tread of the left stepped section of the stepped region SSA. In the second conductive layer 21, the contact plug CC is connected to the tread of the right stepped section of the stepped region SSA. In the third conductive layer 21, the contact plug CC is connected to the tread of the left stepped section of the stepped region SSA. In the fourth conductive layer 21, the contact plug CC is connected to the tread of the right-hand stair section of the stair region SSA. In the fifth (bottommost) conductive layer 21, the contact plug CC is connected to the tread of the left-hand stair section of the stair region SSA.

[0044] Furthermore, the staircase area SSA may be provided on only one side of the connection area 101 in the X direction. In this case, the contact plug CC is connected to the tread of the staircase provided on one side of the connection area 101.

[0045] Since one contact plug CC is provided on each conductive layer 21, the conductive layer 21 of the memory cell region on the side to which the contact plug CC is not connected is electrically connected to the contact plug CC via the bridge region BRA. For example, the uppermost conductive layer 21 of the right-hand second memory cell region 100a_2 does not have a contact plug CC. Therefore, the uppermost conductive layer 21 of the right-hand second memory cell region 100a_2 is electrically connected to the contact plug CC provided on the uppermost conductive layer 21 of the left-hand second memory cell region 100a_2 via the uppermost conductive layer 21 of the bridge region BRA. Also, the second conductive layer 21 of the left-hand second memory cell region 100a_2 does not have a contact plug CC. Therefore, the second conductive layer 21 of the left-hand second memory cell region 100a_2 is electrically connected to the contact plug CC provided on the second conductive layer 21 of the right-hand second memory cell region 100a_2 via the second conductive layer 21 of the bridge region BRA. In this way, one of the memory cell regions 100a_1 and 100a_2 located on either side of the connection region 101 is electrically connected to the contact plug CC provided on the other side via the bridge region BRA.

[0046] [Second example configuration of semiconductor memory device] Figure 9 is a cross-sectional view showing an example of the structure of a semiconductor memory device according to the first embodiment. The semiconductor memory device shown in Figure 9 is a three-dimensional memory in which an array chip C1 and a circuit chip C2 are bonded together.

[0047] The array chip C1 comprises a memory cell array 51 containing multiple memory cells arranged in three dimensions, an insulating film 52 on the memory cell array 51, and an interlayer insulating film 53 below the memory cell array 51. The insulating film 52 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 53 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films.

[0048] The circuit chip C2 is located beneath the array chip C1. The symbol S indicates the bonding surface between the array chip C1 and the circuit chip C2. The circuit chip C2 comprises an interlayer insulating film 54 and a substrate 55 beneath the interlayer insulating film 54. The interlayer insulating film 54 is, for example, a silicon oxide film, or a laminated film including a silicon oxide film and other insulating films. The substrate 55 is an example of a first substrate, and is, for example, a semiconductor substrate such as a silicon substrate. Figure 9 shows the X and Y directions, which are parallel to and perpendicular to the surface (i.e., the top surface) of the substrate 55, and the Z direction, which is perpendicular to the surface of the substrate 55.

[0049] The array chip C1 comprises multiple word lines WL and source lines SL as multiple electrode layers within the memory cell array 51. Figure 9 shows the stepped structure 61 of the memory cell array 51. Each word line WL is electrically connected to the word wiring layer 63 via a contact plug 62. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 64 and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer and a second layer SL2 which is a metal layer. The symbol V indicates a via plug located below the bit line BL.

[0050] The circuit chip C2 comprises a plurality of transistors 31. Each transistor 31 comprises a gate electrode 32 provided on the substrate 55 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 55. The circuit chip C2 also comprises a plurality of contact plugs 33 provided on the source diffusion layer or drain diffusion layer of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and containing a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and containing a plurality of wires.

[0051] The circuit chip C2 further comprises a wiring layer 36 provided on the wiring layer 35 and containing multiple wirings, multiple via plugs 37 provided on the wiring layer 36, and multiple metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip C2 functions as a control circuit (logic circuit) that controls the operation of the array chip C1. This control circuit is composed of transistors 31 and the like and is electrically connected to the metal pads 38.

[0052] The array chip C1 comprises a plurality of metal pads 41 provided on a metal pad 38, and a plurality of via plugs 42 provided on the metal pads 41. The array chip C1 also comprises a wiring layer 43 provided on these via plugs 42 and containing a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and containing a plurality of wirings. The metal pads 41 are, for example, a Cu layer or an Al layer. The via plugs V described above are included in the wiring layer 43.

[0053] The array chip C1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on these via plugs 45 and on the insulating film 52, and a passivation film 47 provided on the metal pads 46 and on the insulating film 52. The metal pads 46 are, for example, Cu layers or Al layers and function as external connection pads (bonding pads) for the semiconductor memory device shown in Figure 9. The passivation film 47 is, for example, an insulating film such as a silicon oxide film and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or other devices via this opening P using bonding wires, solder balls, metal bumps, etc.

[0054] [Contact plug configuration] Next, the configuration of the contact plug 62 will be described. Below, the staircase structure of the second configuration example will be described, as well as the first configuration example. However, the configuration of the contact plug 62 and its surroundings described below can also be applied to the staircase structure of the first configuration example.

[0055] Figure 10 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment.

[0056] The laminate 2 has conductive layers 21 and insulating layers 22 that are alternately stacked in a first direction (Z direction). The laminate 2 includes a memory cell array 51 and a stepped structure 61 having a stepped shape at its end.

[0057] The contact plug 62 is electrically connected to the conductive layer 21 on the step surface of the staircase structure 61. The contact plug 62 extends along the Z direction, penetrating the laminate 2 from the step surface and extending through the laminate 2. Therefore, the contact plug 62 is drawn out from the laminate 2 to the upper (back) side of the array chip C1, that is, the side where the widest conductive layer 21 is provided.

[0058] The wiring 71 is provided on the upper surface of the array chip C1. The wiring 71 is provided so as to extend in a direction substantially perpendicular to the Z direction, on the opposite side of the laminate 2 from the surface on which the step surface is provided. The wiring 71 electrically connects the contact plug 62 to the contact plug 72.

[0059] The contact plug 72 electrically connects the wiring 71 to the transistor 31 provided on the circuit chip C2.

[0060] Therefore, the switch circuit (transistor 31) is electrically connected to the conductive layer 21 via contact plugs 62, 72 and wiring 71, etc.

[0061] Figure 11 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. Figure 11 shows an enlarged view of the dashed frame in Figure 10.

[0062] The contact plug 62 is connected to the conductive layer 21 at its end.

[0063] The insulating film 73 is provided around the contact plug 62. As a result, the contact plug 62 is electrically insulated from the conductive layer 21 through which the contact plug 62 passes.

[0064] Next, we will explain the manufacturing method for semiconductor memory devices.

[0065] Figures 12A to 12N are cross-sectional views showing an example of a semiconductor memory device manufacturing method according to the first embodiment.

[0066] First, as shown in Figure 12A, a hole HR and a contact hole CH are formed that penetrate the laminate 2a, in which the sacrificial layer 21c and the insulating layer 22 are alternately stacked in the first direction, in the first direction (Z direction).

[0067] Next, as shown in Figure 12B, insulating members are formed in the hole HR and the contact hole CH to form an insulating column CLHR in the hole HR, and an insulating film 73 (spacer) is formed on the inner surface of the contact hole CH.

[0068] Next, as shown in Figure 12C, the sacrificial member 83 is embedded in the contact hole CH.

[0069] Next, as shown in Figure 12D, a staircase structure 61 is formed at the end of the laminate 2.

[0070] Next, as shown in Figure 12E, an insulating film 84 is formed on the laminate 2a, and an insulating film 85 is formed on the insulating film 84. The insulating film 84 functions as a stopper film for the contact plug 62. The insulating film 84 contains, for example, SiO2. The insulating film 85 contains, for example, SiN.

[0071] Next, as shown in Figure 12F, the insulating films 84 and 85 are processed so that they remain on the sacrificial member 83.

[0072] Next, as shown in Figure 12G, an interlayer insulating film 53 is formed on the laminate 2a, and the upper surface of the interlayer insulating film 53 is flattened.

[0073] Next, as shown in Figure 12H, the sacrificial layer 21c is replaced with the conductive layer 21.

[0074] Next, the substrate 81 is peeled off as shown in Figure 12I. Note that Figure 12I is inverted vertically from Figure 12H. The substrate 81 is, for example, a silicon substrate.

[0075] Next, as shown in Figure 12J, the sacrificial member 83 is removed.

[0076] Next, as shown in Figure 12K, a portion of the insulating film 84 is removed until the insulating film 85 is exposed.

[0077] Next, the insulating film 85 is removed as shown in Figure 12L.

[0078] Next, as shown in Figure 12M, the insulating film 84 is removed. This exposes the conductive layer 21 in the space where the insulating film 84 was removed. A portion of the insulating film 73 is also removed.

[0079] Next, as shown in Figure 12N, a conductive member is embedded in the contact hole CH (the space where the sacrificial member 83 and insulating films 84 and 85 have been removed). The conductive member is, for example, tungsten (W). This forms a contact plug 62 that connects to the conductive layer 21 exposed on the step surface. In the example shown in Figure 12N, a void is formed, but it is not necessary for a void to be formed.

[0080] Subsequently, the wiring 71 and other components are formed and bonded to the circuit chip C2, thereby completing the semiconductor memory device shown in Figure 10.

[0081] As described above, according to the first embodiment, the contact plug 62 is electrically connected to the conductive layer 21 on the step surface of the staircase structure 61. The contact plug 62 extends along the first direction (Z direction) from the step surface through the laminate 2 and penetrates through the laminate 2.

[0082] Furthermore, the configuration of the contact plug 62 and its surroundings according to the first embodiment can also be applied to the staircase structure shown in Figures 5 to 8B according to the first configuration example, as described above.

[0083] (Comparative Example 1) Figure 13 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first comparative example. The first comparative example differs from the first embodiment in that the contact plug 62 is formed after the formation of the stepped structure 61.

[0084] In the example shown in Figure 13, the left contact plug 62 of the two contact plugs 62 is formed shallower than the desired depth and is not connected to the conductive layer 21 (open). The right contact plug 62 of the two contact plugs 62 is formed deeper than the desired depth and penetrates through the conductive layer 21 to connect to the conductive layer 21 below (penetration). Furthermore, as the number of layers increases and the thickness of the conductive layer 21 decreases, open connections and penetrations become more likely to occur. In other words, it becomes difficult to properly connect the contact plugs 62 to the conductive layer 21.

[0085] In contrast, in the first embodiment, the stepped structure 61 is formed after the contact hole CH (contact plug 62) is formed. As a result, assuming that the contact plug 62 penetrates the laminate 2, the contact plug 62 extends from the back side of the laminate 2 and connects to the conductive layer 21. This makes it possible to suppress the occurrence of open holes and through-holes during the formation of the contact plug 62. Therefore, a semiconductor memory device can be formed more appropriately.

[0086] (First embodiment, first modified example) Figures 14A to 14J are cross-sectional views showing an example of a method for manufacturing a semiconductor memory device according to a first modification of the first embodiment. In the first modification of the first embodiment, the method for forming the contact plug 62 is different from that of the first embodiment. Note that Figure 14A is performed after the same process as in Figures 12A to 12D.

[0087] After forming the staircase structure 61 (see Figure 12D), an insulating film 84 is formed on the laminate 2a as shown in Figure 14A. In the first modified example of the first embodiment, the insulating film 85 is not formed.

[0088] Next, as shown in Figure 14B, the insulating film 84 is processed so that it remains on the sacrificial member 83 exposed on the step surface.

[0089] Next, as shown in Figure 14C, a sacrificial film 86 is formed on the laminate 2. The sacrificial film 86 contains, for example, SiN.

[0090] Next, as shown in Figure 14D, the sacrificial film 86 is processed so that it remains on the insulating film 84 and on the sacrificial layer 21c exposed on the step surface. In the example shown in Figure 14D, a portion of the sacrificial film 86 is also provided on the insulating column CLHR.

[0091] Next, as shown in Figure 14E, an interlayer insulating film 53 is formed, and the upper surface of the interlayer insulating film 53 is flattened.

[0092] Next, as shown in Figure 14F, the sacrificial layer 21c and the sacrificial film 86 are replaced with the conductive layer 21.

[0093] Next, the substrate 81 is peeled off as shown in Figure 14G. Note that Figure 14G is inverted vertically from Figure 14F.

[0094] Next, as shown in Figure 14H, the sacrificial member 83 is removed.

[0095] Next, as shown in Figure 14I, a portion of the insulating film 84 is removed until the conductive layer 21 is exposed.

[0096] Next, as shown in Figure 14J, a conductive material is embedded in the contact hole CH. The conductive material is, for example, tungsten (W). This forms a contact plug 62 that connects to the conductive layer 21.

[0097] Subsequently, the wiring 71 and other components are formed and bonded to the circuit chip C2, thereby completing the semiconductor memory device shown in Figure 10.

[0098] As in the first modification of the first embodiment, the method of forming the contact plug 62 may be different. In this case as well, the same effects as in the first embodiment can be obtained.

[0099] (Second Embodiment) Figure 15 shows an example of the configuration of a semiconductor memory device according to the second embodiment.

[0100] The array chip C1 is provided with two stacked structures 2_1 and 2_2 and wiring 111. Stacked structure 2_1 has a memory cell array 51_1 and a stepped structure 61. Stacked structure 2_2 has a memory cell array 51_2 and a stepped structure 61.

[0101] The two laminated structures 2_1 and 2_2 are arranged such that their staircase structures 61 face each other. Therefore, the two laminated structures 2_1 and 2_2 are divided in the middle.

[0102] The contact plugs 62 connected to each of the two laminates 2_1 and 2_2 extend through the laminates 2_1 and 2_2 on the side where the step surface is provided and on the side opposite to the side where the step surface is provided.

[0103] The contact plug 62 is electrically connected to the switch circuit (transistor 31) provided on the circuit chip C2.

[0104] Circuit chip C2 is provided with a sense amplifier SA and a switch circuit. The switch circuit includes multiple transistors 31.

[0105] The two sense amplifiers SA are positioned so as to sandwich the switch circuit. Each of the two sense amplifiers SA is connected to the two stacked units 2_1 and 2_2.

[0106] Multiple transistors 31 include transistors 31l, 31r, 31s1, and 31s2.

[0107] Transistor 31l is connected to the laminate 2_1 via contact plug 62.

[0108] Transistor 31r is connected to the laminate 2_2 via contact plug 62.

[0109] Transistor 31s1 is positioned between transistor 31l and transistor 31r. Transistor 31s1 is shared by the two stacked structures 2_1 and 2_2. Sharing of transistor 31s1 is made possible by electrically connecting the conductive layers 21 in stacked structures 2_1 and 2_2 via wiring in the wiring layer, which is provided on the circuit chip C2 side of the array chip C1. However, due to constraints on the wiring in the wiring layer, it is difficult to connect all layers of the conductive layer 21. For example, conductive layers 21 of the same layer are electrically connected to each other.

[0110] Transistor 31s2 is positioned between transistor 31l and transistor 31r. Transistor 31s2 is shared by the two stacked structures 2_1 and 2_2. Sharing of transistor 31s2 is made possible by the electrical connection of the conductive layers 21 in stacked structures 2_1 and 2_2 via wiring 111. For example, conductive layers 21 of the same layer are electrically connected. In the example shown in Figure 15, transistor 31s2 is positioned below the stepped structure 61 of stacked structure 2_1, and is therefore positioned between transistor 31l and transistor 31s1.

[0111] In other words, the contact plug 62 connected to the laminate 2_1 is electrically connected to the switch circuit (transistor 31). The contact plug 62 connected to the laminate 2_1 is electrically connected to the contact plug 62 connected to the laminate 2_2. No wiring or anything else is connected from the stepped end of the contact plug 62 connected to the laminate 2_1.

[0112] The wiring 111 is provided on the back side of the laminates 2_1 and 2_2, that is, on the side opposite to the side where the step surface is provided relative to the laminates 2_1 and 2_2. As will be explained later, the wiring 111 electrically connects the contact plug 62 that penetrates the laminate 2_1 and the contact plug 62 that penetrates the laminate 2_2.

[0113] Figure 16 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second embodiment.

[0114] The wiring 111 is provided within an insulating film 52 located above the semiconductor layer (embedded source line BSL). The wiring 111 is electrically connected to the contact plug 62 via the contact plug C111. The contact plug C111 penetrates the embedded source line BSL and connects to the upper end of the contact plug 62.

[0115] The wiring 111 electrically connects the contact plugs 62 of the two stacked structures 2_1 and 2_2. As a result, the transistor 31s2 of the switch circuit is shared by the two stacked structures 2_1 and 2_2.

[0116] The insulating film 112 is provided on the insulating film 52 and the wiring 111.

[0117] The insulating film 113 is provided on the insulating film 112.

[0118] The wiring 114 is provided on the insulating film 112. The wiring 114 is electrically connected to the embedded source line BSL via a contact plug C114. The contact plug C114 penetrates the insulating film 52 and connects to the embedded source line BSL in the cell region.

[0119] The insulating layers 115, 116, and 117 are provided on the side of the array chip C1 facing the circuit chip C2. The word wiring layer 63 is provided within the insulating layer 117.

[0120] The two contact plugs 62 that share transistor 31s1 are electrically connected by wiring included in the word wiring layer 63.

[0121] Of the two contact plugs 62 that share transistor 31s2, wiring is drawn out from the contact plug 62 on the laminated body 2_1 side and connected to transistor 31s2. Of the two contact plugs 62 that share transistor 31s2, no wiring or other connections are drawn out from the contact plug 62 on the laminated body 2_2 side.

[0122] Figures 17A to 17S are cross-sectional views showing an example of a semiconductor memory device manufacturing method according to the second embodiment. In the following description, one of the two stacked bodies 2_1 and 2_2 that are formed simultaneously will be explained.

[0123] First, as shown in Figure 17A, an insulating film 52 is formed on the substrate 121, and a semiconductor layer (embedded source line BSL) is formed on the insulating film 52. The substrate 121 is, for example, a silicon substrate.

[0124] The embedded source line (BSL) is, for example, a polysilicon layer. More specifically, the embedded source line (BSL) has a structure in which a semiconductor layer (e.g., a polysilicon layer), an insulating layer, and another semiconductor layer (e.g., a polysilicon layer) are stacked (see Figure 23).

[0125] Next, as shown in Figure 17B, the embedded source wire BSL is processed to form insulating members 122 that insulate the embedded source wire BSL at each position where the contact plug 62 is formed.

[0126] Figure 18 is a plan view showing an example of an embedding pattern for the insulating member 122 according to the second embodiment.

[0127] As shown in Figure 18, the dashed circles indicate the positions where the contact plugs 62 are formed. The pattern of the insulating member 122 is formed to separate the contact plugs 62. This electrically insulates the contact plugs 62 from each other.

[0128] Next, as shown in Figure 17C, a laminated body 2a is formed to create a series of opposing staircase structures 61.

[0129] The sacrificial layer 21c has a thick film portion 21ca at a position corresponding to the stepped surface, i.e., the end that connects to the through-contact plug 62. The thickness of the thick film portion 21ca in the Z direction is greater than that of the other parts of the sacrificial layer 21c.

[0130] Next, as shown in Figure 17D, a contact hole CH is formed that passes through the step surface and penetrates the laminate 2a in the Z direction. The contact hole CH is a through-hole that exposes the semiconductor layer BSL. The contact hole CH is formed to penetrate the thick film portion 21ca.

[0131] Next, as shown in Figure 17E, a portion of the sacrificial layer 21c is removed (recessed) on the inner circumferential surface of the contact hole CH. This creates multiple recesses 21cb in the sacrificial layer 21c that are not connected to the contact plug 62. Additionally, a recess 21cc is formed in the sacrificial layer 21c that is connected to the contact plug 62.

[0132] Next, as shown in Figure 17F, an insulating layer 123 is formed on the inner circumferential surface of the contact hole CH. In this case, the thickness of the insulating layer 123 is greater than half the width of the recess 21cb in the Z direction (the thickness of the sacrificial layer in the Z direction). Therefore, the recess 21cb is filled by the insulating layer 123. On the other hand, the thickness of the insulating layer 123 is less than half the width of the recess 21cc in the Z direction (the thickness of the sacrificial layer in the Z direction). Therefore, the recess 21cc is not filled by the sacrificial layer.

[0133] Next, as shown in Figure 17G, a portion of the insulating layer 123 is removed (recessed). In this step, the portion of the insulating layer 123 that is formed on the side surface of the insulating layer 123, the thick film portion 21ca of the sacrificial layer 21c, and the upper surface of the semiconductor layer BSL is removed. As a result, the thick film portion 21ca of the sacrificial layer 21c and the semiconductor layer BSL are exposed.

[0134] Next, as shown in Figure 17H, an insulating layer 124 (liner film) is formed on the inner surface of the contact hole CH, and the contact hole CH is filled with a sacrificial member 125. The insulating layer 124 contains, for example, SiO2.

[0135] Next, as shown in Figure 17I, a memory hole MH is formed, and a columnar portion CL is formed within the memory hole MH.

[0136] Next, as shown in Figure 17J, an insulating layer 115 is formed, a slit ST is formed, and the sacrificial layer 21c is replaced with a conductive layer 21.

[0137] Next, as shown in Figure 17K, a contact hole CH is formed on the sacrificial member 125. This exposes the upper surface of the sacrificial member 125.

[0138] Next, as shown in Figure 17L, the sacrificial member 125 and the insulating layer 124 (liner film) are removed.

[0139] Next, as shown in Figure 17M, a contact plug 62 is formed inside the contact hole CH. The contact plug 62 is electrically connected to the conductive layer 21 at its stepped surface.

[0140] Next, as shown in Figure 17N, a word wiring layer 63 is formed, which includes the contact plug 62 and the wiring drawn out from the columnar part CL, and an insulating layer 117 is formed.

[0141] Next, as shown in Figure 17O, the array chip C1 is bonded to the circuit chip C2. Note that Figure 17O is inverted vertically from Figure 17N.

[0142] Next, as shown in Figure 17P, the substrate 121 is peeled off.

[0143] Next, as shown in Figure 17Q, a contact hole CH is formed from the upper (back) side of the array chip C1, that is, the side where the widest conductive layer 21 is provided. The contact hole CH is formed to penetrate the insulating film 52 and the semiconductor layer BSL, exposing the contact plug 62.

[0144] Next, as shown in Figure 17R, the wiring 111 and contact plug C111 are formed. The wiring 111 and contact plug C111 are formed, for example, by processing the insulating film 52 and embedding a conductive member. The wiring 111 and contact plug C111 electrically connect the contact plug 62 connected to the laminate 2_1 and the contact plug 62 connected to the laminate 2_2.

[0145] Next, as shown in Figure 17S, the insulating film 112, wiring 114, contact plug C114, and insulating film 113 are formed.

[0146] As described above, according to the second embodiment, the contact plug 62 extends through the laminate 2_1 on the side where the step surface is provided and is electrically connected to the switch circuit. The contact plug 62 extends through the laminate 2_1 on the opposite side from where the step surface is provided and is electrically connected to the contact plug 62 of the laminate 2_2. As a result, the transistor 31S2 of the switch circuit is shared by the two laminates 2_1 and 2_2, and the chip area can be reduced.

[0147] (Comparative Example 2) Figure 19 shows an example of the configuration of a semiconductor memory device according to the second embodiment and the second comparative example. The upper part of Figure 19 shows the semiconductor memory device according to the second comparative example. The middle part shows the space Sp that can be reduced in area by providing the wiring 111 according to the second embodiment. The lower part shows the semiconductor memory device according to the second embodiment.

[0148] The second comparative example differs from the second embodiment in that the wiring 111 is not provided and the switch circuit is not shared by the wiring 111.

[0149] As shown in the upper panel, in the second comparative example, transistors 31l and 31r of the switch circuit are provided, corresponding to the two stacked structures 2_1 and 2_2, respectively.

[0150] In the middle section, wiring 111 is provided, and the transistor 31s2 below the laminate 2_1 is shared by the two laminates 2_1 and 2_2, thereby creating an area-reducing space Sp below the laminate 2_2.

[0151] As shown in the lower section, in the second embodiment, the chip area corresponding to space Sp is reduced.

[0152] Thus, in the second embodiment, the switch circuit (transistor 31S2) is shared, and the chip area can be reduced.

[0153] (First modified example of the second embodiment) Figure 20 shows an example of the configuration of a semiconductor memory device according to the first modification of the second embodiment. The first modification of the second embodiment differs from the second embodiment in that it does not have a chip configuration to which the semiconductor memory device is bonded, and a switch circuit is provided below the stacked bodies 2_1 and 2_2.

[0154] In the example shown in Figure 20, a switch circuit (transistor 31) is provided below the laminates 2_1 and 2_2, similar to the configuration shown in Figure 1.

[0155] Similar to Figure 16 in the second embodiment, the transistor 31s2 of the switch circuit is shared by the two stacked structures 2_1 and 2_2. Similar to Figure 16 in the second embodiment, of the two contact plugs 62 that share the transistor 31s2, no wiring is drawn out from the contact plug 62 on the stacked structure 2_2 side.

[0156] As in the first modified example of the second embodiment, the semiconductor memory device may have a switch circuit provided below the stacked structures 2_1 and 2_2. In this case as well, the same effects as in the second embodiment can be obtained.

[0157] (Second modified example of the second embodiment) Figure 21 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a second modification of the second embodiment. The second modification of the second embodiment differs from the second embodiment in that the wiring 131 for sharing is provided on a different layer from the wiring 111 layer.

[0158] Wiring 131 is provided on the same wiring layer as wiring 114. This allows for an increase in the number of wires used to share switch circuits. This further increases the number of shared switch circuits (transistors), and thus further reduces the chip area.

[0159] In the example shown in Figure 21, the contact plug C131 penetrates the insulating film 112 and connects to the wiring provided in the same layer as the wiring 111.

[0160] As in the second modification of the second embodiment, the wiring 131 for sharing may be provided in a layer different from the layer of wiring 111. In this case as well, the same effects as in the second embodiment can be obtained.

[0161] (Third modified example of the second embodiment) Figure 22 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a third modification of the second embodiment. The third modification of the second embodiment differs from the second embodiment in that the contact plug C111 of the wiring 111 is not in direct contact with the contact plug 62.

[0162] The contact plug C111 extends to a position that reaches inside the embedded source wire BSL. The contact plug C111 does not directly contact the contact plug 62, but is electrically connected to the contact plug 62 via the embedded source wire BSL. The embedded source wire BSL has a toppled semiconductor layer.

[0163] Figure 23 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a third modification of the second embodiment. Figure 23 is also an enlarged view of the embedded source line BSL and its surroundings in Figure 22.

[0164] The embedded source line BSL has a stacked semiconductor layer 141, an insulating layer 142, and a semiconductor layer 143. The semiconductor layers 141 and 143 are, for example, polysilicon layers. The insulating layer 142 is, for example, a silicon oxide film.

[0165] If the contact plug 62 extends through the insulating layer 142 to reach the semiconductor layer 143 (Figure 23), or if the insulating layer 142 is removed, then electrical connection between the contact plug C111 and the contact plug 62 is possible via the embedded source wire BSL.

[0166] As in the third modification of the second embodiment, the contact plug C111 of the wiring 111 does not need to be in direct contact with the contact plug 62. In this case as well, the same effects as in the second embodiment can be obtained.

[0167] (Fourth modified example of the second embodiment) Figure 24 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a fourth modification of the second embodiment. The fourth modification of the second embodiment differs from the second modification of the second embodiment in that the contact plug C131 of the wiring 131 is not in direct contact with the contact plug 62. In other words, the fourth modification of the second embodiment is a combination of the second modification of the second embodiment and the third modification of the second embodiment.

[0168] The contact plug C131 extends through the insulating film 52 and the insulating film 112 to a position where it reaches the interior of the embedded source wire BSL. The contact plug C111 does not directly contact the contact plug 62, but is electrically connected to the contact plug 62 via the embedded source wire BSL. The embedded source wire BSL has a toppled semiconductor layer. This allows the contact plug C131 of wiring 131 to be formed simultaneously with the contact plug C114 of wiring 114 in the same process. This helps to suppress an increase in the number of processes.

[0169] As in the fourth modification of the second embodiment, the contact C131 of the wiring 131 does not have to be in direct contact with the contact plug 62. In this case as well, the same effects as in the second modification of the second embodiment can be obtained.

[0170] (Fifth variation of the second embodiment) Figure 25 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a fifth modification of the second embodiment. The fifth modification of the second embodiment differs from the second embodiment in that an embedded source line BSL is not provided at the position corresponding to the staircase structure 61. In addition, the arrangement of the insulating member 122 is different in the fifth modification of the second embodiment compared to the second embodiment.

[0171] The insulating member 122 is placed between the staircase structure 61 and the memory cell array 51.

[0172] To the left of the insulating member 122 shown in Figure 25, the embedded source wire BSL is removed and an insulating film 151 is provided.

[0173] Figure 26 is a plan view showing an example of the configuration of the insulating member 122 according to a fifth modification of the second embodiment.

[0174] The insulating member 122 is provided in an annular shape, for example, surrounding the respective stepped structures 61 of the laminates 2_1 and 2_2. The insulating member 122 is provided in an annular shape, for example, a square annular shape. Inside the ring of the insulating member 122, the embedded source wire BSL is removed and an insulating film 151 is provided.

[0175] This makes it possible to suppress the effect of withstand voltage between the wiring 111 (contact plug C111) and the embedded source wire BSL when the insulating film 52 shown in Figure 25 is thin in the Z direction.

[0176] As in the fifth modified example of the second embodiment, it is not necessary to provide an embedded source line BSL at a position corresponding to the staircase structure 61. In this case as well, the same effects as in the second embodiment can be obtained.

[0177] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0178] 100 Semiconductor memory device, 2 Stack, 2a Stack, 21 Conductive layer, 21c Sacrificial layer, 22 Insulating layer, 31 Transistor, 61 Stepped structure, 62 Contact plug, 71 Wiring, 73 Insulating film, 83 Sacrificial component, 84 Insulating film, 85 Insulating film, 86 Sacrificial film, C1 Array chip, C2 Circuit chip, CH Contact hole

Claims

1. A laminate having a plurality of conductive layers and insulating layers stacked alternately in a first direction, and including a stepped structure having a stepped shape at its end, A contact plug is electrically connected to the conductive layer on the step surface of the staircase structure and extends along the first direction so as to penetrate the laminate from the step surface and through the laminate, A semiconductor memory device equipped with the following features.

2. The laminate and the first chip on which the contact plug is provided, A second chip stacked with the first chip and having a switch circuit provided on it, Furthermore, The semiconductor memory device according to claim 1, wherein the switch circuit is electrically connected to the conductive layer via the contact plug.

3. The semiconductor memory device according to claim 1, further comprising a first wiring provided at a position opposite to the side on which the step surface is provided, extending in a direction substantially perpendicular to the first direction, and electrically connected to the contact plug.

4. A laminate in which sacrificial layers and insulating layers are alternately stacked in a first direction has holes that penetrate in the first direction. A first insulating film is formed on the inner surface of the hole. A sacrificial member is embedded in the aforementioned hole. A step-shaped stair structure is formed at the end of the laminate in the region including the hole. A second insulating film is formed on the sacrificial member exposed on the step surface of the staircase structure. The aforementioned sacrificial layer is replaced with a conductive layer, Remove the aforementioned sacrificial member, A portion of the second insulating film is removed, In the region where the sacrificial member and the second insulating film have been removed, a contact plug is formed that electrically connects to the conductive layer exposed on the step surface. A method for manufacturing a semiconductor memory device, comprising the following:

5. The invention further comprises forming a third insulating film on the second insulating film after forming the second insulating film, Removing a portion of the second insulating film includes removing a portion of the second insulating film until the third insulating film is exposed. After removing a portion of the second insulating film, Remove the third insulating film, Remove the second insulating film. It further possesses the following: The method for manufacturing a semiconductor memory device according to claim 4, wherein forming the contact plug includes forming the contact plug in the region where the sacrificial member, the second insulating film, and the third insulating film have been removed.

6. The method further comprises forming the second insulating film, and then forming the first sacrificial film on the second insulating film and on the sacrificial layer exposed to the step surface. Replacing the sacrificial layer with the conductive layer includes replacing the sacrificial layer and the first sacrificial film with the conductive layer. The method for manufacturing a semiconductor memory device according to claim 4, wherein removing a portion of the second insulating film includes removing a portion of the second insulating film until the conductive layer is exposed.

7. A first laminate having a plurality of first conductive layers and first insulating layers stacked alternately in a first direction, and including a first stepped structure having a stepped shape at its end, A second laminate having a plurality of second conductive layers and second insulating layers stacked alternately in the first direction, and including a second staircase structure having a staircase shape at its end, the second laminate being arranged adjacent to the first laminate so that the first staircase structure and the second staircase structure face each other, A first contact plug is electrically connected to the first conductive layer on the first step surface of the first stair structure and extends to penetrate the first laminate along the first direction, A second contact plug is electrically connected to the second conductive layer on the second step surface of the second stair structure and extends to penetrate the second laminate along the first direction, Equipped with, The first contact plug extends through the first laminate to the side where the first step surface is provided and is electrically connected to the switch circuit. A semiconductor memory device wherein the first contact plug extends through the first laminate on the side opposite to the side on which the first step surface is provided and is electrically connected to the second contact plug.

8. The semiconductor memory device according to claim 7, wherein the switch circuit is shared by a first conductive layer electrically connected to the first contact plug and a second conductive layer electrically connected to the second contact plug.

9. The second contact plug extends through the second laminate on the side where the second step surface is provided, The semiconductor memory device according to claim 7, wherein no wiring is connected from the end of the second contact plug on the second step surface side.

10. The second contact plug extends through the second laminate on the side opposite to the side on which the second step surface is provided, The semiconductor memory device according to claim 7, further comprising a second wiring provided in a direction substantially perpendicular to the first direction, at a position opposite to the side on which the first step surface and the second step surface are provided, relative to the first and second laminates, for electrically connecting the first contact plug and the second contact plug.

11. A first laminate and a second laminate are formed in which a sacrificial layer and an insulating layer are alternately stacked in the first direction. A first staircase structure having a staircase shape is formed at the end of the first laminate, which is opposite to the other, and a second staircase structure having a staircase shape is formed at the end of the second laminate. A first hole is formed that passes through the first step surface of the first staircase structure and penetrates the first laminate in the first direction, and a second hole is formed that passes through the second step surface of the second staircase structure and penetrates the second laminate in the first direction. The aforementioned sacrificial layer is replaced with a conductive layer, A first contact plug is formed in the first hole and the second hole, electrically connected to the conductive layer on the first step surface, and a second contact plug is formed in the second step surface, electrically connected to the conductive layer. A second wiring is formed to electrically connect the first contact plug and the second contact plug at a position opposite to the side on which the first step surface and the second step surface are provided, relative to the first and second laminates. A method for manufacturing a semiconductor memory device, comprising the following:

12. Before forming the first laminate and the second laminate, A fourth insulating film is formed on the substrate. A semiconductor layer is formed on the fourth insulating film, An insulating member is formed at each position where a plurality of the first contact plugs and a plurality of the second contact plugs are formed, which insulates the semiconductor layer. A method for manufacturing a semiconductor memory device according to claim 11, further comprising the above.

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