Circuit boards and semiconductor packages

Abstract

This embodiment relates to a circuit board and a semiconductor package. [Solution] A circuit board according to one embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a first through hole, and a third insulating layer disposed on the second insulating layer and including a second through hole that overlaps perpendicularly with the first through hole, wherein at least a portion of the inner wall of the second through hole overlaps perpendicularly with the inner wall of the first through hole.

Description

Technical Field

[0001] This embodiment relates to a circuit board and a semiconductor package.

Background Art

[0002] In recent years, technologies related to electronic products such as AI and servers have been trending towards multi-functionality and high speed. To cope with such trends, the manufacturing technology of semiconductor chips has also been developing at a rapid pace.

[0003] In particular, for the miniaturization of completed electronic products, the thickness of the applied circuit board has also been reduced, and technologies related to multilayer circuit boards with more circuit layers formed in the same thickness of the circuit board have been actively studied. Also, as the pitch of semiconductor chips becomes narrower and the chip size becomes larger, the technology of chiplets that separate semiconductor chips by function has been studied. In addition, technologies for connecting the separated chiplets to a circuit board have been actively studied. Also, by connecting semiconductor chips with different functions to each other on a circuit board, technologies related to the connection relationship between the circuit board and semiconductor chips, such as connecting semiconductor chips to each other, which were only considered from the perspective of conventional semiconductor packages, have been actively studied.

[0004] A circuit board is formed by printing a circuit line pattern with a conductive material such as copper on an electrically insulating substrate, and generally refers to the substrate (Board) immediately before mounting electronic elements. In order to densely mount many different types of electronic elements on a flat plate, the mounting positions of each component are determined, and a circuit pattern for connecting the components is printed and fixed on the surface of the flat plate.

[0005] Conventional embedded printed circuit boards used a drill bit to form a cavity for incorporating elements, used auxiliary materials such as a release film for placing elements, or used sand blast to form a cavity for incorporating elements.

[0006] The formation of cavities penetrating multiple insulating layers can be achieved by first forming a cavity within the lower insulating layer, and then forming a cavity within the upper insulating layer located on top of the lower insulating layer. However, due to various factors such as differences in the degree of curing between the multiple insulating layers, there is a problem in which a difference in thickness occurs between dissimilar insulating layers in the inner wall region of the cavity due to the sagging of the upper insulating layer. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Korean Published Patent No. 10-2006-0105382 (Publication Date: 2006.10.11.) [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention provides a circuit board and a semiconductor package that can minimize the difference in thickness between multiple insulating layers in a structure that includes a cavity penetrating multiple insulating layers. [Means for solving the problem]

[0009] The circuit board according to this embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a first through-hole, and a third insulating layer disposed on the second insulating layer and including a second through-hole that overlaps perpendicularly with the first through-hole, wherein at least a portion of the inner wall of the second through-hole overlaps perpendicularly with the inner wall of the first through-hole.

[0010] The semiconductor package according to this embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a first through-hole, a third insulating layer disposed on the second insulating layer and including a second through-hole that overlaps perpendicularly with the first through-hole, and electronic elements disposed in the first and second through-holes, wherein at least a portion of the inner wall of the second through-hole overlaps perpendicularly with the inner wall of the first through-hole. [Effects of the Invention]

[0011] According to this embodiment, by adjusting the shape of the inner wall of the through-hole formed in each of the multiple insulating layers, it is possible to prevent differences in thickness between the multiple insulating layers during the process of forming a cavity that penetrates the multiple insulating layers. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view of a circuit board according to an embodiment of the present invention. [Figure 2] This figure shows a cavity formation structure through the first insulating layer, the second insulating layer, and the third insulating layer according to an embodiment of the present invention. [Figure 3] This figure shows the inner walls of the first insulating layer and the second insulating layer in the cavity formation region according to an embodiment of the present invention. [Figure 4] This figure shows the inner walls of the first insulating layer and the second insulating layer in the cavity formation region according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 6] This figure shows a modified example of a circuit board according to an embodiment of the present invention. [Figure 7] This figure shows a modified example of the cavity formation structure through the second and third insulating layers according to an embodiment of the present invention. [Modes for carrying out the invention]

[0013] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0014] However, the technical concept of the present invention is not limited to the embodiments described, but can be realized in various different forms, and within the scope of the technical concept of the present invention, one or more components of the embodiments can be selectively combined or substituted for each other.

[0015] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted in the meaning generally understood by those with ordinary knowledge in the technical field to which the present invention pertains, unless specifically defined and described otherwise. Terms generally used as defined in a dictionary can be interpreted in consideration of their meaning in the context of the related art.

[0016] Also, the terms used in the embodiments of the present invention are for the purpose of explaining the embodiments and are not intended to limit the present invention. In this specification, the singular form can include the plural form unless otherwise specifically stated in the text. When it is described as "at least one (or one or more) of A, B, and C," it can include one or more of all possible combinations of A, B, and C.

[0017] In addition, when describing the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0018] These terms are merely for distinguishing the components from other components, and the essence, order, or sequence of the components are not limited by these terms.

[0019] And when a component is described as "connected," "coupled," or "joined" to another component, it can include not only the case where the component is directly "connected," "coupled," or "joined" to the other component, but also the case where the component is "connected," "coupled," or "joined" by another component between the component and the other component.

[0020] Also, when it is described that each component is "exposed", it must mean not only being exposed to the appearance of the invention product defined in the present invention, but also being exposed to other components other than that component. That is, when it is described that B included in A is exposed from A, B must mean not only being exposed to the appearance of the invention product defined in the present invention, but also being covered by another component C, unless there are special circumstances.

[0021] Also, when it is described that it is formed or arranged "above (on top of)" or "below (beneath)" each component, "above (on top of)" or "below (beneath)" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between the two components. Also, when expressed as "above (on top of)" or "below (beneath)", it may include not only the upward direction but also the downward direction with respect to a reference component.

[0022] Also, the expression that Configuration A is arranged between Configuration B and Configuration C must include the meaning that Configuration A is arranged such that it at least partially overlaps with Configuration B and Configuration C in the horizontal and / or vertical directions.

[0023] Expressions indicating directions include the horizontal direction and the vertical direction. The horizontal direction includes the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction. According to the Cartesian coordinate system, these are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis). The meaning of overlapping along the horizontal direction must include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0024] Also, with reference to a component, one surface and the other surface must include the cases where they respectively mean the upper surface and the lower surface or the lower surface and the upper surface.

[0025] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, Figure 2 is a diagram showing a cavity formation structure through the first insulating layer, second insulating layer and third insulating layer according to an embodiment of the present invention, and Figures 3 and 4 are photographs of the inner walls of the first insulating layer and second insulating layer in the cavity formation region according to an embodiment of the present invention.

[0026] Referring to Figures 1 to 4, the circuit board 10 according to an embodiment of the present invention may include a plurality of insulating layers, a plurality of wiring sections, a plurality of via sections, and a protective layer.

[0027] The circuit board 10 may include multiple insulating layers. The multiple insulating layers may be arranged vertically. The multiple insulating layers may include a first insulating layer 101, a second insulating layer 102 placed on the first insulating layer 101, a third insulating layer 103 placed on the second insulating layer 102, a fourth insulating layer 104 placed on the underside of the first insulating layer 101, a fifth insulating layer 105 placed on the underside of the fourth insulating layer 104, a sixth insulating layer 106 placed on the underside of the fifth insulating layer 105, a seventh insulating layer 107 placed on the underside of the sixth insulating layer 106, and an eighth insulating layer 108 placed on the underside of the seventh insulating layer 108. The first to eighth insulating layers 101, 102, 103, 104, 105, 106, 107, and 108 may be stacked vertically.

[0028] The first to eighth insulating layers 101, 102, 103, 104, 105, 106, 107, and 108 may each be any insulating material, such as photocurable and / or thermosetting. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product commercially available from Ajinomoto Co., Inc., can be used, or a prepreg (PPG) containing glass fibers in the resin can be used. Furthermore, the resin mentioned above may, exemplified, be epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and as inorganic and / or organic fillers, materials such as silica and plastics may be provided. When an insulating resin is used as a core, it may include reinforcing materials such as glass fibers or aramid fibers. If the first to eighth insulating layers 101, 102, 103, 104, 105, 106, 107, and 108 are photocurable insulators, then each of the first to eighth insulating layers 101, 102, 103, 104, 105, 106, 107, and 108 can be PID (Photo Imageable Dielectric).

[0029] On the other hand, although this embodiment describes a coreless structure in which the core layer in the circuit board 10 is omitted, the circuit board 10 can include a core layer. In this case, the fifth insulating layer 105, which is located in the center with respect to the vertical direction of the circuit board 10, can be named the core layer, and by forming it with a greater thickness in the vertical direction compared to the other insulating layers, warpage of the circuit board 10 can be suppressed.

[0030] At least some of the insulating layers may be made of a different material than some of the other insulating layers. For example, the first insulating layer 101, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106, which are located in the vertical center of the circuit board 10, may each be a prepreg (PPG) containing glass fibers in the resin. The second insulating layer 102 and the third insulating layer 103, which are located on the first insulating layer 101, and the seventh insulating layer 107 and the eighth insulating layer 108, which are located on the underside of the sixth insulating layer 106, may each be PID (Photo Imageable Dielectric) or ABF (Ajinomoto Build-up Film).

[0031] The vertical thickness of the first insulating layer 101, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be made thicker than the vertical thickness of the second insulating layer 102, the third insulating layer 103, the seventh insulating layer 107, and the eighth insulating layer 108. This minimizes warping of the circuit board 10 through the first insulating layer 101, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106, which are positioned in the vertical center of the circuit board 10. To ensure the integrity of signal and / or power transmission, the number of insulating layers positioned on the upper surface of the first insulating layer 101 and the number of insulating layers positioned on the lower surface of the sixth insulating layer 106 may be the same, but are not limited to this, and may be different from each other.

[0032] The vertical thicknesses of the first insulating layer 101, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 may be the same. The vertical thicknesses of the second insulating layer 102, the third insulating layer 103, the seventh insulating layer 107, and the eighth insulating layer 108 may be the same as each other. This makes it easy to control the thickness of the electronic elements placed in the cavity, as described later, and the depth of the cavity.

[0033] The circuit board 10 may include a protective layer. The protective layer may include a first protective layer 190 positioned on the upper surface of the third insulating layer 103 and a second protective layer 198 positioned on the lower surface of the eighth insulating layer 108. When semiconductor elements are positioned on the surface of the circuit board 10 with a material such as solder, the first protective layer 190 and the second protective layer 198 can prevent short circuits between solder lines due to their low wettability with the solder, and can prevent problems such as external contaminants penetrating the build-up structure and reducing reliability. The first protective layer 190 and the second protective layer 198 may each be made of a photocurable insulating material. Exemplarily, the first protective layer 190 and the second protective layer 198 may be solder resist or PID (Photo Imageable Dielectric).

[0034] The first protective layer 190 may include a hole 192 for exposing the third wiring section 113 (described later) above the circuit board 10. The first protective layer 190 may include a third through-hole 195 that overlaps vertically with the cavity 150 (described later). The second protective layer 198 may include a hole 199 for exposing the ninth wiring section 119 (described later) below the circuit board 10.

[0035] The circuit board 10 may include a circuit pattern for transmitting electrical signals and / or power to an electronic element such as a semiconductor chip. The circuit pattern may include a plurality of wiring sections and a plurality of via sections.

[0036] Multiple wiring sections may be arranged on the surfaces of multiple insulating layers. Here, "arranged on the surface" can also mean that at least a portion of each wiring section is embedded within the multiple insulating or protective layers and exposed to the outside from the surface. The wiring section may also be named a metal layer. Furthermore, the surfaces of the multiple insulating layers each include one face and another face, and the side between the two faces. Here, one face of an insulating layer can be understood as the top face, and the other face of an insulating layer as the bottom face. "Arranged on the surface" means that the wiring section is located on at least one of the one face, another face, and side of the multiple insulating layers. Some of the multiple insulating layers may have wiring sections arranged on one face and another face, while other parts of the multiple insulating layers may have wiring sections arranged on only one face or only one face.

[0037] The multiple wiring sections may include a first wiring section 111 located on the upper surface of the first insulating layer 101, a second wiring section 112 located on the upper surface of the second insulating layer 102, a third wiring section 113 located on the upper surface of the third insulating layer 103, a fourth wiring section 114 located on the upper surface of the fourth insulating layer 104, a fifth wiring section 115 located on the upper surface of the fifth insulating layer 105, a sixth wiring section 116 located on the lower surface of the fifth insulating layer 105, a seventh wiring section 117 located on the lower surface of the sixth insulating layer 106, an eighth wiring section 118 located on the lower surface of the seventh insulating layer 107, and a ninth wiring section 119 located on the lower surface of the eighth insulating layer 108. Here, the third wiring section 113 and the ninth wiring section 119, which are at least partially covered by protective layers 190 and 198, may be named the first pad section and the second pad section, respectively. The wiring section may also include pad sections for connection to via sections.

[0038] The via portion may be a metallic material placed in via holes formed in each of several insulating layers to connect multiple wiring portions facing each other vertically. Here, the via hole penetrates vertically through at least a portion of each of the several insulating layers, and the via portion may be placed within the via hole.

[0039] The via portion may include a first via portion 123 penetrating at least a part of the first insulating layer 101, a second via portion 121 penetrating at least a part of the second insulating layer 102, a third via portion 122 penetrating at least a part of the third insulating layer 103, a fourth via portion 124 penetrating at least a part of the fourth insulating layer 104, a fifth via portion 125 penetrating at least a part of the fifth insulating layer 105, a sixth via portion 126 penetrating at least a part of the sixth insulating layer 106, a seventh via portion 127 penetrating at least a part of the seventh insulating layer 107, and an eighth via portion 128 penetrating at least a part of the eighth insulating layer 108.

[0040] The first via section 123 can electrically connect the first wiring section 111 and the fourth wiring section 114. The second via section 121 can electrically connect the first wiring section 111 and the second wiring section 112. The third via section 122 can electrically connect the second wiring section 112 and the third wiring section 113. The fourth via section 124 can electrically connect the fourth wiring section 114 and the fifth wiring section 115. The fifth via section 125 can electrically connect the fifth wiring section 115 and the sixth wiring section 116. The sixth via section 126 can electrically connect the sixth wiring section 116 and the seventh wiring section 117. The seventh via section 127 can electrically connect the seventh wiring section 117 and the eighth wiring section 118. The eighth via section 128 can electrically connect the eighth wiring section 118 and the ninth wiring section 119.

[0041] The first via section 123, the second via section 121, the third via section 122, and the fourth via section 124 can each have a shape in which the horizontal width decreases as it goes downwards. The fifth via section 125, the sixth via section 126, the seventh via section 127, and the eighth via section 128 can each have a shape in which the horizontal width increases as it goes downwards. The fifth via section 125 among the multiple via sections may be formed to have a longer vertical length than the other via sections. In the case of the fifth via section 125, it is positioned to penetrate the fifth insulating layer 105 located in the vertical center of the circuit board 10, and the fifth wiring section 115 and the sixth wiring section 116 are positioned above and below the fifth insulating layer 105, respectively, so that the fifth via section 125 can have a longer vertical length than the other via sections. Also, the diameter expansion direction of the via section can be reversed with respect to the fifth insulating layer 105.

[0042] The circuit board 10 may include a cavity 150. The cavity 150 may be formed by a first through hole 151 and a second through hole 152.

[0043] More specifically, the second insulating layer 102 may include a first through-hole 151. The first through-hole 151 may be shaped to penetrate from the upper surface to the lower surface of the second insulating layer 102. The first through-hole 151 may be located in the horizontal center of the second insulating layer 102. Exemplarily, a portion of the upper surface of the first insulating layer 101 may be exposed vertically from the second insulating layer 102 through the first through-hole 151. Together with the second through-hole 152, the first through-hole 151 can form a placement area for the electronic element 1000 (see Figure 5). In this case, a portion of the upper surface of the first insulating layer 101 may be provided as the bottom surface of the cavity, forming the placement surface for the electronic element 1000.

[0044] The first through-hole 151 may have a shape in which its horizontal width gradually narrows towards the first insulating layer 101. As a result, the inner wall 141 of the first through-hole 151 may have the shape of an inclined surface. The inner wall 141 of the first through-hole 151 may be named the first inner wall. The first inner wall 141 may form a first angle with the upper surface of the first insulating layer 101. The first angle may be an obtuse angle. According to the embodiment, the upper surface of the first insulating layer 101 includes one surface that constitutes the bottom surface of the cavity. The first angle described above refers to the angle formed between one surface of the first insulating layer 101 that constitutes the bottom surface of the cavity and the inner wall 141 of the first through-hole that constitutes the inner wall of the cavity.

[0045] The third insulating layer 103 may include a second through-hole 152. The second through-hole 152 may have a shape that penetrates from the top surface to the bottom surface of the third insulating layer 103. The second through-hole 152 may be located in the horizontal center of the third insulating layer 103. Through the second through-hole 152, a portion of the top surface of the first insulating layer 101 can be exposed vertically from the second insulating layer 102 and the third insulating layer 103. The second through-hole 152 may be positioned such that at least a portion of it vertically overlaps with the first through-hole 151 of the second insulating layer 102. The second through-hole 152, together with the first through-hole 151, can form a cavity 150, and the electronic element 1000 may be placed within the cavity 150.

[0046] In one embodiment, the second through-hole 152 may have a shape in which its horizontal width gradually increases toward the first insulating layer 101 or the second insulating layer 102. As a result, the inner wall 143 of the second through-hole 152 may have the shape of an inclined surface. The inner wall 143 of the second through-hole 152 may be named the second inner wall. The second inner wall 143 may form a second angle with the upper surface of the first insulating layer 101 or the upper surface of the second insulating layer 102. The second angle may be acute. In one embodiment, the upper surface of the first insulating layer 101 includes one surface that constitutes the bottom surface of the cavity. The first angle described above refers to the angle formed between one surface of the first insulating layer 101 that constitutes the bottom surface of the cavity and the inner wall 143 of the third through-hole that constitutes the inner wall of the cavity.

[0047] As a result, the first inner wall 141 and the second inner wall 143 may be arranged so that at least a portion of them overlap each other in the vertical direction, as shown in Figures 3 and 4. For example, the upper end of the second inner wall 143 may be arranged so as to overlap the first inner wall 141 in the vertical direction. The region where the first inner wall 141 and the second inner wall 143 intersect may have a groove-like shape that is recessed compared to other regions when viewed from the horizontal direction.

[0048] As described above, in the embodiment, the circuit board 10 has connection pads 158 placed on the bottom surface of the cavity 150, and the terminals of the electronic element 1000 are flip-bonded as shown in Figure 5. According to the prior art, in the process of forming the cavity, a process was used in which a part of the second insulating layer 102 and the third insulating layer 103 was removed using a laser or the like. Therefore, in order to prevent damage to the first insulating layer 101, an etching-blocking layer (not shown) such as copper was placed on one surface of the first insulating layer 101 that constitutes the bottom surface of the cavity 150 to prevent damage to the first insulating layer 101. However, in such a case, as shown in Figure 5, it is difficult to connect the electronic element 1000 to the circuit board 10 by flip bonding when placing it in the cavity 150, so the electronic element 1000 was mounted using wires. In such cases, it is necessary to form a cavity with an area greater than the combined area of ​​the area where the electronic element 1000 is placed and the area where the wire process can be performed, or to mount the electronic element 1000 by connecting the wires to electrodes on the top of the cavity. In such cases, it becomes difficult for the wire process itself to cope with an increase in the number of terminals of the electronic element 1000, and an increase in the number of electrodes 113 exposed on the top of the third insulating layer 103 is necessary because the electrodes 113 exposed on the top of the third insulating layer 103 must be connected to the electronic element 1000 placed in the cavity 150. This problem of having to unnecessarily enlarge the area of ​​the circuit board 10 leads to a decrease in yield due to the unnecessary enlargement of the circuit board 10, and an increase in material costs.

[0049] The structure of the cavity 150 according to this embodiment can solve the above-mentioned problems. However, when forming the cavity 150 that integrally penetrates the second insulating layer 102 and the third insulating layer 103, if the inner wall 141 of the second insulating layer 102 and the inner wall 143 of the third insulating layer 103 cannot be controlled, it causes the cavity 150 to collapse. As a result, the inner wall of the cavity 150 proposed in this invention has an inner wall structure of the cavity 150 that has a different structure from existing processes using lasers, etc., and can have the effect of improving the reproducibility and yield of the circuit board 10. According to this embodiment, the inner wall structure of the second insulating layer 102 and the third insulating layer 103 that form the cavity 150 as described above can prevent the third insulating layer 103 from sagging in the cavity 150 formation region, thus resolving the problems in the comparative example. In other words, by forming the angle of the second inner wall 143, which may sag, at an acute angle with respect to the upper surface of the first insulating layer 101 or the upper surface of the second insulating layer 102, and by arranging the second inner wall 143 to overlap horizontally with the first inner wall 141, it is possible to minimize the occurrence of thickness differences between multiple insulating layers in the cavity 150 formation region.

[0050] Furthermore, when arranging a molding member (not shown) for embedding the electronic element 1000 into the cavity 150, the bonding force with the molding member can be improved by varying the angles of the first inner wall 141 and the second inner wall 143.

[0051] Furthermore, due to the shape of the second inner wall 143, the cross-sectional area of ​​the upper end of the second through-hole 152 is formed to be smaller than the cross-sectional area of ​​the lower end of the second through-hole 152. This reduces the area of ​​the cavity for arranging the electronic element 1000, thereby increasing the design flexibility of the electrodes 113 necessary for mounting other electronic elements (not shown) and / or other circuit boards (not shown) on the circuit board 10.

[0052] With respect to the electronic element 1000 placed within the cavity 150, the first inner wall 141 may have a shape in which the horizontal distance to the side surface of the electronic element 1000 decreases as it goes downwards. The second inner wall 143 may have a shape in which the horizontal distance to the side surface of the electronic element 1000 increases as it goes downwards.

[0053] Although not shown in the diagram, the surface connecting the upper surface of the third insulating layer 103 and the second inner wall 143 can be formed in a rounded shape. In this case, the surface connecting the upper surface of the third insulating layer 103 and the second inner wall 143 can be named the rounded surface. The strength of the third insulating layer 103 can be reinforced in the region connecting the upper surface of the third insulating layer 103 and the second inner wall 143 via the rounded surface.

[0054] As shown in Figures 3 and 4, at least a portion of the first inner wall 141 or the second inner wall 143 may include a curved surface. At least a portion of the curved surface may protrude outward from the surface of the first inner wall 141 or the second inner wall 143. This can reinforce the strength of the second insulating layer 102 and the third insulating layer 103 in the cavity 150 formation region.

[0055] On the other hand, the second inner wall 143 can form a right angle with the upper surface of the first insulating layer 101 or the upper surface of the second insulating layer 102, in which case at least a portion of the first inner wall 141 can be exposed above the third insulating layer 103. In this case, compared to the shape of the second inner wall 143 described above, there is an advantage in that the area for arranging the electronic elements 1000 in the cavity 150 is wider.

[0056] In the region where the first through-hole 151 and the second through-hole 152 intersect, the horizontal widths of the first through-hole 151 and the second through-hole 152 may be the same as those of the first through-hole 151.

[0057] As shown in Figure 4, at least a portion of the third insulating layer 103 may be placed on the first inner wall 141 so as to cover the first inner wall 141. Furthermore, if the first inner wall 141 has a curved surface, at least a portion of the third insulating layer 103 may be placed on the first inner wall 141 so as to cover a portion of the curved surface. In this case, by preventing stress concentration between the first inner wall 141 and the third insulating layer 103, the shape of the cavity 150 can be prevented from collapsing, thereby improving the reliability of the circuit board 10.

[0058] At least a portion of the third insulating layer 103 may be positioned closer to the first insulating layer 101 than to the upper surface of the second insulating layer 102. That is, the vertical length from the lower end of the second inner wall 143 to the bottom surface of the cavity 150 may be shorter than the vertical length of the second insulating layer 102. This can minimize the occurrence of warping of the circuit board 10 due to an increase in the contact area between the second insulating layer 102 and the third insulating layer 103, and prevent the upper end of the second inner wall 143 from sagging downward in the cavity 150 formation region.

[0059] As described above, the first protective layer 190 may include a third through-hole 195 that overlaps the cavity 150 vertically in at least a portion thereof. In this case, the horizontal width of the third through-hole 195 may be greater than the horizontal width of the first through-hole 151 or the horizontal width of the second through-hole 152. This allows at least a portion of the upper surface of the first insulating layer 101 forming the bottom surface of the cavity 150, the inner wall 141 of the first through-hole 151, and the upper surface of the third insulating layer 103 to be exposed above the first protective layer 190 through the third through-hole 195.

[0060] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0061] Referring to Figure 5, the semiconductor package may include an electronic element 1000 located in a cavity 150 within the circuit board 10. A connection pad 158 may be located on the bottom surface of the cavity 150, which is electrically connected to the electronic element 1000. The connection pad 158 may be located on the upper surface of the first insulating layer 101. The electronic element 1000 may be coupled onto the connection pad 158.

[0062] The connecting pad 158 may be positioned so as to overlap horizontally with the first wiring section 111. The connecting pad 158 may also be positioned so as to overlap horizontally with the first inner wall 141. The first inner wall 141 of the first through hole 151 and the connecting pad 158 can be separated horizontally. This minimizes damage to the electronic element 1000 by the first inner wall 141 during the bonding process of the electronic element 1000 onto the connecting pad 158. Furthermore, the separation region provides space for air bubbles to be discharged between the adhesive member (not shown) and the electronic element 1000 during the bonding process of the electronic element 1000 via the adhesive member (not shown), which will be described later. The above-described embodiment is in which the bottom surface of the cavity 150 includes at least a portion of the first insulating layer 101, but is not limited thereto. When another insulating layer is placed between the first insulating layer 101 and the second insulating layer 102, the width of the connecting pad 158 can be made larger than the width of the first through hole 151 so that a recess does not occur on the surface of the other insulating layer, thereby preventing the creation of a separation region.

[0063] An adhesive member (not shown) may be added between the connection pad 158 and the electronic element 1000. The electronic element 1000 can be bonded to the connection pad 158 via a conductive bonding member. The conductive bonding member can be solder, solder paste, etc. According to the prior art, when forming a cavity 150 for arranging the electronic element 1000, an etching-blocking layer (not shown) made of a metal such as copper (Cu) is placed on the bottom surface of the cavity 150, and the etching-blocking layer (not shown) and the electronic element 1000 are bonded via an adhesive member such as DAF (Die Attach Film). However, in such cases, the electrical connection between the electronic element 1000 and the circuit board 10 could be achieved by forming and embedding an additional build-up layer on top of the cavity 150, or by connecting the electrodes of the electronic element 1000 to electrodes 113 exposed outside the cavity 150 of the circuit board 10 with wires, thereby mounting the electronic element 1000 to the circuit board 10. In such cases, there is a drawback that the area of ​​the cavity 150 must be excessively large, and when the number of terminals of the electronic element 1000 is large, there are limitations to wire connection. Therefore, the present invention proposes a structure that allows flip bonding of the electronic element 1000 by arranging patterned electrodes 158, rather than providing the lower surface of the cavity 150 as an etching-blocking layer (not shown) through a method for manufacturing the cavity 150.

[0064] A molding member (not shown) is placed inside the cavity 150 to firmly maintain the coupling state of the electronic elements 1000 inside the cavity 150. The upper surface of the molding member can be exposed on the first protective layer 190, but alternatively, the first protective layer 190 may be positioned to cover up to the upper surface of the molding member.

[0065] Figure 6 shows a modified example of a circuit board according to an embodiment of the present invention.

[0066] In this modified example, the other parts are the same as those of the previously described embodiment, except that there is a difference in the inner wall structure due to the formation of the cavity.

[0067] Referring to Figure 6, the third insulating layer 103 may include a projection 210. That is, a second through-hole 152 can be formed in the third insulating layer 103 located inside the first through-hole 151 of the second insulating layer 102. The projection 210 of the third insulating layer 103 may have a shape in which at least a portion protrudes downward. The projection 210 may be positioned to overlap the second insulating layer 102 horizontally. The projection 210 may have a shape that surrounds the side surface of the second insulating layer 102. The lower end of the projection 210 may be connected to the upper surface of the first insulating layer 101.

[0068] According to this embodiment, a method of laminating a second insulating layer 102 and a third insulating layer 103 can be used to control the depth of the cavity 150. That is, a method of forming a single cavity using a thick insulating layer can be selected, but considering current panel-level exposure technology, the degree of curing of the insulating layer to light, and delamination of the insulating layer during the process due to the coefficient of thermal expansion rate (CTE), forming the cavity 150 by laminating thin insulating layers is more advantageous in terms of yield and reliability. Therefore, the second insulating layer 102 and the third insulating layer 103 can have a thickness thinner than the thickness of the first insulating layer 101 and the insulating layer placed on the underside of the first insulating layer 101. Furthermore, according to this embodiment, when the second through-hole 152 is formed in the third insulating layer 103 located inside the first through-hole 151 of the second insulating layer 102, the third insulating layer 103 can collapse because the second insulating layer 102 supports the third insulating layer 103. In such cases, the mechanical strength of the cavity 150 can be improved by arranging the inclination angle of the inner wall of the first through-hole 151 to be different from that of the inner wall of the second through-hole 152. For example, by setting the inclination angle of the inner wall of the second through-hole 152 to be gentler than that of the inner wall of the first through-hole 151, a structure advantageous for stress distribution can be achieved.

[0069] With the structure described above, the inner wall of the cavity 150 can be formed by the third insulating layer 103. The inner wall of the cavity 150 may include a lower region 214 that horizontally overlaps with the second insulating layer 102, and an upper region 212 that is located on the lower region 214 and does not horizontally overlap with the second insulating layer 102.

[0070] According to this modified example, since the inner wall of the cavity 150 is represented by a single insulating layer, it is possible to prevent the occurrence of thickness differences due to sagging during the formation of a cavity that penetrates multiple insulating layers. Furthermore, the bonding structure of multiple surfaces through the protrusion 210 has the advantage of increasing the bonding force between dissimilar insulating layers.

[0071] Furthermore, the cavity formation structure through a single insulating layer makes it easier to secure the cavity space and has the advantage of preventing eccentricity from occurring during the cavity formation process between dissimilar insulating layers.

[0072] Figure 7 shows a modified example of a cavity formation structure through a second insulating layer and a third insulating layer according to an embodiment of the present invention. Referring to Figure 7, in a structure in which a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 are stacked vertically, a first through-hole can be formed in the second insulating layer 22 during the process of forming the cavity 25, and a second through-hole can be formed inside the third insulating layer 23 on the inside of the first through-hole.

[0073] Due to the sagging of the third insulating layer 23 in the cavity formation region of the cavity 25, including the inner wall 26 of the second through hole, the second insulating layer 22 and the third insulating layer 23 may have regions with different vertical thicknesses.

[0074] Having described above that all components constituting embodiments of the present invention either combine together or operate in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the object of the present invention, all components may also selectively combine one or more to operate. Furthermore, terms such as “includes,” “constitutes,” or “has,” as described above, mean that the component may be inherent, and not exclude other components, unless otherwise stated. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not in an ideal or overly formal sense unless explicitly defined in the present invention.

[0075] The above description is merely illustrative of the technical concept of the present invention, and any person with ordinary skill in the art to which the present invention pertains can make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention should be interpreted in accordance with the appended claims, and all technical concepts within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention.

[0076] On the other hand, when a circuit board having the features of the invention described above is used in IT devices such as smartphones, server computers, and TVs, or in home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor packaging function, it can safely protect semiconductor chips from external moisture and contaminants, and can solve problems such as leakage current or electrical short circuits between terminals, or electrical open circuits at terminals supplying power to semiconductor chips. Furthermore, when it is responsible for signal transmission, it can solve noise problems. As a result, a circuit board having the features of the invention described above can maintain the stable function of IT devices and home appliances, thereby enabling the overall product and the circuit board to which the invention is applied to achieve functional integration or technical interdependence.

[0077] When a circuit board having the features of the invention described above is used in a transport device such as a vehicle, it can solve the problem of signal distortion transmitted to the transport device, or it can safely protect the semiconductor chip that controls the transport device from the outside, and it can solve the problems of leakage current or electrical short circuits between terminals, or electrical open circuits at terminals supplying power to the semiconductor chip, thereby further improving the stability of the transport device. Therefore, the transport device and the circuit board to which the present invention is applied can be functionally integrated or technically interconnected with each other.

Claims

1. The first insulating layer and A second insulating layer is disposed on the first insulating layer and includes a first through-hole, The present invention includes a third insulating layer disposed on the second insulating layer and including a second through-hole that overlaps the first through-hole perpendicularly, The inner wall of the second through-hole is a circuit board in which at least a portion overlaps the inner wall of the first through-hole perpendicularly.

2. The inner wall of the first through hole and the upper surface of the first insulating layer form a first angle. The circuit board according to claim 1, wherein the inner wall of the second through-hole and the upper surface of the first insulating layer form a second angle different from the first angle.

3. The circuit board according to claim 2, wherein the first angle and the second angle are each within 180°.

4. The first angle is obtuse, The circuit board according to claim 2, wherein the second angle is acute.

5. The first angle is obtuse, The circuit board according to claim 2, wherein the second angle is a right angle.

6. The first through-hole has a shape in which the width gradually decreases as it approaches the first insulating layer. The circuit board according to claim 1, wherein the second through-hole has a shape in which the width gradually increases as it approaches the first insulating layer.

7. The materials of the first insulating layer and the second insulating layer are different. The circuit board according to claim 1, wherein the material of the second insulating layer and the third insulating layer are the same.

8. The circuit board according to claim 7, wherein the second insulating layer and the third insulating layer are each PID (Photo Imageable Dielectric).

9. The circuit board according to claim 7, wherein the first insulating layer is a prepreg (PPG).

10. The circuit board according to claim 1, wherein the surface connecting the upper surface of the third insulating layer and the inner wall of the second through hole is a rounded surface.

11. The circuit board according to claim 1, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer or the thickness of the third insulating layer.

12. The circuit board according to claim 1, wherein at least a portion of the first inner wall and the second inner wall includes a curved surface.

13. The circuit board according to claim 1, wherein at least a portion of the third insulating layer is disposed on the surface of the first inner wall.

14. The circuit board according to claim 13, wherein at least a portion of the third insulating layer overlaps the second insulating layer in a horizontal direction.

15. The third insulating layer includes a protrusion, The circuit board according to claim 1, wherein the protruding portion overlaps the second insulating layer in the horizontal direction.

16. The first insulating layer includes a cavity, The circuit board according to claim 15, wherein the inner wall of the cavity includes a lower region that overlaps perpendicularly with the second insulating layer and an upper region that overlaps perpendicularly with the third insulating layer.

17. The circuit board according to claim 1, wherein the first through-hole and the second through-hole form cavities in which electronic elements are arranged.

18. The first insulating layer and A second insulating layer is disposed on the first insulating layer and includes a first through-hole, A third insulating layer is disposed on the second insulating layer and includes a second through-hole that overlaps perpendicularly with the first through-hole, Includes electronic elements disposed in the first through hole and the second through hole, A semiconductor package in which the inner wall of the second through-hole overlaps, at least in part, with the inner wall of the first through-hole in a perpendicular direction.

19. The inner wall of the first through hole and the upper surface of the first insulating layer form a first angle. The semiconductor package according to claim 18, wherein the inner wall of the second through-hole and the upper surface of the first insulating layer form a second angle different from the first angle.

20. The first angle is obtuse, The semiconductor package according to claim 19, wherein the second angle is acute.

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