Degradation diagnostic device, power conversion device, and degradation diagnostic method

Abstract

The present invention aims to provide a degradation diagnosis device, a power converter, and a degradation diagnosis method that can diagnose the degradation of a power converter with a simple configuration. [Solution] The degradation diagnosis device 11A includes a switching time calculation circuit 111A that calculates the switching time SWT of transistor Q, and a degradation diagnosis unit 112 that diagnoses the degradation of the power conversion unit 12 on which transistor Q is provided based on the switching time SWT calculated by the switching time calculation circuit 111A.

Description

Technical Field

[0001] The present invention relates to a deterioration diagnosis device, a power conversion device, and a deterioration diagnosis method.

Background Art

[0002] Patent Document 1 discloses a technique for accumulating time-series data of an on-voltage and an on-current as a pair and monitoring the deterioration state of a power conversion device. In the technique disclosed in Patent Document 1, the on-voltage is directly detected from a device provided in the power conversion device.

[0003] Patent Document 2 discloses a technique for estimating the overheating state of a semiconductor module based on the temperature relationship between the on-voltage and the current flowing through. In the technique disclosed in Patent Document 2, the on-voltage is detected between both terminals of the first terminal and the second terminal of a semiconductor device provided in the power conversion device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Generally, the on-voltage of a switching element such as an IGBT provided in the device disclosed in Patent Document 1 or the semiconductor device disclosed in Patent Document 2 is a very low voltage (for example, about several volts) compared to the element voltage in the off state (for example, several hundred volts or more). In order to detect the change amount of the on-voltage of the switching element and monitor the deterioration state of the power conversion device, it is required to be able to detect a change in voltage lower than the on-voltage (for example, several hundred millivolts or less).

[0006] Furthermore, in methods that directly detect the voltage between the two terminals of a switching element, in addition to a detection circuit that detects minute voltage changes in the switching element's on-voltage, it is also necessary to devise a way to isolate the detection circuit from the two terminals, which have a high voltage when the element is off. For this reason, conventional technology has the problem that the configuration of the detection circuit that detects the on-voltage of the switching element may become complicated.

[0007] The object of the present invention is to provide a degradation diagnosis device, a power conversion device, and a degradation diagnosis method that can diagnose the degradation of a power conversion unit with a simple configuration. [Means for solving the problem]

[0008] To achieve the above objective, a degradation diagnostic device according to one aspect of the present invention comprises a calculation unit for calculating the switching time of a switching element, and a diagnostic unit for diagnosing the degradation of a power conversion unit on which the switching element is provided, based on the switching time calculated by the calculation unit.

[0009] Furthermore, in order to achieve the above objective, a power conversion device according to one aspect of the present invention comprises a degradation diagnostic device according to the above aspect, the switching element, and the power conversion unit having the switching element.

[0010] Furthermore, in order to achieve the above objective, a degradation diagnosis method according to one aspect of the present invention calculates the switching time of a switching element and diagnoses the degradation of a power conversion unit equipped with the switching element based on the calculated switching time. [Effects of the Invention]

[0011] According to each aspect of the present invention, the deterioration of the power conversion unit can be diagnosed with a simple configuration. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram showing an example of a schematic configuration of a degradation diagnosis device and a power conversion device according to the first embodiment of the present invention. [Figure 2] This figure illustrates the principle of deterioration diagnosis using a deterioration diagnosis device according to the first embodiment of the present invention. [Figure 3] This figure illustrates a degradation diagnostic device and a power converter according to a first embodiment of the present invention, and schematically shows the change in the on-voltage of a switching element with respect to the number of power cycles. [Figure 4] This figure illustrates a degradation diagnostic device and a power converter according to a first embodiment of the present invention, and schematically shows the operating waveform of the power converter at the power cycle number PC0 shown in Figure 3. [Figure 5] This figure illustrates a degradation diagnostic device and a power converter according to a first embodiment of the present invention, and schematically shows the operating waveform of the power converter at the power cycle number PC1 shown in Figure 3. [Figure 6] This figure illustrates a degradation diagnostic device and a power converter according to a first embodiment of the present invention, and schematically shows the operating waveform of the power converter at the power cycle number PC2 shown in Figure 3. [Figure 7] This flowchart shows an example of the flow of a deterioration diagnosis method according to the first embodiment of the present invention. [Figure 8] This flowchart shows an example of the flow of the switching time calculation process in the degradation diagnosis method according to the first embodiment of the present invention. [Figure 9] This flowchart shows an example of the flow of the deterioration diagnosis process in the deterioration diagnosis method according to the first embodiment of the present invention. [Figure 10] This is a block diagram showing an example of a schematic configuration of a degradation diagnosis device and a power conversion device according to a second embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing an example of the general configuration of a semiconductor element and a printed circuit board provided in a power conversion device according to a third embodiment of the present invention. [Figure 12] This is a block diagram showing an example of a schematic configuration of a degradation diagnosis device and a power conversion device according to a third embodiment of the present invention. [Figure 13] This figure illustrates the principle of deterioration diagnosis using a deterioration diagnosis device according to a third embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view schematically showing an example of the schematic configuration of a semiconductor element and a printed circuit board provided in a power conversion device according to a fourth embodiment of the present invention. [Figure 15] FIG. 2 is a block diagram showing an example of the schematic configuration of a deterioration diagnosis device and a power conversion device according to a fourth embodiment of the present invention. MODE FOR CARRYING OUT THE INVENTION

[0013] Embodiments of the present invention exemplify devices and methods for embodying the technical idea of the present invention. The technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the components as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

[0014] [First Embodiment] A deterioration diagnosis device, a power conversion device, and a deterioration diagnosis method according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 9.

[0015] 1-1. Configuration of Power Conversion Device: The schematic configuration of a power conversion device 1A according to the present embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the schematic configuration of a power conversion device 1A and deterioration diagnosis devices 11AU and 11AL according to the present embodiment.

[0016] As shown in FIG. 1, the power conversion device 1A includes a deterioration diagnosis device 11AU for the upper arm and a deterioration diagnosis device 11AL for the lower arm according to the present embodiment. The power conversion device 1A includes a transistor QU (an example of a switching element) for the upper arm and a transistor QL (an example of a switching element) for the lower arm. The power conversion device 1A includes a power conversion unit 12 having transistors QU and QL.

[0017] The power conversion device 1A includes a control device 13, a gate drive circuit 14U and a temperature detection circuit 15U for the upper arm, a gate drive circuit 14L and a temperature detection circuit 15L for the lower arm, and a current detection unit 16.

[0018] The control device 13 includes a gate pulse signal generation unit 131U for the upper arm and a gate pulse signal generation unit 131L for the lower arm. The gate pulse signal generation unit 131U generates a gate pulse signal SgU for the upper arm that controls the gate drive circuit 14U. The gate pulse signal generation unit 131U outputs the generated gate pulse signal SgU to the gate drive circuit 14U. The gate pulse signal generation unit 131L generates a gate pulse signal SgL for the lower arm that controls the gate drive circuit 14L. The gate pulse signal generation unit 131L outputs the generated gate pulse signal SgL to the gate drive circuit 14L.

[0019] The power conversion unit 12 is located between the positive electrode line 10P and the negative electrode line 10N provided in the power conversion device 1A. The power conversion unit 12 operates as an inverter that converts the DC power supplied to the positive electrode line 10P and the negative electrode line 10N into AC power.

[0020] The power conversion unit 12 includes a semiconductor element 121U and a temperature detection element 122U for the upper arm, and a semiconductor element 121L and a temperature detection element 122L for the lower arm. The semiconductor elements 121U and 121L are connected in series between the positive electrode line 10P and the negative electrode line 10N. The semiconductor element 121U is connected to the positive electrode line 10P, and the semiconductor element 121L is connected to the negative electrode line 10N.

[0021] Semiconductor element 121U has a transistor QU for the upper arm, a freewheeling diode FWDU, a drain terminal DU, source terminals S1U and S2U, and a gate terminal GU. Semiconductor element 121L has a transistor QL for the lower arm, a freewheeling diode FWDL, a drain terminal DL, source terminals S1L and S2L, and a gate terminal GL. Hereinafter, "semiconductor element 121U and semiconductor element 121L" may be collectively referred to as "semiconductor element 121", "transistor QU and transistor QL" may be collectively referred to as "transistor Q", and "freewheeling diode FWDU and freewheeling diode FWDL" may be collectively referred to as "freewheeling diode FWD". "Drain terminal DU and drain terminal DL" may be collectively referred to as "drain terminal D", "source terminal S1U and source terminal S1L" may be collectively referred to as "source terminal S1", "source terminal S2U and source terminal S2L" may be collectively referred to as "source terminal S", and "gate terminal GU and gate terminal GL" may be collectively referred to as "gate terminal G". Furthermore, the "gate drive circuit 14U and gate drive circuit 14L" may be collectively referred to as "gate drive circuit 14".

[0022] Transistor Q is a wide-bandgap semiconductor device whose main material is, for example, at least one of silicon carbide, gallium nitride, gallium oxide, and diamond. A freewheeling diode FWD is connected in antiparallel to transistor Q. The drain of transistor Q and the cathode of the freewheeling diode FWD are connected to each other and connected to the drain terminal D. The source of transistor Q and the anode of the freewheeling diode FWD are connected to each other and connected to the source terminal S. The gate of transistor Q is connected to the gate terminal G.

[0023] The gate terminal G and source terminal S2 of transistor Q are connected to the output terminals of the gate drive circuit 14. As a result, transistor Q transitions between an on state and an off state depending on the voltage level of the gate-source voltage VGS, which is the voltage difference between the voltage level of the gate drive signal input to the gate terminal G from the gate drive circuit 14 and the voltage level of the source signal input to the source terminal S2.

[0024] A load device (not shown), such as a motor, which is to be driven by the power conversion device 1A, is connected to the connection between semiconductor element 121U and semiconductor element 121L. The power conversion unit 12 converts the DC power supplied to the positive side line 10P and the negative side line 10N into AC power by having transistors QU and QL repeatedly switch between on and off states at predetermined timings and in predetermined combinations. The power conversion unit 12 drives the load device by supplying the AC power converted from the DC power through the connection between semiconductor element 121U and semiconductor element 121L.

[0025] The current detection unit 16 is positioned between the power conversion unit 12 and the load device. The current detection unit 16 detects the element current IL flowing between the connection between semiconductor element 121U and semiconductor element 121L and the load device, and outputs the detected current value ILd, which is the current value of the detected element current IL, to the control device 13.

[0026] The temperature sensing element 122U for the upper arm is located, for example, near the transistor QU. The temperature sensing element 122U is composed of, for example, a temperature-sensing diode. The temperature sensing element 122U detects the temperature of the transistor QU by utilizing the characteristic that its resistivity changes depending on the temperature.

[0027] The temperature sensing element 122L for the lower arm is located, for example, near the transistor QL. The temperature sensing element 122L is composed of, for example, a temperature-sensing diode. The temperature sensing element 122L detects the temperature of the transistor QL by utilizing the characteristic that its resistivity changes depending on the temperature.

[0028] The temperature detection circuit 15U for the upper arm is connected to the temperature detection element 122U. The temperature detection circuit 15U receives the element temperature TPU, which is the temperature of transistor QU detected by the temperature detection element 122U. The temperature detection circuit 15U outputs the temperature detection value TPdU, which is the temperature value of the element temperature TPU input from the temperature detection element 122U, to the control device 13.

[0029] The temperature detection circuit 15L for the lower arm is connected to the temperature detection element 122L. The temperature detection circuit 15L receives the element temperature TPL, which is the temperature of transistor QL detected by the temperature detection element 122L. The temperature detection circuit 15L outputs the temperature detection value TPdL, which is the temperature value of the element temperature TPL input from the temperature detection element 122L, to the control device 13.

[0030] 1-2. Configuration of the deterioration diagnostic device: The schematic configuration of the deterioration diagnostic devices 11AU and 11AL according to this embodiment will be explained with reference to Figure 1.

[0031] As shown in Figure 1, the degradation diagnostic device 11AU for the upper arm includes a switching time calculation circuit 111AU for the upper arm, a degradation diagnostic unit 112U, and a data storage unit 113U. The degradation diagnostic device 11AL for the lower arm includes a switching time calculation circuit 111AL for the lower arm, a degradation diagnostic unit 112L, and a data storage unit 113L.

[0032] The switching time calculation circuit 111AU for the upper arm (an example of a calculation unit) calculates the switching time SWTU of transistor QU. The switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU induced by the rate of change of current when transistor QU switches. In this embodiment, the switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 17U of the wiring section on which transistor QU is provided. The wiring inductance 17U is a parasitic inductance generated in the wiring section on which the semiconductor element 121U is arranged and through which the element current IL flows. The wiring inductance of the wiring section may be the wiring inductance of either part of the wiring to which the drain (i.e., the drain terminal DU of semiconductor element 121U) and the source (i.e., the source terminal S1U of semiconductor element 121U) of transistor QU are connected in the power converter 1A. In this embodiment, the wiring inductance of the wiring section is the wiring inductance 17U of the wiring section between source terminal S1U and source terminal S2U. Details of the process for calculating the switching time SWTU in the switching time calculation circuit 111AU will be described later.

[0033] The upper arm data storage unit 113U (an example of a storage unit) stores switching time data SWTDU, which associates at least one of the element current IL flowing through transistor QU and the element temperature TPU (an example of temperature) of transistor QU with the switching time SWTU. The data storage unit 113U receives the switching time SWTU output from the switching time calculation circuit 111AU, the current detection value ILd of the element current IL output from the current detection unit 16, and the temperature detection value TPdU of the element temperature TPU output from the temperature detection circuit 15U. In this embodiment, the data storage unit 113U stores switching time data SWTDU, which associates both the element current IL flowing through transistor QU and the element temperature TPU of transistor QU, which are input from the current detection unit 16 and the temperature detection circuit 15U, with the switching time SWTU.

[0034] The data storage unit 113U stores the switching time data acquired during a predetermined period after the transistor QU starts operating as initial data IDU. Details of the switching time data SWTDU and initial data IDU stored in the data storage unit 113U will be described later.

[0035] The degradation diagnosis unit 112U for the upper arm (an example of a diagnosis unit) diagnoses the degradation of the power conversion unit 12, which is equipped with transistor QU, based on the switching time SWTU calculated by the switching time calculation circuit 111AU. The degradation diagnosis unit 112U compares the switching time data SWTDU stored in the data storage unit 113U with the initial data IDU to diagnose whether or not the power conversion unit 12 has degraded. Details of the degradation diagnosis of the power conversion unit 12 by the degradation diagnosis unit 112U will be described later.

[0036] The switching time calculation circuit 111AL for the lower arm (an example of a calculation unit) calculates the switching time SWTL of transistor QL. The switching time calculation circuit 111AL calculates the switching time SWTL of transistor QL using the induced voltage VLmL induced by the rate of change of current when transistor QL switches. In this embodiment, the switching time calculation circuit 111AL calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 17L of the wiring section on which transistor QL is provided. The wiring inductance 17L is a parasitic inductance generated in the wiring section on which the semiconductor element 121L is arranged and through which the element current IL flows. The wiring inductance of the wiring section may be the wiring inductance of either part of the wiring to which the drain (i.e., the drain terminal DL of semiconductor element 121L) and the source (i.e., the source terminal S1L of semiconductor element 121L) of transistor QL are connected in the power converter 1A. In this embodiment, the wiring inductance of the wiring section is the wiring inductance 17L of the wiring section between source terminal S1L and source terminal S2L. Details of the process for calculating the switching time SWTL in the switching time calculation circuit 111AL will be described later.

[0037] The lower arm data storage unit 113L (an example of a storage unit) stores switching time data SWTDL, which associates at least one of the element current IL flowing through transistor QL and the element temperature TPL of transistor QL (an example of a temperature) with the switching time SWTL. The data storage unit 113L receives the switching time SWTL output from the switching time calculation circuit 111AL, the current detection value ILd of the element current IL output from the current detection unit 16, and the temperature detection value TPdL of the element temperature TPL output from the temperature detection circuit 15L. In this embodiment, the data storage unit 113L stores switching time data SWTDL, which associates both the element current IL flowing through transistor QL and the element temperature TPL of transistor QL, which are input from the current detection unit 16 and the temperature detection circuit 15L, with the switching time SWTL.

[0038] The data storage unit 113L stores the switching time data acquired during a predetermined period after the transistor QL starts operating as initial data IDL. Details of the switching time data SWTDL and initial data IDL stored in the data storage unit 113L will be described later.

[0039] The degradation diagnosis unit 112L for the lower arm (an example of a diagnosis unit) diagnoses the degradation of the power conversion unit 12, which is equipped with transistor QL, based on the switching time SWTL calculated by the switching time calculation circuit 111AL. The degradation diagnosis unit 112L compares the switching time data SWTDL stored in the data storage unit 113L with the initial data IDL to diagnose whether or not the power conversion unit 12 has degraded. Details of the degradation diagnosis of the power conversion unit 12 by the degradation diagnosis unit 112L will be described later.

[0040] Hereinafter, "switching time calculation circuit 111AU and switching time calculation circuit 111AL" may be collectively referred to as "switching time calculation circuit 111A," "degradation diagnosis unit 112U and degradation diagnosis unit 112L" may be collectively referred to as "degradation diagnosis unit 112," and "data storage unit 113U and data storage unit 113L" may be collectively referred to as "data storage unit 113." Furthermore, "switching time SWTU and switching time SWTL" may be collectively referred to as "switching time SWT," "element temperature TPU and element temperature TPL" may be collectively referred to as "element temperature TP," and "temperature detection value TPdU and temperature detection value TPdL" may be collectively referred to as "temperature detection value TPd." Furthermore, "switching time data SWTDU and switching time data SWTDL" may be collectively referred to as "switching time data SWTD." Furthermore, "initial data IDU and initial data IDL" may be collectively referred to as "initial data ID."

[0041] Here, we will explain the switching time data SWTD stored in the data storage unit 113. The data storage unit 113 stores switching time data SWTD, which associates both the current detection value ILd of the element current IL flowing through transistor Q and the temperature detection value TPd of the element temperature TP of transistor Q with the switching time SWT.

[0042] Specifically, for example, during a predetermined period after the actual use (actual operation) of the power converter 1A begins for the first time (for example, immediately after actual use begins), each time the element current IL flowing through transistor Q and the element temperature TP of transistor Q are changed, the current detection value ILd of the element current IL, the temperature detection value TPd of the element temperature TP, and the switching time SWT are acquired. The data storage unit 113U stores the acquired current-temperature dependency characteristics, which associate the acquired switching time SWT with the acquired current detection value ILd of the element current IL and the temperature detection value TPd of the element temperature TP, as an initial data ID. The "predetermined period after transistor Q starts operating" may not be immediately after transistor Q starts operating, but may be, for example, a period before aging degradation occurs.

[0043] Furthermore, the data storage unit 113 may store the switching time data SWTD acquired before the predetermined period described above after the transistor Q starts operating as the initial data ID. In this case, "before the predetermined period" may be, for example, a period of experimental operation before actual use (i.e., before market introduction).

[0044] During the predetermined period described above, or prior to that predetermined period, the data storage unit 113 may store an initial data ID when the power converter 1A is new, during maintenance of the power converter 1A, or when transistor Q is new, such as when transistor Q is replaced.

[0045] Furthermore, the data storage unit 113 may store switching time data SWTD as the initial data ID, which is based on the characteristics of the switching time SWT that depend on at least one of the element current IL and element temperature TP of the transistor Q. In this case, the switching time data SWTD is obtained from the characteristics of the switching time SWT based on the design value of the power converter 1A, rather than from the characteristics of the switching time SWT based on measured values.

[0046] Next, we will specifically explain the degradation diagnosis performed by the degradation diagnosis unit 112, which uses such switching time data SWTD. The degradation diagnosis unit 112 receives the latest switching time data SWTD and an initial data ID from the data storage unit 113, which includes the current detection value ILd of the element current IL and the temperature detection value TPd of the element temperature TP at the time the latest switching time data SWTD was acquired. The latest switching time data SWTD is the last switching time data SWTD stored from the present time.

[0047] The degradation diagnosis unit 112 diagnoses that the power conversion unit 12 is degraded if the absolute value of the difference between the switching time SWT included in the switching time data SWTD input from the data storage unit 113 and the switching time SWT included in the initial data ID is greater than a predetermined threshold. On the other hand, the data storage unit 113 diagnoses that the power conversion unit 12 is not degraded if the absolute value of the difference is the same as or less than the predetermined threshold. The principle of degradation diagnosis in the degradation diagnosis unit 112 will be described later.

[0048] The degradation diagnosis units 112U, 112L and the data storage units 113U, 113L are provided in the control device 13. The control device 13 has a processor (not shown) which is composed of, for example, a central processing unit (CPU). The processor functions as the degradation diagnosis units 112U, 112L, the data storage units 113U, 113L, and the gate pulse signal generation units 131U, 131L by executing a predetermined program stored in a storage unit (not shown) as one of the computer programs.

[0049] 1-3. Principles of deterioration diagnosis: The principle of degradation diagnosis in the degradation diagnosis device 11A according to this embodiment will be explained with reference to Figure 1, and with reference to Figures 2 and 3. Figure 2 is a diagram illustrating the principle of degradation diagnosis in the degradation diagnosis device 11A. Figure 2(a) is a schematic diagram showing the semiconductor element 121 installed in the power conversion unit 12. Figure 2(b) is a diagram showing the semiconductor element 121 represented as a resistive element. Figure 3 is a graph showing the relationship between the number of power cycles for transistor Q and the drain-source voltage VDS(on) when transistor Q is in the ON state. In the graph shown in Figure 3, the horizontal axis represents the number of power cycles, and the vertical axis represents the drain-source voltage VDS(on) when transistor Q is in the ON state. In the graph shown in Figure 3, the horizontal axis represents the increase in the number of power cycles from left to right, and the vertical axis represents the increase in the drain-source voltage VDS(on) from bottom to top.

[0050] As shown in Figure 2(a), the semiconductor element 121 is soldered by solder 125 onto a conductive pattern 126 formed on, for example, an insulating substrate (not shown). The semiconductor element 121 is connected to a predetermined terminal (not shown) via a wire 123 joined by, for example, wire bonding. The drain terminal DU of the semiconductor element 121 (not shown in Figure 2, see Figure 1) is joined to the wire 123, and the source terminal S1 of the semiconductor element 121 (not shown in Figure 2, see Figure 1) is connected to the solder 125.

[0051] In the upper arm, the element current IL flows from the positive side line 10P (not shown in Figure 2, see Figure 1) through a predetermined terminal 127, conductive pattern 126, solder 125, semiconductor element 121U, and wire 123 to the load device (not shown). On the other hand, in the lower arm, the element current IL flows from the load device (not shown) through wire 123, semiconductor element 121L, solder 125, conductive pattern 126, and predetermined terminal 127 to the negative side line 10N (not shown in Figure 2, see Figure 1). In this way, the element current IL flows through wire 123 and solder 125 in conjunction with the operation of semiconductor element 121.

[0052] One of the wires 123 and solder 125 is connected to the drain terminal D of the semiconductor element 121, and the other of the wires 123 and solder 125 is connected to the source terminal S1 of the semiconductor element 121. Therefore, the semiconductor element 121 in the direction in which the element current IL flows can be represented as a series circuit of three resistive elements, as shown in Figure 2(b): the resistance R123 of the wire 123, the on-resistance Rq of the transistor Q (not shown in Figure 2, see Figure 1) provided on the semiconductor element 121, and the resistance R125 of the solder 125, all connected in series.

[0053] Incidentally, repeated thermal stress is generated at the junction 124 and solder 125 where the wire 123 is joined to the semiconductor element 121 due to the switching operation of transistor Q and the current conduction associated with this switching operation. As a result, the junction 124 and solder 125 of the wire 123 deteriorate. Consequently, for example, a crack CK1 (see Figure 2(a)) may occur at the junction 124 of the wire 123, or a crack CK2 (see Figure 2(a)) may occur at the solder 125. The resistance value of the junction 124 of the wire 123 increases when crack CK1 occurs compared to before crack CK1 occurred, and the magnitude changes depending on the extent of crack CK1. Similarly, the resistance value of the solder 125 increases when crack CK2 occurs compared to before crack CK2 occurred, and the magnitude changes depending on the extent of crack CK2.

[0054] The element current IL flowing through the semiconductor element 121 is a constant current corresponding to the degree to which transistor Q is ON. Therefore, if a crack CK1 occurs in the junction 124, the voltage value V123 at the drain terminal D including the junction 124 will be greater than when crack CK1 does not occur. Similarly, if a crack CK2 occurs in the solder 125, the voltage value V125 at the source terminal S1 including the solder 125 will be greater than when crack CK2 does not occur. Assume that transistor Q is ON and element current IL flows through the semiconductor element 121 when at least one of cracks CK1 and CK2 has occurred. In this case, the voltage between the drain terminal D and source terminal S1 of the semiconductor element 121 (drain-source voltage VDS(on)) will be greater than when cracks CK1 and CK2 do not occur.

[0055] When transistor Q is turned on, the drain-source voltage VDS(on) is the voltage between the drain terminal D and source terminal S1 of semiconductor element 121 at the time the switching operation is completed. On the other hand, when transistor Q is turned off, the drain-source voltage VDS(on) is the voltage between the drain terminal D and source terminal S1 of semiconductor element 121 at the time the switching operation starts. When transistor Q is in the off state, the voltage between the drain terminal D and source terminal S1 of semiconductor element 121 is higher than the drain-source voltage VDS(on).

[0056] Therefore, when transistor Q is operating normally, if at least one of cracks CK1 or CK2 occurs, the change in voltage between the drain terminal D and the source terminal S1 during the switching operation of transistor Q becomes smaller than when cracks CK1 and CK2 do not occur. As a result, the switching time SWT of transistor Q becomes shorter when cracks CK1 and CK2 are present than when they are not. The occurrence of cracks CK1 and CK2 corresponds to the deterioration of the power conversion unit 12 (not shown in Figure 2, see Figure 1). Therefore, the deterioration diagnostic device 11A according to this embodiment (not shown in Figure 2, see Figure 1) diagnoses the deterioration of the power conversion unit 12 by utilizing the phenomenon in which the switching time SWT of transistor Q changes in response to cracks CK1 and CK2.

[0057] The joint 124 and solder 125 of wire 123 deteriorate as the number of power cycles increases, causing cracks CK1 and CK2 to occur and increasing the resistance. Therefore, as shown in Figure 3, the drain-source voltage VDS(on) of semiconductor element 121 when transistor Q is ON increases as the number of power cycles of transistor Q increases. The switching time SWT of transistor Q decreases with increasing drain-source voltage VDS(on). For example, the initial data ID is acquired at power cycle number PC0 and stored in the data storage unit 113 (not shown in Figure 2, see Figure 1). The initial data ID may be acquired within a range of power cycle numbers where the drain-source voltage VDS(on) is the same as the value at power cycle number PC0.

[0058] As the drain-source voltage VDS(on) increases due to the progression of degradation at least one of the junction 124 of wire 123 and the solder 125, the switching time SWT of transistor Q becomes shorter than its initial value. The degradation diagnostic device 11A detects the event of the switching time SWT becoming shorter than its initial value by utilizing the induced voltage generated in the wiring inductance 17 (not shown in Figure 2, see Figure 1) (details will be described later). Therefore, the degradation diagnostic device 11A can diagnose the degradation of the power conversion unit 12 without directly detecting the drain-source voltage between the drain terminal D and source terminal S1 of the semiconductor element 121. As a result, the degradation diagnostic device 11A does not require a detection circuit to detect minute voltage changes in the on-voltage of transistor Q, nor a circuit to isolate it from the off-state transistor Q. Consequently, the degradation diagnostic device 11A can simplify its circuit configuration.

[0059] 1-4. Operation of the degradation diagnostic device and power converter: The operation of the degradation diagnostic device 11A and the power converter 1A according to this embodiment will be explained with reference to Figures 1 to 3 and Figures 4 to 6. Figure 4 is a timing chart showing a portion of the operating waveform of the power converter 1A when transistor Q is turned off at power cycle number PC0 shown in Figure 3. Figure 5 is a timing chart showing a portion of the operating waveform of the power converter 1A when transistor Q is turned off at power cycle number PC1 shown in Figure 3. Figure 6 is a timing chart showing a portion of the operating waveform of the power converter 1A when transistor Q is turned off at power cycle number PC2 shown in Figure 3.

[0060] In Figures 4 through 6, "Sg" represents the gate pulse signal, and "VGS" represents the gate-source voltage, which is the voltage between the gate terminal G and source terminal S2 (gate and source of transistor Q) of semiconductor element 121. In Figures 4 through 6, "VDS" represents the drain-source voltage, which is the voltage between the drain terminal D and source terminal S1 (drain and source of transistor Q) of semiconductor element 121. In Figures 4 through 6, "IL" represents the element current (i.e., drain-source current) flowing through transistor Q. In Figures 4 through 6, "VLm" represents the induced voltage generated in the wiring inductance 17. In Figures 4 through 6, "SWT" represents the switching time of transistor Q.

[0061] In the semiconductor element 121 for the upper arm, the reference potential of the drain-source voltage is the midpoint voltage between the positive electrode line 10P and the negative electrode line 10N, but in Figures 4 to 6, it is represented as 0V for the sake of explanation.

[0062] As shown in Figures 4 to 6, at time t1, the voltage level of the gate pulse signal Sg output from the gate pulse signal generation unit 131 (see Figure 1) switches from a high level to a low level. The switching time calculation circuit 111A (see Figure 1) receives the gate pulse signal Sg as input. Therefore, the switching time calculation circuit 111A starts measuring the switching time of transistor Q from the timing when the voltage level of the gate pulse signal Sg switches from a high level to a low level (time t1 in Figures 4 to 6).

[0063] The gate drive circuit 14 (see Figure 1) outputs a gate drive signal between the gate terminal G and source terminal S2 of the semiconductor element 121 to turn off transistor Q, based on the fact that the voltage level of the gate pulse signal Sg input from the gate pulse signal generation unit 131 becomes low. As a result, the gate-source voltage VGS applied between the gate terminal G and source terminal S2 of the semiconductor element 121 (i.e., between the gate and source of transistor Q) begins to decrease from time t2. The gate drive signal that switches transistor Q is generated in the gate drive circuit 14 based on the gate pulse signal Sg. Therefore, the gate pulse signal Sg corresponds to an example of a control signal that controls transistor Q.

[0064] The gate-source voltage VGS applied to transistor Q reaches the Miller voltage at time t3. When the gate-source voltage VGS applied to transistor Q reaches the Miller voltage, the drain-source voltage VDS applied between the drain terminal D and source terminal S1 of semiconductor element 121 (i.e., between the drain and source of transistor Q) begins to rise from the drain-source voltage VDS(on) when transistor Q is ON.

[0065] As the drain-source voltage VDS rises and the Miller effect disappears at time t4, the element current IL (i.e., drain-source current) flowing through transistor Q begins to decrease. As the element current IL flowing through transistor Q decreases, an induced voltage VLm is generated in the wiring inductance 17, depending on the rate of change of the element current IL.

[0066] Even after time t4, the gate-source voltage VGS at semiconductor element 121 (i.e., transistor Q) decreases, while the drain-source voltage VDS at semiconductor element 121 (i.e., transistor Q) continues to rise. After an overshoot, the drain-source voltage VDS converges to the drain-source voltage VDS(off) when transistor Q is in the off state.

[0067] When the gate-source voltage VGS in semiconductor element 121 (i.e., transistor Q) falls below the threshold voltage Vth of transistor Q at time t5, transistor Q turns off, and the element current IL (i.e., drain-source current) stops flowing. When the element current IL stops flowing, the induced voltage VLm that was present in the wiring inductance 17 disappears, and the voltage value becomes 0V.

[0068] Thus, the timing at which the induced voltage VLm generated in the wiring inductance 17 disappears is the timing at which transistor Q turns off and the switching operation ends. The induced voltage VLm generated in the wiring inductance 17 is input to the switching time calculation circuit 111A (see Figure 1). Therefore, when the induced voltage VLm input from the wiring inductance 17 becomes 0V, the switching time calculation circuit 111A stops measuring the switching time. The switching time calculation circuit 111A outputs the period from the time t1 when the switching time measurement started to the time t5 when the switching time measurement ended as the switching time SWT to the data storage unit 113 (see Figure 1).

[0069] As described above, when transistor Q is operating normally, if at least one of the junction 124 and solder 125 of wire 123 (see Figure 2(a)) deteriorates or cracks CK1 and CK2 occur, the amount of change in the drain-source voltage VDS during the switching operation of transistor Q becomes smaller than when there is no deterioration or cracks CK1 and CK2 have not occurred. Furthermore, even if cracks CK1 and CK2 have not occurred in at least one of the junction 124 and solder 125, the amount of change in the drain-source voltage VDS during the switching operation of transistor Q becomes smaller the greater the degree of deterioration compared to the initial state. Moreover, when transistor Q is operating normally, the rate of change of the drain-source voltage VDS accompanying the operation of transistor Q is almost the same regardless of the degree of deterioration of the junction 124 and solder 125 or the presence or absence of cracks CK1 and CK2.

[0070] The value of power cycle number PC0 is smaller than the values ​​of power cycle numbers PC1 and PC2, respectively, and the value of power cycle number PC1 is smaller than the value of power cycle number PC2. Therefore, the drain-source voltage VDS(on) at power cycle number PC0 (see Figure 4) is lower than the drain-source voltage VDS(on) at power cycle numbers PC1 and PC2, respectively (see Figures 5 and 6). Also, the drain-source voltage VDS(on) at power cycle number PC1 (see Figure 5) is lower than the drain-source voltage VDS(on) at power cycle number PC2 (see Figure 6). Therefore, the switching time SWT0 at power cycle number PC0 (see Figure 4) is longer than the switching times SWT1 and SWT2 at power cycle numbers PC1 and PC2, respectively (see Figures 5 and 6). Also, the switching time SWT1 at power cycle number PC1 (see Figure 5) is longer than the switching time SWT2 at power cycle number PC2 (see Figure 6).

[0071] Deterioration of wire 123 and solder 125 corresponds to deterioration of the power conversion unit 12. Therefore, the deterioration diagnostic device 11A can diagnose whether or not the power conversion unit 12 is deteriorating based on the length of the switching time SWT which changes due to the deterioration of wire 123 and solder 125.

[0072] 1-5. Methods for diagnosing deterioration: The degradation diagnosis method using the degradation diagnosis device 11A according to this embodiment will be explained with reference to Figures 1 and 4 to 6, and with reference to Figures 7 to 9. Figure 7 is a flowchart showing an example of the flow of the degradation diagnosis method according to this embodiment. Figure 8 is a flowchart showing an example of the flow of the switching time calculation process in the degradation diagnosis method according to this embodiment. Figure 9 is a flowchart showing an example of the flow of the degradation diagnosis process in the degradation diagnosis method according to this embodiment.

[0073] As shown in Figure 7, in step ST10, the data storage unit 113 (see Figure 1) stores the initial data ID acquired based on the operation of transistor Q, and then proceeds to the processing in step ST20. The data storage unit 113 stores the switching time data acquired during a predetermined period (for example, the number of power cycles PC0 (see Figure 3)) from the start of operation of transistor Q as the initial data ID.

[0074] In step ST20, the switching time calculation circuit 111A (see Figure 1) calculates the switching time SWT of transistor Q and proceeds to the process in step ST30. Specifically, the switching time calculation circuit 111A calculates the switching time SWT using the induced voltage VLm (see Figures 4 to 6) induced by the rate of change of current when transistor Q switches, and the gate pulse signal Sg (see Figures 4 to 6).

[0075] In step ST30, the degradation diagnosis unit 112 diagnoses the degradation of the power conversion unit 12, which is equipped with transistor Q, based on the switching time SWT calculated in step ST20, and proceeds to the process in step ST40.

[0076] In step ST40, if the degradation diagnosis unit 112 diagnosed in step ST30 that the power conversion unit 12 was degraded (step ST40: YES), it proceeds to step ST50. On the other hand, if the degradation diagnosis unit 112 diagnosed in step ST30 that the power conversion unit 12 was not degraded (step ST40: NO), it returns to the process of step ST20.

[0077] In step ST50, the degradation diagnostic device 11A (see Figure 1) performs a degradation notification process to notify that the power conversion unit 12 is degraded, and then terminates the degradation diagnostic process. The degradation diagnostic device 11A may also notify of the degradation via the control device 13 (see Figure 1), for example, by emitting light. Alternatively, based on the fact that the degradation diagnostic device 11A has performed the degradation diagnostic process, the control device 13 may cause the gate pulse signal generation unit 131 to output a gate pulse signal Sg to the gate drive circuit 14 (see Figure 1) to set transistor Q to the off state, thereby forcibly switching transistor Q to the off state.

[0078] As shown in Figure 8, when the switching time calculation process (step ST20) is started, in step ST201, the switching time calculation circuit 111A (see Figure 1) determines whether or not a gate pulse signal Sg (see Figure 1) has been input from the gate drive circuit 14. For example, when the switching time calculation circuit 111A is calculating the switching time when transistor Q is turned off, it determines that a gate pulse signal Sg has been input when the voltage level switches from a high level to a low level (step ST201: YES), and proceeds to the process in step ST202. On the other hand, when the switching time calculation circuit 111A is calculating the switching time when transistor Q is turned off, it determines that a gate pulse signal Sg has not been input if the voltage level of the gate pulse signal Sg does not switch (step ST201: NO), and terminates the switching time calculation process and proceeds to the degradation diagnosis process (step ST30) shown in Figure 7.

[0079] In step ST202, the switching time calculation circuit 111A starts measuring the switching time SWT of transistor Q and proceeds to the process in step ST203. The switching time calculation circuit 111A has, for example, a counter (not shown) that counts up at a predetermined period, and operates this counter to start measuring the switching time SWT.

[0080] In step ST203, the switching time calculation circuit 111A determines whether the induced voltage VLm input from the wiring inductance 17 (see Figure 1) has disappeared. If the switching time calculation circuit 111A determines that the induced voltage VLm input from the wiring inductance 17 has disappeared (for example, the voltage value of the induced voltage VLm has become 0V) (step ST203: YES), it proceeds to the process in step ST204. On the other hand, if the switching time calculation circuit 111A determines that no induced voltage VLm is input from the wiring inductance 17, or that the induced voltage VLm input from the wiring inductance 17 has not disappeared (for example, the voltage value of the induced voltage VLm is greater than 0V) (step ST203: NO), it repeats the process in step ST203.

[0081] In step ST204, the switching time calculation circuit 111A finishes measuring the switching time SWT of transistor Q and proceeds to the process in step ST205.

[0082] In step ST205, the switching time calculation circuit 111A calculates the time from the input of the gate pulse signal Sg until the induced voltage VLm disappears as the switching time SWT, outputs the calculated switching time SWT to the data storage unit 113, and ends the switching time calculation process to proceed to the degradation diagnosis process (step ST30) shown in Figure 7. The switching time calculation circuit 111A calculates the switching time SWT by multiplying, for example, the period in which the counter counts up by the number of counts from the input of the gate pulse signal Sg until the induced voltage VLm disappears. In this way, the switching time calculation circuit 111A calculates the switching time SWT using the induced voltage VLm generated in the wiring inductance 17 of the wiring section where the transistor Q is provided.

[0083] In this way, the switching time calculation circuit 111A calculates the switching time SWT through the processing from step ST201 to step ST205 using the induced voltage VLm induced by the rate of change of current when transistor Q switches and the gate pulse signal Sg that controls transistor Q.

[0084] As shown in Figure 9, when the degradation diagnosis process (step ST30) is started, in step ST301, the data storage unit 113 determines whether or not the switching time SWT was calculated in the switching time calculation process (step ST20) shown in Figure 7. For example, if the switching time SWT is input from the switching time calculation circuit 111A, the data storage unit 113 determines that the switching time SWT has been calculated (step ST301: YES) and proceeds to the process in step ST302. On the other hand, for example, if the switching time SWT is not input from the switching time calculation circuit 111A, the data storage unit 113 determines that the switching time SWT has not been calculated (step ST301: NO), terminates the degradation diagnosis process, and proceeds to the process in step ST40 shown in Figure 7.

[0085] In step ST302, the data storage unit 113 acquires and stores the current detection value ILd of the current element current IL from the current detection unit 16 (see Figure 1), and then proceeds to the processing in step ST303. The current time refers to the time when the switching time SWT is calculated. The degradation diagnosis unit 112 stores the current detection value ILd as, for example, a voltage value.

[0086] In step ST303, the data storage unit 113 acquires and stores the temperature detection value TPd of the element temperature TP at the present time from the temperature detection circuit 15 (see Figure 1), and then proceeds to the processing in step ST304. The present time refers to the time when the switching time SWT is calculated. The degradation diagnosis unit 112 stores the temperature detection value TPd, for example, as a voltage value.

[0087] In step ST304, the data storage unit 113 stores switching time data SWTD, which associates the current detection value ILd of the element current IL stored in step ST302 and the temperature detection value TPd of the element temperature TP stored in step ST303 with the switching time SWT input in step ST205 of the switching time calculation process (step ST20), and then proceeds to step ST305. In this way, the data storage unit 113 stores switching time data SWTD, which associates at least one (both in this embodiment) of the element current IL flowing through transistor Q and the element temperature TP of transistor Q with the switching time SWT. The data storage unit 113 outputs the switching time data SWTD stored in step ST304 to the degradation diagnosis unit 112.

[0088] In step ST305, the degradation diagnosis unit 112 obtains an initial data ID from the data storage unit 113 that includes the same or closest current detection value and temperature detection value as the current detection value ILd and temperature detection value TPd, respectively, included in the switching time data SWTD input from the data storage unit 113, and proceeds to the processing in step ST306.

[0089] In step ST306, the degradation diagnosis unit 112 determines whether the difference between the switching time data SWTD input in step ST205 (see Figure 8) and the initial data ID acquired in step ST304 is greater than a predetermined threshold. Specifically, the degradation diagnosis unit 112 determines whether the difference between the switching time SWT included in the switching time data SWTD and the switching time SWT included in the initial data ID is greater than a predetermined threshold. If the degradation diagnosis unit 112 determines that the difference is greater than the predetermined threshold (step ST306: YES), it proceeds to step ST307. On the other hand, if the degradation diagnosis unit 112 determines that the difference is the same as or less than the predetermined threshold (step ST306: NO), it proceeds to step ST308. In this way, the degradation diagnosis unit 112 diagnoses whether the power conversion unit 12 is degraded by comparing the accumulated switching time data SWTD and the initial data ID.

[0090] In step ST307, the degradation diagnosis unit 112 sets the state of the power conversion unit 12 to a degraded state, terminates the degradation diagnosis process, and proceeds to the process of step ST40 shown in Figure 7.

[0091] In step ST308, the degradation diagnosis unit 112 sets the state of the power conversion unit 12 to a state of no degradation, terminates the degradation diagnosis process, and proceeds to the process of step ST40 shown in Figure 7.

[0092] As described above, the degradation diagnosis device 11A according to this embodiment includes a switching time calculation circuit 111A that calculates the switching time SWT of transistor Q, and a degradation diagnosis unit 112 that diagnoses the degradation of the power conversion unit 12 on which transistor Q is provided based on the switching time SWT calculated by the switching time calculation circuit 111A.

[0093] Furthermore, the power conversion device 1A according to this embodiment comprises the degradation diagnostic device 11A according to this embodiment, a transistor Q, and a power conversion unit 12 having the transistor Q.

[0094] Furthermore, the degradation diagnosis method according to this embodiment calculates the switching time SWT of transistor Q and diagnoses the degradation of the power conversion unit 12 equipped with transistor Q based on the calculated switching time SWT.

[0095] By having such a configuration, the deterioration diagnosis device 11A, power converter 1A, and deterioration diagnosis method according to this embodiment can diagnose the deterioration of the power converter 12 with a simple configuration.

[0096] [Second Embodiment] A degradation diagnostic device, power converter, and degradation diagnostic method according to a second embodiment of the present invention will be described with reference to Figure 10. The degradation diagnostic device, power converter, and degradation diagnostic method according to this embodiment are characterized in that they calculate the switching time of the switching element using the induced voltage generated at the output terminal of the Rogowski coil, rather than the induced voltage generated in the wiring inductance.

[0097] 2-1. Configuration of the power converter: The schematic configuration of the power converter 1B according to this embodiment will be explained with reference to Figure 10. Figure 10 is a block diagram showing the schematic configuration of the power converter 1B and the degradation diagnostic devices 11BU and 11BL according to this embodiment. With regard to the components of the power converter 1B according to this embodiment, components that perform the same operations and functions as the power converter 1A according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted unless necessary.

[0098] As shown in Figure 10, the power converter 1B comprises the degradation diagnostic devices 11BU and 11BL according to this embodiment, transistors QU and QL, and a power conversion unit 12 having transistors QU and QL. The power converter 1B has the same configuration as the power converter 1A according to the first embodiment, except that the degradation diagnostic devices 11BU and 11BL have Rogowski coils 114U and 114L, so a detailed explanation is omitted.

[0099] 2-2. Configuration of the deterioration diagnostic device: The deterioration diagnostic devices 11BU and 11BL according to this embodiment will be described with reference to Figure 10. With regard to the components of the deterioration diagnostic devices 11BU and 11BL according to this embodiment, components that perform the same actions and functions as the deterioration diagnostic devices 11AU and 11AL according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted unless necessary.

[0100] As shown in Figure 10, the degradation diagnostic device 11BU comprises a switching time calculation circuit 111BU, a degradation diagnostic unit 112U, a data storage unit 113U, and a Rogowski coil 114U.

[0101] The Rogowski coil 114U detects the element current IL flowing through a transistor QU (an example of a switching element). The Rogowski coil 114U may be placed anywhere on the wiring through which the element current IL flows to the ON-state transistor QU. In this embodiment, the Rogowski coil 114U is placed between the positive electrode line 10P and the drain terminal DU of the semiconductor element 121U on which the transistor QU is provided. As a result, the Rogowski coil 114U can detect the element current IL (i.e., drain-source current) flowing through the transistor QU and generate an induced voltage VLmU at the output terminal corresponding to the detected element current IL.

[0102] The switching time calculation circuit 111BU (an example of a calculation unit) calculates the switching time SWTU using the induced voltage VLmU generated at the output terminal of the Rogowski coil 114U based on the rate of change of the element current IL detected when the transistor QU switches. The switching time calculation circuit 111BU uses the induced voltage VLm generated at the output terminal of the Rogowski coil 114U to calculate the switching time SWTU of the transistor QU by the same process as the switching time calculation circuit 111AU in the first embodiment described above.

[0103] The degradation diagnostic device 11BL comprises a switching time calculation circuit 111BL, a degradation diagnostic unit 112L, a data storage unit 113L, and a Rogowski coil 114L.

[0104] The Rogowski coil 114L detects the element current IL flowing through the transistor QL (an example of a switching element). The Rogowski coil 114L may be placed anywhere on the wiring through which the element current IL flows to the ON-state transistor QL. In this embodiment, the Rogowski coil 114L is placed between the connection between semiconductor element 121U and semiconductor element 121L and the drain terminal DL of the semiconductor element 121L on which the transistor QL is provided. As a result, the Rogowski coil 114L can detect the element current IL (i.e., drain-source current) flowing through the transistor QL and generate an induced voltage VLmL at the output terminal corresponding to the detected element current IL.

[0105] The switching time calculation circuit 111BL (an example of a calculation unit) calculates the switching time SWTL using the induced voltage VLmL generated at the output terminal of the Rogowski coil 114L based on the rate of change of the element current IL detected when the transistor QL switches. The switching time calculation circuit 111BL uses the induced voltage VLmL generated at the output terminal of the Rogowski coil 114L to calculate the switching time SWTL of the transistor QL by the same process as the switching time calculation circuit 111AL in the first embodiment described above.

[0106] The power converter 1B, like the power converter 1A according to the first embodiment, has wiring inductance on the wiring where transistors QU and QL are located. Therefore, an induced voltage is generated in the wiring inductance in the power converter 1B as well. In this embodiment and the first embodiment, the induced voltage can have any value as long as the point in time when the induced voltage disappears can be detected. The induced voltages VLmU and VLmL generated at the output terminals by the Rogowski coils 114U and 114L are large enough for the switching time calculation circuits 111BU and 111BL to detect the point in time when they disappear. Therefore, the switching time calculation circuits 111BU and 111BL do not utilize the induced voltage generated in the wiring inductance.

[0107] 2-3. Principles of Deterioration Diagnosis: The principle for diagnosing the degradation of the power conversion unit 12 in this embodiment is the same as the principle for diagnosing the degradation of the power conversion unit 12 in the first embodiment described above, so no explanation is provided.

[0108] 2-4. Operation of the degradation diagnostic device and power converter: The operation of the degradation diagnostic devices 11BU, 11BL and the power converter 1B according to this embodiment is the same as the operation of the degradation diagnostic devices 11AU, 11AL and the power converter 1A according to the first embodiment, except that the induced voltages VLmU and VLmL generated at the output terminals of the Rogowski coils 114U and 114L are used instead of the induced voltage generated in the wiring inductance, so a detailed explanation is omitted.

[0109] 2-5. Methods for diagnosing deterioration: The degradation diagnosis method according to this embodiment is the same as the degradation diagnosis method according to the first embodiment, except that in the processing from step ST201 to step ST205 (see Figure 8), the induced voltages VLmU and VLmL generated at the output terminals of the Rogowski coils 114U and 114L are used instead of the induced voltage generated in the wiring inductance, so a detailed explanation is omitted. That is, in the degradation diagnosis method according to this embodiment, the switching time calculation circuits 111AU and 111AL calculate the switching times SWTU and SWTL using the induced voltages VLmU and VLmL generated by the rate of change of the element current IL detected when transistors QU and QL switch, at the respective output terminals of the Rogowski coils 114U and 114L, which detect the element current IL flowing through transistors QU and QL.

[0110] As described above, the degradation diagnostic device 11BU, 11BL according to this embodiment includes a switching time calculation circuit 111BU, 111BL that calculates the switching times SWTU, SWTL of transistors QU, QL, and a degradation diagnostic unit 112U, 112L that diagnoses the degradation of the power conversion unit 12, which is equipped with transistors QU, QL, based on the switching times SWTU, SWTL calculated by the switching time calculation circuit 111BU, 111BL.

[0111] Furthermore, the present invention comprises a power conversion device 1B according to this embodiment, degradation diagnostic devices 11BU and 11BL according to this embodiment, transistors QU and QL, and a power conversion unit 12 having transistors QU and QL.

[0112] Furthermore, the degradation diagnosis method according to this embodiment calculates the switching times SWTU and SWTL of transistors QU and QL, and diagnoses the degradation of the power conversion unit 12, which is equipped with transistors QU and QL, based on the calculated switching times SWTU and SWTL.

[0113] By having such a configuration, the deterioration diagnostic devices 11BU, 11BL, power converter 1B, and deterioration diagnostic method according to this embodiment can diagnose the deterioration of the power converter 12 with a simple configuration.

[0114] [Third Embodiment] A degradation diagnostic device, power converter, and degradation diagnostic method according to a third embodiment of the present invention will be described with reference to Figures 11 to 13. The degradation diagnostic device, power converter, and degradation diagnostic method according to this embodiment are characterized in that the power converter includes surface-mount semiconductor elements. With regard to the components of the degradation diagnostic device and power converter according to this embodiment, components that perform the same operations and functions as the degradation diagnostic devices 11AU, 11AL and power converter 1A according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted unless necessary.

[0115] 2-1. Configuration of the power converter: The schematic configuration of the power conversion device according to this embodiment will be explained with reference to Figures 11 and 12. Figure 11 is a schematic cross-sectional view showing an example of the schematic configuration of surface-mount semiconductor elements 128U, 128L and printed circuit board 129C provided in the power conversion device 1C (see Figure 12) according to this embodiment. The surface-mount semiconductor elements 128U, 128L and printed circuit board 129C are provided in the power conversion unit 12C of the power conversion device 1C.

[0116] As shown in Figure 11, the power conversion unit 12C has a surface-mount semiconductor element 128U having a transistor QU (an example of a switching element) for the upper arm. The power conversion unit 12C also has a surface-mount semiconductor element 128L having a transistor QL (an example of a switching element) for the lower arm. The power conversion unit 12C has a printed circuit board (an example of a circuit board) 129C on which the surface-mount semiconductor elements 128U and 128L are mounted.

[0117] The surface-mount semiconductor element 128U includes a transistor QU, a drain terminal DU, a source terminal SU, and a sealing portion 1281. The drain terminal DU (an example of the first terminal) is exposed to the outer surface 1281a (an example of the first outer surface) of the surface-mount semiconductor element 128U when the element current flowing through the transistor QU is input to it. Specifically, the outer surface 1281a is the outer surface of the sealing portion 1281. The source terminal SU (an example of the second terminal) is exposed to the outer surface 1281a.

[0118] The drain (not shown) of transistor QU is connected to the drain terminal DU by a conductive junction member 1284a, and the source (not shown) of transistor QU is connected to the source terminal SU by a conductive junction member 1284b. As a result, transistor QU is electrically connected to the drain terminal DU and the source terminal SU, and when transistor QU is ON, the element current input from the drain terminal DU is output from the source terminal SU via transistor QU.

[0119] The sealing portion 1281 covers the transistor QU, the drain terminal DU, and the source terminal SU, leaving a portion of each of the drain terminal DU and source terminal SU exposed. The sealing portion 1281 may be, for example, a resin seal made of a molding material.

[0120] The surface-mount semiconductor element 128L includes a transistor QL, a drain terminal DL, a source terminal SL, and a sealing portion 1282. The drain terminal DL (an example of the first terminal) is exposed to the outer surface 1282a (an example of the first outer surface) of the surface-mount semiconductor element 128L, where the element current flowing through transistor QL is input. Specifically, the outer surface 1282a is the outer surface of the sealing portion 1282. The source terminal SL (an example of the second terminal) is exposed to the outer surface 1282a.

[0121] The drain (not shown) of transistor QL is connected to the drain terminal DL by a conductive junction member 1285a, and the source (not shown) of transistor QL is connected to the source terminal SL by a conductive junction member 1285b. As a result, transistor QL is electrically connected to the drain terminal DL and the source terminal SL, and when transistor QL is ON, the element current input from the drain terminal DL is output from the source terminal SL via transistor QL.

[0122] The sealing portion 1282 covers the transistor QL, the drain terminal DL, and the source terminal SL, leaving a portion of each of the drain terminal DL and source terminal SL exposed. The sealing portion 1282 may be, for example, a resin seal made of a molding material.

[0123] The printed circuit board 129C has wiring patterns 1291, 1292, and 1293, a positive terminal 1294, a negative terminal 1295, an intermediate terminal 1296, and an insulating portion 1297.

[0124] One end of the wiring pattern 1291 is electrically connected to the drain terminal DU of the surface-mount semiconductor element 128U. The other end of the wiring pattern 1291 is connected to the positive terminal 1294. One end of the wiring pattern 1291 is exposed on the outer surface 1297b of the printed circuit board 129C. One end of the wiring pattern 1291 is exposed at multiple locations on the outer surface 1297b. Solder 21a is formed to cover the exposed portion of one end of the wiring pattern 1291. Thus, one end of the wiring pattern 1291 and the solder 21a are electrically and mechanically connected. The drain terminal DU is placed on the solder 21a and is electrically and mechanically connected to the solder 21a. As a result, one end of the wiring pattern 1291 and the drain terminal DU are electrically connected via the solder 21a.

[0125] The other end of the wiring pattern 1291 is connected to the positive terminal 1294. The positive terminal 1294 is exposed on the outer surface 1297a of the printed circuit board 129C. As a result, the positive terminal 1294 is electrically connected to the drain terminal DU of the surface-mount semiconductor element 128U via the wiring pattern 1291 and solder 21a.

[0126] One end of the wiring pattern 1292 has a bifurcated shape, with the surface-mount semiconductor elements 128U and 128L facing each other, and is exposed at two locations on the outer surface 1297b of the printed circuit board 129C. One end of the wiring pattern 1292 is exposed on the surface-mount semiconductor element 128U side, and the other end of the wiring pattern 1292 is exposed on the surface-mount semiconductor element 128L side. Each of the two ends of the wiring pattern 1292 is exposed at, for example, multiple locations on the outer surface 1297b.

[0127] For example, solder 21b is formed to cover one exposed portion of one end of the wiring pattern 1292. Therefore, one end of the wiring pattern 1292 and the solder 21b are electrically and mechanically connected. The source terminal SU of the surface-mount semiconductor element 128U is placed on the solder 21b and is electrically and mechanically connected to the solder 21b. As a result, one end of the wiring pattern 1292 and the source terminal SU are electrically connected via the solder 21b.

[0128] For example, solder 22a is formed to cover the exposed portion of one end of the wiring pattern 1292. Therefore, the other end of the wiring pattern 1292 and the solder 22a are electrically and mechanically connected. The drain terminal DL of the surface-mount semiconductor element 128L is placed on the solder 22a and is electrically and mechanically connected to the solder 22a. As a result, the other end of the wiring pattern 1292 and the drain terminal DL are electrically connected via the solder 22a.

[0129] The other end of the wiring pattern 1292 is connected to the intermediate terminal 1296. The intermediate terminal 1296 is exposed on the outer surface 1297a of the printed circuit board 129C. As a result, the intermediate terminal 1296 is electrically connected to the source terminal SU of the surface-mount semiconductor element 128U via the wiring pattern 1292 and solder 21b. Furthermore, the intermediate terminal 1296 is electrically connected to the drain terminal DL of the surface-mount semiconductor element 128L via the wiring pattern 1292 and solder 22a. The source terminal SU and the drain terminal DL are connected to the intermediate terminal 1296 via the wiring pattern 1292. Therefore, the intermediate terminal 1296 corresponds to the connection point between the source terminal SU and the drain terminal DL.

[0130] One end of the wiring pattern 1293 is electrically connected to the source terminal SL of the surface-mount semiconductor element 128L. One end of the wiring pattern 1293 is exposed on the outer surface 1297b of the printed circuit board 129C. One end of the wiring pattern 1293 is exposed at multiple locations on the outer surface 1297b. Solder 22b is formed over the exposed portion of one end of the wiring pattern 1293. Thus, one end of the wiring pattern 1293 and the solder 22b are electrically and mechanically connected. The source terminal SL is placed on the solder 22b and is electrically and mechanically connected to the solder 22b. As a result, one end of the wiring pattern 1293 and the source terminal SL are electrically connected via the solder 22b.

[0131] The other end of the wiring pattern 1293 is connected to the negative terminal 1295. The negative terminal 1295 is exposed on the outer surface 1297a of the printed circuit board 129C. As a result, the negative terminal 1295 is electrically connected to the source terminal SL of the surface-mount semiconductor element 128L via the wiring pattern 1293 and solder 22b.

[0132] As will be explained in detail later, the positive terminal 1294 is connected to the positive line 10P (not shown in Figure 11, see Figure 12), the negative terminal 1295 is connected to the negative line 10N (not shown in Figure 11, see Figure 12), and the intermediate terminal 1296 is connected to a load device (not shown). Therefore, the surface-mount semiconductor element 128U and the surface-mount semiconductor element 128L are connected in series between the positive line 10P and the negative line 10N via the printed circuit board 129C. The surface-mount semiconductor element 128U is positioned on the positive line 10P side, and the surface-mount semiconductor element 128L is positioned on the negative line 10N side. Therefore, the surface-mount semiconductor element 128U corresponds to the semiconductor element for the upper arm, and the surface-mount semiconductor element 128L corresponds to the semiconductor element for the lower arm.

[0133] When the transistor QU for the upper arm is ON and the transistor QL for the lower arm is OFF, the element current input from the positive side line 10P via the positive side terminal 1294 passes through the wiring pattern 1291, the surface-mount semiconductor element 128U, and the wiring pattern 1292 and is output from the intermediate terminal 1296. Also, when the transistor QU for the upper arm is OFF and the transistor QL for the lower arm is ON, the element current input from the load device via the intermediate terminal 1296 passes through the wiring pattern 1292, the surface-mount semiconductor element 128L, and the wiring pattern 1293 and is output from the negative side terminal 1295.

[0134] Therefore, in the surface-mount semiconductor device 128U, the wiring pattern 1291 corresponds to an example of a first wiring pattern configured to be electrically connected to the drain terminal DU (an example of a first terminal) of the surface-mount semiconductor device 128U, allowing device current to flow. Furthermore, in the surface-mount semiconductor device 128U, the positive terminal 1294 corresponds to an example of a third terminal connected to the wiring pattern 1291, exposed on the outer surface 1297a (an example of a second outer surface) of the printed circuit board 129C, and receiving device current. In addition, in the surface-mount semiconductor device 128U, the wiring region 1292U from the source terminal SU to the intermediate terminal 1296 of the wiring pattern 1292 corresponds to an example of a second wiring pattern electrically connected to the source terminal SU, allowing device current to flow. Moreover, in the surface-mount semiconductor device 128U, the intermediate terminal 1296 corresponds to an example of a fourth terminal connected to the wiring region 1292U, exposed on the outer surface 1297a, and outputting device current.

[0135] On the other hand, in the surface-mount semiconductor device 128L, the wiring region 1292L from the intermediate terminal 1296 to the drain terminal DL of the wiring pattern 1292 corresponds to an example of a first wiring pattern that is electrically connected to the drain terminal DL (an example of a first terminal) and through which the device current flows. Also, in the surface-mount semiconductor device 128L, the intermediate terminal 1296 corresponds to an example of a third terminal that is connected to the wiring region 1292L, exposed on the outer surface 1297a of the printed circuit board 129C, and through which the device current is input. Furthermore, in the surface-mount semiconductor device 128L, the wiring pattern 1293 corresponds to an example of a second wiring pattern that is electrically connected to the source terminal SL (an example of a second terminal) and through which the device current flows. In addition, the negative terminal 1295 corresponds to an example of a fourth terminal that is connected to the wiring pattern 1293, exposed on the outer surface 1297a, and through which the device current is output.

[0136] The printed circuit board 129C has a detection terminal 1291a (an example of a fifth terminal in the surface-mount semiconductor element 128U) which is formed integrally with the wiring pattern 1291 (an example of a first wiring pattern in the surface-mount semiconductor element 128U) and exposed on the outer surface 1297a. The printed circuit board 129C also has a detection terminal 1293a which is formed integrally with the wiring pattern 1293 (an example of a second wiring pattern in the surface-mount semiconductor element 128L) and exposed on the outer surface 1297a.

[0137] Figure 12 is a block diagram showing an example of a schematic configuration of the power converter 1C according to this embodiment. As shown in Figure 12, the surface-mount semiconductor element 128U and the surface-mount semiconductor element 128L are connected in series between the positive electrode line 10P and the negative electrode line 10N. The intermediate terminal 1296 is connected to a load device (not shown). The current detection unit 16 is positioned between the intermediate terminal 1296 and the load device. The current detection unit 16 detects the element current IL flowing between the intermediate terminal 1296 and the load device, and outputs the detected current value ILd, which is the current value of the detected element current IL, to the control device 13. In this way, the current detection unit 16 in this embodiment can detect the element current IL at the same location as the current detection unit 16 in the first embodiment.

[0138] The gate terminal GU and source terminal SU of the surface-mount semiconductor element 128U are connected to the output terminals of the gate drive circuit 14U for the upper arm. As a result, the transistor QU provided on the surface-mount semiconductor element 128U transitions between an on state and an off state depending on the voltage level of the gate-source voltage VGSU, which is the voltage difference between the voltage level of the gate drive signal input to the gate terminal GU from the gate drive circuit 14U and the voltage level of the source signal input to the source terminal SU.

[0139] The input terminals of the switching time calculation circuit 111AU for the upper arm are connected to the positive terminal 1294 and the detection terminal 1291a. The switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU induced by the rate of change of current when the transistor QU provided on the surface-mount semiconductor element 128U switches. In this embodiment, the switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 91 in the region between the positive terminal 1294 and the detection terminal 1291a of the wiring pattern 1291.

[0140] The gate terminal GL and source terminal SL of the surface-mount semiconductor element 128L are connected to the output terminals of the gate drive circuit 14L for the lower arm. As a result, the transistor QL provided on the surface-mount semiconductor element 128L transitions between an on state and an off state depending on the voltage level of the gate-source voltage VGSL, which is the voltage difference between the voltage level of the gate drive signal input to the gate terminal GL from the gate drive circuit 14L and the voltage level of the source signal input to the source terminal SL.

[0141] The input terminals of the switching time calculation circuit 111AL for the lower arm are connected to the negative terminal 1295 and the detection terminal 1293a. The switching time calculation circuit 111AL calculates the switching time SWTL using the induced voltage VLmL induced by the rate of change of current when the transistor QL provided on the surface-mount semiconductor element 128L switches. In this embodiment, the switching time calculation circuit 111AL calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 93 in the region between the negative terminal 1295 and the detection terminal 1293a of the wiring pattern 1293.

[0142] 3-2. Configuration of the deterioration diagnostic device: The degradation diagnostic devices 11AU and 11AL according to this embodiment are the same as the degradation diagnostic devices 11AU and 11AL according to the first embodiment, except that the location of the wiring inductance for detecting the induced voltages VLmU and VLmL is different, so a detailed explanation is omitted.

[0143] 3-3. Principles of deterioration diagnosis: The principle of degradation diagnosis in the degradation diagnosis devices 11AU and 11AL according to this embodiment will be explained using Figure 13 with reference to Figures 11 and 12. Figure 13 is a diagram illustrating the principle of degradation diagnosis in the degradation diagnosis devices 11AU and 11AL. Since the principle of degradation diagnosis is the same for both the degradation diagnosis devices 11AU and 11AL, the principle of degradation diagnosis will be explained using the degradation diagnosis device 11AU. Figure 13(a) is a schematic diagram showing the vicinity of the drain terminal DU of the surface mount semiconductor element 128U mounted on the printed circuit board 129C. Figure 2(b) is a diagram representing the surface mount semiconductor element 128U as a resistive element.

[0144] As shown in Figure 13(a), the surface-mount semiconductor element 128U is soldered to the printed circuit board 129C by solder 21a formed on its outer surface 1297b. This electrically connects the drain terminal DU to the wiring pattern 1291 via the solder 21a. Within the sealing portion 1281, the drain terminal DU is connected to the drain (not shown) of transistor QU by a conductive bonding member 1284a. Although not shown, the source terminal SU (not shown in Figure 13, see Figure 11) is also connected to transistor QU by a conductive bonding member 1284b (not shown in Figure 13, see Figure 11), similar to the drain terminal DU, and connected to the wiring region 1292U (not shown in Figure 13, see Figure 11) of the wiring pattern 1292 by solder 21b (not shown in Figure 13, see Figure 11).

[0145] In the upper arm, the element current IL flows from the positive side line 10P (not shown in Figure 13, see Figure 12) through the positive side terminal 1294 (not shown in Figure 13, see Figure 11), wiring pattern 1291, solder 21a, drain terminal DU, junction member 1284a, transistor QU, junction member 1284b, source terminal SU, solder 21b, wiring area 1292U of wiring pattern 1292, and intermediate terminal 1296 (not shown in Figure 13, see Figure 11) to the load device (not shown). In other words, on the surface mount semiconductor element 128U side, a current path PH is formed through the positive side terminal 1294, wiring pattern 1291, solder 21a, drain terminal DU, junction member 1284a, transistor QU, junction member 1284b, source terminal SU, wiring area 1292U of wiring pattern 1292, and intermediate terminal 1296.

[0146] The drain terminal DU of the surface-mount semiconductor element 128U is connected to the bonding member 1284a and solder 21a, and the source terminal SU of the surface-mount semiconductor element 128U is connected to the bonding member 1284b and solder 21b. Therefore, the surface-mount semiconductor element 128U in the current path PH of the element current IL can be represented as a series circuit of three resistive elements, as shown in Figure 13(b): the combined resistance Rcdu of solder 21a, drain terminal DU, and bonding member 1284a, the on-resistance Rqu of transistor QU, and the combined resistance Rcsu of solder 21b, source terminal SU, and bonding member 1284b, all connected in series.

[0147] Incidentally, repeated thermal stress is generated in the solders 21a and 21b due to the switching operation of transistor QU and the current conduction associated with this switching operation. As a result, the solders 21a and 21b deteriorate. Consequently, for example, a crack CKU (see Figure 2(a)) may occur in solder 21a, or a crack (not shown) may occur in solder 21b. The joining members 1284a and 1284b may also deteriorate over time due to the switching operation of transistor QU and the current conduction associated with this switching operation. The resistance values ​​of solders 21a and 21b increase when cracks occur, and the magnitude changes depending on the degree of cracking. Similarly, the resistance values ​​of joining members 1284a and 1284b increase when they deteriorate over time, and the magnitude changes depending on the degree of deterioration.

[0148] The element current IL flowing through the surface-mount semiconductor element 128U is a constant current corresponding to the degree of the transistor QU being ON. For example, if at least one of a crack CKU in the solder 21a and aging deterioration in the bonding member 1284a occurs, the voltage value Vcdu at the combined resistance Rcdu of the solder 21a, drain terminal DU, and bonding member 1284a will be greater than when at least one of the crack CKU and aging deterioration does not occur. Similarly, if at least one of a crack in the solder 21b and aging deterioration in the bonding member 1284b occurs, the voltage value Vcsu at the combined resistance Rcsu of the solder 21b, source terminal SU, and bonding member 1284b will be greater than when at least one of the crack and aging deterioration does not occur. Suppose that at least one of a crack CKU and aging deterioration occurs on the drain terminal DL side or a crack and aging deterioration occurs on the source terminal SL side, causing the transistor QU to be ON and the element current IL to flow through the surface-mount semiconductor element 128U. In this case, the voltage between the drain terminal DU and the source terminal SU of the surface-mount semiconductor element 128U (drain-source voltage VDSU(on)) will be greater than when the crack or aging degradation does not occur.

[0149] When transistor QU is turned on, the drain-source voltage VDSU(on) is the voltage between the drain terminal DU and source terminal SU of the surface-mount semiconductor element 128U at the end of the switching operation. On the other hand, when transistor QU is turned off, the drain-source voltage VDSU(on) is the voltage between the drain terminal DU and source terminal SU of the surface-mount semiconductor element 128U at the start of the switching operation. When transistor QU is off, the voltage between the drain terminal DU and source terminal SU of the surface-mount semiconductor element 128U is higher than the drain-source voltage VDSU(on).

[0150] Therefore, when transistor QU is operating normally, if at least one of the following occurs: a crack in the solder 21a, 21b and aging deterioration in the bonding members 1284a, 1284b, the change in voltage between the drain terminal DU and the source terminal SU during the switching operation of transistor QU becomes smaller than when at least one of the crack and aging deterioration does not occur. As a result, the switching time SWTU of transistor QU becomes shorter when at least one of the crack and aging deterioration occurs than when at least one of the crack and aging deterioration does not occur. The occurrence of at least one of the crack and aging deterioration corresponds to the deterioration of the power conversion unit 12C (not shown in Figure 13, see Figure 12). Therefore, the deterioration diagnostic device 11AU according to this embodiment (not shown in Figure 13, see Figure 12) diagnoses the deterioration of the power conversion unit 12C by utilizing the event that the switching time SWTU of transistor QU changes in response to the occurrence of at least one of the crack and aging deterioration.

[0151] As the number of power cycles increases, the solder 21a, 21b and the bonding members 1284a, 1284b deteriorate, resulting in cracks and aging degradation, and an increase in their resistance. Therefore, similar to the first embodiment described above, in this embodiment as well, the drain-source voltage VDSU(on) of the surface-mount semiconductor element 128U when transistor QU is in the ON state increases as the number of power cycles of transistor QU increases. The switching time SWTU of transistor QU decreases with increasing drain-source voltage VDSU(on).

[0152] As the drain-source voltage VDSU(on) increases due to the progression of degradation of at least one of the solders 21a, 21b and the bonding members 1284a, 1284b, the switching time SWTU of transistor QU becomes shorter than its initial value. The degradation diagnostic device 11AU according to the first embodiment detects the event of the switching time SWTU becoming shorter than its initial value by utilizing the induced voltage generated in the wiring inductance 17U. In contrast, the degradation diagnostic device 11AU detects the event of the switching time SWTU becoming shorter than its initial value by utilizing the induced voltage generated in the wiring inductance 91 (not shown in Figure 13, see Figure 12). Since the wiring inductance 91 is part of the wiring pattern 1291 that forms the current path PH of the element current IL, an induced voltage is generated according to the rate of change of the element current IL in the current path PH, and therefore, similar to the wiring inductance 17U in the first embodiment, it can detect the event of the switching time SWTU becoming shorter than its initial value.

[0153] Although a detailed explanation is omitted, similarly on the surface-mount semiconductor element 128L side, a current path is formed through the intermediate terminal 1296, the wiring region 1292L of the wiring pattern 1292, the solder 22a, the drain terminal DL, the bonding member 1285a, the transistor QL, the bonding member 1285b, the source terminal SL, the solder 22b, the wiring pattern 1293, and the negative terminal 1295 (not shown in Figure 13, see Figure 11). Repeated thermal stress is generated in the solder 22a, 22b and the bonding members 1285a, 1285b due to the switching operation of the transistor QL and the current conduction associated with this switching operation. As a result, cracks may occur in the solder 22a, 22b, and the bonding members 1285a, 1285b may deteriorate over time. Therefore, in the surface-mount semiconductor element 128L, similar to the surface-mount semiconductor element 128U, the switching time SWTL of transistor QL becomes shorter than its initial value as the drain-source voltage increases due to the progression of degradation of at least one of the solder 22a, 22b and the bonding members 1285a, 1285b. The degradation diagnostic device 11AL (not shown in Figure 13, see Figure 12) according to this embodiment detects the event of the switching time SWTL becoming shorter than its initial value by utilizing the induced voltage generated in the wiring inductance 93 (not shown in Figure 13, see Figure 12).

[0154] Thus, the degradation diagnostic devices 11AU and 11AL can diagnose the degradation of the power conversion unit 12C without directly detecting the drain-source voltage between the drain terminals DU and DL and the source terminals SU and SL of the surface-mount semiconductor elements 128U and 128L. As a result, the degradation diagnostic devices 11AU and 11AL do not require a detection circuit to detect minute voltage changes in the ON voltage of transistors QU and QL, nor a circuit to isolate them from the OFF state of transistors QU and QL. Consequently, the degradation diagnostic devices 11AU and 11AL can be simplified in their circuit configuration.

[0155] 3-4. Operation of the degradation diagnostic device and power converter: The operation of the degradation diagnostic devices 11AU, 11AL and the power converter 1C according to this embodiment is the same as the operation of the degradation diagnostic devices 11AU, 11AL and the power converter 1A according to the first embodiment, except that the induced voltages VLmU and VLmL generated in the wiring inductances 91 and 93 are used instead of the induced voltages VLmU and VLmL generated in the wiring inductances 17U and 17L. In other words, the switching time calculation circuit 111A (an example of a calculation unit) provided in the degradation diagnostic device 11A according to this embodiment calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 91 of the wiring pattern 1291 between the positive terminal 1294 and the detection terminal 1291a when the power converter 12C has a detection terminal 1291a formed integrally with the wiring pattern 1291. On the other hand, if the power conversion unit 12C has a detection terminal 1293a formed integrally with the wiring pattern 1293, the switching time calculation circuit 111A calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 93 of the wiring pattern 1293 between the negative terminal 1295 and the detection terminal 1293a.

[0156] Here, the case where "the power conversion unit 12C has a detection terminal 1291a formed integrally with the wiring pattern 1291" corresponds to the surface-mount semiconductor element 128U side, so the switching time calculation circuit 111AU for the upper arm calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 91 of the wiring pattern 1291 between the positive terminal 1294 and the detection terminal 1291a. The wiring inductance 91 in the wiring pattern 1291 corresponds to an example of the wiring inductance of the wiring section where the transistor QU is provided when the power conversion unit 12C has a detection terminal 1291a (an example of a fifth terminal) formed integrally with the wiring pattern 1291 (an example of a first wiring pattern). Furthermore, in the case where "the power conversion unit 12C has a detection terminal 1293a formed integrally with the wiring pattern 1293," this corresponds to the surface-mount semiconductor element 128L side, so the switching time calculation circuit 111AL for the lower arm calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 93 of the wiring pattern 1293 between the negative terminal 1295 and the detection terminal 1293a. The wiring inductance 93 in the wiring pattern 1293 corresponds to an example of the wiring inductance of the wiring section where the transistor QL is provided in the case where the power conversion unit 12C has a detection terminal 1293a (an example of a fifth terminal) formed integrally with the wiring pattern 1293 (an example of a second wiring pattern).

[0157] 3-5. Methods for diagnosing deterioration: The degradation diagnosis method according to this embodiment is the same as the degradation diagnosis method according to the first embodiment described above, except that the induced voltages VLmU and VLmL generated in wiring inductances 91 and 93 are used instead of the induced voltages VLmU and VLmL generated in wiring inductances 17U and 17L, so a detailed explanation is omitted.

[0158] As described above, the degradation diagnosis device 11A according to this embodiment includes a switching time calculation circuit 111A that calculates the switching time SWT of transistor Q, and a degradation diagnosis unit 112 that diagnoses the degradation of the power conversion unit 12C on which transistor Q is provided based on the switching time SWT calculated by the switching time calculation circuit 111A.

[0159] Furthermore, the power conversion device 1C according to this embodiment comprises the degradation diagnostic device 11A according to this embodiment, a transistor Q, and a power conversion unit 12C having the transistor Q.

[0160] Furthermore, the degradation diagnosis method according to this embodiment calculates the switching time SWT of transistor Q and diagnoses the degradation of the power conversion unit 12C on which transistor Q is provided based on the calculated switching time SWT.

[0161] By having such a configuration, the degradation diagnostic device 11A, power converter 1C, and degradation diagnostic method according to this embodiment can diagnose the degradation of the power converter 12C having surface-mount semiconductor elements 128U and 128L with a simple configuration.

[0162] [Fourth Embodiment] A fourth embodiment of the present invention, comprising a degradation diagnostic device, a power converter, and a degradation diagnostic method, will be described with reference to Figures 14 and 15. The degradation diagnostic device, power converter, and degradation diagnostic method according to this embodiment are characterized in that the power converter includes surface-mount semiconductor elements, and the configuration of the printed circuit board differs from that of the printed circuit board 129C in the third embodiment. With regard to the components of the degradation diagnostic device and power converter according to this embodiment, components that perform the same operations and functions as the degradation diagnostic devices 11AU, 11AL and power converter 1C in the third embodiment are denoted by the same reference numerals, and their descriptions are omitted unless necessary.

[0163] 4-1. Configuration of the power converter: The schematic configuration of the power conversion device according to this embodiment will be explained with reference to Figures 14 and 15. Figure 14 is a schematic cross-sectional view showing an example of the schematic configuration of surface-mount semiconductor elements 128U, 128L and printed circuit board 129D provided in the power conversion device 1D (see Figure 15) according to this embodiment. The surface-mount semiconductor elements 128U, 128L and printed circuit board 129D are provided in the power conversion unit 12D of the power conversion device 1D.

[0164] Since the surface-mount semiconductor elements 128U and 128L in this embodiment have the same configuration as the surface-mount semiconductor elements 128U and 128L in the third embodiment described above, their explanation will be omitted.

[0165] The printed circuit board 129D has the same configuration as the printed circuit board 129C in the third embodiment, except for the detection terminals. As shown in Figure 14, the printed circuit board 129D has detection terminals 1292a and 1292b formed integrally with the wiring pattern 1292. As described in the third embodiment above, in the surface-mount semiconductor element 128U, the wiring region 1292U from the source terminal SU to the intermediate terminal 1296 of the wiring pattern 1292 corresponds to an example of a second wiring pattern that is electrically connected to the source terminal SU and through which element current flows. Therefore, the printed circuit board 129D has a detection terminal 1292a (an example of a fifth terminal in the surface-mount semiconductor element 128U) formed integrally with the wiring region 1292U (an example of a second wiring pattern in the surface-mount semiconductor element 128U) and exposed on the outer surface 1297a.

[0166] In the surface-mount semiconductor element 128L, the wiring region 1292L from the intermediate terminal 1296 to the drain terminal DL of the wiring pattern 1292 corresponds to an example of a first wiring pattern through which the element current flows, and is electrically connected to the drain terminal DL (an example of a first terminal). Therefore, the printed circuit board 129D has a detection terminal 1292b (an example of a fifth terminal in the surface-mount semiconductor element 128L) which is formed integrally with the wiring region 1292L (an example of a first wiring pattern in the surface-mount semiconductor element 128L) and exposed on the outer surface 1297a.

[0167] Figure 15 is a block diagram showing an example of the schematic configuration of the power converter 1D according to this embodiment. As shown in Figure 15, the input terminals of the switching time calculation circuit 111AU for the upper arm are connected to the detection terminal 1292a and the intermediate terminal 1296. The switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU induced by the rate of change of current when the transistor QU provided on the surface-mount semiconductor element 128U switches. In this embodiment, the switching time calculation circuit 111AU calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 92U of the wiring region 1292U between the intermediate terminal 1296 and the detection terminal 1292a of the wiring pattern 1292. The wiring inductance 92U of the wiring region 1292U corresponds to an example of the wiring inductance of the wiring section where the transistor QU is provided when the detection terminal 1292a (an example of a fifth terminal in the surface-mount semiconductor element 128U) is formed integrally with the wiring region 1292U (an example of a second wiring pattern in the surface-mount semiconductor element 128U).

[0168] The input terminals of the switching time calculation circuit 111AL for the lower arm are connected to the intermediate terminal 1296 and the detection terminal 1292b. The switching time calculation circuit 111AL calculates the switching time SWTL using the induced voltage VLmL induced by the rate of change of current when the transistor QL provided on the surface-mount semiconductor element 128L switches. In this embodiment, the switching time calculation circuit 111AL calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 92L of the wiring region 1292L between the intermediate terminal 1296 and the detection terminal 1292b of the wiring pattern 1292. The wiring inductance 92L of the wiring region 1292L corresponds to an example of the wiring inductance of the wiring section where the transistor QU is provided when the detection terminal 1292b (an example of a fifth terminal in the surface-mount semiconductor element 128L) is formed integrally with the wiring region 1292L (an example of a first wiring pattern in the surface-mount semiconductor element 128L).

[0169] 4-2. Configuration of the deterioration diagnostic device: The degradation diagnostic devices 11AU and 11AL according to this embodiment are the same as the degradation diagnostic devices 11AU and 11AL according to the first embodiment, except that the location of the wiring inductance for detecting the induced voltages VLmU and VLmL is different, so a detailed explanation is omitted.

[0170] 4-3. Principles of Deterioration Diagnosis: The principle of degradation diagnosis in the degradation diagnosis devices 11AU and 11AL according to this embodiment is the same as the principle of degradation diagnosis in the degradation diagnosis devices 11AU and 11AL according to the third embodiment described above, except that the location of the wiring inductance for detecting the induced voltages VLmU and VLmL is different, so a detailed explanation is omitted.

[0171] 4-4. Operation of the degradation diagnostic device and power converter: The operation of the degradation diagnostic devices 11AU, 11AL and the power converter 1D according to this embodiment is the same as the operation of the degradation diagnostic devices 11AU, 11AL and the power converter 1C according to the third embodiment, except that the induced voltages VLmU and VLmL generated in the wiring inductances 92U and 92L are used instead of the induced voltages VLmU and VLmL generated in the wiring inductances 91 and 93. In other words, the switching time calculation circuit 111A (an example of a calculation unit) provided in the degradation diagnostic device 11A according to this embodiment calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 92U of the wiring pattern 1292 (specifically, the wiring region 1292U) between the detection terminal 1292a and the intermediate terminal 1296, when the power converter 12D has a detection terminal 1292a formed integrally with the wiring pattern 1292. On the other hand, if the power conversion unit 12D has a detection terminal 1292b formed integrally with the wiring pattern 1292, the switching time calculation circuit 111A calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 92L of the wiring pattern 1292 (specifically, the wiring region 1292L) between the intermediate terminal 1296 and the detection terminal 1292b.

[0172] Here, when "the power conversion unit 12D has a detection terminal 1292a formed integrally with the wiring pattern 1292", it corresponds to the surface-mount semiconductor element 128U side, so the switching time calculation circuit 111AU for the upper arm calculates the switching time SWTU using the induced voltage VLmU generated in the wiring inductance 92U of the wiring pattern 1292 (specifically, the wiring region 1292U) between the detection terminal 1292a and the intermediate terminal 1296. Also, when "the power conversion unit 12D has a detection terminal 1292b formed integrally with the wiring pattern 1292", it corresponds to the surface-mount semiconductor element 128L side, so the switching time calculation circuit 111AL for the lower arm calculates the switching time SWTL using the induced voltage VLmL generated in the wiring inductance 92L of the wiring pattern 1292 (specifically, the wiring region 1292L) between the intermediate terminal 1296 and the detection terminal 1292b.

[0173] 4-5. Methods for diagnosing deterioration: The degradation diagnosis method according to this embodiment is the same as the degradation diagnosis method according to the third embodiment described above, except that the induced voltages VLmU and VLmL generated in the wiring inductances 92U and 92L are used instead of the induced voltages VLmU and VLmL generated in the wiring inductances 91 and 93, so a detailed explanation is omitted.

[0174] As described above, the degradation diagnosis device 11A according to this embodiment includes a switching time calculation circuit 111A that calculates the switching time SWT of transistor Q, and a degradation diagnosis unit 112 that diagnoses the degradation of the power conversion unit 12D on which transistor Q is provided, based on the switching time SWT calculated by the switching time calculation circuit 111A.

[0175] Furthermore, the power conversion device 1D according to this embodiment comprises a degradation diagnosis device 11A according to this embodiment, a transistor Q, and a power conversion unit 12D having the transistor Q.

[0176] Furthermore, the degradation diagnosis method according to this embodiment calculates the switching time SWT of transistor Q and diagnoses the degradation of the power conversion unit 12D on which transistor Q is provided based on the calculated switching time SWT.

[0177] By having such a configuration, the degradation diagnosis device 11A, power converter 1D, and degradation diagnosis method according to this embodiment can diagnose the degradation of the power converter 12D having surface-mount semiconductor elements 128U and 128L with a simple configuration.

[0178] The present invention is not limited to the embodiments described above and can be modified in various ways. In the first to fourth embodiments described above, the degradation diagnostic devices 11AU, 11AL, 11BU, 11BL, power converters 1A, 1B, 1C, 1D, and degradation diagnostic method for the turn-off operation of transistors QU and QL have been described, but the present invention is not limited thereto. For example, the degradation diagnostic devices 11AU, 11AL, 11BU, 11BL, power converters 1A, 1B, 1C, 1D, and degradation diagnostic method can also be applied to the turn-on operation of transistors QU and QL.

[0179] In the first to fourth embodiments described above, the switching time calculation circuits 111AU, 111AL, 111BU, and 111BL start measuring the switching times SWTU and SWTL based on the input of gate pulse signals SgU and SgL, but the present invention is not limited thereto. The switching time calculation circuits 111AU, 111AL, 111BU, and 111BL may also be based on the timing before the induced voltages VLmU and VLmL generated at the same location disappear, for example, the timing when the gate-source voltage VGS starts to decrease (in the case of turn-off) or increase (in the case of turn-on), or the timing when the drain-source voltage VDS starts to increase (in the case of turn-off) or decrease (in the case of turn-on).

[0180] In the first to fourth embodiments described above, the degradation diagnosis unit 112 diagnoses degradation based on whether the difference between the switching time SWT included in the initial data ID obtained from the data storage unit 113 and the switching time SWT included in the latest switching time data SWTD is greater than a predetermined threshold. However, the present invention is not limited thereto. For example, the degradation diagnosis unit 112 may diagnose degradation based on whether the difference between the switching time SWT at the start of actual use, corrected for at least one of the current element current IL and element temperature TP of the transistor Q, and the switching time SWT included in the latest switching time data SWTD is greater than a predetermined threshold.

[0181] Furthermore, the degradation diagnosis unit 112 may diagnose the degradation of the power conversion unit 12 by comparing a predetermined value (e.g., a constant value) set in advance for the switching time of transistor Q with the switching time SWT included in the latest switching time data SWTD. In this case, the degradation diagnosis unit 112 may diagnose that the power conversion unit 12 has degraded if the switching time SWT exceeds the threshold.

[0182] In the degradation diagnostic device 11A according to the first, third, and fourth embodiments described above, and the degradation diagnostic devices 11BU and 11BL according to the second embodiment described above, the degradation diagnostic units 112U and 112L and the data storage units 113U and 113L are provided in the control device 13, but the present invention is not limited thereto. For example, a functional block that performs the same functions as the degradation diagnostic units 112U and 112L and the data storage units 113U and 113L may be provided in a server connected to a communication network that manages the power converters 1A, 1B, 1C, and 1D. In this case as well, the same effects as in the first to fourth embodiments described above can be obtained. Furthermore, in this case, degradation in multiple power converters can be diagnosed by a single server.

[0183] The semiconductor elements 121U and 121L in the second embodiment may be replaced with surface-mount semiconductor elements 128U and 128L. In this case, the printed circuit board on which the surface-mount semiconductor elements 128U and 128L are mounted does not need to have the detection terminals 1291a and 1293a in the third embodiment and the detection terminals 1292a and 1292b in the fourth embodiment. Similar to the second embodiment, for example, a Rogowski coil 114U can be placed between the positive electrode line 10P and the surface-mount semiconductor element 128U. Furthermore, a Rogowski coil 114L can be placed between the connection between transistor QU and transistor QL, which corresponds to the intermediate terminal 1296 in the third and fourth embodiments, and the surface-mount semiconductor element 128L. This allows the element current IL flowing through the surface-mount semiconductor elements 128U and 128L to be detected by the Rogowski coils 114U and 114L, thus achieving the same effects as the second embodiment.

[0184] The technical scope of the present invention is not limited to the illustrative and described embodiments, but also includes all embodiments that produce effects equivalent to those aimed at by the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of features of the invention defined by the claims, but can be defined by any desired combination of specific features from all disclosed features. [Explanation of symbols]

[0185] 1A, 1B, 1C, 1D Power Converter 11A, 11AL, 11AU, 11BL, 11BU Degradation Diagnosis Device 12, 12C, 12D Power Conversion Section 15, 15L, 15U Temperature detection circuit 16 Current detection unit 17, 17L, 17U, 91, 92U, 92L, 93 Wiring Inductance 111A, 111AL, 111AU, 111BL, 111BU Switching Time Calculation Circuit 112, 112L, 112U Deterioration Diagnosis Unit 113, 113L, 113U Data Storage Unit 114L, 114U Logoski Coil 121, 121L, 121U semiconductor devices 122L, 122U Temperature sensing element 123 Wire 124 Joint 21a, 21b, 125 solder 128U, 128L surface mount semiconductor devices 129C, 129D Printed Circuit Board 1281a,1282a,1297a,1297b Outer surface 1284a, 1284b, 1285a, 1285b Joining members Wiring patterns 1291, 1292, 1293 1291a, 1292a, 1292b, 1293a Detection terminals 1292L,1292U wiring area 1294 Positive terminal 1295 Negative terminal 1296 Intermediate terminal CK1, CK2, CKU cracks ID, IDL, IDU Initial Data IL element current ILd Current detection value Q, QL, QU transistors SWT, SWT0, SWT1, SWT2, SWTL, SWTU switching time SWTD, SWTDL, SWTDU Switching Time Data TP, TPL, TPU element temperature TPd, TPdL, TPdU Temperature detection values VLm, VLmL, VLmU Induced Voltage

Claims

1. A calculation unit for calculating the switching time of a switching element, A diagnostic unit that diagnoses the deterioration of the power conversion unit on which the switching element is provided, based on the switching time calculated by the calculation unit. A deterioration diagnostic device equipped with the following features.

2. The calculation unit calculates the switching time using the induced voltage induced by the rate of change of current when the switching element switches. The deterioration diagnostic device according to claim 1.

3. The calculation unit calculates the switching time using the control signal for controlling the switching element and the induced voltage. The deterioration diagnostic device according to claim 2.

4. The calculation unit calculates the time from the input of the control signal until the induced voltage disappears as the switching time. The deterioration diagnostic device according to claim 3.

5. The system includes a storage unit that stores switching time data relating at least one of the element current flowing through the switching element and the temperature of the switching element to the switching time. The deterioration diagnostic device according to claim 2.

6. The storage unit stores the switching time data based on the characteristics of the switching time that depend on at least one of the element current and the temperature, the switching time data acquired during a predetermined period after the switching element starts operating, or the switching time data acquired before the predetermined period as initial data. The deterioration diagnostic device according to claim 5.

7. The diagnostic unit compares the switching time data stored in the storage unit with the initial data to diagnose whether the power conversion unit has deteriorated. The deterioration diagnostic device according to claim 6.

8. The switching element is a wide-bandgap semiconductor element whose main material is at least one of silicon carbide, gallium nitride, gallium oxide, and diamond. The deterioration diagnostic device according to claim 2.

9. The calculation unit calculates the switching time using the induced voltage generated in the wiring inductance of the wiring section on which the switching element is provided. A deterioration diagnostic device according to any one of claims 2 to 8.

10. The switching element is equipped with a Rogowski coil for detecting the element current flowing through the switching element, The calculation unit calculates the switching time using the induced voltage generated at the output terminal of the Rogowski coil based on the rate of change of the element current detected when the switching element switches. A deterioration diagnostic device according to any one of claims 2 to 8.

11. A deterioration diagnostic device according to any one of claims 1 to 8, The aforementioned switching cable, The power conversion unit having the switching element and A power conversion device equipped with the following features.

12. A deterioration diagnostic device according to claim 9, The aforementioned switching cable, The power conversion unit having the switching element and A power conversion device equipped with the following features.

13. A deterioration diagnostic device according to claim 10, The aforementioned switching cable, The power conversion unit having the switching element and A power conversion device equipped with the following features.

14. The power conversion unit is A surface-mount semiconductor element having the aforementioned switching element, The circuit board on which the surface mount semiconductor element is mounted and It has, The aforementioned surface-mount semiconductor device is The element current flowing through the switching element is input to a first terminal exposed on the first outer surface of the surface-mount semiconductor element, The element current is output to the second terminal which is exposed on the first outer surface and It has, The aforementioned circuit board is A first wiring pattern electrically connected to the first terminal through which the element current flows, A third terminal connected to the first wiring pattern and exposed on the second outer surface of the circuit board, to which the element current is input, A second wiring pattern that is electrically connected to the second terminal and through which the element current flows, A fourth terminal connected to the second wiring pattern and exposed on the second outer surface, from which the element current is output, A fifth terminal formed integrally with the first wiring pattern or the second wiring pattern and exposed on the second outer surface has The power conversion device according to claim 11.

15. The calculation unit described above, If the power conversion unit has a fifth terminal formed integrally with the first wiring pattern, the switching time is calculated using the induced voltage generated in the wiring inductance of the first wiring pattern between the third terminal and the fifth terminal. If the power conversion unit has the fifth terminal formed integrally with the second wiring pattern, the switching time is calculated using the induced voltage generated in the wiring inductance of the second wiring pattern between the fourth terminal and the fifth terminal. The power conversion device according to claim 14.

16. The power conversion unit is A surface-mount semiconductor element having the aforementioned switching element, The circuit board on which the surface mount semiconductor element is mounted and It has, The aforementioned surface-mount semiconductor device is The element current flowing through the switching element is input to a first terminal exposed on the first outer surface of the surface-mount semiconductor element, The element current is output to the second terminal which is exposed on the first outer surface and It has, The aforementioned circuit board is A first wiring pattern electrically connected to the first terminal through which the element current flows, A third terminal connected to the first wiring pattern and exposed on the second outer surface of the circuit board, to which the element current is input, A second wiring pattern that is electrically connected to the second terminal and through which the element current flows, A fourth terminal connected to the second wiring pattern and exposed on the second outer surface, from which the element current is output, A fifth terminal formed integrally with the first wiring pattern or the second wiring pattern and exposed on the second outer surface has The power conversion device according to claim 12.

17. The wiring inductance of the aforementioned wiring section is If the power conversion unit has the fifth terminal formed integrally with the first wiring pattern, the wiring inductance of the first wiring pattern between the third terminal and the fifth terminal is: If the power conversion unit has a fifth terminal formed integrally with the second wiring pattern, then the wiring inductance of the second wiring pattern between the fourth terminal and the fifth terminal is The power conversion device according to claim 16.

18. The power conversion unit is A surface-mount semiconductor element having the aforementioned switching element, The circuit board on which the surface mount semiconductor element is mounted and It has, The aforementioned surface-mount semiconductor device is The element current flowing through the switching element is input to a first terminal exposed on the first outer surface of the surface-mount semiconductor element, The element current is output to the second terminal which is exposed on the first outer surface and It has, The aforementioned circuit board is A first wiring pattern electrically connected to the first terminal through which the element current flows, A third terminal connected to the first wiring pattern and exposed on the second outer surface of the circuit board, to which the element current is input, A second wiring pattern that is electrically connected to the second terminal and through which the element current flows, The fourth terminal is connected to the second wiring pattern, is exposed on the second outer surface, and outputs the element current. has The power conversion device according to claim 13.

19. The switching time of the switching element is calculated, Based on the calculated switching time, the deterioration of the power conversion unit equipped with the switching element is diagnosed. Methods for diagnosing deterioration.

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