SST-type power converter and control method for SST-type power converter

Abstract

In an SST-type power converter, an initial charging circuit is not added to the AC grid side, thereby suppressing the inrush current during initial charging. [Solution] As initial charging, secondary DC capacitor C dc2 Charge the secondary DC capacitor C dc2 After the initial charge is complete, the primary DC capacitor C dc1 Initial charging begins, and the primary DC capacitor C dc1 Normal operation begins after the initial charge is complete. Primary DC capacitor C dc1 During the initial charging phase, the pulse width of the secondary converter of the isolated DC / DC converter is gradually increased.

Description

[Technical Field]

[0001] The present invention relates to a technology that eliminates the need for an initial charging circuit on the AC grid side in a Solid State Transformer (hereinafter referred to as SST) system, which is configured by connecting multiple power converters (AC / DC converters + isolated DC / DC converters) in series or in parallel. [Background technology]

[0002] Figure 1 shows an example of a circuit configuration in which an SST type power converter is directly connected to a high-voltage AC system without a commercial transformer. In the circuit configuration of Figure 1, the primary side DC capacitor C dc1 or secondary DC capacitor C dc2 An inrush current occurs during the initial charging of a battery. Generally, this inrush current can be suppressed by using an initial charging circuit in a high-voltage AC system. However, an initial charging circuit located in a high-voltage AC system requires insulation equivalent to high voltage, which leads to an increase in device size and cost.

[0003] Non-patent document 1 describes a secondary DC capacitor C in an SST type power converter. dc2 From the primary side DC capacitor C dc1 A method is disclosed that eliminates the need for an initial charging circuit from a high-voltage AC system by charging the battery.

[0004] Patent Document 1 discloses an initial charging method using a small-capacity commercial transformer and a Scott transformer in a converter that is directly connected to a high-voltage system.

[0005] Patent Document 2 discloses an initial charging circuit in a high-voltage cell inverter system using a multi-winding transformer, in which windings are added to the multi-winding transformer and an AC auxiliary power supply and a commercial frequency transformer are connected.

[0006] Patent Document 3 discloses a driving method for an isolated DC / DC converter that suppresses the DC superposition of transformer current in order to suppress the high-frequency transformer current during initial charging. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2017-192297 [Patent Document 2] Japanese Patent Publication No. 2012-244680 [Patent Document 3] Japanese Patent Publication No. 2023-88235 [Patent Document 4] Japanese Patent Publication No. 2022-43627 [Patent Document 5] Japanese Patent Publication No. 2022-50739 [Patent Document 6] Japanese Patent Publication No. 2020-92592 [Non-patent literature]

[0008] [Non-Patent Document 1] Y. Jiang, X. Ren, H. Weng, Z. Li and D. Xu, "A Soft Start Approach of Solid-State Transformer", 2021 IEEE 1st International Power Electronics and Application Symposium (PEAS), Shanghai, China, 2021, pp. 1-6 [Non-Patent Document 2] Yuki Kinoshita, Hitoshi Haga, "LLC Converter for PEV Charger with Wide Voltage Gain Using a 6-Switch Bridge," Transactions of the Institute of Electrical Engineers of Japan, Vol. 140, No. 1, pp. 36-44, 2020. [Non-Patent Document 3] J. Shi, W. Gou, H. Yuan, T. Zhao, AQ Huang, "Research on voltage and power balance control for cascaded modular solid-state transformer", IEEE Transaction on Power Electronics.2011.P1154-1166. [Non-Patent Document 4] P. Sochor, H. Akagi, "Energy-balancing control of a delta-configured modular multilevel cascade inverter for utility-scale photovoltaic systems", 2015 IEEE Energy Conversion Congress and Exposition (ECCE), Montreal, QC, Canada, 2015, pp. 4706-4713 [Non-Patent Document 5] Shigenori Inoue, Yasushi Akagi, "Operating Voltage and Loss Analysis of Bidirectional Isolated DC / DC Converters," Transactions of the Institute of Electrical Engineers of Japan, Vol. 127, No. 2, pp. 188-197 (2007). [Non-Patent Document 6] AKJain and R.Ayyanar, “PWM control of dual active bridge: Comprehensive analysis and experimental verification” in IEEE Transactions on Power Electronics, vol. 26, no. 4, pp. 1215-1227, April 2011 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] Non-patent document 1 describes how to perform initial charging from a DC bus to bring the primary DC capacitor C dc1The initial charging circuit (on the AC system side) has been removed. However, the secondary DC capacitor C dc2 From the primary side DC capacitor C dc1 When charging, the low impedance of the high-frequency transformer causes an inrush current to be generated in the high-frequency transformer.

[0010] Components that draw inrush current during initial charging (such as high-frequency transformers and switching devices) require a current capacity that can withstand this inrush current. Therefore, a smaller inrush current is desirable because it allows the use of smaller, lower-cost components with lower current capacities.

[0011] Patent documents 1 and 2 require additional windings for multi-winding transformers or commercial transformers, which increases the size of the device.

[0012] Patent Document 3 describes a method that can suppress the inrush current of a low-impedance high-frequency transformer, but it requires a high-performance control controller to generate a special switching pattern, raising concerns about increased costs.

[0013] For the reasons described above, a challenge in SST-type power converters is to suppress the inrush current during initial charging without adding an initial charging circuit to the AC grid side. [Means for solving the problem]

[0014] The present invention was devised in view of the above-mentioned conventional problems, and one embodiment thereof is an SST type power converter having m (m: an integer of 2 or more) cells per phase, each cell comprising an AC-DC converter, a primary DC capacitor connected to the DC side of the AC-DC converter, an isolated DC-DC converter with one DC side connected to the primary DC capacitor, and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter, the AC side of the AC-DC converter is connected to an AC system via an AC side switch, and the SST type power converter is connected to a load or power supply via one or more initial charging circuits and one or more DC buses, which are formed by connecting a plurality of the secondary DC capacitors in parallel and connecting a DC side switch and a resistor in parallel, wherein the isolated DC The DC-DC converter comprises a primary converter whose DC side is connected to the primary DC capacitor, a high-frequency transformer connected to the AC side of the primary converter, a secondary converter whose AC side is connected to the other side of the high-frequency transformer, and a secondary DC capacitor connected to the DC side of the secondary converter. The control unit of the SST type power converter is characterized in that, as an initial charge, it charges the secondary DC capacitor, after the initial charging of the secondary DC capacitor is completed, it starts initial charging of the primary DC capacitor, after the initial charging of the primary DC capacitor is completed, it starts normal operation, and during the initial charging of the primary DC capacitor, it gradually increases the pulse width of the secondary converter of the isolated DC-DC converter.

[0015] Furthermore, in one embodiment, a current control unit that outputs a pulse width command value for the primary side converter and a pulse width command value for the secondary side converter of the isolated DC-DC converter based on the secondary side DC current command value which is the output current command value of the isolated DC-DC converter, the primary side DC voltage which is the voltage of the primary side DC capacitor, and the secondary side DC voltage which is the voltage of the secondary side DC capacitor; an initial charge control unit that outputs a pulse width command value for the primary side converter and a pulse width command value for the secondary side converter of the isolated DC-DC converter at the time of initial charging based on the primary side DC voltage and the secondary side DC voltage; and the The device is characterized by comprising: a first switch that outputs the pulse width command value of the primary converter and the pulse width command value of the secondary converter output by the current control unit when the initial charge completion flag of the secondary DC capacitor is 1, and the pulse width command value of the primary converter and the pulse width command value of the secondary converter output by the initial charge control unit when the initial charge completion flag of the primary DC capacitor is 0; a gate generation unit that generates the gate signal of the primary converter and the gate signal of the secondary converter based on the output of the first switch; and a first AND circuit that enables the gate signal of the primary converter when the initial charge completion flag of the primary DC capacitor is 1, and enables the gate signal of the secondary converter when the initial charge completion flag of the secondary DC capacitor is 1.

[0016] In another embodiment, the DC bus is one, and the initial charge control unit compares the secondary DC voltage with the secondary initial charge completion voltage value of the secondary DC capacitor and outputs 1 if the secondary DC voltage is equal to or greater than the secondary initial charge completion voltage value, and 0 otherwise, as the initial charge completion flag of the secondary DC capacitor and the on / off signal of the DC switch; a first multiplier that outputs the product of the pulse width command value of the secondary converter and the initial charge completion flag of the secondary DC capacitor; a rate of change limiting unit that gradually increases the output value when the output of the first multiplier becomes 1; and the primary DC voltage or the average voltage value of the primary DC voltage or the rated value of the primary voltage and the primary initial charge completion value of the primary DC capacitor The device is characterized by comprising: a third multiplier that multiplies the charge completion voltage value; an adder that adds a fixed value to the output of the third multiplier; a second switch that outputs the smaller of the output of the rate of change limiter and the adder as the pulse width command value of the secondary converter during the initial charging of the primary DC capacitor; a second hysteresis comparator that compares the primary DC voltage of each cell with the primary initial charge completion voltage value and outputs 1 if the primary DC voltage is equal to or greater than the primary initial charge completion voltage value, and 0 otherwise; and a second AND circuit that outputs 1 if the output of the second hysteresis comparator is 1 for all cells, and 0 otherwise, as the initial charge completion flag for the primary DC capacitor and the opening / closing signal for the AC switch.

[0017] In one embodiment, the DC buses are multiple, and the initial charge control unit includes a first hysteresis comparator that compares the secondary DC voltage with the secondary initial charge completion voltage value of the secondary DC capacitor and outputs 1 as an on / off signal for the DC switch if the secondary DC voltage is equal to or greater than the secondary initial charge completion voltage value, and 0 otherwise; a third AND circuit that outputs 1 as an initial charge completion flag for the secondary DC capacitor if the output of the first hysteresis comparator is 1 for all DC buses, and 0 otherwise; a first multiplier that outputs the product of the pulse width command value of the secondary converter and the initial charge completion flag of the secondary DC capacitor; a rate of change limiting unit that gradually increases the output value when the output of the first multiplier becomes 1; and the primary DC voltage or the average voltage value of the primary DC voltage or The device is characterized by comprising: a third multiplier that multiplies the rated value of the secondary voltage by the primary initial charge completion voltage value of the primary DC capacitor; an adder that adds a fixed value to the output of the third multiplier; a second switch that outputs the smaller of the output of the rate of change limiter and the adder as the pulse width command value of the secondary converter during the initial charging of the primary DC capacitor; a second hysteresis comparator that compares the primary DC voltage of the primary DC capacitor of each cell with the primary initial charge completion voltage value and outputs 1 if the primary DC voltage is equal to or greater than the primary initial charge completion voltage value, and 0 otherwise; and a second AND circuit that outputs 1 if the output of the second hysteresis comparator is 1 in all cells, and 0 otherwise, as the initial charge completion flag of the primary DC capacitor and the opening / closing signal of the AC switch.

[0018] In one embodiment, the primary DC voltage command value is greater than the value obtained by multiplying the turns ratio of the high-frequency transformer by the secondary DC voltage, the isolated DC-DC converter is of the DAB type, the initial charge control unit comprises a P controller that amplifies the deviation between the primary DC voltage and the primary DC voltage command value, a third hysteresis comparator that compares the primary DC voltage with a boost start voltage threshold of the primary DC voltage and outputs 1 if the primary DC voltage is greater than or equal to the boost start voltage threshold, and 0 otherwise, a second multiplier that outputs the product of the output of the P controller and the output of the third hysteresis comparator, and a limiter that limits the output of the second multiplier to within a limit value and outputs it as a phase difference command value during initial charging, and the gate generation unit generates the gate signal of the primary converter and the gate signal of the secondary converter based on the phase difference command value. [Effects of the Invention]

[0019] According to the present invention, in an SST type power converter, it is possible to suppress the inrush current during initial charging without adding an initial charging circuit to the AC grid side. [Brief explanation of the drawing]

[0020] [Figure 1] This figure shows the main circuit configuration (single DC bus) of the SST type power converter in Embodiment 1. [Figure 2] This figure shows the main circuit configuration (multiple DC buses) of the SST type power converter in Embodiment 1. [Figure 3] A diagram showing an example of a cell circuit configuration. [Figure 4] A block diagram showing the control unit. [Figure 5] A diagram showing the initial charge control unit of Embodiment 1. [Figure 6] A diagram showing the initial charge control unit of Embodiment 2. [Figure 7] A diagram showing the initial charge control unit of Embodiment 3. [Modes for carrying out the invention]

[0021] Hereinafter, Embodiments 1 to 3 of the SST type power conversion device according to the present invention will be described in detail based on FIGS. 1 to 7.

[0022] [Embodiment 1] FIG. 1 shows the main circuit configuration of the SST type power conversion device of Embodiment 1. As shown in FIG. 1, an AC / DC converter connected to a high-voltage AC system via an AC side switch MC_AC and reactors Lu, Lv, Lw, and a primary side DC capacitor C connected to the DC side of the AC / DC converter dc1 and, the primary side DC capacitor C dc1 to an isolated DC / DC converter DC / DC having one DC side connected thereto, and a secondary side DC capacitor C connected to the other DC side of the isolated DC / DC converter DC / DC dc2 and, are included. The secondary side DC capacitor C [[ID=???]] dc2 is connected to a load or a power source via an initial charging circuit 1 and a DC bus DC2. The initial charging circuit 1 includes a DC side switch MC_DC and a resistor R pre connected in parallel with the DC side switch MC_DC.

[0023] Here, the AC / DC converter, the primary side DC capacitor C dc1 , the isolated DC / DC converter DC / DC, and the secondary side DC capacitor C dc2 are taken as one cell. In FIG. 1, the number of cells per phase is m (m: an integer of 2 or more). Also, three cells in three phases form one unit, and there are m units.

[0024] The AC sides of the cells in each phase are connected in series. The DC sides (secondary side DC capacitors C dc2 ) of each cell are connected in parallel. V u , V v , V w represent the AC system voltage, i u , i v , i w represent the AC system current, V dc1ak (V dc1u1 ~V dc1w4 ) represent the primary side DC voltage of the primary side DC capacitor C dc1 of each cell, and V dc2 It should be noted that there seems to be an unclear tag "??? dc2 " in the original text. If this is an error, please correct it for a more accurate translation.The secondary DC capacitor C dc2 This shows the secondary DC voltage, V LV_bus This indicates the voltage of the DC bus DC2.

[0025] Figure 1 illustrates a configuration with m=4 as an example, and includes 12 secondary DC capacitors C. dc2 These are connected in parallel. Secondary DC capacitor C dc2 It is connected to a load or power supply via one initial charging circuit 1 and one DC bus DC2. The DC bus DC2 has the DC bus voltage V required for initial charging. LV_bus It is assumed that the following is applied.

[0026] Furthermore, this embodiment 1 can also handle multiple DC buses as shown in Figure 2. Figure 2 also has a configuration of m=4, but consists of two units and six secondary DC capacitors C. dc2 These are connected in parallel, and one DC bus DC21 is connected via the initial charging circuit 1, with the remaining two units and six secondary DC capacitors C. dc2 These are connected in parallel and one DC bus DC22 is connected via the initial charging circuit 1. DC bus DC21 and DC bus DC22 have voltages V21 and DC22, respectively. LV_bus1 , V LV_bus2 It is connected to a load or power supply.

[0027] In the following explanation, this configuration uses the primary DC voltage of the kth unit connected to the xth phase DC bus DC2x as V dc1axk Let's assume that.

[0028] Figure 3 shows the circuit configuration of a single cell. In the cell circuit configuration of Figure 3(a), a Modular Multilevel Cascade (hereinafter referred to as the MMC method) is used for the AC / DC converter, and a Dual Active Bridge (hereinafter referred to as the DAB method) is used for the isolated DC / DC converter. In Figure 3(b), the MMC method is used for the AC / DC converter, and the LLC method is used for the isolated DC / DC converter. In either configuration, each cell is equipped with a switching device. In each cell, voltage and current are controlled by the on / off operation (driving) of the switching device. The driving method of the device is selected to suit the circuit configuration, and for the DAB method, a pulse width control method, as exemplified by Patent Document 4, is used, and for the LLC method, a control method, as exemplified by Non-Patent Document 2, is used.

[0029] As shown in Figure 3(a), one end of switching devices S1 and S2 is connected to one AC terminal of the cell. One end of switching devices S3 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S3 are connected to the primary DC capacitor C. dc1 It is connected to one end of the switching devices S2 and S4. The other end of the switching devices S2 and S4 is connected to the primary DC capacitor C. dc1 It is connected to the other end.

[0030] Primary DC capacitor C dc1 Switching devices S5 and S6 are connected in series between one end and the other. Also, the primary DC capacitor C dc1 Switching devices S7 and S8 are connected in series between one end and the other end.

[0031] One end of the primary winding of the high-frequency transformer Tr is connected to the connection point of switching devices S5 and S6. The other end of the primary winding of the high-frequency transformer Tr is connected to the connection point of switching devices S7 and S8.

[0032] A secondary DC capacitor C is located between one DC terminal of the cell and the other DC terminal. dc2 The following is connected: Secondary DC capacitor C dc2Switching devices S9 and S10 are connected in series between one end and the other. Also, the secondary DC capacitor C dc2 Switching devices S11 and S12 are also connected in series between one end and the other end.

[0033] One end of reactor L2 is connected to the connection point of switching devices S9 and S10. One end of reactor L1 is connected to the connection point of switching devices S11 and S12. The secondary winding of a high-frequency transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2. Switching devices S1 to S4 are AC / DC converters. Switching devices S5 to S8 are primary side converters DAB_PR of an isolated DC / DC converter. Switching devices S9 to S12 are secondary side converters DAB_SE of an isolated DC / DC converter. The number of turns of the primary winding of the high-frequency transformer Tr is N1, the number of turns of the secondary winding is N2, and the turns ratio is N tr Let = N1 / N2.

[0034] In Figure 3(b), a capacitor C is placed between the reactor L1 and the connection point of the switching devices S11 and S12. r A capacitor C is connected between the reactor L2 and the connection point of the switching devices S9 and S10. r The following are connected. The rest is the same as in Figure 3(a). In Figure 3(b), the primary side converter is LLC_PR and the secondary side converter is LLC_SE.

[0035] In Figure 3(a), i dc2x V represents the secondary DC current, which is the output current of an isolated DC / DC converter. dc2x The secondary DC capacitor C dc2 This indicates the voltage of the (DC bus).

[0036] Figure 4 shows block diagrams of the control unit of an SST type power converter. Figure 4(a) is the control block diagram of the AC / DC converter side in the MMC type, Figure 4(b) is the control block diagram of the DC / DC converter side in the DAB type, and Figure 4(c) is the control block diagram of the DC / DC converter side in the LLC type.

[0037] Figure 4(a) is composed as shown in Non-Patent Document 3.

[0038] The primary side DC voltage averaging control unit 2 controls the primary side DC voltage V of all cells. dc1axk The average voltage value V dc1_ave Controlled to the primary DC voltage V of each cell. dc1axk and average voltage value V dc1_ave It takes the input and outputs the system current command value using P control.

[0039] The system current control unit 3 controls the active and inactive components on the rotating coordinate system based on the system current command value and the system current detection value, and the d-axis voltage command V d_ref q-axis voltage command V q_ref It outputs [this]. It is configured using a P or PI controller.

[0040] The dq inverse converter 4 controls the d-axis voltage command V d_ref q-axis voltage command V q_ref The system phase ωt is input, and the voltage command value on the rotating coordinate system synchronized with the system voltage is the voltage command value V on the fixed coordinate system. u_ref , V v_ref , V w_ref Convert to.

[0041] The primary DC voltage phase balance control unit 5 performs balance control of the primary DC voltage in each phase. Non-patent document 4 is an example. The output of the primary DC voltage phase balance control unit 5 is the voltage command value V of the AC / DC converter of each cell. u_ref1 ~V u_refm , V v_ref1 ~V v_refm , V w_ref1 ~V w_refm This is the result. P r_flg1This is the primary DC capacitor C output by the initial charge control unit 8, which will be described later. dc1 This is a flag indicating that the initial charging is complete. Each block in Figure 4(a) is the primary DC capacitor C dc1 It will only operate after the initial charge is complete.

[0042] Figure 4(b) is a block diagram of the control unit on the DC / DC side of the isolated DC-DC converter in the DAB system, and consists of the following components.

[0043] The current command generation unit 6 generates a secondary DC voltage V dc2x Overall value control or secondary DC current i dc2axk It is configured by control. The current command generation unit 6 generates a secondary DC current command value i dc2axk_ref The following will be output.

[0044] The current control unit 7 is the control applied during normal operation. The secondary DC current command value i is output from the current command generation unit 6. dc2axk_ref and primary side DC voltage V dc1axk , secondary DC voltage V dc2x The input is used, and according to the output of the current controller, the pulse width command value W of the primary side converter DAB_PR of the isolated DC / DC converter, which is the DAB method's manipulated variable. PRaxk = 1, pulse width command value W of the secondary side converter DAB_SE. SEaxk =1 or phase difference command value θ axk Outputs the phase difference command value θ. axk This is the phase difference command value between the voltages of the primary side converter DAB_PR and the secondary side converter DAB_SE. Since the current control unit 7 is not directly related to the essence of the present invention, a detailed explanation is omitted. For example, the processing of the current control unit is described in Patent Document 4. Note that the pulse width command value W PRaxk, W SEaxk This adjusts the zero-voltage period of the H-bridge output voltage, W PRaxk , W SEaxk =1 is square wave output, W PRaxk, W SEaxk =0 results in zero voltage output for the entire period.

[0045] The initial charge control unit 8 is the control applied during the initial charge. The primary-side DC voltage V dc1axk , the secondary-side DC voltage V dc2x are input, and the pulse width command value W PRaxk_ch of the primary-side converter DAB_PR of the isolated DC / DC converter DC / DC during the initial charge, which is the operation amount of the DAB method, the pulse width command value W SEaxk_ch of the secondary-side converter DAB_SE, and the phase difference command value θ axk_ch (in Embodiment 1 and Embodiment 2, θ = 0), the initial charge completion flag P dc1 of the primary-side DC capacitor C r_flg1 , the initial charge completion flag P<0000 of the secondary-side DC capacitor C dc2 r_flg2 and the open / close signal P MC_AC of the AC-side switch MC_AC, the open / close signal P MC_DCx of the DC-side switch MC_DCx are output.

[0046] The first switch 9 switches the phase difference command value and the pulse width command value according to the initial charge completion flag P dc1 of the primary-side DC capacitor C r_flg1 . Specifically, during the initial charge period of the primary-side DC capacitor C dc1 [[ID=,,,, the output of the initial charge control unit 8 is selected, and after the initial charge is completed, the output of the current control unit 7 is selected. dc2 dc2 dc2

[0047] The gate generation unit 10 takes the phase difference command value, the pulse width command value, and the switching frequency command value f sw as input and generates the gate signals of the primary-side converter DAB_PR and the secondary-side converter DAB_SE of each cell that realizes the command values. Since the gate generation unit 10 has no direct relation to the present invention, detailed description thereof is omitted. Note that, for example, there is Patent Document 5.

[0048] The first AND circuit 11 inputs the initial charge completion flag P r_flg1, P r_flg2 and each gate signal, and enables the output of the gate generation unit 10 according to the initial charge completion flags P r_flg1 and P r_flg2 of each DC capacitor.

[0049] Figure 4(c) is a block diagram of the control unit of an isolated DC / DC converter in the LLC system, and the differences from the DAB system control unit in Figure 4(b) are explained below.

[0050] The current control unit 7 is the control applied during normal operation. The secondary DC current command value i dc2axk_ref and primary side DC voltage V dc1axk , secondary DC voltage V dc2x The input is the pulse width command value W of the primary side converter LLC_PR of the isolated DC / DC converter, which is the manipulated variable of the LLC system. PRaxk = 1, pulse width command value W of secondary side converter LLC_SE. SEaxk = 1 and switching frequency f swaxk It outputs [this value]. Note that in the LLC method, the pulse width command value is set to a square wave.

[0051] The initial charge control unit 8 is a control applied during initial charging. Primary DC voltage V dc1axk , secondary DC voltage V dc2x The input is the pulse width command value W of the primary side converter LLC_PR of the isolated DC / DC converter during initial charging, which is the manipulated variable of the LLC system. PRaxk_ch = 1, pulse width command value W of secondary side converter LLC_SE. SEaxk_ch and switching frequency command f swaxk_ch Primary DC capacitor C dc1 Initial charging complete flag P r_flg1 , secondary DC capacitor C dc2 Initial charging complete flag P r_flg2 , AC side switch MC_AC opening / closing signal P MC_AC , the switching signal P of the DC side switch MC_DCx MC_DCx It outputs the switching frequency command f during initial charge control. swaxk_ch This is set to the minimum switching frequency during normal operation.

[0052] Figure 5 shows a block diagram of the initial charge control unit 8 in this embodiment 1. The initial charge control unit 8 in this embodiment 1 is a single DC bus and has a primary side DC voltage command value V dc_refThe turns ratio of the high-frequency transformer Tr and the secondary DC voltage V dc2x The relationship between the value obtained by multiplying by V is dc1_ref ≤N tr V dc2x This applies in the case of transformer turns ratio N. tr The relationship between the number of turns on the primary side N1 and the number of turns on the secondary side N2 is N tr = N1 / N2

[0053] Figure 5(a) shows the secondary DC capacitor C of the initial charge control unit 8. dc2 This is a block diagram of the initial charge control, and it consists of the following:

[0054] The first hysteresis comparator 12 is a secondary DC capacitor C dc2 The secondary side initial charge completion voltage value V dc2_th and secondary DC voltage V dc2 Comparing this, the secondary DC voltage V dc2 The voltage value V is the voltage value when the initial charge of the secondary side is complete. dc2_th The secondary DC capacitor C is 1 when the above conditions are met, and 0 otherwise. dc2 Initial charging complete flag P r_flg2 , the switching signal P of the DC side switch MC_DC MC_DC It outputs the following. Note that the primary DC capacitor C dc1 Open / close signal P during initial charging MC_DC Initial charging complete flag P r_flg2 Hysteresis is implemented to prevent the value from changing frequently in a short period of time due to the influence of noise and other factors.

[0055] Figure 5(b) shows the primary DC capacitor C of the initial charge control unit 8. dc1 This is a block diagram of the initial charge control, and it consists of the following:

[0056] The first multiplier 13 receives the pulse width command value W of the secondary side converter DAB_SE (or LLC_SE) of the square wave driven isolated DC / DC converter. SE =1 and secondary DC capacitor C dc2 Initial charging complete flag P r_flg2The product of the two values ​​is output. The rate of change limiting unit 14 takes the output of the first multiplier 13 as input, and when the output of the first multiplier 13 becomes 1, it changes the pulse width command value of the secondary converter DAB_SE (or LLC_SE) from 0 to 1 in a ramp-like manner at the set rate of change. However, the rate of change is determined by the peak value of the allowable transformer current and the charging time.

[0057] The third multiplier 22 measures the primary DC voltage V of each cell. dc1axk and the reciprocal of the primary side initial charge completion voltage value, 1 / V dc1_th Outputs the product of the primary DC voltage V. dc1axk Instead, its average voltage value V dc1_ave Alternatively, the primary side DC voltage V may be used. dc1axk Alternatively, the rated value of the primary voltage may be used. The rated value of the primary voltage is, for example, the voltage value of inputs and outputs assumed to be in a standard operating state defined in the design. If the rated value is given as a range, the maximum value or representative value can be used as the voltage value for determining the control command value in this embodiment 1. The adder 23 adds a fixed value α to the output of the third multiplier 22. The fixed value α is set to a value such as 10%. The second switch 24 receives two inputs, the output of the adder 23 and the output of the rate of change limiter 14, and selects the smaller one to obtain the pulse width command value W of the secondary converter during the initial charging of the primary DC capacitor Cdc1. SEaxk_ch It outputs as follows. As a result, immediately after the initial charging of the primary DC capacitor Cdc1 begins, the primary DC voltage V dc1axk = 0, and the pulse width command value W output by the second switch 24. SEaxk_ch The primary DC voltage V is limited to a fixed value α. dc1axk As charging progresses, the pulse width command value W of the secondary converter will be set. SEaxk_ch The upper limit also increases, and the pulse width command value WSEaxk_ch of the secondary converter changes in a ramp-like manner. If the primary DC capacitor Cdc1 is short-circuited due to some abnormality, the pulse width command value W of the secondary converter SEaxk_ch Since it does not exceed the fixed value α, the generation of inrush current can be suppressed.

[0058] The second hysteresis comparator 15 is a primary DC capacitor Cdc1 Primary side initial charge completion voltage value V dc1_th and primary side DC voltage V dc1axk Comparing this, the primary DC voltage V dc1axk The primary side initial charge completion voltage value V dc1_th If the above conditions are met, it outputs 1; otherwise, it outputs 0. Hysteresis is provided so that the initial charge completion flag of each cell does not change when normal operation starts. The second AND circuit 16 takes the output of the second hysteresis comparator 15 of each cell as input, and outputs 1 if all cells (3m) are 1, and 0 otherwise, to the opening and closing signal P of the AC side switch MC_AC. MC_AC and primary DC capacitor C dc1 Initial charging complete flag P r_flg1 Output as follows.

[0059] In the control block shown in Figures 4(b) and 4(c), which is common to each embodiment, the current control unit 7 sets the command value to achieve the current command value (the pulse width command value W of the primary side converter DAB_PR of the isolated DC / DC converter). PRaxk = 1, pulse width command value W of the secondary side converter DAB_SE. SEaxk =1 and the phase difference command value θ in the DAB method axk In the LLC method, the switching frequency f swaxk Outputs ).

[0060] In the initial charge control unit 8, the primary DC capacitor C dc1 Initial charging complete flag P r_flg1 , secondary DC capacitor C dc2 Initial charging complete flag P r_flg2 and pulse width command value W PRaxk =1, W SEaxk_ch , AC side switch MC_AC opening / closing signal P MC_AC , the switching signal P of the DC side switch MC_DCx MC_DCx It outputs the phase difference command value θ during initial charging. axk_ch =0, but in the LLC method, the switching frequency command f swaxk_ch This is added to the output.

[0061] Initial charging begins with the secondary DC capacitor C dc2First, proceed from the secondary DC capacitor C dc2 Once charging is complete, the secondary DC capacitor C dc2 Initial charging complete flag P r_flag2 and the switching signal P of the DC side switch MC_DC MC_DC Let this be 1. Secondary DC capacitor C dc2 After the initial charging is complete (P r_flag2 =1), primary DC capacitor C dc1 Initial charging begins, and the primary DC capacitor C dc1 Once the initial charging is complete, the primary DC capacitor C dc1 Initial charging complete flag P r_flag1 and the switching signal P of the AC side switch MC_AC MC_AC Let this be 1. Primary DC capacitor C dc1 After initial charging is complete (P r_flg1 Normal operation starts at =1).

[0062] In the first switch 9, the primary DC capacitor C dc1 Initial charging complete flag P r_flg1 This switches the output of the current control unit 7 and the initial charge control unit 8. The gate generation unit 10 outputs the gate signal of the isolated DC / DC converter that realizes the command value determined by the first switch 9. The first AND circuit 11 outputs the initial charge completion flag P r_flg1 , P r_flg2 Enable the gate signal accordingly.

[0063] In this embodiment 1 shown in Figure 5, a single DC bus and a primary DC voltage command value V dc1_ref The turns ratio N of the high-frequency transformer Tr tr Secondary DC voltage V dc2 If it is less than the value obtained by multiplying by (V dc1_ref ≤N tr V dc2 This applies to ).

[0064] In the initial charge control unit 8, the secondary DC capacitor C dc2 and primary DC capacitor C dc1 Initial charge control is performed. First, the secondary DC capacitor C shown in Figure 5(a) is used. dc2In the initial charge control, the DC bus DC2 is used to power the resistor R of the initial charge circuit 1. pre via the secondary DC capacitor C dc2 Charge it.

[0065] The first hysteresis comparator 12 controls the secondary DC voltage V dc2 and secondary DC capacitor C dc2 The secondary side initial charge completion voltage value V dc2_th Compare the output of the first hysteresis comparator 12 with the secondary DC capacitor C. dc2 Initial charging complete flag P r_flg2 Furthermore, the switching signal P of the DC side switch MC_DC MC_DC This is the result. Note that the primary DC capacitor C dc1 Initial charging complete flag P r_flg2 or opening / closing signal P MC_DC To prevent the secondary initial charge completion voltage V from changing frequently in a short period of time, dc2_th and secondary DC voltage V dc2 A hysteresis comparator is used for comparison.

[0066] The primary DC capacitor C shown in Figure 5(b) dc1 Initial charging is performed by the secondary DC capacitor C dc2 This should be done after the initial charging is complete. However, the primary DC capacitor C dc1 When the secondary converters DAB_SE and LLC_SE are started with a square wave output during charging, an excessive inrush current occurs due to the low impedance of the high-frequency transformer Tr.

[0067] As shown in Patent Document 6, the inrush current of the transformer can be suppressed by adjusting the duty cycle. However, as shown in Non-Patent Documents 5 and 6, the DAB method operates with a fixed duty cycle of 50%, requiring additional duty cycle control. This leads to an increase in the calculation time within the controller.

[0068] Furthermore, it is necessary to drive the auxiliary power supply for the gate driver of the primary-side converter DAB_PR before the initial charge of the primary-side DC voltage. This requires an auxiliary power supply with high-voltage equivalent isolation performance that uses the DC bus as input, leading to increased cost and size of the auxiliary power supply. Therefore, the inrush current of the transformer current is suppressed by increasing the pulse width command value of the secondary-side converters DAB_SE and LLC_SE from zero in a ramp-like manner.

[0069] Specifically, the pulse width command value W of the secondary converter DAB_SE (LLC_SE) that produces a square wave output. SE and secondary DC capacitor C dc2 Initial charging complete flag P r_flg2 By taking the product of and limiting the rate of change of that value, the pulse width command value W of the secondary side converter DAB_SE (LLC_SE) is set at the timing of the start of initial charging. SEaxk_ch The value can be gradually increased (for example, from 0 to a ramp-like change). Note that the primary DC capacitor C dc1 During initial charging, the primary side converter DAB_PR is gate-off, and the phase difference command value θ axk_ch The value is set to zero, the primary side converter LLC_PR is set to gate off, and the switching frequency command fswaxk_ch is set to the lowest value within the set range.

[0070] Next, the primary DC voltage V of all cells is measured using the second hysteresis comparator 15. dc1axk and primary DC capacitor C dc1 Primary side initial charge completion voltage value V dc1_th The two are compared. Then, the second AND gate 16 outputs the logical OR of the second hysteresis comparator 15. The output of the second AND gate 16 is the primary DC capacitor C dc1 Initial charging complete flag P r_flg1 Furthermore, the switching signal P of the AC side switch MC_AC MC_AC This is the result. Note that the initial charge completion flag P is displayed when normal operation starts. r_flg1 or opening / closing signal P MC_AC To prevent the primary DC voltage V from changing frequently in a short period of time, dc1axk and the primary side initial charge completion voltage value V dc1_th A hysteresis comparator is used for comparison.

[0071] This embodiment 1 is an SST-type power converter that takes a high-voltage grid input and outputs a DC voltage without a commercial transformer, and it is possible to reduce the initial charging circuit 1 on the high-voltage AC grid side. By reducing the initial charging circuit 1 on the high-voltage AC grid side, it is possible to avoid increasing the size and cost of the device.

[0072] This embodiment 1 allows for the suppression of inrush current flowing through each element and the high-frequency transformer Tr without complex control, even under conditions where a single DC bus DC2 output is available and no voltage boosting is required, even considering the turns ratio of the high-frequency transformer Tr from the DC bus DC2. This enables a reduction in the current capacity of each switching device and allows implementation with a low-performance controller, leading to expected cost reductions.

[0073] [Embodiment 2] This second embodiment applies when there are multiple DC buses. Note that the primary DC voltage command value V dc_ref and the turns ratio N of the high-frequency transformer Tr tr Secondary DC voltage V dc2 The relationship of the multiplied values ​​is the same as in Embodiment 1, V dc1_ref ≤N tr V dc2x And apply it.

[0074] Figure 6 is a block diagram of the initial charge control unit 8 in this second embodiment, and compared to the first embodiment, the secondary DC capacitor C dc2 The initial charging control has been modified.

[0075] The first hysteresis comparator 12 controls the secondary DC voltage V dc2x and secondary DC capacitor C dc2 The secondary side initial charge completion voltage value V dc2x_th Comparing this with the secondary DC voltage V dc2x The secondary DC capacitor C dc2 The secondary side initial charge completion voltage value V dc2x_th The switching signal P of the DC-side switch MC_DCx is 1 in the above cases and 0 otherwise. MC_DCx Outputs.

[0076] The third AND gate 17 takes the output of the first hysteresis comparator 12 on each DC bus as input, and the secondary DC capacitor C of all DC buses is 1 when all DC buses are 1, and 0 otherwise. dc2 Initial charging complete flag P r_flg2 Outputs.

[0077] In this embodiment 2 shown in Figure 6, there are multiple DC buses, and the primary side DC voltage command value V dc1_ref The turns ratio N of the high-frequency transformer tr Secondary DC voltage V dc2x If it is less than the value obtained by multiplying by (V dc1_ref ≤N tr V dc2x This applies to ).

[0078] Primary DC capacitor C dc1 The initial charging method is the same as in Embodiment 1. In Embodiment 2, the number of first hysteresis comparators 12 is increased to the number of DC buses compared to Figure 5(a). The first hysteresis comparators 12 control each secondary DC voltage V dc2x and secondary DC capacitor C dc2 The secondary side initial charge completion voltage value V dc2x_th Compare them.

[0079] The output of each first hysteresis comparator 12 is the opening / closing signal P of the DC-side switch MC_DCx connected to each DC bus. MC_DCx This is the result. Also, by taking the logical OR of the outputs of each first hysteresis comparator 12, all secondary DC capacitors C connected to each DC bus are obtained. dc2 Initial charging complete flag P r_flg2 This is the result.

[0080] This second embodiment, in addition to the first embodiment, can suppress the inrush current flowing through each element and high-frequency transformer even for multiple DC buses.

[0081] [Embodiment 3] Figure 7 shows a block diagram of the initial charge control unit 8 of this embodiment 3. In this embodiment 3, the isolated DC / DC converter is of the DAB type, and the primary side DC voltage command value V dc1_refand the turns ratio N of the high-frequency transformer Tr tr Secondary DC voltage V dc2x The relationship between the values ​​obtained by multiplying by V is dc1_ref >N tr V dc2x This applies when the following conditions are met. This control block diagram adds boost control based on phase difference compared to embodiments 1 and 2. The boost control unit is composed as follows.

[0082] The P controller 18 controls the primary side DC voltage command value V dc1_ref and primary side DC voltage V dc1axk The deviation is taken as input, and the value amplified by the P gain is output.

[0083] The third hysteresis comparator 19 controls the primary DC voltage V dc1axk and the boost start voltage threshold V dc1_th2 Compare the magnitudes of the primary DC voltages V dc1axk The boost start voltage threshold V dc1_th2 The boost operation start flag is output as 1 in the above cases, and as 0 otherwise. Boost start voltage threshold V dc1_th2 The turns ratio N of the transformer tr The secondary DC voltage value N, taking this into consideration. tr V dc2x Set it lower.

[0084] The second multiplier 20 outputs the product of the output of the P controller 18 and the boost operation start flag. The limiter 21 limits the output of the second multiplier 20 to within the limit value, thereby setting the phase difference command value θ of the DAB type isolated DC / DC converter. axk_ch It outputs as follows. The limit value is determined by the allowable value of the transformer current and the charging time. This phase difference command value θ axk_ch Based on this, the gate generation unit 10 in Figure 4(b) generates gate signals for the primary side converter DAB_PR and the secondary side converter DAB_SE.

[0085] In this embodiment 3 shown in Figure 7, the DAB method is used, and the primary side DC voltage command value V dc1_ref The turns ratio N of the high-frequency transformer Tr tr Secondary DC voltage V dc2x If the value is greater than the multiplied value, then V dc1_ref >Ntr V dc2x This applies to the secondary DC capacitor C. dc2 The initial charging control is the same as in Embodiment 1 for a single DC bus and the same as in Embodiment 2 for multiple DC buses.

[0086] After the output voltage of the secondary converter DAB_SE becomes a square wave output (i.e., the pulse width command value W of the secondary converter DAB_SE in Figure 5(b)) SEaxk_ch After the voltage changes in a ramp-like manner from 0 to 1, the phase difference between the output voltages of the primary side converter DAB_PR and the secondary side converter DAB_SE is controlled, thereby controlling the primary side DC voltage V dc1axk Boost the voltage.

[0087] First, the primary DC voltage V dc1axk and primary side DC voltage command value V dc1_ref The deviation is taken and input to the P controller 18 to calculate the phase difference required for initial charging. Next, the primary DC voltage V is calculated using the third hysteresis comparator 19. dc1axk and the boost start voltage threshold V dc1_th2 The magnitude relationship is compared, and a boost operation start flag is output.

[0088] Furthermore, by taking the product of the boost operation start flag and the output of the P controller 18, the primary side DC voltage command value V is obtained. dc1_ref and primary side DC voltage V dc1axk Control can be started when the deviation is small. However, since the DAB-type isolated DC / DC converter is in an unloaded state during initial charging, voltage control tends to be unstable. Therefore, the gain of the P controller 18 is set to a relatively small value.

[0089] Furthermore, a limiter 21 is used to limit the phase difference command value of the DAB-type isolated DC / DC converter. The limiter's limit value is determined by the peak value of the transformer current and the desired charging time.

[0090] This third embodiment can suppress the inrush current flowing through each element and the high-frequency transformer, even under conditions where voltage boosting from the DC bus is required in the DAB method.

[0091] Although the present invention has been described in detail only with respect to the specific examples described above, it will be obvious to those skilled in the art that a wide variety of modifications and alterations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and alterations fall within the scope of the claims.

[0092] For example, the following modifications are included. In each embodiment, the command values ​​that define the output, such as pulse width and phase difference, are gradually increased in a ramp-like and continuous manner from approximately 0 to 1. It is also possible to make this a curved variation rather than a linear one by interposing a first-order lag filter or a leading filter. Alternatively, it is possible to set a starting point within the range of 0 or more and less than 1, and change from the starting point to an endpoint that is greater than or equal to 1. In such cases, the starting point should be set according to the conditions that the initial inrush current can tolerate, and the endpoint should be set so that excessive voltage-current oscillations do not occur during the transition after the completion of initial charging. [Explanation of Symbols]

[0093] C dc1 ...Primary side DC capacitor, C dc2 ...Secondary DC capacitor, AC / DC...AC-DC converter, DC / DC...Isolated DC-DC converter, MC_AC...AC side switch, MC_DC...DC side switch, 1...Initial charging circuit, R pre ...Resistor, DC2...DC bus, 2...Primary DC voltage averaging control unit, 3...System current control unit, 4...dq inverse converter, 5...Primary DC voltage phase balance control unit, 6...Current command generation unit, 7...Current control unit, 8...Initial charge control unit, 9...First switch, 10...Gate generation unit, 11...First AND circuit, 12...First hysteresis comparator, 13...First multiplier, 14...Change rate limiting unit, 15...Second hysteresis comparator, 16...Second AND circuit, 17...Third AND circuit, 18...P controller, 19...Third hysteresis comparator, 20...Second multiplier, 21...Limiter, 22...Third multiplier, 23...Adder, 24...Second switch

Claims

1. An SST type power converter having m (m: an integer of 2 or more) cells per phase, each cell comprising an AC-DC converter, a primary DC capacitor connected to the DC side of the AC-DC converter, an isolated DC-DC converter with one DC side connected to the primary DC capacitor, and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter, wherein the AC side of the AC-DC converter is connected to an AC system via an AC side switch, and the SST type power converter is connected to a load or power source via one or more initial charging circuits and one or more DC buses, each consisting of a plurality of secondary DC capacitors connected in parallel and a DC side switch and resistor connected in parallel, The isolated DC converter comprises a primary converter whose DC side is connected to the primary DC capacitor, a high-frequency transformer connected to the AC side of the primary converter, a secondary converter whose AC side is connected to the other side of the high-frequency transformer, and the secondary DC capacitor connected to the DC side of the secondary converter. The control unit of the SST type power converter is As an initial charge, the secondary DC capacitor is charged, and after the initial charge of the secondary DC capacitor is complete, the initial charge of the primary DC capacitor is started, and after the initial charge of the primary DC capacitor is complete, normal operation is started. An SST-type power conversion device characterized by gradually increasing the pulse width of the secondary converter of the isolated DC-DC converter during the initial charging of the primary DC capacitor.

2. A current control unit outputs a pulse width command value for the primary side converter and a pulse width command value for the secondary side converter of the isolated DC-DC converter based on the secondary side DC current command value, which is the output current command value of the isolated DC-DC converter, the primary side DC voltage, which is the voltage of the primary side DC capacitor, and the secondary side DC voltage, which is the voltage of the secondary side DC capacitor. An initial charge control unit outputs, based on the primary DC voltage and the secondary DC voltage, the pulse width command value of the primary converter and the pulse width command value of the secondary converter of the isolated DC-DC converter during initial charging, the opening / closing signal of the AC switch, the opening / closing signal of the DC switch, the initial charge completion flag of the primary DC capacitor, and the initial charge completion flag of the secondary DC capacitor. A first switch outputs the pulse width command value of the primary converter and the pulse width command value of the secondary converter output by the current control unit when the initial charge completion flag of the primary DC capacitor is 1, and the pulse width command value of the primary converter and the pulse width command value of the secondary converter output by the initial charge control unit when the initial charge completion flag of the primary DC capacitor is 0. A gate generation unit that generates the gate signal of the primary side converter and the gate signal of the secondary side converter based on the output of the first switch, A first AND circuit enables the gate signal of the primary converter when the initial charge completion flag of the primary DC capacitor is 1, and enables the gate signal of the secondary converter when the initial charge completion flag of the secondary DC capacitor is 1. The SST type power converter according to claim 1, characterized by being equipped with the following features.

3. There is one DC bus, The initial charge control unit, A first hysteresis comparator compares the secondary DC voltage with the secondary initial charge completion voltage value of the secondary DC capacitor and outputs 1 if the secondary DC voltage is equal to or greater than the secondary initial charge completion voltage value, and 0 otherwise, as the initial charge completion flag for the secondary DC capacitor and the on / off signal for the DC switch. A first multiplier that outputs the product of the pulse width command value of the secondary side converter and the initial charge completion flag of the secondary side DC capacitor, When the output of the first multiplier becomes 1, a rate of change limiting unit that gradually increases the output value, A third multiplier that multiplies the primary DC voltage or the average voltage value of the primary DC voltage or the rated value of the primary voltage by the primary initial charge completion voltage value of the primary DC capacitor, An adder that adds a fixed value to the output of the third multiplier, A second switch outputs the smaller of the output of the rate of change limiting unit and the adder as the pulse width command value of the secondary converter during the initial charging of the primary DC capacitor, A second hysteresis comparator compares the primary DC voltage of each cell with the primary initial charge completion voltage value and outputs 1 if the primary DC voltage is equal to or greater than the primary initial charge completion voltage value, and 0 otherwise. A second AND circuit outputs 1 when the output of the second hysteresis comparator is 1 in all cells, and 0 otherwise, as the initial charge completion flag for the primary DC capacitor and the opening / closing signal for the AC switch, The SST type power converter according to claim 2, characterized by comprising:

4. The aforementioned DC bus is multiple, The initial charge control unit, A first hysteresis comparator compares the secondary DC voltage with the secondary initial charge completion voltage value of the secondary DC capacitor and outputs 1 as an opening / closing signal for the DC switch if the secondary DC voltage is equal to or greater than the secondary initial charge completion voltage value, and 0 otherwise. A third AND circuit outputs 1 as an initial charge completion flag for the secondary DC capacitor if the output of the first hysteresis comparator is 1 in all DC buses, and 0 otherwise. A first multiplier that outputs the product of the pulse width command value of the secondary side converter and the initial charge completion flag of the secondary side DC capacitor, When the output of the first multiplier becomes 1, a rate of change limiting unit that gradually increases the output value, A third multiplier that multiplies the primary DC voltage or the average voltage value of the primary DC voltage or the rated value of the primary voltage by the primary initial charge completion voltage value of the primary DC capacitor, An adder that adds a fixed value to the output of the third multiplier, A second switch outputs the smaller of the output of the rate of change limiting unit and the adder as the pulse width command value of the secondary converter during the initial charging of the primary DC capacitor, A second hysteresis comparator compares the primary DC voltage of the primary DC capacitor of each cell with the primary initial charge completion voltage value, and outputs 1 if the primary DC voltage is equal to or greater than the primary initial charge completion voltage value, and 0 otherwise. A second AND circuit outputs 1 when the output of the second hysteresis comparator is 1 in all cells, and 0 otherwise, as the initial charge completion flag for the primary DC capacitor and the opening / closing signal for the AC switch, The SST type power converter according to claim 2, characterized by comprising:

5. The primary DC voltage command value is greater than the value obtained by multiplying the turns ratio of the high-frequency transformer by the secondary DC voltage, and the isolated DC-DC converter is of the DAB type. The initial charge control unit, A P controller that amplifies the difference between the primary DC voltage and the primary DC voltage command value, A third hysteresis comparator compares the primary DC voltage with a boost start voltage threshold for the primary DC voltage and outputs 1 if the primary DC voltage is equal to or greater than the boost start voltage threshold, and outputs 0 otherwise. A second multiplier that outputs the product of the output of the P controller and the output of the third hysteresis comparator, The second multiplier includes a limiter that limits the output to within a specified limit and outputs it as the phase difference command value during initial charging, The SST type power converter according to claim 3 or 4, characterized in that the gate generation unit generates the gate signal of the primary side converter and the gate signal of the secondary side converter based on the phase difference command value.

6. Each phase has m (m: an integer of 2 or more) cells comprising: an AC-DC converter; a primary DC capacitor connected to the DC side of the AC-DC converter; an isolated DC-DC converter with one DC side connected to the primary DC capacitor; and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter. The AC side of the AC-DC converter is connected to an AC system via an AC switch, and the load or power supply is connected via one or more DC buses to one or more initial charging circuits, which consist of multiple secondary DC capacitors connected in parallel and a DC switch and resistor connected in parallel. The isolated DC-DC converter comprises a primary converter whose DC side is connected to the primary DC capacitor, a high-frequency transformer connected to the AC side of the primary converter, a secondary converter whose AC side is connected to the other side of the high-frequency transformer, and the secondary DC capacitor connected to the DC side of the secondary converter, and is a control method for an SST type power converter. The control unit of the SST type power converter is As an initial charge, the secondary DC capacitor is charged, and after the initial charge of the secondary DC capacitor is complete, the initial charge of the primary DC capacitor is started, and after the initial charge of the primary DC capacitor is complete, normal operation is started. A control method for an SST-type power converter, characterized by gradually increasing the pulse width of the secondary converter of the isolated DC-DC converter during the initial charging of the primary DC capacitor.

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