Semiconductor memory

Abstract

To improve the yield of semiconductor memory devices. [Solution] The semiconductor memory device according to the embodiment comprises a first region and a second region arranged in a second direction, a plurality of wiring layers and a plurality of first insulating films arranged alternately in the first direction, a memory pillar extending in the first direction in the second region and passing through the plurality of wiring layers and the plurality of first insulating films, wherein the memory pillar comprises a first semiconductor extending in the first direction, a second insulating film provided between the first semiconductor and the plurality of wiring layers and the plurality of first insulating films, a charge storage film provided between the second insulating film and the plurality of wiring layers and the plurality of first insulating films, a plurality of third insulating films provided between the charge storage film and the plurality of wiring layers, and a plurality of fourth insulating films including a first film type provided between the charge storage film and the plurality of first insulating films, and a fifth insulating film provided in the first region so as to cover the side portions in the second direction at the ends of the plurality of wiring layers and including a second film type having a lower etching rate to hydrofluoric acid than the first film type.

Description

Technical Field

[0001] Embodiments relate to semiconductor memory devices.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatilely, a NAND-type flash memory is known. In a NAND-type flash memory, a three-dimensional memory structure may be adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the yield of the semiconductor memory device.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment comprises, when viewed in a first direction, a plurality of wiring layers and a plurality of first insulating films arranged alternately in the first direction, spanning a first region and a second region aligned in a second direction intersecting the first direction, and a memory pillar extending in the first direction in the second region, passing through the plurality of wiring layers and the plurality of first insulating films, the portion passing through the plurality of wiring layers functions as a plurality of memory cells, wherein the memory pillar comprises a first semiconductor extending in the first direction, a second insulating film provided between the first semiconductor and the plurality of wiring layers and the plurality of first insulating films, a charge storage film provided between the second insulating film and the plurality of wiring layers and the plurality of first insulating films, a plurality of third insulating films provided between the charge storage film and the plurality of wiring layers, and a plurality of fourth insulating films including a first film type provided between the charge storage film and the plurality of first insulating films, and a fifth insulating film provided in the first region so as to cover the side portions in the second direction at the ends of the plurality of wiring layers, and including a second film type having a lower etching rate to hydrofluoric acid than the first film type. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 3] Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to this embodiment. [Figure 4] Figure 4 is a plan view showing an example of a planar layout in the memory area of ​​a memory cell array in a semiconductor memory device according to this embodiment. [Figure 5] Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 6] Figure 6 is an enlarged cross-sectional view of region VI in Figure 5, showing an example of the cross-sectional structure in the memory region of the memory cell array provided in the semiconductor memory device according to the embodiment. [Figure 7]Figure 7 is a cross-sectional view along line VII-VII in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view along line VIII-VIII in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to this embodiment. [Figure 9] Figure 9 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to this embodiment. [Figure 10] Figure 10 is a cross-sectional view along the line X'-X' in Figure 9 of the extraction region of the memory cell array in the semiconductor memory device according to the embodiment. [Figure 11] Figure 11 is a flowchart showing an example of the manufacturing process for a memory cell array in a semiconductor memory device according to this embodiment. [Figure 12] Figure 12 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 13] Figure 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array included in a semiconductor memory device according to this embodiment. [Figure 14] Figure 14 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 15] Figure 15 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to this embodiment. [Figure 16] Figure 16 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 17] Figure 17 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 18] Figure 18 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory cell array in a semiconductor memory device according to this embodiment. [Figure 19]FIG. 19 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing an example of a cross-sectional structure in a memory region of a memory cell array included in the semiconductor memory device according to the first modification of the embodiment. [Figure 26] FIG. 26 is a cross-sectional view showing an example of a cross-sectional structure in a memory region of a memory cell array included in the semiconductor memory device according to the second modification of the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and the dimensions and ratios in the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When particularly distinguishing between elements having the same configuration, different letters or numbers may be added to the end of the same reference numeral. [[ID=зо]]

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] 1. Structure 1.1 Memory System A semiconductor memory device according to an embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0011] The semiconductor memory device 3 is, for example, a NAND flash memory capable of storing data non-volatilely.

[0012] Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0013] 1.2 Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 3 according to the embodiment will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] The memory cell array 10 is a collection of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erasure unit when erasing data stored by a memory cell transistor. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between it and the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, each transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0016] The logic control circuit 12 receives control signals input from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it has received is a command CMD or address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. The logic control circuit 12 also outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is ready or busy.

[0017] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read, write, erase, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used to select block BLK, word lines, and bit lines, respectively. Status information STA is used to notify the memory controller 2 whether the operation has been completed successfully. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc., and performs read operations, write operations, erase operations, etc.

[0019] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0022] The semiconductor memory device 3 according to this embodiment includes a structure formed by bonding together, for example, a first semiconductor substrate on which various control circuits are formed and a second semiconductor substrate on which a memory cell array 10 is formed. Each of the first and second semiconductor substrates is, for example, a silicon substrate. The various control circuits formed on the first semiconductor substrate include, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17. In the following description, an example is given in which the second semiconductor substrate is removed after the first and second semiconductor substrates have been bonded together during the manufacturing process of the semiconductor memory device 3. Depending on the structure of the memory cell array 10, a part of the second semiconductor substrate may remain after bonding.

[0023] 1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. Figure 2 shows block BLK0. Block BLK0 includes, for example, five string units SU0 to SU4.

[0024] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0025] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0026] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Within string units SU0 to SU4, the gates of selection transistors ST1 are connected to selection gate lines SGD0 to SGD4, respectively. Within the same block BLK, the gate of selection transistor ST2 is connected to selection gate line SGS.

[0027] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0028] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0029] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to this embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0030] 1.4 Structure of a memory cell array An example of the structure of the memory cell array 10 provided in the semiconductor memory device 3 according to the embodiment is described below. In the following description, the extension direction of the word line WL is the X direction. The extension direction of the bit line BL is the Y direction. When viewed from the source line SL side, the direction in which the selected gate lines SGD and SGS, and the stacked wiring corresponding to the word line WL are stacked is the Z direction or upward direction. The opposite direction of the upward direction is the downward direction. In the plan view, hatching is added as appropriate to improve the visibility of the drawing. The hatching added to the plan view is not necessarily related to the material or characteristics of the component to which the hatching is added.

[0031] 1.4.1 Overview Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to an embodiment. In Figure 3, regions corresponding to four blocks BLK0 to BLK3 are shown. The sequential numbers at the end to distinguish the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in Figure 3 is repeatedly arranged in the Y direction. As shown in Figure 3, the memory cell array 10 includes a plurality of members SLT and a plurality of members SHE. The planar layout of the memory cell array 10 is divided in the X direction, for example, into a memory area MA and an extraction area HA.

[0032] The memory area MA is an area used for storing data, containing multiple NAND strings NS. The extraction area HA is an area used for connecting the stacked wiring, which is composed of multiple wiring layers (e.g., word lines WL0 to WL7, and selection gate lines SGS and SGD) stacked apart from each other in the Z direction, to the raw decoder module 16.

[0033] Multiple SLT members each extend along the X direction and are aligned in the Y direction. Each SLT member traverses the memory area MA and the extraction area HA in the X direction at the boundary region between adjacent blocks BLK. In other words, each region demarcated by an SLT member corresponds to one block BLK in the memory cell array 10. Each SLT member has a structure in which, for example, an insulator and plate-shaped contacts are embedded. Each SLT member separates adjacent stacked wiring through it.

[0034] Multiple members SHE are arranged in the memory area MA. Each of the multiple members SHE is provided across the memory area MA in the X direction and aligned in the Y direction. The right-hand end of each member SHE is included in the lead-out area HA. ​​For example, in the memory area MA, four members SHE are each arranged between adjacent members SLT in the Y direction. Each region of the memory area MA separated by members SLT and SHE corresponds to one string unit SU in the memory cell array 10. Each member SHE has, for example, a structure with an embedded insulator. Each member SHE separates adjacent selection gate lines SGD through the member SHE.

[0035] The planar layout of the memory cell array 10 in the semiconductor memory device 3 according to this embodiment is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units SU formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT.

[0036] 1.4.2 Memory Area (Flat layout) Figure 4 is a plan view showing an example of a planar layout in the memory region of a memory cell array in a semiconductor memory device according to the embodiment. As shown in Figure 4, in the memory region MA, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each component SLT includes contacts LI and spacers SP.

[0037] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows in the Y direction, in the region between two adjacent members SLT. In the example shown in Figure 4, one member SHE overlaps each of the 5th, 10th, 15th, and 20th memory pillar MPs, counting from the top of the paper.

[0038] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example shown in Figure 4, two bit lines BL are positioned to overlap with one memory pillar MP. If multiple bit lines BL overlap with a memory pillar MP, one bit line BL and the corresponding memory pillar MP are electrically connected via a contact CV. If only one bit line BL overlaps with a memory pillar MP, that bit line BL and the corresponding memory pillar MP are electrically connected via a contact CV.

[0039] For example, the contact CV between a memory pillar MP in contact with a component SHE and the corresponding bit line BL is omitted. In other words, the contact CV between a memory pillar MP and a bit line BL in contact with two different selection gate lines SGD is omitted. The number and arrangement of memory pillars MP and component SHE between adjacent component SLTs are not limited to the configuration shown in Figure 4 and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0040] Contact LI is a conductor extending in the XZ plane. The lower surface of contact LI is in contact with a source wire SL (not shown). Spacer SP is an insulator provided on the side of contact LI. In other words, spacer SP is provided in contact with contact LI so as to sandwich it in the Y direction.

[0041] (Cross-sectional structure) Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure of the memory region of the memory cell array in the semiconductor memory device according to the embodiment. As shown in Figure 5, the memory cell array 10 further includes wiring layers 21-25 and insulating layers 40-46. Figure 6 is an enlarged cross-sectional view of region VI in Figure 5, showing an example of the cross-sectional structure of the memory pillar in the semiconductor memory device according to the embodiment.

[0042] As shown in Figure 5, the insulating layer 40, wiring layer 21, insulating layer 41, wiring layer 22, and insulating layer 42 are stacked in this order. The wiring layer 21 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 21 is used as a source line SL. The wiring layer 21 contains, for example, phosphorus-doped silicon. The wiring layer 22 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 22 is used as a selection gate line SGS. The wiring layer 22 contains, for example, tungsten. The wiring layer 22 may also include a barrier film, for example, aluminum oxide (AlO), to cover its surface. The insulating layer 40 includes, for example, wiring and pads (not shown) for the semiconductor memory device 3 to connect to external devices.

[0043] Above the insulating layer 42, the wiring layer 23 and the insulating layer 43 are stacked alternately, one layer at a time. In the example shown in Figure 5, eight wiring layers 23 and eight insulating layers 43 are stacked alternately, one layer at a time. Each wiring layer 23 is formed, for example, as a plate stretched along the X direction on the XY plane. Each wiring layer 23 is used as word lines WL0 to WL7, in order from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten. Each wiring layer 23 may also contain a barrier film, for example, AlO, covering its surface.

[0044] Above the uppermost insulating layer 43, the wiring layer 24, insulating layer 44, and insulating layer 45 are stacked in this order. The wiring layer 24 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 24 is used as a selected gate wire SGD. The wiring layer 24 contains, for example, tungsten. The wiring layer 24 may also contain a barrier film, for example, AlO, covering its surface.

[0045] The number of wiring layers 22, 23, and 24 is not limited to the above structure. For example, multiple wiring layers 22 or 24 may be provided. For example, the wiring layer 23 may be stacked in nine or more layers. The number of insulating layers 42, 43, and 44 may vary depending on the number of wiring layers 22, 23, and 24.

[0046] A wiring layer 25 is laminated above the insulating layer 45. The wiring layer 25 is formed, for example, in a line extending along the Y direction. The wiring layer 25 is used as a bit line BL. In a region not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper.

[0047] An insulating layer 46 is stacked above the wiring layer 25. The insulating layer 46 includes, for example, a plurality of wirings (not shown) for connecting the memory cell array 10 to a low decoder module 16 and a sense amplifier module 17, which are located further above it.

[0048] As shown in Figure 6, each insulating layer 43 includes a first insulating film 43a, a second insulating film 43b, and a third insulating film 43c. The first insulating film 43a is provided in the center of the insulating layer 43. The first insulating film 43a includes, for example, silicon oxide (SiO). The second insulating film 43b is provided so as to cover the lower surface of the corresponding first insulating film 43a. The third insulating film 43c is provided so as to cover the upper surface of the corresponding first insulating film 43a. That is, the second insulating film 43b and the third insulating film 43c are provided so as to sandwich the corresponding first insulating film 43a in the Z direction. The second insulating film 43b and the third insulating film 43c include a different film type than the first insulating film 43a, for example, carbon-doped silicon oxide (SiOC). When SiOC is used for the second insulating film 43b and the third insulating film 43c, the elemental ratio of carbon is adjusted so that the etching rate during etching with hydrofluoric acid is lower than that of the film type used for the cover insulating film 36, which will be described later.

[0049] Although not shown in the figures, each of the insulating layers 41, 42, and 44 similarly includes a first insulating film, a second insulating film, and a third insulating film, respectively. Each first insulating film is provided in the center of the corresponding insulating layer 41, 42, or 44. Each first insulating film contains, for example, SiO. Each second insulating film is provided so as to cover the lower surface of the corresponding first insulating film. Each third insulating film is provided so as to cover the upper surface of the corresponding first insulating film. That is, the second and third insulating films are provided so as to sandwich the corresponding first insulating film in the Z direction. Each second and each third insulating film contains a different film type than the first insulating film, for example, SiOC. When SiOC is used for the second and third insulating films, the elemental ratio of carbon is adjusted so that the etching rate during etching with hydrofluoric acid is lower than that of the film type used for the cover insulating film 36, which will be described later.

[0050] As shown in Figure 5, the insulating layer 45 includes an insulator 45a and a coating film 45b. The insulator 45a includes, for example, TEOS (Tetra Ethoxy Silane). The coating film 45b is provided between the insulator 45a and the underlying multilayer wiring. The coating film 45b is thinner than, for example, the thickness in the Z direction of the wiring layers 22-24 and the insulating layers 41-44, and has a film thickness of about 6 nm. The coating film 45b includes a different film type than the insulator 45a, for example, SiOC. When SiOC is used for the coating film 45b, the elemental ratio of carbon is adjusted so that the etching rate during etching with hydrofluoric acid is lower than that of the film type used for the cover insulating film 36, which will be described later.

[0051] Each of the memory pillars MP is provided extending along the Z direction. Each of the memory pillars MP penetrates the wiring layers 22-24 and the insulating layers 41-44.

[0052] Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, and a multilayer film 32. The core film 30 is provided stretched along the Z direction. For example, the upper end of the core film 30 is located within the insulating layer 45, and the lower end of the core film is located within the wiring layer 21. The core film 30 includes, for example, an insulator such as SiO. The semiconductor film 31 covers the periphery of the core film 30. At the lower end of the memory pillar MP, a portion of the semiconductor film 31 is in contact with the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion in contact with the semiconductor film 31 and the wiring layer 21.

[0053] In the structure of the memory pillar MP shown in Figure 5, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a selection transistor ST2. The portions where the memory pillar MP intersects with each wiring layer 23 function as memory cell transistors MT0 to MT7, respectively. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a selection transistor ST1.

[0054] A columnar contact CV is provided on the upper surface of the semiconductor film 31 within the memory pillar MP. In the region shown in Figure 5, two of the six memory pillar MPs are shown, each with two corresponding contact CVs. For memory pillar MPs in this region that do not overlap with member SHE and do not have contact CVs connected to them, other contact CVs are connected in a region not shown.

[0055] Each contact CV has a wiring layer 25, i.e., one bit line BL, in contact with its upper surface. One contact CV is connected to each wiring layer 25 in each of the spaces separated by members SLT and SHE. In other words, each wiring layer 25 is electrically connected, for example, to one memory pillar MP in each region between adjacent members SLT and SHE, and to one memory pillar MP in each region between two adjacent members SHE.

[0056] The SLT members are formed, for example, to extend along the XZ plane. Each SLT member divides the wiring layers 22-24 and the insulating layers 41-44 in the Y direction. Each SLT member may have a tapered shape, for example, in which its width in the Y direction decreases from top to bottom.

[0057] Within the component SLT, the contact LI is provided so as to extend along the XZ plane, and the spacer SP is provided between the contact LI and the wiring layers 22-24 and the insulating layers 41-45. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is located, for example, within the wiring layer 21. Note that the contact LI may be omitted depending on the structure of the memory cell array 10.

[0058] Component SHE is formed, for example, as a plate extending along the XZ plane, and divides the wiring layer 24. The upper end of component SHE is located within the insulating layer 45. The lower end of component SHE is located within, for example, the uppermost insulating layer 43. Component SHE contains an insulator such as SiO. The upper end of component SHE and the upper end of component SLT may or may not be aligned. Similarly, the upper end of component SHE and the upper end of the memory pillar MP may or may not be aligned.

[0059] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar MP in a semiconductor memory device according to the embodiment. More specifically, Figure 6 shows the cross-sectional structure of the memory pillar MP in the XY plane including the wiring layer 23. As shown in Figure 6, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, a block insulating film 35, and a cover insulating film 36.

[0060] As shown in Figure 6, in a cross-section including the wiring layer 23, the memory pillar MP has a circular cross-sectional shape. As shown in Figures 6 and 7, in a cross-section including the wiring layer 23, the core film 30 is provided, for example, in the center of the memory pillar MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The block insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the block insulating film 35.

[0061] The semiconductor film 31 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 33 is used as a potential barrier between the semiconductor film 31 and the charge storage film 34. The tunnel insulating film 33 includes, for example, SiO. The charge storage film 34 has the function of storing charge. The charge storage film 34 includes, for example, silicon nitride (SiN). The block insulating film 35 suppresses back tunneling of charge from the wiring layer 23 to the memory pillar MP. The block insulating film 35 includes, for example, SiO.

[0062] As shown in Figure 8, in a cross-section including the insulating layer 43, the memory pillar MP has a circular cross-sectional shape. As shown in Figures 6 and 8, in a cross-section including the insulating layer 43, the core film 30 is provided, for example, in the center of the memory pillar MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The cover insulating film 36 surrounds the sides of the charge storage film 34. The insulating layer 43 surrounds the sides of the cover insulating film 36.

[0063] The cover insulating film 36 effectively divides the charge storage film 34. The cover insulating film 36 suppresses the movement of charge stored in the charge storage film 34 in the Z direction. This suppresses data interference between memory cell transistors MT. The cover insulating film 36 contains a different film type than the coating film 45b, and may include, for example, SiO, hafnium oxide, or zirconium oxide.

[0064] As shown in Figures 7 and 8, the radial thickness R34a of the charge storage film 34 in the XY cross-section including the wiring layer 23 is greater than the radial thickness R34b of the charge storage film 34 in the XY cross-section including the insulating layer 43. The radial thickness R35 of the block insulating film 35 in the XY cross-section including the wiring layer 23 is less than the radial thickness R36 of the cover insulating film 36 in the XY cross-section including the insulating layer 43. The combined radial thickness of the charge storage film 34 and the block insulating film 35 in the XY cross-section including the wiring layer 23 (R34a + R35) is approximately equal to or less than the combined radial thickness of the charge storage film 34 and the cover insulating film 36 in the XY cross-section including the insulating layer 43 (R34b + R36) (R34a + R35 ≤ R34b + R36).

[0065] Although not shown in the figures, in the XY cross-sections including wiring layers 22 and 24, the memory pillar MP has the same configuration as shown in Figures 6 and 7, similar to the XY cross-section including wiring layer 23. In the XY cross-sections including insulator layers 41, 42, 44, and 45, the memory pillar MP has the same configuration as shown in Figures 6 and 8, similar to the XY cross-section including insulator layer 43.

[0066] The radii of the memory pillars MP in each XY cross-section including wiring layers 22-24 do not necessarily have to be equal. The radii of the memory pillars MP in each XY cross-section including insulator layers 41-45 do not necessarily have to be equal. For example, the memory pillars MP may have a tapered shape such that their diameter decreases from top to bottom. Also, the cross-sectional shape of the memory pillars MP in an XY cross-section including either wiring layers 22-24 or insulator layers 41-45 may be elliptical.

[0067] With the above configuration, each memory pillar MP can function as a single NAND string NS.

[0068] 1.4.3 Drawer area (Flat layout) Figure 9 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the embodiment. In Figure 9, the extraction region HA and a part of the nearby memory region MA are shown. Note that in Figure 9, some insulating layers are omitted for simplicity of explanation. As shown in Figure 9, in the extraction region HA, the memory cell array 10 includes a plurality of contacts CC.

[0069] As shown in Figure 9, in the lead-out region HA, each of the wiring layers 22, 23, and 24 has a terrace portion that does not overlap in the Z direction with the wiring layers 23 and 24 located above it. The shape of the terrace portion in the lead-out region HA is similar to a step, terrace, rimstone, etc. The terrace portions of each of the wiring layers 22, 23, and 24 are aligned in the X direction, for example. Contacts CC are connected to each of the terrace portions of wiring layers 22 and 23, respectively.

[0070] As shown in Figure 9, the selected gate line SGD includes selected gate lines SGD0 to SGD4, which are divided into five sections in the Y direction by four members SHE at the terrace portion of the corresponding wiring layer 24. Each section of selected gate lines SGD0 to SGD4, divided in the Y direction by the four members SHE, is insulated from one another. Contact CC is connected to each terrace portion of selected gate lines SGD0 to SGD4.

[0071] Multiple contact CCs are provided in the lead-out region HA, corresponding to the selected gate lines SGS and SGD, and the word lines WL0 to WL7, respectively. As shown in Figure 9, the multiple contact CCs corresponding to the selected gate line SGD are arranged in the Y direction. The multiple contact CCs corresponding to the selected gate line SGS and the word lines WL0 to WL7 are arranged, for example, in the X direction.

[0072] (Cross-sectional structure) Figure 10 is a cross-sectional view along the line X'-X' in Figure 9 of the extraction region of the memory cell array in the semiconductor memory device according to the embodiment. Figure 10 shows the XZ cross-section of the extraction region HA and contact CC. As shown in Figure 10, in the extraction region HA, the memory cell array 10 further includes a plurality of wiring layers 26.

[0073] As shown in Figure 10, in the lead-out region HA, a staircase structure is provided such that each terrace portion of the wiring layers 22 to 24 descends sequentially in the direction away from the memory region MA. The insulating layers 42 to 44, which are stacked so as to be in contact with the upper surface of each wiring layer 22 to 24, are provided so as to cover one of the corresponding terrace portions of the wiring layers 22 to 24. That is, the staircase structure is such that each pair of wiring layer 22 and insulating layer 42, each pair of wiring layer 23 and insulating layer 43, and each pair of wiring layer 24 and insulating layer 44 each constitute one step of the staircase.

[0074] The insulating layer 45 is provided so as to embed the staircase structure. Specifically, the coating film 45b is provided so as to cover the top surface (tread) and side surface (riser) of the staircase structure. That is, the coating film 45b covers each terrace portion and the X-direction side portion at each end of the wiring layers 22 to 24. The insulator 45a is embedded above the coating film 45b.

[0075] Multiple contact CCs are provided extending in the Z direction. The upper surface of each contact CC is in contact with the wiring layer 26. The lower surface of each contact CC is in contact with one of the wiring layers 22 to 24 to which the contact CC corresponds. Each contact CC penetrates (passes through) in the Z direction the insulating layer 45 provided at the position where the contact CC is located in a plan view, and one of the insulating layers 42 to 44 provided so as to cover the terrace portion of the wiring layers 22 to 24 to which the contact corresponds.

[0076] Multiple wiring layers 26 are provided in contact with each of the multiple contact CCs. Each contact CC is electrically connected to the low decoder module 16 via the corresponding wiring layer 26.

[0077] 2. Manufacturing method Figure 11 is a flowchart showing an example of the manufacturing process for a memory cell array in a semiconductor memory device according to the embodiment. Figures 12 to 24 each show an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the embodiment. Figures 12 to 14, 16 to 17, and 22 to 24 show the region corresponding to Figure 10 and a part of the memory region MA shown in Figure 5. Figures 15 and 18 to 21 show the region corresponding to Figure 6.

[0078] As shown in Figure 11, in the manufacturing process of the memory cell array 10, processes S101 to S114 are executed in order. An example of the manufacturing process of the memory cell array 10 will be described below with reference to Figures 12 to 24 as appropriate.

[0079] In this embodiment, as a method for forming the multiple wiring layers 22, 23, and 24 corresponding to the selected gate lines SGS and SGD, and the word lines WL0 to WL7, for example, a method in which the structure corresponding to each wiring layer 22, 23, and 24 is formed with a sacrificial member, and then the sacrificial member is replaced with a conductive material to form each wiring layer (hereinafter referred to as "replacement") will be described.

[0080] First, processes S101 and S102 are performed in order to form a layered structure and a step structure in the extraction region HA. Specifically, an insulating layer 41, a sacrificial member 51, and an insulating layer 42 are stacked on the second semiconductor substrate W2 in this order. Eight layers of sacrificial member 52 and eight layers of insulating layer 43 are stacked alternately, one layer at a time, on the insulating layer 42. A sacrificial member 53 and an insulating layer 44 are stacked on the uppermost insulating layer 43 in this order (S101). Note that each of the insulating layers 41, 42, 43, and 44 is formed by stacking a second insulating film, a first insulating film, and a third insulating film in that order, respectively. The sacrificial members 51, 52, and 53 include, for example, SiN. Subsequently, as shown in Figure 12, a step structure is formed in the extraction region HA (S102). First, a mask is formed by photolithography or the like, with an opening in the part corresponding to the lowest step of the step structure. Then, anisotropic etching using the mask removes one step of the sacrificial member 52 and insulating layer 43. Next, the portion of the mask corresponding to the second lowest step of the staircase structure is removed. After that, anisotropic etching using the mask removes one step of the sacrificial member 52 and insulating layer 43. In this way, by repeatedly reducing the mask area and performing anisotropic etching, the sacrificial member 52 and insulating layer 43 are processed into a staircase shape. Finally, the portion of the mask corresponding to the second highest step of the staircase structure is removed, and anisotropic etching using the mask removes the sacrificial member 53 and insulating layer 44. In this way, the sacrificial member 53 and insulating layer 44 are processed into a staircase shape.

[0081] Next, process S103 is performed to deposit the coating film 45b and form the insulator 45a. Specifically, as shown in Figure 13, first, the coating film 45b is deposited on the surface of the laminated structure using CVD (Chemical Vapor Deposition) or the like. At this time, the coating film 45b is deposited not only on the top surface (tread) of the stair structure but also on the side surface (riser). After that, the insulator 45a is formed on the coating film 45b so as to embed the stair structure. For example, the top surface of the insulator 45a is flattened by CMP (Chemical Mechanical Polishing). As a result, the insulating layer 45 is formed.

[0082] Next, the process in S104 is executed to form holes MH corresponding to the memory pillars MP. Specifically, first, a mask is formed by photolithography or the like, with the regions corresponding to each memory pillar MP open. Then, as shown in Figure 14, multiple holes MH corresponding to each memory pillar MP are formed by anisotropic etching using this mask. Each hole MH penetrates the insulating layers 41-45 and the sacrificial members 51-53, respectively. The bottom of each hole MH is inside the second semiconductor substrate W2, and a part of the second semiconductor substrate W2 is exposed.

[0083] Next, process S105 is executed, forming a portion of the configuration corresponding to the core film 30, semiconductor film 31, and multilayer film 32 of the memory pillar MP. Specifically, as shown in Figure 15, first, the cover insulating film 36, charge storage film 34b, tunnel insulating film 33, semiconductor film 31, and core film 30 are deposited in order from the outside of the hole MH by ALD (Atomic Layer Deposition) or CVD. At this time, the thickness of the cover insulating film 36 is the radial thickness R36 of the cover insulating film 36 in the XY cross-section including the insulating layer 43. The thickness of the charge storage film 34b is the radial thickness R34b of the charge storage film 34 in the XY cross-section including the insulating layer 43. The charge storage film 34b contains, for example, SiN.

[0084] Next, the process in S106 is executed to form slits SH corresponding to the member SLT. Specifically, first, a mask is formed by photolithography or the like, with openings in the regions corresponding to each member SLT. Then, as shown in Figure 16, multiple slits SH corresponding to each member SLT are formed by anisotropic etching using this mask. Each slit SH divides the insulating layers 41-45 and the sacrificial members 51-53 in the Y direction. At the bottom of each slit SH, a portion of the second semiconductor substrate W2 is exposed.

[0085] Next, the process in S107 is performed to remove the sacrificial members 51, 52, and 53. Specifically, as shown in Figures 17 and 18, the sacrificial members 51, 52, and 53 are selectively etched and removed using a solution or gas containing phosphoric acid. This etching process is performed through the slit SH. The three-dimensional structure of the memory cell array 10 from which the sacrificial members 51, 52, and 53 have been removed is supported by a plurality of memory pillars MP and a plurality of support pillars (not shown) arranged as appropriate. The cover insulating film 36 is exposed in the areas from which the sacrificial members 51, 52, and 53 have been removed.

[0086] Next, the process in S108 is performed to remove the cover insulating film 36 in the exposed portion. Specifically, as shown in Figure 19, a solution or gas containing hydrofluoric acid (e.g., buffered hydrofluoric acid; BHF) is used to selectively isotropically etch and remove the cover insulating film 36 exposed in the portion where the sacrificial members 51, 52, and 53 have been removed. This etching process is performed through the slit SH. In the portion where the cover insulating film 36 has been removed, the charge storage film 34b is exposed.

[0087] Next, the process in S109 is executed to selectively grow the charge storage film 34 in the exposed portion. Specifically, as shown in Figure 20, the charge storage film 34a is grown on the surface of the charge storage film 34b, using the charge storage film 34b in the exposed portion as a seed. The combined thickness of the charge storage film 34b and the charge storage film 34a is the radial thickness R34a of the charge storage film 34 in the XY cross-section including the wiring layer 23. The charge storage film 34a contains, for example, SiN. In the following description, the charge storage films 34a and 34b will be described as a single charge storage film 34.

[0088] Next, process S110 is performed to deposit the block insulating film 35. Specifically, as shown in Figure 21, the block insulating film 35 is deposited on the surface of the exposed portion of the charge storage film 34 using ALD or CVD. The thickness of the block insulating film 35 is the radial thickness R35 of the block insulating film 35 in the XY cross-section including the wiring layer 23.

[0089] Next, the S111 process is performed to form wiring layers 22, 23, and 24. Specifically, as shown in Figure 22, a conductive material (e.g., tungsten) is embedded in the space where the sacrificial members 51, 52, and 53 have been removed via the slit SH by CVD or the like. If the wiring layers 22, 23, and 24 include a barrier film, the conductive material is embedded after the S110 process, for example, after AlO or the like has been formed as a barrier film. Subsequently, the conductive material formed inside the slit SH is removed by an etch-back process, and the conductive material is separated from adjacent wiring layers in the Z direction. As a result, wiring layer 22 which functions as a selective gate line SGS, multiple wiring layers 23 which each function as word lines WL0 to WL7, and wiring layer 24 which functions as a selective gate line SGD are formed.

[0090] Next, the process in S112 is executed, and as shown in Figure 23, a member SLT is formed in each slit SH. Also, although not shown, a member SHE is formed in the selected gate line SGD from the memory area MA to a part of the extraction area HA. ​​Specifically, first, a spacer SP is formed to cover the side and bottom surfaces of the slit SH. Then, a part of the spacer SP provided at the bottom of the slit SH is removed, and a part of the second semiconductor substrate W2 is exposed at the bottom of the slit SH. Then, a conductor (contact LI) is formed inside the slit SH, and the conductor formed outside the slit SH is removed, for example, by CMP. After that, multiple grooves are formed parallel to the member SLT in the region corresponding to the member SHE between adjacent member SLTs in the Y direction. Then, an insulator (for example, SiO) is embedded in each groove, thereby forming a member SHE that divides the wiring layer 24 in the Y direction. After that, as shown in Figure 23, an insulator 45a is further stacked.

[0091] Next, processes S113 to S114 are performed to form contact CC and CV, wiring layers 25 and 26, and an insulating layer 46, as shown in Figure 24. Specifically, first, a mask with openings corresponding to the contact CC and CV is formed by photolithography or the like. Then, holes corresponding to each of the contact CC and CV are formed by anisotropic etching using the mask. After that, a conductor is embedded in the holes to form the contact CC and CV (S113). Next, a wiring layer 25 that functions as a bit line BL is formed in contact with the upper surface of the contact CV and extending in the Y direction. A wiring layer 26 is formed in contact with the upper surface of the contact CC and extending in the Y direction. After that, an insulating layer 46 is formed above the wiring layers 25 and 26 (S114). After the completion of process S114, for example, a second semiconductor substrate W2 including the memory cell array 10 is bonded to the first semiconductor substrate. After bonding, for example, a portion of the second semiconductor substrate W2 and the laminated film 32 is removed, and the wiring layer 21 and the insulating layer 40 are formed. At this time, the wiring layer 21 and the semiconductor film 31 of the memory pillar MP are electrically connected.

[0092] The structure of the memory cell array 10 is formed by the manufacturing process described above. However, the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing step, or some steps may be omitted or integrated. Furthermore, each manufacturing step may be rearranged to the extent possible.

[0093] 3. Effects according to the embodiment According to the embodiment, this effect can improve the yield of semiconductor memory devices, and this effect will be described in detail below.

[0094] In the manufacturing process of the memory cell array 10 of the semiconductor memory device 3 according to this embodiment, when the cover insulating film 36 is removed in the process S108 shown in Figure 11, etching is performed using a solution or gas containing hydrofluoric acid. At this time, the solution or gas containing hydrofluoric acid flows not only around the memory pillar MP through the parts where the slit SH and sacrificial members 51, 52, and 53 have been removed, but also into the parts in the draw-out region HA where the staircase structure is formed. As a result, the solution or gas containing hydrofluoric acid may unintentionally remove parts of the insulating layers 42, 43, 44, and 45 in the side (riser) parts of the staircase structure. If the solution or gas containing hydrofluoric acid removes parts of the insulating layers 42, 43, 44, and 45 in the side parts of the staircase structure, for example, a hammerhead-shaped void is formed in the side parts of the staircase structure. Subsequently, in the process S111, a conductive material (for example, tungsten) is poured in to fill the void. As a result, the wiring layers forming the staircase structure are connected to the upper and lower wiring layers via the hammerhead-shaped portion, which could lead to short circuits between the wiring layers.

[0095] According to this embodiment, a coating film 45b is formed on the side surface of the stepped structure in the extraction region HA of the memory cell array 10. The coating film 45b contains, for example, SiOC, and its etching rate with hydrofluoric acid is lower than that of the cover insulating film 36. Therefore, during etching using a hydrofluoric acid-containing solution or gas in the process S108 shown in Figure 11, the removal of the insulating layers 42, 43, 44, and 45 on the side surface of the stepped structure is suppressed. As a result, voids are less likely to occur on the side surface of the stepped structure, and the occurrence of short circuits between wiring layers via conductive material embedded in these voids is suppressed, thereby improving the yield of the semiconductor memory device 3.

[0096] Furthermore, according to this embodiment, the radial thickness R34a of the charge storage film 34 in the XY cross-section including the wiring layers 22, 23, or 24 is greater than the radial thickness R34b of the charge storage film 34 in the XY cross-section including the insulating layers 41, 42, 43, 44, or 45. In other words, the continuity of the charge storage film 34 in the Z direction is effectively interrupted by the cover insulating film 36 in the cross-section including the insulating layers 41, 42, 43, 44, and 45. This makes it possible to suppress the movement of charges trapped in the charge storage film 34 to the charge storage film 34 corresponding to other adjacent memory cell transistors MT in the Z direction when the memory cell transistor MT is operating. That is, it is possible to suppress unintended changes in the data stored in the memory cell transistor MT due to charge movement, thereby improving the reliability of the semiconductor memory device 3.

[0097] 4. Variations The semiconductor memory device 3 according to this embodiment can be modified in various ways. The differences between the first and second modifications of the embodiment are described below.

[0098] 4.1 First Variation Figure 25 is a cross-sectional view showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to a first modified embodiment. The region shown in Figure 25 corresponds to the region shown in Figure 6 in the embodiment.

[0099] As shown in Figure 25, the memory cell array 10 of the semiconductor memory device 3 according to the first modified embodiment includes an insulating layer 43A instead of the insulating layer 43. The insulating layer 43A does not include the first insulating film 43a and the third insulating film 43c, but includes the second insulating film 43b.

[0100] Furthermore, although not shown in the figures, the insulating layers 41, 42, and 44 are similarly replaced with a configuration that includes the second insulating film, but does not include the first insulating film and the third insulating film.

[0101] 4.2 Second Variation Figure 26 is a cross-sectional view showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to a second modified embodiment. The region shown in Figure 26 corresponds to the region shown in Figure 6 in the embodiment.

[0102] As shown in Figure 26, the memory cell array 10 of the semiconductor memory device 3 according to the second modified embodiment includes an insulating layer 43B instead of the insulating layer 43. The insulating layer 43B includes a first insulating film 43a, a second insulating film 43b, and a fourth insulating film 43d. The second insulating film 43b is provided in the center of the insulating layer 43B. The first insulating film 43a is provided so as to cover the lower surface of the second insulating film 43b. The fourth insulating film 43d is provided so as to cover the upper surface of the second insulating film 43b. That is, the first insulating film 43a and the fourth insulating film 43d are provided so as to sandwich the corresponding second insulating film 43b in the Z direction. The fourth insulating film 43d includes, for example, SiO.

[0103] Furthermore, although not shown in the figures, the insulating layers 41, 42, and 44 are similarly configured such that the second insulating film is provided in the center of the insulating layer, and the first insulating film and the fourth insulating film cover the lower and upper surfaces of the second insulating film, sandwiching the second insulating film in the Z direction. The fourth insulating film includes, for example, SiO.

[0104] 5. Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0105] 1…Memory system 2…Memory controller 3…Semiconductor memory 10…Memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module 21, 22, 23, 24, 25, 26...wiring layer 30…Core film 31… Semiconductor film 32… Multilayer film 33...Tunnel insulating film 34, 34a, 34b...charge storage film 35…Block Insulating Film 36…Cover insulating film 40, 41, 42, 43, 43A, 43B, 44, 45, 46… Insulating layer 43a, 43b, 43c, 43d… insulating film 45a...insulator 45b...Coating film 51, 52, 53... Sacrificial members BL...bit line BLK...block CC, CV, LI… Contact CU... Cell Unit HA…Drawer area MA...Memory area MH... Hall MP...Memory Pillar MT...Memory cell transistor NS...NAND string SGD, SGS... Selectable gate lines SH...Slit SHE, SLT... components SL…Source Line SP...Spacer ST1, ST2…Selection transistor SU... String Unit W2… Semiconductor substrate WL...Word line

Claims

1. Viewed in a first direction, the system comprises a plurality of wiring layers and a plurality of first insulating films arranged alternately in the first direction, spanning a first region and a second region aligned in a second direction intersecting the first direction, A memory pillar extending in the first direction in the second region, passing through the plurality of wiring layers and the plurality of first insulating films, wherein the portion passing through the plurality of wiring layers functions as a plurality of memory cells, wherein the memory pillar comprises a first semiconductor extending in the first direction, a second insulating film provided between the first semiconductor and the plurality of wiring layers and the plurality of first insulating films, a charge storage film provided between the second insulating film and the plurality of wiring layers and the plurality of first insulating films, a plurality of third insulating films provided between the charge storage film and the plurality of wiring layers, and a plurality of fourth insulating films including a first film type provided between the charge storage film and the plurality of first insulating films, Within the first region, a fifth insulating film is provided so as to cover the side portions in the second direction at the ends of the plurality of wiring layers, and includes a second film type having a lower etching rate to hydrofluoric acid than the first film type, A semiconductor memory device equipped with the following features.

2. The second film species contains carbon, The semiconductor memory device according to claim 1.

3. The second film type includes carbon-doped silicon oxide, The semiconductor memory device according to claim 2.

4. The first film species includes silicon oxide, hafnium oxide, or zirconium oxide. The semiconductor memory device according to claim 3.

5. The plurality of wiring layers, within the first region, are greater than themselves among the plurality of wiring layers. The staircase structure has a wiring layer provided above and a terrace portion provided so as not to overlap in the first direction, which are arranged in the second direction. The semiconductor memory device according to claim 1.

6. The fifth insulating film further covers the terrace portion of the plurality of wiring layers, The memory pillar passes through the fifth insulating film in the first direction. The semiconductor memory device according to claim 5.

7. The thickness of the fifth insulating film is smaller than the thickness of each of the plurality of first insulating films. The semiconductor memory device according to claim 6.

8. The charge storage film is A plurality of first portions are provided between the second insulating film and the plurality of third insulating films, and the thickness in the second direction is a first thickness, A plurality of second portions are provided between the second insulating film and the plurality of fourth insulating films, and each second portion has a second thickness such that its thickness in the second direction is smaller than the first thickness, including, The semiconductor memory device according to claim 1.

9. Each of the plurality of fourth insulating films includes a portion that is sandwiched in the first direction by the plurality of first portions of the charge storage film that are spaced apart in the first direction. The semiconductor memory device according to claim 8.

10. The plurality of third insulating films have a third thickness in the second direction, The plurality of fourth insulating films have a fourth thickness in the second direction, The sum of the second thickness and the fourth thickness is approximately equal to or greater than the sum of the first thickness and the third thickness. The semiconductor memory device according to claim 8.

11. The first insulating film includes the second film type, The semiconductor memory device according to claim 1.

12. Each of the plurality of first insulating films is A third membrane type different from the second membrane type, and a third portion extending in the second direction, A plurality of fourth portions, including the second film type, extending in the second direction and provided so as to sandwich the third portion in the first direction, A semiconductor memory device according to claim 11, including the above.

13. Each of the plurality of first insulating films is A third portion comprising the second membrane type and extending in the second direction, A plurality of fourth portions, including a third film type different from the second film type, extending in the second direction and provided so as to sandwich the third portion in the first direction, A semiconductor memory device according to claim 11, including the above.

14. Further including a contact extending in a first direction within the first region and connected to one of the terrace portions of the plurality of wiring layers, The semiconductor memory device according to claim 5.

15. Viewed in a first direction, the system comprises a plurality of wiring layers and a plurality of first insulating films arranged alternately in the first direction, spanning a first region and a second region aligned in a second direction intersecting the first direction, Within the first region, a fifth insulating film containing a second film type containing carbon-doped silicon oxide is provided to cover the side portions in the second direction at the ends of the plurality of wiring layers, A memory pillar extending in the first direction in the second region, passing through the plurality of wiring layers and the plurality of first insulating films, with the portion passing through the plurality of wiring layers functioning as a plurality of memory cells, A semiconductor memory device equipped with the following features.

16. The plurality of wiring layers, within the first region, are greater than themselves among the plurality of wiring layers. The staircase structure has a wiring layer provided above and a terrace portion provided so as not to overlap in the first direction, which are arranged in the second direction. The semiconductor memory device according to claim 15.

17. The fifth insulating film further covers the terrace portion of the plurality of wiring layers, The memory pillar passes through the fifth insulating film in the first direction. The semiconductor memory device according to claim 16.

18. The thickness of the fifth insulating film is smaller than the thickness of each of the plurality of first insulating films. The semiconductor memory device according to claim 17.

19. The aforementioned memory pillar is A first semiconductor extending in the first direction, A second insulating film is provided between the first semiconductor, the plurality of wiring layers, and the plurality of first insulating films, A charge storage film is provided between the second insulating film and the plurality of wiring layers and the plurality of first insulating films, A plurality of third insulating films are provided between the charge storage film and the plurality of wiring layers, A plurality of fourth insulating films are provided between the charge storage film and the plurality of first insulating films, A semiconductor memory device according to claim 15, including the above.

20. Further including a plurality of contacts extending in a first direction within the first region and connected to each of the terrace portions of the plurality of wiring layers, The semiconductor memory device according to claim 16.

Images