Verification method, verification apparatus, program, and storage medium

Abstract

The present invention provides a verification method, verification apparatus, program, and storage medium that can suppress the occurrence of false errors in integrated circuits including CDC locations. [Solution] The verification method for an integrated circuit according to the embodiment comprises the steps of acquiring circuit operation information of the integrated circuit to be verified by logic simulation, and analyzing the circuit operation information to extract verification combinations. The verification method according to the embodiment further comprises the step of verifying the logic operation of the verification combinations that span clock domains for each flip-flop.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for verifying an integrated circuit, a verification apparatus, a program, and a storage medium.

Background Art

[0002] In an integrated circuit, a plurality of clock signals having different periods may be used. Hereinafter, a circuit block driven by the same clock signal is referred to as a "clock domain", and crossing different clock domains is referred to as "CDC (clock domain crossing)". At a location where CDC occurs (hereinafter referred to as a "CDC location"), depending on the timing of the data from the transmission-side clock domain and the clock signal of the reception-side clock domain, the reception-side clock domain may not be able to correctly capture the data. For verifying the signal transfer operation between different clock domains, clock domain crossing verification (hereinafter referred to as "CDC verification") is performed.

[0003] Conventionally, CDC verification and logic simulation are combined to confirm that the CDC verification is valid. Since the CDC verification is performed statically, for example, at a location where clock signals such as a CLKMUX (clock multiplexer) converge, when the selector signal is not fixed, the analysis target of the CDC verification may include combinations that cannot actually occur. When combinations that cannot actually occur are analyzed, the number of pseudo errors tends to increase. On the other hand, for the errors generated in the CDC verification, by performing a logic simulation, it is determined whether the errors in the CDC verification are correct.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] Even when combining CDC verification with logic simulation, the number of false errors in the CDC verification itself does not decrease. When a large number of false errors occur, it becomes relatively difficult to identify the real problem from among the errors in the CDC verification, increasing the possibility that the real problem may be overlooked. In addition, the process of identifying the real problem from among the errors in the CDC verification increases the costs of processing time, processing equipment, and human resources.

[0006] The problem that the embodiments of the present invention aim to solve is to provide a verification method, verification apparatus, program, and storage medium that can suppress the occurrence of false errors in integrated circuits including CDC locations. [Means for solving the problem]

[0007] A verification method for an integrated circuit according to an embodiment of the present invention comprises the steps of acquiring circuit operation information of the integrated circuit to be verified by logic simulation, and analyzing the circuit operation information to extract verification combinations. The verification method according to the embodiment further comprises the step of verifying the logic operation of the verification combination at locations that span clock domains for each flip-flop. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a flowchart of the verification method according to the embodiment. [Figure 2] Figure 2 is a diagram showing a detailed flowchart of step S3 in the verification method according to the embodiment. [Figure 3A] Figure 3A is a diagram illustrating the process of step S1 in the verification method according to the embodiment. [Figure 3B] Figure 3B is a diagram illustrating the process of step S1 in the verification method according to the embodiment. [Figure 3C] Figure 3C is a diagram illustrating the process of step S1 in the verification method according to the embodiment. [Figure 4] Figure 4 is a timing chart illustrating the processing of step S2 in the verification method according to the embodiment. [Figure 5] Figure 5 is a timing chart illustrating the processing of step S31a in the verification method according to the embodiment. [Figure 6] Figure 6 is a table illustrating the process of step S31b in the verification method according to the embodiment. [Figure 7A] Figure 7A is a table illustrating the process of step S31c in the verification method according to the embodiment. [Figure 7B] Figure 7B is a table illustrating the process of step S31c in the verification method according to the embodiment. [Figure 8A] Figure 8A is a table illustrating the process of step S32 in the verification method according to the embodiment. [Figure 8B] Figure 8B is a table illustrating the process of step S32 in the verification method according to the embodiment. [Figure 9A] Figure 9A is a diagram illustrating the process of step S4 in the verification method according to the embodiment. [Figure 9B] Figure 9B is a diagram illustrating the process of step S4 in the verification method according to the embodiment. [Figure 9C] Figure 9C is a diagram illustrating the process of step S4 in the verification method according to the embodiment. [Figure 9D] Figure 9D is a diagram illustrating the process of step S4 in the verification method according to the embodiment. [Figure 9E] Figure 9E is a diagram illustrating the process of step S4 in the verification method according to the embodiment. [Figure 10] Figure 10 is a schematic diagram of the verification apparatus according to the embodiment. [Figure 11] Figure 11 is a block diagram of the verification device according to the embodiment. [Modes for carrying out the invention]

[0009] Embodiments will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals and the description thereof will be omitted. The drawings are schematic.

[0010] In addition, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the materials, shapes, structures, arrangements, etc. of each component. Various changes can be made to this embodiment within the scope of the claims.

[0011] [Embodiment] (Verification Method) FIG. 1 is a flowchart of a verification method according to an embodiment. The verification method according to the embodiment includes the following steps. The specific content of the processing method for each step will be described later with reference to FIGS. 3 to 9E. First, the overall flow will be described.

[0012] In FIG. 1, after starting verification, in step S1, points to be observed in logic simulation are specified. In step S2, the states of the points specified in step S1 are observed in logic simulation. In steps S1 and S2 above, circuit operation information of the integrated circuit to be verified is obtained by logic simulation. In step S3, the circuit operation information of the points (hereinafter referred to as "observation points") observed in step S2 is analyzed to extract verification combinations of the observation points.

[0013] In step S4, for the observation points specified in step S1, for each verification combination extracted in step S3, more specifically, for each between flip flops (hereinafter referred to as "FF") and for each combination of clock signals, CDC verification is performed.

[0014] In step S5, it is determined whether CDC verification has been performed for all observation points. If CDC verification has not been performed for all observation points, the process returns to step S2, and for the observation points where CDC verification has not been performed, the missing processing is carried out, and then CDC verification is performed. However, it is not necessarily required to return to step S2 if CDC verification has not been performed for all observation points. For example, if the flow is to perform the processing up to step S3 for all observation points before proceeding to step S4, it is also acceptable to return to step S4. If CDC verification has been performed for all observation points, the verification is terminated.

[0015] Step S3 in the flowchart of Figure 1 includes further detailed steps. Figure 2 is a diagram showing a detailed flowchart of step S3 in the verification method according to the embodiment.

[0016] In Figure 2, after starting step S3, step S31 extracts combinations of observed point states. Step S31 includes more detailed steps S31a, S31b, and S31c. In step S31a, values ​​are extracted from the point information observed in the logic simulation. In step S31b, the combinations of values ​​extracted in step S31a are written out. In step S31c, identical combinations are removed from the combinations of values ​​written out in step S31b.

[0017] In step S32, the combination of values ​​obtained in step S31c and the information of the observation points identified in step S1 are used to extract the combination of the propagating clock signal. After completing steps S31 and S32, step S3 is terminated.

[0018] Next, we will explain the specific processing steps in the flowchart of the verification method described in Figures 1 and 2.

[0019] Figures 3A, 3B, and 3C illustrate the specific processing of step S1 in the verification method according to the embodiment. In step S1, the points where different clock signals merge are traced from the circuit data described in RTL (Resister Transfer Level) and the data describing the timing constraints (hereinafter referred to as "timing constraints"). Then, locations that can structurally cross clock domains are extracted and identified as points to be observed in logic simulation. Specifically, the following processing is performed as shown in (a1) to (b2).

[0020] (a1) Extract the points in the RTL or timing constraints where a "create_clock" statement that defines the base clock signal or a "create_generated_clock" statement that defines the derived clock signal is written.

[0021] (a2) From the points extracted in (a1), trace the circuit described in RTL in the downstream direction of the signal.

[0022] (b1) In the RTL, extract the points where the clock pulse input pin (hereinafter referred to as the "CP pin") of the flip-flop is defined.

[0023] (b2) From the points extracted in (b1), trace the circuit described in RTL in the upstream direction of the signal.

[0024] Figures 3A, 3B, and 3C show an example of specifically performing the aforementioned processes (a1) to (b2) on an integrated circuit 100, which is an example of an integrated circuit.

[0025] Figure 3A shows the state after step S1 has started, where the clock signal specification statement and the CP pin specification statement have been extracted at observation point 1, which is part of the integrated circuit 100 and the timing constraint, by the aforementioned processes (a1) and (b1). Figure 3A shows the state before the tracing of processes (a2) and (b2) is performed.

[0026] As a result of performing process (a1), at observation point 1, three clock signals clk_a, clk_b, and clk_c, defined by a basic clock signal definition statement or a derived clock signal definition statement, are extracted to the clock signal definition unit C11 of the integrated circuit 100 and the timing constraint. In addition, three clock signals clk_d, clk_e, and clk_f, defined by a basic clock signal definition statement or a derived clock signal definition statement, are extracted to the clock signal definition unit C12 of the integrated circuit 100 and the timing constraint.

[0027] On the other hand, as a result of performing processing (b1), the CP pin FFCP11 of FF11 and the CP pin FFCP12 of FF12 were extracted at observation point 1.

[0028] With respect to Figure 3A, the process (a2) is then performed to trace the circuits through which the clock signals clk_a, clk_b, and clk_c propagate in the circuit region 11 located downstream of the clock signal defining unit C11 in the integrated circuit 100. Similarly, the circuits through which the clock signals clk_d, clk_e, and clk_f propagate are traced in the circuit region 12 located downstream of the clock signal defining unit C12. This process of tracing the circuits through which the clock signals propagate in the circuit region located downstream of the clock signal defining unit is defined as the first trace.

[0029] Furthermore, with respect to Figure 3A, the process (b2) is continued to trace the circuit that generates the signal input to CP pin FFCP11 in the circuit region 11 located upstream of CP pin FFCP11 in the integrated circuit 100. Similarly, the circuit that generates the signal input to CP pin FFCP12 is traced in the circuit region 12 located upstream of CP pin FFCP12. This process of tracing the circuit that generates the signal input to CP pins in the circuit region located upstream of CP pins is defined as the second trace.

[0030] The tracing continues until the trace performed downstream from the clock signal regulating unit C11 and the trace performed upstream from the CP pin FFCP11 collide, and a circuit that receives a signal from the clock signal regulating unit C11 and outputs a signal to the CP pin FFCP11 is extracted. Similarly, the tracing continues until the trace performed downstream from the clock signal regulating unit C12 and the trace performed upstream from the CP pin FFCP12 collide, and a circuit that receives a signal from the clock signal regulating unit C12 and outputs a signal to the CP pin FFCP12 is extracted.

[0031] Figure 3B shows the point at which tracing is completed in circuit regions 11 and 12, as described above with reference to Figure 3A.

[0032] In circuit region 11, selectors 111 and 112 are extracted, which receive signals from the clock signal definition unit C11 and output signals to the CP pin FFCP11 of FF11. Selector 111 receives clock signals clk_a and clk_b and selection signal sel2 as inputs and outputs the selected clock signal sg111. Selector 112 receives the selected clock signal sg111, clock signal clk_c and selection signal sel1 as inputs and outputs the selected clock signal sg14. The selected clock signal sg14 is input to the CP pin FFCP11 of FF11.

[0033] Here, the function of the selector will be explained using selector 111 as an example. When the value of the selection signal sel2 is 0 (logical low level), selector 111 selects the clock signal clk_a to be input to the input terminal marked "0" and outputs it as the selected clock signal sg111. When the value of the selection signal sel2 is 1 (logical high level), selector 111 selects the clock signal clk_b to be input to the input terminal marked "1" and outputs it as the selected clock signal sg111.

[0034] In circuit region 12, selectors 121 and 122 are extracted, which receive signals from the clock signal definition unit C12 and output signals to the CP pin FFCP12 of the FF12. Selector 121 receives clock signals clk_d and clk_e and selection signal sel4, and outputs the selected clock signal sg121. Selector 122 receives the selected clock signal sg121, clock signal clk_f and selection signal sel3, and outputs the selected clock signal sg15. The selected clock signal sg15 is input to the CP pin FFCP12 of the FF12.

[0035] FF11 generates signal sg11 based on the post-selection clock signal sg14 input to CP pin FFCP11 and outputs it from the data output terminal. Between the two flip-flops FF11 and FF12 at observation point 1, there is a logic circuit L11. Signal sg11 output from the data output terminal of FF11 passes through logic circuit L11 to become signal sg12, which is input to the data input terminal of FF12. FF12 generates signal sg13 based on signal sg12 input to the data input terminal and the post-selection clock signal sg15 input to CP pin FFCP12, and outputs it from the data output terminal.

[0036] At the end of the trace in step S1 shown in Figure 3B, the timing relationship between signal sg12 and the selected clock signal sg15 is unknown, and therefore it is unclear whether it will be CDC. However, since multiple clock signals are input to the circuit that generates signal sg12 and the selected clock signal sg15, signal sg12 and the selected clock signal sg15 can structurally be CDC. Therefore, in step S1, observation point 1, which includes the circuit described above, is extracted and identified.

[0037] Figure 3C shows the circuit regions 21 and 22 at observation point 2 of the integrated circuit 100 after the same processing as described with reference to Figures 3A and 3B has been performed, and the tracing of circuit regions 21 and 22 has been completed. The diagram before the tracing was performed, similar to Figure 3A, is not explained.

[0038] In circuit region 21, a selector 211 is extracted that receives a signal from the clock signal definition unit C21 and outputs a signal to the CP pin FFCP21 of FF21. Selector 211 receives the clock signals clk_a and clk_b and the selection signal sel5 as inputs and outputs the selected clock signal sg24. The selected clock signal sg24 is input to the CP pin FFCP21 of FF21.

[0039] In circuit region 22, selectors 221 and 222 are extracted, which receive signals from the clock signal definition unit C22 and output signals to the CP pin FFCP22 of FF22. Selector 221 receives clock signals clk_d and clk_e and selection signal sel7, and outputs the selected clock signal sg221. Selector 222 receives clock signal clk_g, the selected clock signal sg221 and selection signal sel6, and outputs the selected clock signal sg25. The selected clock signal sg25 is input to the CP pin FFCP22 of FF22.

[0040] FF21 generates signal sg21 based on the selected clock signal sg24 input to the CP pin FFCP21 and outputs it from the data output terminal. Between the two flip-flops FF21 and FF22 at observation point 2, there is a logic circuit L21. Signal sg21 output from the data output terminal of FF21 passes through logic circuit L21 to become signal sg22, which is input to the data input terminal of FF22. FF22 generates signal sg23 based on signal sg22 input to the data input terminal and the selected clock signal sg25 input to the CP pin FFCP22, and outputs it from the data output terminal.

[0041] At the end of the trace in step S1 shown in Figure 3C, the timing relationship between signal sg22 and the selected clock signal sg25 is unknown, and therefore it is unclear whether it will be CDC. However, since multiple clock signals are input to the circuit that generates signal sg22 and the selected clock signal sg25, it is structurally possible for it to be CDC. Therefore, in step S1, observation point 2, which includes the circuit described above, is extracted and identified.

[0042] In step S1, the same processes (a1) to (b2) are performed at other observation points in the integrated circuit 100, and observation points containing circuits that can structurally become CDCs are extracted and identified. Once all observation points of the integrated circuit 100 have been identified, step S1 is terminated.

[0043] Figure 4 is a timing chart illustrating the specific processing of step S2 in the verification method according to the embodiment. In step S2, the state of the observation point identified in step S1 is observed by logic simulation. More specifically, the control signal or output clock signal of the observation point identified in step S1 is observed by logic simulation, and information such as the logic simulation operation waveform is output. As an example, Figure 4 shows the case where the state of observation point 1 identified as shown in Figure 3B is observed by logic simulation and the logic simulation operation waveform is output.

[0044] Referring to Figure 3B, in the circuit region 11 of the identified observation point 1, the selectors 111 and 112 are input with selection signals sel2 and sel1. In the circuit region 12, the selectors 121 and 122 are input with selection signals sel4 and sel3. Figure 4 shows the logic simulation waveforms observed by logic simulation, showing the states that the selection signals sel1 to sel4 at observation point 1 take during a series of operations of the integrated circuit 100.

[0045] In Figure 4, the horizontal axis of the logic simulation waveform represents time, and the vertical axis represents the logic level. The logic level can be either a binary value of 0 or 1, or an undefined X (not shown in Figure 4, which is either 0 or 1, but the specific state is not determined). This logic simulation may be performed using a test vector, which describes the input signals that cause the integrated circuit 100 to perform the operation to be verified, relative to the time axis. Alternatively, the logic simulation may be performed using a state transition diagram or command table of the integrated circuit 100. In Figure 4, the logic levels of the selection signals sel1 to sel4 change at different timings.

[0046] In step S2, if a logic simulation waveform including all nodes of the integrated circuit 100 already exists, the logic simulation waveform of the observation point may be extracted from that logic simulation waveform.

[0047] Figures 5, 6, 7A, 7B, 8A, and 8B illustrate the specific processing of step S3 in the verification method according to the embodiment. In step S3, verification combinations of points whose states were observed in step S2 are extracted. Since CDC verification is performed between flip-flops, the observation results obtained in step S2 are decomposed into combinations of states that can be taken between flip-flops, and the combinations of clock signals are compressed into combinations of propagating clock signals, thereby reducing and extracting the verification combinations for which CDC verification is performed. Step S3 includes steps S31 and S32. Step S31 includes further detailed steps S31a, S31b, and S31c.

[0048] Figure 5 is a timing chart illustrating the specific processing of step S31a included in step S31. Step S31a extracts values ​​from the observation point information observed in the logic simulation in step S2. More specifically, in the logic simulation waveform obtained in step S2, as shown in Figure 4, the mode is divided as described later at the timing when the state of any signal changes. In Figure 5, the waveforms of the selection signals sel1 to sel4 are the same as in Figure 4.

[0049] In Figure 5, the combination of states of selection signals sel1 to sel4 is called a "mode," and the series of modes that switch over time are called modes M1 to MN (where N is a natural number). Observation point 1 of the integrated circuit 100 is in mode M1 in its initial state. Next, in response to the change of selection signal sel1 from 0 to 1, the mode of observation point 1 switches to mode M2. Next, in response to the change of selection signal sel4 from 0 to 1, the mode of observation point 1 switches to mode M3. Similarly thereafter, when any of the states of selection signals sel1 to sel4 change, the mode of observation point 1 switches to a different mode, and as the last change shown in Figure 5, when selection signal sel4 changes from 1 to 0, it switches to mode M8.

[0050] Figure 6 is a table illustrating the specific processing of step S31b, which is included in step S31. While step S31a divides the logic simulation waveform into modes M1 to M8, step S31b writes out the combinations of values ​​for the selection signals sel1 to sel4 for each mode.

[0051] In the logic simulation waveform shown in Figure 5, the values ​​of the selection signals sel1 to sel4 are, for example, 0, 0, 1, 0 in mode M1 and 1, 0, 1, 0 in mode M2. In Figure 6, modes M1 and M2 are listed in the rows of the table, and the selection signals sel1 to sel4 are listed in the columns of the table, writing out the values ​​of the selection signals sel1 to sel4 in modes M1 and M2. This process of writing out the values ​​of the selection signals in each mode is performed for all modes in the logic simulation waveform.

[0052] Figures 7A and 7B are tables illustrating the specific processing of step S31c, which is included in step S31. In step S31c, duplicate combinations of values ​​for the mode-specific selection signals sel1 to sel4, which were written out in step S31b, are excluded.

[0053] The table shown in Figure 7A is the same as the table in Figure 6. In the table in Figure 7A, the combinations of values ​​for selection signals sel1 to sel4 in mode M7 are the same as those for mode M3. The combinations of values ​​for mode M7 are represented by mode M3, and mode M7 is removed from the table. Also, the combinations of values ​​for selection signals sel1 to sel4 in mode M8 are the same as those for mode M2. The combinations of values ​​for mode M8 are represented by mode M2, and mode M8 is removed. Figure 7B is a table obtained by removing the identical combinations from Figure 7A as described above and leaving only the combinations of different values.

[0054] Figures 8A and 8B are tables illustrating the specific processing in step S32. In step S32, combinations of propagating clock signals are extracted. Figures 9A to 9C are diagrams illustrating the specific processing in step S4. Details will be described later, but they illustrate examples of combinations of propagating clock signals extracted in step S32, so please refer to them as well.

[0055] The table in Figure 8A, like the table in Figure 7B, shows the combinations of values ​​for the selection signals sel1 to sel4 that can be taken in modes M1 to M8. The table in Figure 8A further lists the propagating clock signals. The combinations of propagating clock signals for each of modes M1 to M8 in the table in Figure 8A are extracted by referring to the table in Figure 8A and the circuit at observation point 1 in Figure 3B, as follows.

[0056] Referring to Figure 8A, in mode M1, the selection signals sel1 and sel2 take the values ​​of 0 and 0, respectively. Referring to Figure 3B, when the selection signal sel2=1 is input to selector 111, it selects the clock signal clk_b and outputs it as the selected clock signal sg111. Similarly, when the selection signal sel1=0 is input to selector 112, it selects the selected clock signal sg111 and outputs it as the selected clock signal sg14. As described above, in mode M1, the clock signal clk_a propagates to the CP pin FFCP11. Figure 9A illustrates that in mode M1 at observation point 1, the clock signal clk_a propagates to the CP pin of FF11.

[0057] On the other hand, referring to Figure 8A, in mode M1, the selection signals sel3 and sel4 take values ​​of 1 and 0, respectively. Referring to Figure 3B, when the selection signal sel4=0 is input to selector 121, it selects the clock signal clk_d and outputs it as the selected clock signal sg121. Similarly, when the selection signal sel3=1 is input to selector 122, it selects the clock signal clk_f and outputs it as the selected clock signal sg15. Thus, in mode M1, the clock signal clk_f propagates to the CP pin FFCP12. Figure 9A illustrates that in mode M1, the clock signal clk_f propagates to the CP pin of FF12.

[0058] Next, referring to Figure 8A, in modes M2 to M4, the selection signal sel1 takes the value 1, and sel2 takes the value 0 or 1. Referring to Figure 3B, when the selection signal sel1=1 is input to selector 112, it selects the clock signal clk_c and outputs it as the selected clock signal sg14.

[0059] In modes M2 to M4, regardless of whether the selection signal sel2 input to selector 111 is 0 or 1, the post-selection clock signal sg111, which is the output of selector 111, does not propagate to the output of selector 112, and the clock signal propagated as the post-selection clock signal sg14 is the same. In this case, 0 and 1 for sel2 can be treated as indistinguishable. This is referred to as "don't care" for the value of the selection signal sel2 input to selector 111 in modes M2 to M4 of observation point 1, and will be denoted as "sel2=*" hereafter.

[0060] As described above, in modes M2 to M4, the clock signal clk_c propagates to the CP pin FFCP11. Figure 9B illustrates that the clock signal clk_c propagates to the CP pin of FF11 in modes M2 to M4.

[0061] On the other hand, referring to Figure 8A, in modes M2 to M4, the selection signal sel3 takes the value 1, and sel4 takes the value 0 or 1. Referring to Figure 3B, when the selection signal sel3=1 is input to selector 122, it selects the clock signal clk_f and outputs it as the post-selection clock signal sg15. The post-selection clock signal sg121, which is the output of selector 121, does not propagate to the output of selector 122, so the result is the same regardless of whether the selection signal sel4 input to selector 121 is 0 or 1. As described above, in modes M2 to M4, the clock signal clk_f propagates to the CP pin FFCP12. Figure 9B illustrates that in modes M2 to M4, the clock signal clk_f propagates to the CP pin of FF12.

[0062] Next, referring to Figure 8A, in modes M5 to M6, the selection signal sel1 takes the value 1, and sel2 takes the value 0 or 1. This is the same as in modes M2 to M4, so a detailed explanation will be omitted, but the clock signal clk_c propagates to the CP pin FFCP11. Figure 9C illustrates that the clock signal clk_c propagates to the CP pin of FF11 in modes M5 to M6.

[0063] On the other hand, referring to Figure 8A, in modes M5 to M6, the selection signal sel3 takes the value 0 and sel4 takes the value 1. Referring to Figure 3B, when the selection signal sel3=0 is input to selector 122, it selects the post-selection clock signal sg121 and outputs it as the post-selection clock signal sg15. When the selection signal sel4=1 is input to selector 121, it selects the clock signal clk_e and outputs it as the post-selection clock signal sg121. As described above, in modes M5 to M6, the clock signal clk_e propagates to the CP pin FFCP12. Figure 9C illustrates that in modes M5 to M6, the clock signal clk_e propagates to the CP pin of FF12.

[0064] As described above, while referring to the circuit data of observation point 1 in Figure 3B, the combinations of propagating clock signals are extracted for each mode in the table in Figure 8A, and the propagating clock signals are listed for each range enclosed by a rectangle in Figure 8A.

[0065] Figure 8B is a table showing the combinations of clock signals propagating in each mode, taken from the table in Figure 8A. Here, a combination of clock signals refers to the combinations of clock signals that can be input to two different flip-flops (FFs) included in the observation point. In the column direction of the table in Figure 8B, we take the clock signals clk_a, clk_b, and clk_c that can be input to FF11 at observation point 1, and in the row direction of the table in Figure 8B, we take the clock signals clk_d, clk_e, and clk_f that can be input to FF12. The rows and columns may be swapped. In the table in Figure 8B, there are 3 × 3 = 9 possible combinations of clock signals.

[0066] Figure 8B shows that there are combinations of clock signals that propagate, indicated by circles. Specifically, from the table in Figure 8A, in mode M1, clk_a is input to FF11 and clk_f is input to FF12, so in Figure 8B, a circle is drawn at the intersection of clk_a and clk_f. Also from the table in Figure 8A, in modes M2 to M4, clk_c is input to FF11 and clk_f is input to FF12, so in Figure 8B, a circle is drawn at the intersection of clk_c and clk_f. Furthermore, from the table in Figure 8A, in modes M5 to M6, clk_c is input to FF11 and clk_e is input to FF12, so in Figure 8B, a circle is drawn at the intersection of clk_c and clk_e.

[0067] As described above, at observation point 1, the number of clock signal combinations can be compressed from 9 to 3. Although a detailed explanation is omitted, the number of clock signal combinations can be similarly compressed at observation point 2. Referring to Figure 3C, at observation point 2, there are two clock signals that can be input to FF21, clk_a and clk_b, and three clock signals that can be input to FF22, clk_g, clk_d and clk_e. At observation point 2, there are 2 × 3 = 6 possible combinations of clock signals. By performing the same processing as at observation point 1, the number of propagating clock signal combinations can be compressed from 6.

[0068] In other words, in step S32, a table like the one in Figure 8B is generated for each observation point, and the combinations of clock signals propagating in each mode at each observation point are extracted.

[0069] Figures 9A to 9E illustrate the specific processing of step S4 in the verification method according to the embodiment. In step S4, for the observation points identified in step S1, CDC verification is performed for each verification unit and for each clock signal combination, using each FF (flip-flop) space extracted in step S3 as the verification unit to verify the logical operation. As explained in step S3, for the FF spaces of the identified observation points, the clock signal combinations shown in Figure 8B as an example are possible based on the operating specifications. Therefore, CDC verification is performed for each FF space for the clock signal combinations illustrated with circles in Figure 8B.

[0070] As shown in Figure 9A, at observation point 1 of the integrated circuit 100, in mode M1, clk_a propagates to FF11 and clk_f propagates to FF12. CDC verification is performed on this combination, and the verification result is output as CDC verification result-11.

[0071] As shown in Figure 9B, at observation point 1, in modes M2 to M4, clk_c propagates to FF11 and clk_f propagates to FF12. CDC validation is performed on this combination, and the validation result is output as CDC validation result-12.

[0072] As shown in Figure 9C, at observation point 1, in modes M5-M6, clk_c propagates to FF11 and clk_e propagates to FF12. CDC validation is performed on this combination, and the validation result is output as CDC validation result-13.

[0073] Although a detailed explanation is omitted, as shown in Figure 9D, at observation point 2 of the integrated circuit 100, in mode MN1 (where N is a natural number), clk_a propagates to FF21 and clk_e propagates to FF22. CDC verification is performed on this combination, and the verification result is output as CDC verification result-21.

[0074] As shown in Figure 9E, at observation point 2, in mode MN2 (where N2 is a natural number different from N1), clk_b propagates to FF21 and clk_g propagates to FF22. CDC validation is performed on this combination, and the validation result is output as CDC validation result-22.

[0075] As described above, CDC verification is performed at all observation points of the integrated circuit 100, and the verification results are output. As previously stated, in step S5, it is determined whether CDC verification has been performed for all observation points.

[0076] Since CDC verification is performed between flip-flops (FFs), the processing speed of CDC verification can be improved by decomposing the mode for each FF and compressing the combination of clock signals.

[0077] (Effectiveness of the verification method) In the verification method according to the embodiment, by performing CDC verification based on circuit operating state information obtained by logic simulation, CDC verification can be performed on a state in which actual operation is possible, thereby suppressing the occurrence of false errors. In other words, according to the embodiment, a verification method is provided that can suppress the occurrence of false errors in integrated circuits including CDC locations. Furthermore, according to the embodiment, the processing speed of CDC verification can be improved by decomposing the mode for each FF and compressing the combination of clock signals.

[0078] (Verification device) Next, a verification apparatus according to an embodiment that can implement the verification method described above will be described. Figure 10 is a schematic diagram of the verification apparatus 200 according to an embodiment.

[0079] As shown in Figure 10, the verification device 200 comprises a central processing unit (CPU) server 31, a storage medium 32, a computer device 33, and a network 34. In the following description, the central processing unit server 31 will also be referred to as the CPU server 31.

[0080] The verification device 200 connects a CPU server 31, a storage medium 32, and a user-operated computer device 33 via a network 34. The CPU server 31 stores the computer program used in the verification device 200. The storage medium 32 stores the input and output information necessary to execute the computer program used in the verification device 200. The computer device 33 is operated by the user. The computer program may be recorded on the storage medium 32 and read and stored by the CPU server 31 when the CPU server 31 performs processing.

[0081] The CPU server 31 may be, for example, an engineering workstation, a mainframe, or a supercomputer. The storage medium 32 may be, for example, a hard disk or SSD (Solid State Drive), a semiconductor memory storage device, or a storage medium (media). The computer device 33 may be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a PDA (Personal Digital Assistant). The network 34 may be, for example, the internet, an intranet, a LAN, a telephone network, or a dedicated line. However, in practice, it is not limited to these examples.

[0082] Figure 11 is a block diagram of the verification device 200 according to the embodiment. As shown in Figure 11, the CPU server 31 includes a verification control unit 310, an observation point identification unit 311, a logic simulation execution unit 312, a verification combination extraction unit 313, and a CDC verification execution unit 314.

[0083] The verification combination extraction unit 313 includes a state combination extraction unit 3131 and a clock signal combination extraction unit 3132. The state combination extraction unit 3131 includes a logic simulation value extraction unit 3131a, a state combination output unit 3131b, and a state combination organization unit 3131c.

[0084] The verification control unit 310, the observation point identification unit 311, the logic simulation execution unit 312, the verification combination extraction unit 313, and the CDC verification execution unit 314 may be, for example, a CPU or microprocessor. However, the system is not limited to these examples.

[0085] Furthermore, as shown in Figure 11, the storage medium 32 includes a circuit data storage area 320, an observation point information storage area 321, a test vector storage area 3221, and a logic simulation result storage area 3222. The storage medium 32 further includes a state combination storage area 3231, a clock signal combination storage area 3232, and a CDC verification result storage area 324.

[0086] Furthermore, as shown in Figure 11, the computer device 33 includes an input device 331 and an output device 332.

[0087] The processing method performed by the verification device 200 shown in Figure 11 will now be described. The designer inputs instructions to perform CDC verification into the input device 331 of the computer device 33. The input device 331 of the computer device 33 transmits the instructions input by the designer to the CPU server 31. In the CPU server 31, the verification control unit 310 outputs control signals to the CPU server 31 and each block of the storage medium 32.

[0088] Corresponding to step S1 in the flowchart of Figure 1, the observation point identification unit 311 reads the circuit data and timing constraints of the integrated circuit 100 from the circuit data storage area 320 and performs the process of identifying the observation point. As shown in Figures 3B and 3C, the observation point identification unit 311 identifies the observation point and outputs the information of the identified observation point to the observation point information storage area 321.

[0089] Corresponding to step S2 in the flowchart of Figure 1, the logic simulation execution unit 312 performs the following processing. The logic simulation execution unit 312 reads the circuit data and timing constraints of the integrated circuit 100, the information of the identified observation point, and the test vector information from the circuit data storage area 320, the observation point information storage area 321, and the test vector storage area 3221, respectively. Using the read information, the logic simulation execution unit 312 performs a logic simulation to observe the state of the identified point and obtains the logic simulation results shown in Figure 4. The logic simulation execution unit 312 outputs the logic simulation results to the logic simulation result storage area 3222.

[0090] In accordance with step S31 included in step S3 of the flowchart in Figure 2, the state combination extraction unit 3131 included in the verification combination extraction unit 313 performs the following processing.

[0091] Corresponding to step S31a in the flowchart of Figure 2, the logic simulation value extraction unit 3131a of the state combination extraction unit 3131 reads the logic simulation results from the logic simulation result storage area 3222. As shown in Figure 5, the logic simulation value extraction unit 3131a divides the changes in the signal state in the logic simulation results into modes such as mode M1 to M8, and identifies combinations of signal values ​​such as selection signals sel1 to sel4 in each mode.

[0092] Corresponding to step S31b in the flowchart of Figure 2, the state combination output unit 3131b of the state combination extraction unit 3131 writes out the combinations of signal values ​​for each mode, as shown in Figure 6.

[0093] Corresponding to step S31c in the flowchart of Figure 2, the state combination sorting unit 3131c of the state combination extraction unit 3131 excludes identical combinations of signal values ​​in each mode, as shown in Figure 7B.

[0094] The state combination extraction unit 3131 outputs information obtained by excluding identical signal value combinations from the combinations of signal values ​​in each mode, as shown in Figure 7B, to the state combination storage area 3231.

[0095] Corresponding to step S32 included in step S3 of the flowchart in Figure 2, the clock signal combination extraction unit 3132 included in the verification combination extraction unit 313 performs the following processing. The clock signal combination extraction unit 3132 reads information from the state combination storage area 3231, excluding identical combinations from the signal value combinations in each mode. As shown in Figure 8B, the clock signal combination extraction unit 3132 generates a table listing the clock signal combinations propagating in each mode at each observation point and outputs it to the clock signal combination storage area 3232.

[0096] Corresponding to step S4 of the flowchart in Figure 1, the CDC verification unit 314 performs the following processing. The CDC verification unit 314 reads the circuit data and timing constraints of the integrated circuit 100 from the circuit data storage area 320. The CDC verification unit 314 also reads tables from the observation point information storage area 321 and the clock signal combination storage area 3232, respectively, which contain observation point information and combinations of clock signals propagating in each mode for each observation point. Using the read information, the CDC verification unit 314 performs CDC verification for each observation point as explained in Figures 9A to 9E, and outputs the verification results to the CDC verification result storage area 324.

[0097] Corresponding to step S5 in the flowchart of Figure 1, the verification control unit 310 determines whether CDC verification has been performed for all observation points. If CDC verification has been performed for all observation points, the verification control unit 310 terminates the CDC verification and outputs the CDC verification results through the output device 332. If CDC verification has not been performed for all observation points, the verification control unit 310 performs the same processing and CDC verification as described above for the observation points for which CDC verification has not been performed.

[0098] (Effectiveness of the verification device) In the verification apparatus according to the embodiment, by performing CDC verification based on circuit operation state information obtained by logic simulation, CDC verification can be performed on a state in which actual operation is possible, thereby suppressing the occurrence of false errors. According to the embodiment, a verification apparatus can be provided that can implement a verification method that can suppress the occurrence of false errors in integrated circuits including CDC locations. Furthermore, according to the embodiment, the processing speed of CDC verification can be improved by decomposing the mode for each FF and compressing the combination of clock signals.

[0099] (Verification Program) Next, a verification program according to an embodiment that can implement the verification method described above will be described.

[0100] The verification program according to the embodiment includes procedures corresponding to each step in the flowchart of the verification method according to the embodiment shown in Figures 1 and 2. The specific processing performed by the verification program is as shown in Figures 3A to 9E. Furthermore, the verification program according to the embodiment is stored in and executed in the CPU server 31 of the verification device according to the embodiment shown in Figures 10 and 11. Alternatively, the verification program may be stored in a storage medium 32 and read and stored in the CPU server 31 when the processing of the flowchart in Figures 1 and 2 is performed.

[0101] (Effects of the verification program) In the verification program according to the embodiment, CDC verification is performed based on circuit operation state information obtained by logic simulation, so that CDC verification can be performed on a state that can actually operate, thereby suppressing the occurrence of false errors. According to the embodiment, a verification program can be provided that can implement a verification method that can suppress the occurrence of false errors in integrated circuits including CDC locations. Furthermore, according to the embodiment, the processing speed of CDC verification can be improved by decomposing the mode for each FF and compressing the combination of clock signals.

[0102] [Other embodiments] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0103] For example, in the verification method according to the embodiment, a flowchart is shown showing the process returning to step S2 if it is determined in step S5 that CDC verification has not been performed for all observation points. However, the step to which the process returns from step S5 is not limited to step S2; for example, if the process is to perform the steps up to step S3 for all observation points before proceeding to step S4, the process may return to step S4. [Explanation of Symbols]

[0104] 1, 2 Observation points 11, 12, 21, 22 circuit area 31 CPU (Central Processing Unit) Server 32 Storage medium 100 Integrated Circuits 200 Verification devices 311 Observation Point Identification Section 312 Logic Simulation Implementation Unit 313 Verification Combination Extraction Unit 3131 State combination extraction unit 3131a Logical Simulation Value Extraction Unit 3131b Status combination output section 3131c State combination sorting section 3132 Clock signal combination extraction unit 314 CDC Verification Implementation Department 320 Circuit data storage area 321 Observation Point Information Storage Area 3222 Logical Simulation Result Storage Area 3231 State combination memory area 3232 Clock signal combination memory area 324 CDC Validation Results Storage Area C11, C12, C21, C22 Clock signal definition section clk_a~clk_g clock signals FF11, FF12, FF21, FF22 Flip-flops FFCP11, FFCP12, FFCP21, FFCP22 Clock pulse input terminals (CP pins) Steps S1-S5, S31, S31a, S31b, S31c, S32 sel1~sel7 Selection Signals

Claims

1. The steps include obtaining circuit operation information of the integrated circuit under verification through logic simulation, The steps include: analyzing the circuit operation information and extracting verification combinations; For each flip-flop, the logical operation of the verification combination across clock domains is verified. Equipped with, Methods for verifying integrated circuits.

2. The step of acquiring the circuit operation information is: Steps include identifying the point where the clock signals merge, The steps include observing the state of the identified point using the logic simulation, including, The verification method described in claim 1.

3. The step of identifying the aforementioned points is, A first trace is performed by extracting the definition of the clock signal from the circuit data and timing constraints, and tracing the circuit region to which the extracted clock signal is input. From the aforementioned circuit data, a second trace is performed to extract the specifications for the flip-flop's clock pulse input terminal and trace the circuit region that generates the signal to be input to the extracted clock pulse input terminal. including, The verification method described in claim 2.

4. The step of extracting the aforementioned verification combination is: The steps include: extracting combinations of the state of the points observed from the results of the logic simulation; The steps include: extracting a combination of clock signals propagating from the combination of states of the aforementioned points; including, The verification method described in claim 2.

5. The step of extracting combinations of the states of the aforementioned points is: The steps include extracting the value of the control signal from the information of the aforementioned point, The steps include writing out the extracted combination of control signal values, A step of excluding identical combinations from the aforementioned combinations of values, including, The verification method described in claim 4.

6. An observation point identification unit identifies points to be observed in logic simulation based on circuit data and timing constraints, A logic simulation implementation unit that observes the state of the identified point using logic simulation, A state combination extraction unit extracts combinations of the state of the points observed from the results of the logic simulation, A clock signal combination extraction unit extracts a combination of clock signals propagating from the combination of states of the aforementioned points, A CDC verification unit verifies the logic operation of the combination of the propagating clock signals between flip-flops at points that cross clock domains, Equipped with, A verification device for integrated circuits.

7. The aforementioned state combination extraction unit, A logic simulation value extraction unit extracts the value of a control signal from the information of the aforementioned points, A state combination output unit that writes out the extracted combination of the aforementioned values, A state combination sorting unit that excludes identical combinations from the aforementioned combinations of values, including, The verification apparatus according to claim 6.

8. A computer program used in an integrated circuit verification device, Identifying points to observe in logic simulation based on circuit data and timing constraints. Observe the state of the identified point using logical simulation. Extracting combinations of the state of the points observed from the results of the aforementioned logic simulation, Extracting a combination of propagating clock signals from the combination of states of the aforementioned points, To verify the logic operation at points that cross clock domains for each combination of the propagating clock signals between flip-flops, A program that causes the aforementioned computer to execute.

9. A storage medium used in an integrated circuit verification device, Identifying points to observe in logic simulation based on circuit data and timing constraints. Observe the state of the identified point using logical simulation. Extracting combinations of the state of the points observed from the results of the aforementioned logic simulation, Extracting a combination of propagating clock signals from the combination of states of the aforementioned points, To verify the logic operation at points that cross clock domains for each combination of the propagating clock signals between flip-flops, A computer-readable storage medium that contains a program to be executed by a computer.

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