Semiconductor memory device and its control method

Abstract

The present invention provides a semiconductor memory device and a control method thereof that can suppress the degradation of memory characteristics or restore memory characteristics. [Solution] The semiconductor memory device according to this embodiment comprises a memory device including a plurality of memory cells composed of transistors and capable of holding data. The controller writes data to the plurality of memory cells using a first range from a first voltage that is one-quarter of the range between the lowest threshold voltage and the highest threshold voltage of the plurality of memory cells available for holding data, up to the highest threshold voltage. The controller heats the plurality of memory cells while data has been written to the first range.

Description

Technical Field

[0004] , ,

[0005] , , ,

[0001] This embodiment relates to a semiconductor memory device and a control method thereof.

Background Art

[0002] When the number of cycles of write operations and erase operations (hereinafter also referred to as the number of P / E (Program / Erase) cycles) of a NAND type flash memory increases, memory characteristics such as the threshold voltage of memory cells deteriorate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device and a control method thereof that can suppress deterioration of memory characteristics or recover memory characteristics.

Means for Solving the Problems

[0005] The semiconductor memory device according to this embodiment comprises a memory device consisting of transistors and including a plurality of memory cells capable of holding data. The controller writes data to the plurality of memory cells using a first range from a first voltage that is one-quarter of the range between the lowest threshold voltage and the highest threshold voltage of the plurality of memory cells available for data holding, up to the highest threshold voltage. The controller heats the plurality of memory cells while data has been written to the first range. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram illustrating an example configuration of the memory system of the first embodiment. [Figure 2] A circuit diagram showing the circuit configuration of a particular block within a memory cell array. [Figure 3] A cross-sectional view of a portion of the block. [Figure 4] A cross-sectional view showing the structure of a memory cell in more detail. [Figure 5] A graph showing an example of the relationship between the threshold voltage of a memory cell and the data. [Figure 6] A graph showing the relationship between the number of P / E cycles and the amount of threshold voltage shift in the memory cell. [Figure 7] A graph showing the relationship between the number of P / E cycles and the variation in the threshold voltage of memory cells. [Figure 8] A graph showing the degree of threshold voltage recovery at each voltage level of the memory cell. [Figure 9] A graph showing the degree of threshold voltage recovery at each voltage level of the memory cell. [Figure 10] A graph showing an example of the writing state of a memory cell according to the first embodiment. [Figure 11] A graph showing the writing state of a memory cell according to Modification 1 of the first embodiment. [Figure 12] A graph showing the writing state of a memory cell according to Modification 2 of the first embodiment. [Figure 13] A cross-sectional view showing an example configuration of NAND flash memory. [Figure 14] Cross-sectional view showing a configuration example of a NAND flash memory. [Figure 15] Planar view showing a configuration example of a heater. [Figure 16] Flowchart showing an example of a method for recovering a memory cell according to the second embodiment. [Figure 17] Graph showing the states of voltage levels S3 and S4 adjacent to each other. [Figure 18] Graph showing the states of voltage levels S3 and S4 after annealing. [Figure 19] An example of a correspondence table showing the correspondence between the number of defective bits and the annealing temperature. [Figure 20] Graph showing adjacent voltage levels to be written when specifying the annealing temperature.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same reference numerals are given to the same elements.

[0008] (First Embodiment) FIG. 1 is a block diagram for explaining a configuration example of a memory system according to the first embodiment.

[0009] The memory system 1 of this embodiment is connected to a host device 5 via a host bus. The memory system 1 can be requested by the host device 5 to write data, read data, and erase data.

[0010] The host device 5 is, for example, a personal computer or a server. The host bus is a bus based on an interface standard such as SD™ interface, SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), PCIe (Peripheral component interconnect express), or NVMe (Non-volatile memory express). The memory system 1 may be connected to the host device 5 by wireless communication.

[0011] The memory system 1 of this embodiment includes a NAND flash memory 100 and a memory controller 200. For example, the memory system 1 is an SSD (Solid State Drive), a memory card, a USB memory, etc.

[0012] The memory controller 200 is electrically coupled to the NAND flash memory 100. The memory controller 200 sends a command CMD, address information ADD, and a plurality of control signals to the NAND flash memory 100. The NAND flash memory 100 is an example of a memory device in this embodiment. The NAND flash memory 100 is a non-volatile semiconductor memory device. For example, the NAND flash memory 100 is a collection of a plurality of semiconductor chips. The memory controller 200 includes a storage unit 201 that stores a program for controlling the NAND flash memory 100, etc.

[0013] The NAND flash memory 100 receives the command CMD, address information ADD, and several control signals. Data DT is transferred between the NAND flash memory 100 and the memory controller 200. In the following, the data DT transferred from the memory controller 200 to the NAND flash memory 100 during the write sequence is called the write data. The write data DT is written into the NAND flash memory 100. During the read sequence, the data DT transferred from the NAND flash memory 100 to the memory controller 200 is called the read data. The read data DT is read from the NAND flash memory 100.

[0014] The NAND flash memory 100 includes, for example, a memory cell array 110, a command register 120, an address register 130, a row control circuit 140, a sense amplifier circuit 150, a driver circuit 160, a voltage generation circuit 170, an input / output circuit 180, and a sequencer 190.

[0015] The memory cell array 110 stores data. Multiple bit lines and multiple word lines are provided within the memory cell array 110. The memory cell array 110 contains multiple blocks BLK (BLK0, BLK1, ..., BLKk-1), where k is a natural number greater than or equal to 2. A block BLK is a collection of multiple memory cells. Each memory cell is associated with one bit line and one word line. The memory cell array 110 includes multiple select gate lines for selecting control units within the memory cell array 110.

[0016] For example, among multiple blocks, a certain number of specific blocks BLK store information INF such as setting information and management information for the operation of the NAND flash memory 100, and information AN regarding the state / status of the NAND flash memory 100. In the following, this information INF will also be called ROM information INF. A block BLK that stores ROM information INF will also be called a ROM block.

[0017] The internal configuration of the memory cell array 110 will be described later.

[0018] The command register 120 holds the command CMD from the memory controller 200. The command CMD is a signal that includes instructions to the sequencer 190 to execute, for example, a read sequence, a write sequence, and an erase sequence.

[0019] The address register 130 holds address information (selected address) ADD from the memory controller 200. The address information ADD includes, for example, block addresses, page addresses (word line addresses), and column addresses. The block address, page address, and column address are used for selecting blocks (BLK), word lines, select gate lines, and bit lines, respectively. Hereinafter, a block selected based on its block address is referred to as a selected block. A word line selected based on its page address is referred to as a selected word line.

[0020] The row control circuit 140 controls the operation of rows in the memory cell array 110. The row control circuit 140 selects one block BLK in the memory cell array 110 based on the block address in the address register 130. The row control circuit 140 transfers, for example, the voltage applied to the wiring corresponding to the selected word line to the selected word line in the selected block. The row control circuit 140 controls the selection and deselection of select gate lines based on the address information ADD. The row control circuit 140 includes a block decoder, a word line decoder, a select gate line decoder, and a switch circuit, etc.

[0021] The sense amplifier circuit 150 controls the operation of the columns of the memory cell array 110. In the write sequence, the sense amplifier circuit 150 applies a voltage to each bit line provided in the memory cell array 110 in accordance with the write data DT from the memory controller 200. In the read sequence, the sense amplifier circuit 150 determines the data stored in the memory cell based on the presence or absence of current generation or fluctuations in the potential of the bit line. The sense amplifier circuit 150 transfers the data based on this determination result to the memory controller 200 as read data DT. The sense amplifier circuit 150 includes a bit line selection circuit and an amplifier circuit, etc.

[0022] The driver circuit 160 outputs multiple voltages to the memory cell array 110 that are used in read sequences, write sequences, erase sequences, etc. Based on the address information ADD in the address register 130, the driver circuit 160 applies predetermined voltages to the wiring corresponding to word lines and bit lines, etc.

[0023] The voltage generation circuit 170 generates multiple voltages for various operations of the NAND flash memory 100. The voltage generation circuit 170 outputs the generated voltages to the driver circuit 160.

[0024] The input / output circuit 180 functions as an interface circuit on the NAND flash memory 100 side between the NAND flash memory 100 and the memory controller 200. For example, the input / output circuit 180 communicates with the memory controller 200 based on a NAND interface standard such as ONFi (Open NAND flash interface). Command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REN, ready busy signal RBn, and input / output signal DQ are used for communication between the NAND flash memory 100 and the memory controller 200.

[0025] The command latch enable signal CLE indicates that the input / output signal DQ received by the NAND flash memory 100 is the command CMD. The address latch enable signal ALE indicates that the signal DQ received by the NAND flash memory 100 is the address information ADD. The write enable signal WEn commands the NAND flash memory 100 to accept input from input / output signal DQ. The read enable signal REn commands the NAND flash memory 100 to accept output from input / output signal DQ.

[0026] The ready-busy signal RBn is a signal that the NAND flash memory 100 uses to notify the memory controller 200 whether the NAND flash memory 100 is in a ready state to receive commands from the memory controller 200 or in a busy state that does not receive commands.

[0027] The input / output signal DQ is, for example, an 8-bit wide signal set. The input / output signal DQ may include command CMD, address information ADD, write / read data DT, etc.

[0028] The sequencer 190 controls the operation of the entire NAND flash memory 100. For example, the sequencer 190 controls each circuit based on the command CMD in the command register 120.

[0029] Figure 2 is a circuit diagram showing the circuit configuration of one block BLK within the memory cell array 110.

[0030] One block BLK contains multiple (e.g., five) string units SU (SU0 to SU4). Each string unit SU contains multiple NAND strings NS. The number of block BLKs in the memory cell array 110, the number of string units SU in each block BLK, and the number of NAND strings NS in each string unit SU are arbitrary.

[0031] Each NAND string NS contains multiple memory cells MT (MT0 to MTn-1) and select transistors STD and STS, where n is a natural number greater than or equal to 2. The multiple memory cells MT are connected in series between the source of select transistor STD and the drain of select transistor STS.

[0032] Memory cells (MTs) hold data in a virtually non-volatile manner. A memory cell (also called a memory cell transistor) MT is a field-effect transistor having a control gate and a charge storage layer.

[0033] The gate of the select transistor STD in each of the string units SU0 to SU4 is connected to a corresponding drain-side select gate line SGD0 to SGD4. The gate of the select transistor STS in each of the string units SU0 to SU4 is connected to a common source-side select gate line SGS, for example. The gate of the select transistor STS may be connected to a different select gate line SGS for each of the string units SU0 to SU4.

[0034] The control gates of memory cells MT0 to MTn-1, which belong to the same block BLK, are each connected to one of the multiple word lines WL (WL0 to WLn-1), corresponding to each other.

[0035] Within the memory cell array 110, the drains of the select transistor STD of NAND strings NS belonging to the same column are connected to a corresponding bit line from among multiple bit lines BL(BL0~BL(m-1)), where m is a natural number greater than or equal to 2. The sources of multiple select transistors STS are commonly connected to the source line SL.

[0036] A string unit SU is a collection of NAND strings NS connected to different bit lines BL and the same select gate line SGD. In the following, a collection of memory cells MT (memory cell group) commonly connected to the same word line WL in each string unit SU is also called a cell unit CU. The data for each cell unit CU is also called a page. A block BLK is a collection of multiple string units SU that share multiple word lines WL. The memory cell array 110 is a collection of multiple block BLKs that share multiple bit lines BL.

[0037] Figure 3 is a cross-sectional view of a portion of the block BLK.

[0038] In Figure 3, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the direction perpendicular to the surface of the substrate (e.g., semiconductor substrate) 20 used to form the NAND flash memory 100.

[0039] As shown in Figure 3, the memory cell array 110 has a structure (stacked wiring) in which multiple conductive layers 22 (22a, 22b, 22c) and multiple insulating layers 32 (32a, 32b, 32c) are stacked in the Z direction.

[0040] The p-type well region 21 is provided within the semiconductor layer of the semiconductor substrate 20.

[0041] An insulating layer 32a is provided on the upper surface of the p-type well region 21. A conductive layer 22a is provided on the upper surface of the insulating layer 32a. The conductive layer 22a is, for example, a plate-shaped layer extending along the XY plane consisting of the X and Y directions. The conductive layer 22a is used as a select gate wire (SGS). The conductive layer 22a contains, for example, tungsten.

[0042] Multiple insulating layers 32b and multiple conductive layers 22b are alternately stacked in the Z direction on the upper surface of the conductive layer 22a. The conductive layer 22b is, for example, a plate-like layer extending along the XY plane. The stacked conductive layers 22b are used as word lines WL0 to WLn-1, in order from the semiconductor substrate 20 side. The conductive layer 22b contains, for example, tungsten.

[0043] A conductive layer 22c is provided above the uppermost conductive layer 22b, via an insulating layer 32c. The conductive layer 22c is, for example, a plate-like layer extending along the XY plane. The conductive layer 22c is used as a select gate wire SGD. The conductive layer 22c contains, for example, tungsten.

[0044] An insulating layer 34 is provided on the upper surface of the conductive layer 22c. The insulating layer 34 may be composed of multiple insulating layers. A conductive layer 25 is provided on the upper surface of the insulating layer 34. The conductive layer 25 is, for example, a line-shaped layer extended in the Y direction. The conductive layer 25 is used as a bit line BL. In a region not shown, multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 contains, for example, copper.

[0045] Each memory pillar MP extends along the Z direction and is provided within the stacked wiring. The memory pillar MP penetrates the insulating layer 32 and the conductive layer 22. The bottom of the memory pillar MP is in contact with the p-type well region 21. The side surface of the memory pillar MP faces the conductive layer 22. The portion where the memory pillar MP intersects with the conductive layer 22a functions as a select transistor STS. The portion where the memory pillar MP intersects with one conductive layer 22b functions as one memory cell MT. The portion where the memory pillar MP intersects with the conductive layer 22c functions as a select transistor STD.

[0046] Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a multilayer film 42. The core member 40 is provided extending along the Z direction. For example, the upper end of the core member 40 is located above the conductive layer 22c. The semiconductor layer 41 is provided between the lower end of the core member 40 and the p-type well region 21. The semiconductor layer 41 covers the periphery of the core member 40. At the lower part of the memory pillar MP, a portion of the semiconductor layer 41 is in contact with the p-type well region 21. The multilayer film 42 covers the sides of the semiconductor layer 41. The core member 40 includes, for example, an insulator such as silicon oxide. The semiconductor layer 41 includes, for example, silicon.

[0047] Contact CVs are provided on the upper surface of the semiconductor layer 41 within the memory pillar MP. In the illustrated region, two contact CVs corresponding to two of the six memory pillar MPs are shown. Of the multiple memory pillar MPs shown in Figure 3, those that do not overlap with the slit SHE and to which no contact CVs are connected are connected to contact CVs in an area not shown (for example, an area in the depth direction or front direction of the paper).

[0048] One conductive layer 25 (i.e., one bit line BL) is in contact with the upper surface of contact CV.

[0049] The slit SLT has a portion provided, for example, along the XZ plane, and divides a plurality of conductive layers 22. The contact LI is provided along the slit SLT. A portion of the upper end of the contact LI is in contact with the insulating layer 34. The lower end of the contact LI is in contact with the p-type well region 21. The contact LI is used, for example, as part of the source wire SL. At least a spacer SP is provided between the contact LI and the conductive layer 22. The contact LI is separated and insulated from the conductive layer 22 by the spacer SP.

[0050] The slit SHE has a portion that is provided, for example, along the XZ plane, and divides at least the conductive layer 22c. The upper end of the slit SHE is in contact with the insulating layer 34. The lower end of the slit SHE is in contact with the insulating layer 32c between the uppermost conductive layer 22b and the conductive layer 22c. The slit SHE contains an insulator, for example, silicon oxide.

[0051] Multiple such configurations are arranged in the depth direction (or front direction) of the page in Figure 3. A string unit SU is formed by a collection of multiple NAND strings NS arranged in the depth direction.

[0052] The structure of the memory cell array 110 is not limited to the example described above and may have other structures. For example, the memory cell array 110 may be provided above the semiconductor substrate 20 via an insulating layer. In this case, elements constituting the low control circuit 140, etc. (for example, field-effect transistors) may be provided on the semiconductor substrate 20 below the memory cell array 110.

[0053] Figure 4 is a cross-sectional view showing the structure of the memory cell MT in more detail.

[0054] As shown in Figure 4, the laminated film 42 includes a gate insulating film 421, a charge storage layer 422, and a block insulating film 423.

[0055] The semiconductor layer 41 functions as the current path for the NAND string NS. The semiconductor layer 41 is the region where the channels of the memory cell MT and the select transistors STD and STS are formed (hereinafter referred to as the channel region). The channel region of the memory cell MT faces the conductive layer 22 in a direction parallel to the surface of the semiconductor substrate 20.

[0056] The gate insulating film 421 surrounds the side surface of the semiconductor layer 41. The charge storage layer 422 surrounds the side surface of the gate insulating film 421. The block insulating film 423 surrounds the side surface of the charge storage layer 422. The charge storage layer 422 is provided between the gate insulating film 421 and the block insulating film 423.

[0057] The gate insulating film 421 functions as a tunnel barrier between the semiconductor layer 41 and the charge storage layer 422. The gate insulating film 421 includes, for example, silicon oxide.

[0058] The charge storage layer 422 can store the charge injected into the charge storage layer 422 from the semiconductor layer 41 via the gate insulating film 421. The charge storage layer 422 includes, for example, silicon nitride. The charge storage layer 422 may also contain silicon.

[0059] The blocking insulating film 423 prevents the transfer of charge between the charge storage layer 422 and the conductive layer 22. The blocking insulating film 423 includes, for example, silicon oxide or aluminum oxide.

[0060] In the NAND flash memory 100, when memory cells MT0 to MTn-1 and select transistors STD and STS are turned on, current flows between the bit line BL and contact LI (source line SL) via the memory pillar MP.

[0061] A single memory cell (MT) can store one or more bits of data through the association between the MT's threshold voltage and the data to be stored. A memory cell MT that stores one bit of data is called an SLC (Single-Liquid Cell). A memory cell MT that stores two bits of data is called an MLC (Multi-Liquid Cell). A memory cell MT that stores three bits of data is called a TLC (Triangular-Liquid Cell). A memory cell MT that stores four bits of data is called a QLC (Quick-Liquid Cell).

[0062] In the following explanation, we will assume that the memory cell MT is TLC as an example. Note that this embodiment is applicable to SLC, MLC, and QLC.

[0063] Figure 5 is a graph showing an example of the relationship between the threshold voltage Vth of a memory cell and the data. The horizontal axis represents the threshold voltage of the memory cell MT. The vertical axis represents the number of memory cells. The memory cell MT can be set to the erase state Er and the threshold voltage of voltage levels S1 to S7. This allows the memory cell MT to store data at eight voltage levels, i.e., 3-bit data (Er, S1 to S7). The voltage level is the threshold voltage level of the memory cell MT corresponding to each data.

[0064] Figure 6 is a graph showing the relationship between the number of P / E cycles and the shift amount of the memory cell threshold voltage. The horizontal axis of this graph represents the number of P / E cycles of the memory cell MT. The number of P / E cycles indicates the number of cycles when data is repeatedly written (programmed) and erased (erased). The vertical axis shows the average shift amount (voltage) of the threshold voltage of the memory cell MT that stores the eight data points of the TLC.

[0065] In Figure 6, a recovery process by heating (annealing) is performed each time the P / E cycle reaches 10,000, 20,000, ... cycles. The temperature conditions for annealing will be described later.

[0066] In this recovery process simulation, after each P / E cycle, the memory cell data is erased once, and new data with erase level Er (shown as R in Figure 6) or voltage level S3 (shown as C in Figure 6) is written to the memory cell. Next, annealing is performed while the memory cell is holding erase level Er or voltage level S3. Then, the eight TLC data are written to the memory cell, and the threshold voltage of the memory cell for each data (Er, S1~S7) is compared with the threshold voltage of each data (Er, S1~S7) in the initial state (before the P / E cycle). The difference in threshold voltage of each data (Er, S1~S7) at this time is defined as the shift amount. Figure 6 shows the average shift amount of the threshold voltage for the eight TLC data (Er, S1~S7) in this recovery process.

[0067] As shown in Figure 6, the threshold voltage Vth of the memory cell MC, on which eight TLC data points have been written, increases with increasing P / E cycles compared to their initial threshold voltages. That is, the amount of shift in the threshold voltage Vth increases with increasing P / E cycles. Here, it can be seen that the degree of recovery of the data stored in the memory cell during annealing differs between the erase level Er (shown as R in Figure 6) and the voltage level S3 (shown as C in Figure 6). Note that the erase level Er is the lowest threshold voltage level among the eight threshold voltage levels of the memory cell MT, as shown in Figure 5. Voltage level S3 is the fourth highest threshold voltage level among the eight threshold voltage levels of the memory cell MT.

[0068] For example, when a recovery process is performed after 10,000 P / E cycles, the threshold voltage when the memory cell MC is annealed while maintaining the erase level Er (R in Figure 6) decreases slightly and recovers somewhat, as shown by the dashed arrow, but does not return to the same threshold voltage as the original initial state. On the other hand, when the memory cell MC is annealed while maintaining the voltage level S3 (C in Figure 6), the threshold voltage recovers to almost the same threshold voltage as the original initial state, as shown by the solid arrow.

[0069] Furthermore, in the recovery process performed when the P / E count reaches 20,000, 30,000, etc., the threshold voltage when the memory cell MC is annealed while maintaining the erase level Er (R in Figure 6) recovers slightly, but does not return to the original threshold voltage. On the other hand, when the memory cell MC is annealed while maintaining the voltage level S3 (C in Figure 6), the threshold voltage recovers to almost the original threshold voltage with each annealing, regardless of the increase in the P / E count.

[0070] Figure 7 is a graph showing the relationship between the number of P / E cycles and the variation in the threshold voltage of memory cells. The horizontal axis of this graph represents the number of P / E cycles of the memory cell MT. The vertical axis represents the average variation in the threshold voltage Vth of the memory cell MT that stores the eight data points of the TLC.

[0071] Figure 7 also shows the degree of recovery of the memory cell MT when the memory cell MC is annealed while maintaining the erase level Er (shown as R in Figure 7) and when the memory cell MC is annealed while maintaining the voltage level S3 (shown as C in Figure 7).

[0072] The average variation in the threshold voltage Vth of a memory cell MC on which eight TLC data points have been written increases with increasing P / E cycles.

[0073] When the P / E cycle count reaches 10,000, and the memory cell MC is annealed while maintaining the erase level Er (R in Figure 7), the average variation in the threshold voltage decreases and recovers, as shown by the dashed arrow, but does not return to its original state. On the other hand, when the memory cell MC is annealed while maintaining voltage level S3 (C in Figure 7), the average variation in the threshold voltage recovers to almost the original initial state or a state better than the original state, as shown by the solid arrow. In other words, by annealing the memory cell MC while maintaining voltage level S3 (C in Figure 7), the average variation in the threshold voltage is significantly reduced.

[0074] Furthermore, in annealing performed when the P / E cycle reaches 20,000, 30,000, etc., if the memory cell MC is annealed while maintaining the erase level Er (R in Figure 7), the average variation in threshold voltage recovers, but does not return to its original state. On the other hand, if the memory cell MC is annealed while maintaining the voltage level S3 (C in Figure 7), the average variation in threshold voltage recovers to its original state or a better state with each annealing, regardless of the increase in the P / E cycle.

[0075] Thus, performing annealing at voltage level S3 is more effective in restoring the memory characteristics of memory cells MT than performing annealing at erase level Er. Furthermore, at voltage level S3, annealing can restore the memory cells MT to almost their original memory characteristics, regardless of the number of P / E cycles. Memory characteristics refer to the electrical characteristics of the memory cells MT, such as the threshold voltage and the variation in that threshold voltage.

[0076] Figure 8 is a graph showing the degree of recovery of each of the eight memory cells that store the TLC data after annealing. The horizontal axis represents the number of P / E cycles. The vertical axis represents the average threshold voltage shift (voltage) of the memory cells MT that store the eight TLC data.

[0077] When the P / E cycle reaches 10,000, a recovery process by annealing is performed. At this time, if the memory cell MC is annealed while maintaining the erase level Er and voltage level S1, the memory cell MT does not recover sufficiently. On the other hand, if the memory cell MC is annealed while maintaining voltage levels S2 to S7, the memory cell MT recovers to its original state.

[0078] Figure 9 is a graph showing the degree of threshold voltage recovery at each voltage level set during annealing of a memory cell. The horizontal axis shows the voltage levels Er, S1 to S7 of the memory cell MT during annealing. The vertical axis shows the average recovery amount (voltage) of the eight threshold voltages Vth when eight TLC data are written to the memory cell MT after annealing. As can be seen in the graph in Figure 9, the memory cell MT that maintained the erase level Er and voltage level S1 during annealing has not recovered sufficiently. On the other hand, the memory cell MT that maintained voltage levels S2 to S7 during annealing has recovered almost to its original state. However, since the recovery amount of voltage level S2 is close to the lower limit, it is preferable to anneal the memory cell MT when it maintains voltage levels S3 to S7.

[0079] To recover memory cells MT that maintain voltage levels S3 to S7, annealing is preferably performed at a temperature of, for example, 85 to 125 degrees Celsius. It has been found that recovery of memory cells MT that maintain voltage levels S3 to S7 can be achieved by annealing at a temperature of 85 degrees Celsius or higher. Furthermore, the NAND flash memory 100 cannot be operated at temperatures higher than 125 degrees Celsius according to its specifications. Therefore, the temperature conditions for annealing are preferably in the range of 85 to 125 degrees Celsius. Even without using a furnace or heater, the memory cell array 110 can raise the temperature of the memory cells MT to 85 to 125 degrees Celsius by repeating write and erase cycles.

[0080] Therefore, in the memory system 1 as a semiconductor memory device according to this embodiment, during recovery processing, data is written only to the 4th to 8th voltage levels S3 to S7, which have a threshold voltage of voltage level S3 or higher, out of the 1st to 8th voltage levels Er and 3 bits S1 to S7, in order of increasing threshold voltage of the memory cell MT. Voltage levels Er, S1, and S2 are not used and no data is written to them. In other words, multiple memory cells MT in the memory cell array 110 store data using only voltage levels S3 to S7. The threshold voltage of the memory cell MT in the erase state is also set within the range (R1) of voltage levels S3 to S7. As a result, the threshold voltage of the memory cell can be recovered from degradation due to P / E cycles at temperatures of approximately 85 to 125 degrees Celsius.

[0081] Figure 10 is a graph showing an example of the memory cell writing state according to the first embodiment. The horizontal and vertical axes of this graph may be the same as those in Figure 5.

[0082] The threshold voltage range of a memory cell MT that can be used for data retention is the range (operable range) Rfull between the lowest threshold voltage LL and the highest threshold voltage LH. Under normal operation, the memory cell MT can have any threshold voltage within the operating range Rfull.

[0083] However, in this embodiment, during normal operation, the memory cell MT uses only one threshold voltage within the range R1 of voltage levels S3 to S7. That is, during normal operation, the memory controller 200 writes data to multiple memory cells MT in the memory cell array 110 only within the range R1 of voltage levels S3 to S7.

[0084] In the memory characteristics recovery process of the memory cell MT, the memory controller 200 heats all or part of the memory cells MT in the memory cell array 110 to a temperature of 85 to 125 degrees Celsius while data is written to the range R1. As a result, the memory cells MT are heated (annealed) while data is written to the threshold voltage within the range R1. Consequently, as described above, the memory characteristics of the memory cells MT are recovered well.

[0085] If the memory controller 200 writes data to all memory cells MT in the memory cell array 110 only within the range R1, the memory characteristics of all memory cells MT in the memory cell array 110 can be restored in the same manner.

[0086] In the above embodiment, it is preferable that the memory controller 200 writes data within the voltage level range R1 of S3 to S7. In this case, as shown in Figure 10, the range R1 is from a voltage higher than the minimum threshold voltage LL to the maximum threshold voltage LH, which is about 3 / 8 of the operating range Rfull.

[0087] However, as explained with reference to Figures 8-10, in normal operation, the memory cell MT can also include voltage level S2. In this case, in normal operation, the memory controller 200 writes data to multiple memory cells MT in the memory cell array 110 within the voltage level range R2 of S2 to S7, and does not write data to threshold voltages below range R2. Range R2 is the range from a voltage higher than the minimum threshold voltage LL to the maximum threshold voltage LH, which is about one-quarter of the operable range Rfull. The memory controller 200 anneals the memory cell MT with data written to threshold voltages within range R2 as the first range. Even in this case, as described above, the memory characteristics of the memory cell MT can be restored well.

[0088] In normal operation, the memory controller 200 only writes data to threshold voltages within the range R1 or R2 of the memory cell MT, so during recovery processing, it is only necessary to perform annealing. The memory controller 200 may perform annealing periodically, for example, once every 24 hours. Alternatively, the memory controller 200 may perform annealing based on the number of P / E cycles, for example, once every 10,000 P / E cycles. When performing annealing based on the number of P / E cycles, the memory controller 200 may perform annealing only on the portion where the number of P / E cycles has reached a predetermined value. This allows the recovery processing of the memory cell MT to be performed without interfering with user use.

[0089] (Variation 1) Figure 11 is a graph showing the writing state of the memory cell according to Modification 1 of the first embodiment. The horizontal and vertical axes of this graph may be the same as those in Figure 5.

[0090] In Modification 1, the memory controller 200 stores 1-bit data (S3_1, S4_1) in the memory cell MT within the range R1. Thus, the memory controller 200 may use the memory cell MT as an SLC (Single Level Cell).

[0091] Furthermore, the memory controller 200 may store 1-bit data in the memory cell MT within the range R2.

[0092] (Modification 2) Figure 12 is a graph showing the writing state of the memory cell according to Modification 2 of the First Embodiment. The horizontal and vertical axes of this graph may be the same as those in Figure 5.

[0093] In the modified example 2, the memory controller 200 stores 2-bit data (S3_2, S4_2, S5_2, S6_2) within the range R1 in the memory cell MT. Thus, the memory controller 200 may use the memory cell MT as an MLC (Multiple Level Cell).

[0094] Furthermore, the memory controller 200 may store 2-bit data in the memory cell MT within the range R2.

[0095] In the erase operation of the first embodiment, the memory controller 200 may first lower the threshold voltage of the memory cell MT to below range R1 or R2, and then transition it to the erase threshold voltage within range R1 or R2. That is, the memory controller 200 may first write data with a voltage level below range R1 or R2 to the memory cell MT, and then return it to the erase level within range R1 or R2. Even in this case, the range of threshold voltage used in normal operation is range R1 or R2.

[0096] Of course, during the erase operation, the memory controller 200 may directly transition the threshold voltage of the memory cell MT to the erase state threshold electrode set within range R1 or R2 without lowering it from range R1 or R2.

[0097] (heater) In this embodiment, the memory controller 200 may perform annealing using the heat generated when operating the memory cell array 110. Alternatively, a heater HTR may be placed on the memory cell array 110, and the heater HTR may heat the memory cell array 110.

[0098] Figures 13 and 14 are cross-sectional views showing an example configuration of a NAND flash memory 100. The NAND flash memory 100 comprises a wiring board PCB and a plurality of memory chips CH stacked on the wiring board PCB. Wires BW connect the memory chips CH and the wiring board PCB. A resin MR covers the plurality of memory chips CH and the wires BW. In Figure 13, the heater HTR is located on the resin MR. That is, the heater HTR may be located outside the package of the memory chips CH. In Figure 14, the heater HTR is located between the memory chips CH and the wiring board PCB. That is, the heater HTR may be located inside the package of the memory chips CH. In this embodiment, the heater HTR may be arranged in either of the configurations shown in Figures 13 and 14.

[0099] Figure 15 is a plan view showing an example of the heater configuration. When the heater HTR shown in Figure 13 or Figure 14 is viewed from the Z direction, the heater HTR is composed of meandering heating wiring, for example, as shown in Figure 15. The heating wiring consists of a single wire, and heat is generated by passing current from one end to the other. The memory controller 200 may supply power to the heater HTR. Alternatively, an external power supply (not shown) may supply power to the heater HTR.

[0100] Such a heater HTR may heat the memory cell array 110 during the recovery process of the memory cell MT.

[0101] (Second Embodiment) Figure 16 is a flowchart showing an example of a memory cell recovery method according to the second embodiment.

[0102] First, the host device 5 specifies the memory chip on which to perform the recovery process (S10). The timing of the recovery process is determined based on factors such as the number of P / E cycles performed on the memory cell and the elapsed time set periodically.

[0103] In the second embodiment, the memory controller 200, in normal operation, writes only data for multiple adjacent voltage levels within range R1 or R2 to the memory cell MT. For example, Figure 17 is a graph showing the states of adjacent voltage levels S3 and S4. Therefore, the annealing of the recovery process is performed while retaining the data without saving the data to other memory chips.

[0104] Next, the memory controller 200 anneals the memory cells MT of the specified memory chip (S40). For example, Figure 18 is a graph showing the state of voltage levels S3 and S4 after annealing. Annealing increases the variation in the threshold voltages of voltage levels S3 and S4, and may cause a transition from one voltage level to the other. In other words, annealing generates bad bits in the memory cells MT of the target memory chip. The area of ​​S34 in Figure 18 indicates the number of bad bits (number of data that became bad).

[0105] Next, the memory controller 200 reads data from a predetermined number of memory cells MT of the target memory chip (S50). At this time, the number of data to be read (number of bits to be read) is arbitrary and may be the number of data corresponding to one page or the number of data corresponding to multiple pages.

[0106] Next, the memory controller 200 counts the number of bad data (bad bits) that have transitioned from one voltage level S3 or S4 of the read data to the other voltage level (S60). For example, the memory controller 200 counts the number of bad bits shown in S34 of Figure 18.

[0107] Here, the memory unit 201 shown in Figure 1 stores a correspondence table showing the relationship between the number of bad bits and the temperature of the memory cell MT during the recovery process. The correspondence table shows the relationship between temperature and the number of bad bits obtained when the same product is annealed at various temperatures. For example, Figure 19 is an example of a correspondence table showing the relationship between the number of bad bits and the annealing temperature. In this correspondence table, when the annealing temperature was 85 degrees, the number of bad bits was 10. When the annealing temperature was 90 degrees, the number of bad bits was 30. When the annealing temperature was 105 degrees, the number of bad bits was 50. When the annealing temperature was 115 degrees, the number of bad bits was 70. When the annealing temperature was 125 degrees, the number of bad bits was 100. Based on this correspondence between annealing temperature and the number of bad bits, the memory controller 200 can determine the annealing temperature from the number of bad bits.

[0108] The number of data read to count the number of faulty bits can be arbitrary, but it is the same predetermined number as the number of data read in step S50. This allows the memory controller 200 to accurately determine the temperature from the faulty bits based on the correspondence table.

[0109] The memory controller 200 refers to the correspondence table stored in the storage unit 201 and identifies the temperature corresponding to the number of bad bits counted in step S60 (S70). Based on this, the memory controller 200 refers to the correspondence table and identifies the temperature of the memory cell MT during annealing.

[0110] Next, the memory controller 200 determines whether the annealing temperature was appropriate (S80). That is, it determines whether the annealing temperature identified in step S70 is within the range of 85 to 125 degrees. If the annealing temperature is not within the range of 85 to 125 degrees (NO in S80), steps S40 to S80 are repeated. In this case, in step S40, the operation and time of the memory cell MT during heating, or the power to the heater HTR is changed, and the annealing is performed again.

[0111] If the annealing temperature is within the range of 85 to 125 degrees (YES in S80), the memory controller 200 writes data to the multiple memory cells MT that have undergone recovery processing to confirm whether the memory characteristics have actually been recovered (S90).

[0112] If the memory characteristics have recovered sufficiently (YES for S90), the memory controller 200 terminates the recovery process.

[0113] If the memory characteristics have not fully recovered (NO in S90), it means that the memory characteristics will not recover even if the memory cell MT is annealed at the appropriate temperature. Therefore, the memory controller 200 determines that the memory cell MT is damaged and renders it unusable. Alternatively, the memory controller 200 discards the memory chip.

[0114] According to the second embodiment, the temperature of the memory cells MT inside the memory chip can be determined. This allows annealing during the recovery process to be performed at an appropriate temperature. The other configurations and operations of the second embodiment are the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0115] Furthermore, the voltage levels used for writing during the recovery process (e.g., S3, S4) may be closer to each other than the voltage levels used during normal operation. That is, the memory controller 200 may write data with a smaller difference between adjacent voltage levels when determining the annealing temperature. In this case, the memory controller 200 makes the first voltage difference between adjacent voltage levels written during the recovery process smaller than the second voltage difference between adjacent voltage levels written during normal operation. For example, Figure 20 is a graph showing the adjacent voltage levels written when determining the annealing temperature. In Figure 20, voltage levels S3 and S4 are narrower and closer together than in the normal writing state. As a result, although a write operation is required when determining the annealing temperature in the recovery process, the data stored in the memory cell MT is more likely to transition to other voltage levels (more likely to fail). That is, bad bits are more likely to occur, and the temperature can be determined more precisely (with greater sensitivity).

[0116] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0117] 1. Memory System 5 Host device 100 NAND flash memory 200 memory controllers 110 memory cell array 120 command registers 130 Address Registers 140 Low control circuit 150 Sense Amplifier Circuit 160 Driver Circuit 170 Voltage Generating Circuit 180 Input / Output Circuits 190 Sequencer PCB wiring board CH memory chip HTR Heater

Claims

1. A memory device comprising transistors and including multiple memory cells capable of holding data, A controller that writes data to the plurality of memory cells using a first range from a first voltage that is one-quarter of the range between the lowest threshold voltage and the highest threshold voltage of the plurality of memory cells that can be used to hold data, up to the highest threshold voltage, The controller is a semiconductor memory device that heats the plurality of memory cells while data has been written to the first range.

2. The semiconductor memory device according to claim 1, wherein the controller heats the plurality of memory cells at a temperature of 85 to 125 degrees Celsius.

3. The semiconductor memory device according to claim 1, wherein the controller writes data only to the fourth to eighth voltage levels out of the three bits of the first to eighth voltage levels, in order of increasing threshold voltage of the memory cell.

4. The semiconductor memory device according to claim 1, wherein the controller sets the threshold voltages of the plurality of memory cells in the data erasure state to a first range.

5. The semiconductor memory device according to claim 1, wherein the controller periodically performs a heating process on the plurality of memory cells.

6. The semiconductor memory device according to claim 1, wherein the controller heats the plurality of memory cells by operating the plurality of memory cells.

7. The memory device further comprises a heater, The semiconductor memory device according to claim 1, wherein the controller heats the plurality of memory cells with the heater.

8. The semiconductor memory device according to claim 1, wherein the controller writes data of multiple adjacent voltage levels within the first range to the multiple memory cells, reads data from a predetermined number of the multiple memory cells after the multiple memory cells have been heated, counts the number of data that have transitioned from one voltage level to the other among the read data, and determines the temperature of the multiple memory cells at the time of heating based on the number of data.

9. The controller has a storage unit that stores a correspondence table showing the relationship between the number of data and the temperature of the plurality of memory cells. The semiconductor memory device according to claim 8, wherein the controller determines the temperature of the plurality of memory cells when heated based on the number of data points by referring to the correspondence table.

10. A control method for a semiconductor memory device comprising a memory device consisting of transistors and including a plurality of memory cells capable of holding data, and a controller for controlling the memory device, In a data writing operation, data is written to the plurality of memory cells using a first range from a first voltage that is one-quarter of the range between the lowest threshold voltage and the highest threshold voltage of the plurality of memory cells available for data retention, up to the highest threshold voltage. A control method for a semiconductor memory device, comprising heating the plurality of memory cells while data has been written to the first range.

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