Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor in which the degradation of high-temperature load reliability is suppressed. [Solution] In the multilayer ceramic capacitor 1 of the present invention, when the inner electrode layer 30 closest to the main surface outer layer portion 11 is defined as the outermost inner electrode layer 301, the outermost inner electrode layer 301 has an inner electrode presence region 311 and an inner electrode separation region 312, the inner electrode separation region 312 includes a magnesium or manganese segregation region 321, and the ratio (B / A) of the distance B in the length direction L of the magnesium or manganese segregation region 321 to the distance A in the length direction L of the inner electrode presence region 311 is 50% or more and 75% or less.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] For example, the multilayer ceramic capacitor described in Patent Document 1 includes a capacitor body made of a ceramic sintered body composed of a dielectric such as barium titanate. Inside the capacitor body, an internal electrode layer made of a noble metal material such as silver or a silver - palladium alloy or a base metal material such as nickel is disposed through a ceramic layer serving as a dielectric layer. The internal electrode layer is alternately led out to one end face and the other end face of the capacitor body. One alternately led - out internal electrode layer and the other internal electrode layer are electrically connected to external electrodes having different potentials, respectively.

[0003] The internal electrode layer of the multilayer capacitor described in Patent Document 1 is composed of a metal material, and the external electrode is composed of a plurality of metal components including a metal that is the same as or can be alloyed with this and a glass component. The external electrode is adhered to a wiring board through a conductive resin adhesive. The area occupancy ratio of the metal component to the cross - sectional area of the external electrode is in the range of 60% to 95%. Thereby, the multilayer capacitor described in Patent Document 1 can be mounted on a wiring board at a low cost with high reliability without using solder.

Prior Art Documents

Patent Documents

[0004] [[ID=?]]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, the conventional multilayer ceramic capacitors described above have a problem in that the dielectric layer becomes partially thinned, and the high-temperature load reliability decreases starting from the thinned area. In particular, thinning of the dielectric layer due to metal segregation can occur in the dielectric layer of the effective layer that is close to the boundary with the outer layer. As a result, the high-temperature load reliability of the multilayer ceramic capacitor may decrease.

[0006] Therefore, the present invention aims to provide a multilayer ceramic capacitor in which the decrease in high-temperature load reliability is suppressed. [Means for solving the problem]

[0007] The multilayer ceramic capacitor of the present invention comprises a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, further comprising a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, wherein the dielectric layers and the internal electrode layers are alternately stacked, and an outer layer portion disposed to sandwich the inner layer portion from the first main surface side and the second main surface side, and disposed on the first end surface In a multilayer ceramic capacitor including a first external electrode and a second external electrode disposed on the second end face, when the internal electrode layer closest to the outer layer is defined as the outermost internal electrode layer, in a cross-section parallel to the length and height directions, the outermost internal electrode layer has an internal electrode presence region and an internal electrode separation region, the internal electrode separation region includes a magnesium or manganese segregation region, and the ratio (B / A) of the lengthwise distance B of the magnesium or manganese segregation region to the lengthwise distance A of the internal electrode presence region is 50% or more and 75% or less. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the deterioration of high-temperature load reliability is suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is an external perspective view of a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view of line 101-101 in Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along line 102-102 of Figure 2. [Figure 4] Figure 4 is a cross-sectional view taken along line 103-103 in Figure 2. [Figure 5] Figure 5 is a cross-sectional view of line 104-104 in Figure 2. [Figure 6] Figure 6 is an enlarged view of the framed area 110 in Figure 2. [Figure 7] Figure 7 is a diagram corresponding to Figure 7 for a conventional multilayer ceramic capacitor. [Figure 8A] Figure 8A is a scanning electron microscope image of a cross-section of a multilayer ceramic capacitor. [Figure 8B] Figure 8B shows a mapping image of magnesium in a cross-section of a multilayer ceramic capacitor. [Figure 8C] Figure 8C shows a manganese mapping image in a cross-section of a multilayer ceramic capacitor. [Figure 9] Figure 9 is a table showing the evaluation results of high-temperature load reliability. [Modes for carrying out the invention]

[0010] (Multilayer ceramic capacitor) A multilayer ceramic capacitor 1 according to one embodiment of the present disclosure will be described with reference to the drawings. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 2. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 2. Figure 5 is a cross-sectional view taken along line 104-104 of Figure 2.

[0011] As shown in FIG. 1, the shape of the multilayer ceramic capacitor 1 is substantially a rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed apart from each other at both ends of the laminate 2.

[0012] In FIG. 1, an arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 2. This height direction T is also the thickness direction and the lamination direction of the multilayer ceramic capacitor 1 and the laminate 2. In FIG. 1, an arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 2 that is orthogonal to the height direction T. In FIG. 1, an arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 2 that is orthogonal to the height direction T and the length direction L. The pair of external electrodes 40 are respectively disposed at one end and the other end in the length direction L of the laminate 2.

[0013] The cross-section shown in FIG. 2 is called an LT cross-section. The cross-section shown in FIG. 3 is called a WT cross-section. The cross-sections shown in FIG. 4 and FIG. 5 are called LW cross-sections.

[0014] (Laminate) The two surfaces facing each other in the height direction T of the laminate 2 are called the first main surface 3 and the second main surface 4. The two surfaces facing each other in the length direction L orthogonal to the height direction T of the laminate are called the first end surface 7 and the second end surface 8. The two surfaces facing each other in the width direction W orthogonal to the height direction T and the length direction L of the laminate 2 are called the first side surface 5 and the second side surface 6.

[0015] As shown in FIG. 1, the shape of the laminate 2 is substantially a rectangular parallelepiped shape. The length in the length direction L of the laminate 2 may not be longer than the length in the width direction W. The shape of the corners and the ridge lines of the laminate 2 is preferably a rounded shape. A corner is a portion where three surfaces of the laminate intersect. A ridge line is a portion where two surfaces of the laminate intersect. A part or all of the shape of the surface constituting the laminate 2 may be a shape with irregularities or the like formed thereon.

[0016] The size of the laminate 2 is not limited. The preferable length in the length direction L of the laminate 2 is 0.2 mm or more and 6 mm or less. The preferable length in the height direction T of the laminate 2 is 0.05 mm or more and 5 mm or less. The preferable length in the width direction W of the laminate 2 is 0.1 mm or more and 5 mm or less.

[0017] (Height direction division) As shown in FIGS. 2 and 3, the laminate 2 is divided in the height direction T into an effective layer portion 10 and a main surface side outer layer portion 11 (outer layer portion). The main surface side outer layer portion 11 includes a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13. The first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 are located at positions sandwiching the effective layer portion 10 in the height direction T. That is, the laminate 2 is divided into a first main surface side outer layer portion 12, an effective layer portion 10, and a second main surface side outer layer portion 13.

[0018] (Dielectric layer) The effective layer portion 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 that are alternately laminated in the height direction T. The effective layer portion 10 includes, in the height direction T, the internal electrode layer 30 located on the most first main surface 3 side to the internal electrode layer 30 located on the most second main surface side 4. In the effective layer portion 10, the plurality of internal electrode layers 30 are arranged to face each other through the dielectric layer 20. The effective layer portion 10 is a portion that generates capacitance and functions substantially as a capacitor. The dielectric layer 20 included in the effective layer portion 10 is called an inner layer dielectric layer 21. The dielectric layer 20 included in the first main surface side outer layer portion 12 and the dielectric layer 20 included in the second main surface side outer layer portion 13 are called an outer layer dielectric layer 22.

[0019] The plurality of dielectric layers 20 are made of a dielectric material. Examples of the dielectric material are dielectric ceramics containing components such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. The dielectric material may be obtained by adding sub-components such as manganese compounds, iron compounds, copper compounds, cobalt compounds, nickel compounds to these main components. The preferable material of the dielectric material is a material containing barium titanate as the main component.

[0020] The preferred thickness of the dielectric layer 20 is 0.2 μm or more and 10 μm or less. The preferred number of layers of the laminated dielectric layer 20 is 15 or more and 1200 or less. This number of layers of the dielectric layer 20 is the sum of the number of layers of the inner dielectric layer 21 and the number of layers of the outer dielectric layer 22.

[0021] (Internal electrode layer) The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged alternately in the height direction T with a dielectric layer 20 in between them. The first internal electrode layers 31 are drawn out to the first end face 7. The second internal electrode layers 32 are drawn out to the second end face 8.

[0022] As shown in Figure 4, the first internal electrode layer 31 is divided into a first opposing portion 33 and a first lead-out portion 35. The first opposing portion 33 is the portion that faces the second internal electrode layer 32 with the dielectric layer 20 in between. The first lead-out portion 35 is the portion that is led out from the first opposing portion 33 to the first end face 7. The first lead-out portion 35 is exposed to the first end face 7.

[0023] As shown in Figure 5, the second internal electrode layer 32 is divided into a second opposing portion 34 and a second lead-out portion 36. The second opposing portion 34 is the portion that faces the first internal electrode layer 31 with the dielectric layer 20 in between. The second lead-out portion 36 is the portion that is led out from the second opposing portion 34 to the second end face 8. The second lead-out portion 36 is exposed to the second end face 8.

[0024] In the multilayer ceramic capacitor 1, capacitance is formed when the first opposing portion 33 and the second opposing portion 34 face each other via the dielectric layer 20. As a result, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0025] The shapes of the first opposing portion 33 and the second opposing portion 34 are not limited. A preferred shape for the first opposing portion 33 and the second opposing portion 34 is rectangular. Similarly, the shapes of the first pull-out portion 35 and the second pull-out portion 36 are not limited. A preferred shape for the first pull-out portion 35 and the second pull-out portion 36 is rectangular. In the above-described rectangular shape, the shape of the corner portion of the rectangular shape may be rounded. The shape of the corner portion of the rectangular shape may be formed at an angle.

[0026] The length in the width direction W of the first opposing portion 33 and the length in the width direction W of the first drawer portion 35 may be the same. The length of either the length in the width direction W of the first opposing portion 33 or the length of the width direction W of the first drawer portion 35 may be shorter. The length in the width direction W of the second opposing portion 34 and the length of the width direction W of the second drawer portion 36 may be the same. The length of either the length in the width direction W of the second opposing portion 34 or the length of the width direction W of the second drawer portion 36 may be shorter.

[0027] Examples of materials for the first internal electrode layer 31 and the second internal electrode layer 32 are conductive materials such as metals like nickel, copper, silver, palladium, and gold, or alloys containing at least one of these metals. When using an alloy, examples of materials for the first internal electrode layer 31 and the second internal electrode layer 32 are alloys of silver and palladium, etc.

[0028] A preferred thickness for each of the first internal electrode layer 31 and the second internal electrode layer 32 is between 0.2 μm and 2.0 μm. The preferred sum of the number of layers of the first internal electrode layer 31 and the number of layers of the second internal electrode layer 32 is between 15 and 1000.

[0029] (Outer layer on main surface side) As shown in Figures 2 and 3, the portion consisting of an assembly of multiple dielectric layers 20 located between the first main surface 3 and the internal electrode layer 30 closest to the first main surface 3 is called the first main surface side outer layer portion 12. The first main surface side outer layer portion 12 is located on the first main surface 3 side of the laminate 2. The portion consisting of an assembly of multiple dielectric layers 20 located between the second main surface 4 and the internal electrode layer 30 closest to the second main surface 4 is called the second main surface side outer layer portion 13. The second main surface side outer layer portion 13 is located on the second main surface 4 side of the laminate 2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may be the same as the dielectric layers 20 used in the effective layer portion 10. The material of the inner dielectric layer 21 and the material of the outer dielectric layer 22 may be the same.

[0030] (electrode facing part) The portion where the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 face each other is called the electrode opposing portion 14. The electrode opposing portion 14 is part of the effective layer portion 10. Figures 4 and 5 show the width W and length L ranges of the electrode opposing portion 14. The electrode opposing portion 14 is also called the capacitor effective portion.

[0031] (Division in the W direction) The laminate 2 is divided in the width direction W into a first side outer layer portion 15, an electrode facing portion 14, and a second side outer layer portion 16. The first side outer layer portion 15 is the portion that includes a dielectric layer 20 located between the electrode facing portion 14 and the first side surface 5. The second side outer layer portion 16 is the portion that includes a dielectric layer 20 located between the electrode facing portion 14 and the second side surface 6. Figures 3, 4, and 5 show the width direction W range of the first side outer layer portion 15, the electrode facing portion 14, and the second side outer layer portion 16. The first side outer layer portion 15 and the second side outer layer portion 16 are called the W gap or side gap.

[0032] (Section in the L direction) The laminate 2 is divided in the length direction L into a first end-face side outer layer portion 17, an electrode-facing portion 14, and a second end-face side outer layer portion 18. The first end-face side outer layer portion 17 is the portion that includes the dielectric layer 20 and the first lead portion 35 located between the electrode-facing portion 14 and the first end face 7. The first end-face side outer layer portion 17 is an assembly of the portions of the multiple dielectric layers 20 on the first end face 7 side and the multiple first lead portions 35. The second end-face side outer layer portion 18 is the portion that includes the dielectric layer 20 and the second lead portion 36 located between the electrode-facing portion 14 and the second end face 8. The second end-face side outer layer portion 18 is an assembly of the portions of the multiple dielectric layers 20 on the second end face 8 side and the multiple second lead portions 36. Figures 2, 4, and 5 show the longitudinal range L of the first end-face outer layer 17, the electrode-facing portion 14, and the second end-face outer layer 18. The first end-face outer layer 17 and the second end-face outer layer 18 are called the L gap or end gap.

[0033] (external electrode) The external electrode 40 includes a first external electrode 41 and a second external electrode 42. The first external electrode 41 is an external electrode positioned on the first end face 7 side of the laminate 2. The second external electrode 42 is an external electrode positioned on the second end face 8 side of the laminate 2.

[0034] The basic configuration of the first external electrode 41 and the second external electrode 42 is the same. The first external electrode 41 and the second external electrode 42 have a shape that is generally symmetrical with respect to the WT cross section at the center of the length L of the multilayer ceramic capacitor 1.

[0035] The first external electrode 41 is positioned on the first end face 7. The first external electrode 41 contacts the first lead-out portion 35 of each of the multiple first internal electrode layers 31 exposed on the first end face 7. The first external electrode 41 is electrically connected to the multiple first internal electrode layers 31. The first external electrode 41 may also be positioned on a portion of the first main surface 3 and a portion of the second main surface 4, as well as on a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is formed extending from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as on a portion of the first side surface 5 and a portion of the second side surface 6.

[0036] The second external electrode 42 is positioned on the second end face 8. The second external electrode 42 contacts the second lead-out portion 36 of each of the multiple second internal electrode layers 32 exposed on the second end face 8. The second external electrode 42 is electrically connected to the multiple second internal electrode layers 32. The second external electrode 42 may also be positioned on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed extending from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0037] Within the laminate 2, capacitance is formed when the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 face each other via the dielectric layer 20. As a result, capacitor characteristics are exhibited between the first external electrode 41 to which the first internal electrode layer 31 is connected and the second external electrode 42 to which the second internal electrode layer 32 is connected.

[0038] (base electrode layer) As shown in Figures 2, 4, and 5, the first external electrode 41 includes a first base electrode layer 51 and a first plating layer 71. The first plating layer 71 is placed on the first base electrode layer 51. The second external electrode 42 includes a second base electrode layer 52 and a second plating layer 72. The second plating layer 72 is placed on the second base electrode layer 52.

[0039] The first base electrode layer 51 is positioned on the first end face 7. The first base electrode layer 51 contacts the first pull-out portion 35 of each of the multiple first internal electrode layers 31 exposed on the first end face 7. The first base electrode layer 51 is formed extending from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0040] The second base electrode layer 52 is positioned on the second end face 8. The second base electrode layer 52 contacts the second lead-out portion 36 of each of the multiple second internal electrode layers 32 exposed on the second end face 8. The second base electrode layer 52 is formed extending from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0041] The first base electrode layer 51 and the second base electrode layer 52 are baked layers. The baked layers preferably contain a metal component. Preferably, in addition to the metal component, the baked layers contain at least one of a glass component and a ceramic component. The metal component includes at least one selected from, for example, copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc. The glass component includes at least one selected from, for example, boron, silicon, barium, magnesium, aluminum, lithium, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20. The ceramic component may be a different type of ceramic material from the dielectric layer 20. The ceramic component includes at least one selected from, for example, barium titanate, calcium titanate, a mixed crystal material in which some of the barium in barium titanate is replaced with calcium, strontium titanate, calcium zirconate, etc.

[0042] An example of a baked layer is a layer formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer is formed by simultaneously baking the laminated chip, which is the material for the laminate containing multiple internal electrode layers and multiple dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, the baked layer is formed by baking the laminated chip to obtain a laminate, then applying a conductive paste to the laminate and baking it. When baking the conductive paste after obtaining the laminate, it is preferable that the baked layer is formed by baking a conductive paste in which a ceramic material has been added instead of a glass component. When using a conductive paste with added ceramic material, it is preferable that the added ceramic material is the same type of ceramic material as the dielectric layer. There may be multiple baked layers.

[0043] A preferred thickness of the first base electrode layer 51 on the first end face 7 in the longitudinal direction L is approximately 10 μm to 200 μm in the central part of the height direction T and width direction W of the first base electrode layer 51.

[0044] A preferred thickness of the second base electrode layer 52 on the second end face 8 in the longitudinal direction L is approximately 10 μm to 200 μm in the central part of the second base electrode layer 52 in the height direction T and width direction W.

[0045] When the first base electrode layer 51 is provided on a portion of at least one of the first main surface 3 or the second main surface 4, a preferred example of the thickness of the first base electrode layer 51 in the height direction T provided in this portion is approximately 3 μm to 40 μm in the central part of the length direction L and width direction W of the first base electrode layer 51 provided in this portion.

[0046] When the first base electrode layer 51 is also provided on a portion of at least one of the first side surface 5 or the second side surface 6, a preferred thickness of the first base electrode layer 51 in the width direction W provided in this portion is approximately 3 μm to 40 μm in the central part of the first base electrode layer 51 in the length direction L and height direction T.

[0047] When a second base electrode layer 52 is provided on a portion of at least one of the first main surface 3 or the second main surface 4, a preferred thickness of the second base electrode layer 52 in the height direction T provided in this portion is approximately 3 μm to 40 μm in the central part of the second base electrode layer 52 in the length direction L and width direction W.

[0048] When a second base electrode layer 52 is provided on a portion of at least one of the first side surface 5 or the second side surface 6, a preferred thickness of the second base electrode layer 52 in the width direction W provided in this portion is approximately 3 μm to 40 μm in the central part of the second base electrode layer 52 in the length direction L and height direction T.

[0049] The first plating layer 71 is positioned to cover the first base electrode layer 51. The second plating layer 72 is positioned to cover the second base electrode layer 52.

[0050] The first plating layer 71 and the second plating layer 72 may contain at least one selected from, for example, copper, nickel, tin, silver, palladium, a silver-palladium alloy, gold, etc. The first plating layer 71 and the second plating layer 72 may each be formed by multiple layers. A preferred structure for the first plating layer 71 and the second plating layer 72 is a two-layer structure in which a tin plating layer is formed on top of a nickel plating layer.

[0051] The first plating layer 71 is positioned to cover the first underlay electrode layer 51. In this embodiment, the first plating layer 71 includes a first nickel plating layer 73 and a first tin plating layer 75. The first tin plating layer 75 is located on the first nickel plating layer 73.

[0052] The second plating layer 72 is positioned to cover the second under electrode layer 52. In this embodiment, the second plating layer 72 includes a second nickel plating layer 74 and a second tin plating layer 76. The second tin plating layer 76 is located on top of the second nickel plating layer 74.

[0053] The nickel plating layer prevents the first and second base electrode layers 51 and 52 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The tin plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. The tin plating layer facilitates the mounting of the multilayer ceramic capacitor 1. The preferred thicknesses of the first nickel plating layer 73, the first tin plating layer 75, the second nickel plating layer 74, and the second tin plating layer 76 are 2 μm to 10 μm.

[0054] The external electrode 40 may include a conductive resin layer containing conductive particles and a thermosetting resin. If the external electrode 40 includes a conductive resin layer, the conductive resin layer may be positioned to cover the baking layer. If the conductive resin layer is positioned to cover the baking layer, the conductive resin layer is positioned between the baking layer and the plating layer. The baking layer corresponds to the first base electrode layer 51 and the second base electrode layer 52. The plating layer corresponds to the first plating layer 71 and the second plating layer 72. The conductive resin layer may completely cover the baking layer. The conductive resin layer may cover a portion of the baking layer.

[0055] A conductive resin layer containing thermosetting resin is more flexible than a conductive layer made of a plated film or a fired conductive paste. Therefore, when a multilayer ceramic capacitor is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer acts as a buffer layer. As a result, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor.

[0056] Examples of metals that make up conductive particles include silver, copper, nickel, tin, bismuth, or alloys containing at least two of these metals. Conductive particles preferably contain silver. An example of conductive particles is silver metal powder. Silver has the lowest resistivity among metals. Silver is suitable as an electrode material. Silver is a noble metal. Silver is resistant to oxidation. Silver has high weather resistance. For these reasons, silver metal powder is suitable as conductive particles.

[0057] The conductive particles may be metal powders with a silver coating on their surface. When using conductive particles with a silver coating on the surface of the metal powder, the metal powder is preferably copper, nickel, tin, bismuth, or an alloy thereof. It is preferable to use silver-coated metal powder in order to maintain the properties of silver while making the base metal inexpensive.

[0058] The conductive particles may be copper or nickel that has been treated to prevent oxidation. The conductive particles may be metal powder in which tin, nickel, or copper is coated on the surface of the metal powder. When using metal powder in which tin, nickel, or copper is coated on the surface of the metal powder, the metal powder is preferably an alloy powder containing silver, copper, nickel, tin, bismuth, or at least two of these metals.

[0059] The shape of the conductive particles is not limited. Examples of conductive particle shapes include spherical and flattened shapes. It is preferable to use a mixture of spherical and flattened metal powders.

[0060] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. When multiple conductive particles come into contact with each other, an electrical pathway is formed within the conductive resin layer.

[0061] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins. Among these, epoxy resin is one of the most suitable resins. Epoxy resin has excellent heat resistance, moisture resistance, and adhesion. The resin in the conductive resin layer preferably contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] The conductive resin layer may be formed in multiple layers. The preferred thickness of the thickest part of the conductive resin layer is 10 μm to 150 μm.

[0063] The above describes the basic configuration of the multilayer ceramic capacitor 1. The preferred length L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 40, is 0.2 mm to 6 mm. The preferred length T of the multilayer ceramic capacitor 1 is 0.05 mm to 5 mm. The preferred length W of the multilayer ceramic capacitor 1 is 0.1 mm to 5 mm.

[0064] (Segregation of magnesium or manganese) In the multilayer ceramic capacitor 1 of this embodiment, a region where magnesium or manganese is segregated is formed in the internal electrode layer 30. This will be explained with reference to Figures 6 and 7. Figure 6 is an enlarged view of the framed area 110 in Figure 2. Figure 6 shows a part of the LT cross-section of the ceramic capacitor 1. Figure 7 shows a similar part in a conventional multilayer ceramic capacitor as in Figure 6.

[0065] (Outermost inner electrode layer and inner side inner electrode layer) Of the internal electrode layers 30, the one closest to the main surface side outer layer portion 11 is designated as the outermost internal electrode layer 301. Of the internal electrode layers 30, the one located on the interior side of the laminate 2 in the height direction T compared to the outermost internal electrode layer 301 is designated as the interior side internal electrode layer 302. The outermost internal electrode layer 301 shown in Figure 6 is the internal electrode layer 30 in contact with the first main surface side outer layer portion 12. In this case, the interior side internal electrode layer 30 refers to the internal electrode layer 30 located on the side closer to the second main surface side outer layer portion 13.

[0066] (Region where internal electrodes exist and region where internal electrodes are separated) The outermost internal electrode layer 301 includes an internal electrode presence region 311 and an internal electrode separation region 312. Similarly, the inner internal electrode layer 302 includes an internal electrode presence region 311 and an internal electrode separation region 312.

[0067] The internal electrode region 311 and the internal electrode separation region 312 will be described below. In the following description, the outermost internal electrode layer 301 will be used as an example to explain the internal electrode region 311 and the internal electrode separation region 312. Note that the following description also applies to the inner side internal electrode layer 302. Also, in Figures 6 and 7, the internal electrode region 311 and the internal electrode separation region 312 in the inner side internal electrode layer 302 are omitted.

[0068] The internal electrode presence region 311 is the region in the LT cross-section where the internal electrode layer 30 exists continuously in the length direction L. The internal electrode separation region 312 is the region in the LT cross-section where the internal electrode layer 30 is separated in the length direction L. No material constituting the internal electrode layer 30 is present in the internal electrode separation region 312. In the internal electrode separation region 312, the material constituting the internal electrode layer 30 is missing.

[0069] (Segregated region and non-segregated region) The internal electrode separation region 312 includes a segregation region 321 and a non-segregation region 322. The segregation region 321 is a region where magnesium or manganese is segregated. The non-segregation region 322 is a region where neither magnesium nor manganese is segregated. Magnesium and manganese usually segregate as oxides.

[0070] There are various configurations for the distribution of segregated regions 321 and non-segregated regions 322 in the internal electrode separation region 312. One internal electrode separation region 312 may include one or more segregated regions 321 and one or more non-segregated regions 322. One internal electrode separation region 312 may include only one segregated region 321 or only one non-segregated region 322.

[0071] The first internal electrode separation region 3121 shown in Figure 6 is an example that includes multiple segregation regions 321 and multiple non-segregation regions 322. The first internal electrode separation region 3121 includes two segregation regions 321 and three non-segregation regions 322.

[0072] The second internal electrode separation region 3122 shown in Figure 6 is an example that includes only the non-segregating region 322 and does not include the segregating region 321. The third internal electrode separation region 3123 is an example that includes only the segregating region 321 and does not include the non-segregating region 322.

[0073] (Ratio of the distance between the internal electrode region and the segregation region) Let's explain the distance of the segregation region 321. Let distance A be the length L of the internal electrode presence region 311. Let distance B be the length L of the segregation region 321. In the multilayer ceramic capacitor 1 of this embodiment, distance B / distance A is between 50% and 75%.

[0074] In Figure 6, distance 201 represents the length L of the internal electrode layer 30. Distance 211 represents the length L of the internal electrode presence region 311. Distance 212 represents the length L of the internal electrode separation region 312. Distance 214 represents the length L of the segregation region 321. Distance 215 represents the length L of the non-segregation region 322.

[0075] In the above-mentioned distance B / distance A, distance B is the sum of the distances 214 of the segregation region 321 contained in the internal electrode layer 30 of a predetermined length. Similarly, in distance B / distance A, distance A is the sum of the distances 211 of the internal electrode presence region 311 contained in the internal electrode layer 30 of a predetermined length. In other words, the above-mentioned distance B / distance A represents the ratio of the sum of distances 214 to the sum of distances 211 in the internal electrode layer 30 of a predetermined length. Furthermore, for each distance described below, if there are multiple objects, each distance is the sum of the distances of the multiple objects.

[0076] Here, the predetermined length can be, for example, 20 μm.

[0077] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the distance B / distance A is 50% or more and 75% or less. This makes it possible to suppress the thinning of the dielectric layer 20 due to segregation of oxides such as magnesium or manganese in the multilayer ceramic capacitor 1 of this embodiment. As a result, the multilayer ceramic capacitor 1 of this embodiment can improve high-temperature load reliability.

[0078] (Extension of the segregation region) In addition to Figure 6, Figure 7 will be used to explain the thinning of the dielectric layer. Figure 7 shows the same parts as in Figure 6 for a conventional multilayer ceramic capacitor.

[0079] When the ratio of distance B to distance A becomes less than 50%, high-temperature load reliability tends to decrease. A decrease in the ratio of distance B to distance A means that the length L of the segregation region 321 becomes relatively shorter in the internal electrode layer 30.

[0080] Assume that the same amount of magnesium oxide or manganese oxide segregates in the multilayer ceramic capacitor 1 of this embodiment shown in Figure 6 and in the conventional multilayer ceramic capacitor shown in Figure 7. Magnesium oxide or manganese oxide tends to segregate in the internal electrode separation region 312 of the internal electrode layer 30.

[0081] In both the multilayer ceramic capacitor 1 of this embodiment shown in Figure 6 and the conventional multilayer ceramic capacitor shown in Figure 7, the segregation region 321 is located within the internal electrode separation region 312 in the length direction L.

[0082] However, in the multilayer ceramic capacitor 1 of this embodiment shown in Figure 6, the segregation region 321 does not extend beyond the internal electrode layer 30 in the height direction T. In other words, the segregation region 321 is contained within the internal electrode separation region 312. This is because, in the multilayer ceramic capacitor 1 of this embodiment, the distance B, that is, the length L of the segregation region 321, is sufficiently long.

[0083] On the other hand, in the conventional multilayer ceramic capacitor shown in Figure 7, the segregation region 321 extends beyond the internal electrode layer 30 in the height direction T. In other words, the segregation region 321 is not contained within the internal electrode separation region 312. This is because, in the conventional multilayer ceramic capacitor, the distance B, i.e., the length L of the segregation region 321, is short.

[0084] (Distance of the internal electrode separation region) One reason why the segregation region 321 in conventional multilayer ceramic capacitors extends beyond the internal electrode layer 30 in the height direction T is thought to be that the length L of the internal electrode separation region 312 is not sufficiently long relative to the amount of magnesium oxide or manganese oxide. In conventional multilayer ceramic capacitors, no non-segregation region 322 remains in the internal electrode separation region 312 where the segregation region 321 is formed.

[0085] In contrast, in the multilayer ceramic capacitor 1 of this embodiment shown in Figure 6, a non-segregated region 322 remains in the internal electrode separation region 3121 where the segregated region 321 is formed. This indicates that the length L of the internal electrode separation region 312, length 212, is sufficiently long relative to the amount of magnesium oxide or manganese oxide.

[0086] In other words, as mentioned above, magnesium oxide or manganese oxide tends to segregate in the internal electrode separation region 312 of the internal electrode layer 30. Therefore, in order to contain the segregation region 321 within the internal electrode separation region 312 and prevent the segregation region 321 from protruding from the internal electrode layer 30 in the height direction T, it is preferable that the length L of the internal electrode separation region 312 is sufficiently long to accommodate the magnesium oxide or manganese oxide.

[0087] (Thinning of the dielectric layer) The thickness of the inner dielectric layer 21 will be explained with reference to Figures 6 and 7. Arrows 401, 421, and 422 in Figure 6 indicate the thickness of the inner dielectric layer 21 between the outermost inner electrode layer 301 and the inner side inner electrode layer 302 in the multilayer ceramic capacitor 1 of this embodiment.

[0088] Thickness 401 indicates the thickness of the inner dielectric layer 21 in the internal electrode presence region 311 of the outermost inner electrode layer 301. Thickness 421 indicates the thickness of the inner dielectric layer 21 in the segregation region 321 of the outermost inner electrode layer 301. Thickness 422 indicates the thickness of the inner dielectric layer 21 in the non-segregation region 322 of the outermost inner electrode layer 301.

[0089] In the conventional multilayer ceramic capacitor shown in Figure 7, the thickness 421 is thinner than the thicknesses 401 and 422. This is because the segregation region 321 protrudes from the internal electrode layer 30 in the height direction T. The arrow 431 in Figure 7 indicates the distance that the segregation region 321 protrudes from the internal electrode layer 30 in the height direction T. The thickness 421 of the inner dielectric layer 21 in the segregation region 321 is shorter by the distance 431 that the segregation region 321 protrudes from the internal electrode layer 30.

[0090] In contrast, in the multilayer ceramic capacitor 1 of this embodiment, the thickness 421 is equal to the thicknesses 401 and 422. In the multilayer ceramic capacitor 1 of this embodiment, the segregation region 321 does not protrude from the internal electrode layer 30 in the height direction T. Therefore, the thickness of the inner dielectric layer 21 in the segregation region 321 is the same as the thickness of the inner dielectric layer 21 in the internal electrode presence region 311.

[0091] Thus, the multilayer ceramic capacitor 1 of this embodiment can suppress the thinning of the dielectric layer 20 due to segregation of oxides such as magnesium or manganese. As a result, the multilayer ceramic capacitor 1 of this embodiment can improve high-temperature load reliability.

[0092] (If distance B / distance A is greater than 75%) Next, we will explain the case where distance B / distance A is greater than 75%. When distance B / distance A is greater than 75%, metals such as nickel that make up the internal electrode layer 30 are more likely to sphere. The sphereized metal may protrude from the surface of the internal electrode layer 30 in the height direction T. Also, the sphereized metal may be located inside the dielectric layer 20. As a result, the dielectric layer 20 becomes substantially thinner, and the high-temperature load reliability of the multilayer ceramic capacitor decreases.

[0093] (Length of segregated region and length of non-segregated region) In this embodiment, the internal electrode separation region 312 of the multilayer ceramic capacitor 1 includes a non-segregation region 322, and it is preferable that the length L of the segregation region 321 in the internal electrode separation region 312 is longer than the length L of the non-segregation region 322 in the internal electrode separation region 312. Here, the non-segregation region 322 is a region in which magnesium or manganese is not segregated.

[0094] Furthermore, if the internal electrode separation region 312 contains multiple segregation regions 321, the distance of the segregation regions 321 mentioned above is the sum of the distances of the multiple segregation regions 321. Similarly, if the internal electrode separation region 312 contains multiple non-segregation regions 322, the distance of the non-segregation regions 322 mentioned above is the sum of the distances of the multiple non-segregation regions 322.

[0095] Let's take the internal electrode separation region 3121 in Figure 6 as an example. The internal electrode separation region 3121 contains two segregation regions 321 and three non-segregation regions 322 in the length direction L. The length L of the segregation region 321 in the internal electrode separation region 3121 is the sum of the length L distances 214 of the two segregation regions 321 contained within the internal electrode separation region 3121. Similarly, the length L of the non-segregation region 322 in the internal electrode separation region 3121 is the sum of the length L distances 215 of the three non-segregation regions 322 contained within the internal electrode separation region 3121.

[0096] As shown in Figure 6, the sum of the length L distances 214 of the two segregation regions 321 is longer than the sum of the length L distances 215 of the three non-segregation regions 322. In this way, by making the length L distance of the segregation regions 321 in the internal electrode separation region 312 longer than the length L distance of the non-segregation regions 322, the thinning of the dielectric layer 20 due to overhang in the height T direction of the segregation regions 321 can be further suppressed. As a result, the high-temperature load reliability of the multilayer ceramic capacitor 1 can be further improved.

[0097] (Distance B / distance A in the outermost inner electrode layer and distance B / distance A in the inner inner electrode layer) In the multilayer ceramic capacitor 1 of this embodiment, the ratio (C) of the distance B / distance A of the inner side inner electrode layer 302 to the distance B / distance A of the outermost inner electrode layer 301 is preferably 0.1 or more and 0.6 or less.

[0098] By having the above-mentioned ratio (C) be between 0.1 and 0.6, it is possible to maintain the length L of the internal electrode presence region 311 contained in the inner side internal electrode layer 302, that is, to suppress the length L of the internal electrode separation region 312 contained in the inner side internal electrode layer 302, while increasing the length L of the non-segregation region 322 contained in the outermost internal electrode layer 301. This makes it possible to improve the reliability of the multilayer ceramic capacitor 1 while maintaining the capacitance of the multilayer ceramic capacitor 1.

[0099] On the other hand, if the ratio (C) is less than 0.1, the length L of the segregation region 321 included in the inner electrode layer 302 becomes shorter, making it difficult to maintain the capacitance of the multilayer ceramic capacitor 1.

[0100] (Continuity of the internal electrode layer on the inner side) In the multilayer ceramic capacitor 1 of this embodiment, the ratio D of the distance 214 in the length direction L of the segregation region 321 contained in the inner-side inner electrode layer 302 to the distance 211 in the length direction L of the inner electrode present region 311 contained in the inner-side inner electrode layer 302 is preferably 75% or more and 100% or less. By satisfying the above condition regarding the distance between the inner electrode present region 311 and the segregation region 321 in the inner-side inner electrode layer 302, a highly continuous inner-side inner electrode layer 302 can be obtained. This makes it possible to ensure high capacitance in the multilayer ceramic capacitor 1.

[0101] The ratio (C) of the distance B / distance A of the inner inner electrode layer 302 to the distance B / distance A of the outermost inner electrode layer 301 is between 0.1 and 0.6. The ratio D of the distance 214 in the length direction L of the segregation region 321 contained in the inner inner electrode layer 302 to the distance 211 in the length direction L of the inner electrode presence region 311 contained in the inner inner electrode layer 302 is 25% or less.

[0102] On the other hand, if the ratio D of the aforementioned distances is less than 75%, the metals such as nickel that make up the internal electrode layer 30 tend to spheroidize in the internal electrode layer 302. The spheroidized metal may protrude from the surface of the internal electrode layer 30 in the height direction T. In this case, the spheroidized metal thins the dielectric layer 20. As a result, the high-temperature load reliability of the multilayer ceramic capacitor deteriorates.

[0103] Furthermore, if the ratio D of the aforementioned distances is less than 75%, the continuity of the internal electrode layer 302 decreases. As a result, it becomes difficult to secure a high capacitance in the multilayer ceramic capacitor 1.

[0104] (Continuity of the internal electrode layer on the inner side) In the multilayer ceramic capacitor 1 of this embodiment, the ratio E of the distance L in the longitudinal direction of the segregation region 321 in the outermost layer internal electrode layer 301 and the distance L in the longitudinal direction of the internal electrode separation region 312 is preferably 90% or more and 100% or less.

[0105] By ensuring that the segregation region 321 and the internal electrode separation region 312 of the outermost internal electrode layer 301 satisfy the above ratio, the thinning of the dielectric layer 20 due to segregation of magnesium oxide or manganese oxide can be suppressed. As a result, the high-temperature load reliability of the multilayer ceramic capacitor 1 can be further improved.

[0106] When the ratio E mentioned above is less than 90%, the thickness of the dielectric layer 20 tends to decrease in the voids of either the magnesium oxide or manganese oxide segregation concentrated in the internal electrode layer 30, i.e., in the non-segregation region 322 of the internal electrode separation region 312. When the thickness of the dielectric layer 20 decreases, the electric field concentrates in the thin portion of the dielectric layer 20. As a result, the multilayer ceramic capacitor 1, particularly the dielectric layer 20, deteriorates, its insulation resistance decreases, and ultimately the multilayer ceramic capacitor 1 becomes more prone to failure.

[0107] (Measurement method) Referring to Figures 8A to 8C, the measurement method for the length L of the segregation region 321 will be explained. Figures 8A to 8C show the results of observing the WT cross-section of the multilayer ceramic capacitor 1 of this embodiment. Figures 8A to 8C show the results of observing the same part of the multilayer ceramic capacitor 1. Figure 8A shows an image from a scanning electron microscope (SEM). Figures 8B and 8C show analytical images from a wave-length-dispersive X-ray fluorescence spectroscopy (WDX). Specifically, Figure 8B is a mapping image of magnesium. Figure 8C is a mapping image of manganese.

[0108] The observation position of the WT cross section is the center of the length L and width W of the multilayer ceramic capacitor 1. The position in the height direction T is the effective layer portion 10 near the boundary with the outer layer portion 12 on the first main surface side. In other words, it is the portion near the internal electrode layer 30 that is closest to the first main surface 3 in the height direction T. The shape and size of the WT cross section to be observed can be, for example, a rectangle with a side length of 20 μm.

[0109] (Measuring distance) The distances of each part, such as the internal electrode region 311 described above, can be measured from the scanning electron microscope image shown in Figure 8A. When measuring, aligning the scale direction of the scanning electron microscope with the continuity direction of the internal electrode layer 30 makes distance measurement easier.

[0110] (Measurement of magnesium and manganese segregation) Magnesium and manganese segregation is performed using a wavelength-dispersive X-ray fluorescence analyzer. Specifically, for magnesium, the region with a count of 30 counts / second (cps: number of photoelectrons entering the detector per second) or higher is defined as the segregation region, and for manganese, the region with a count of 50 counts / second or higher is defined as the segregation region. Conversely, the region with a count of less than these values ​​is defined as the non-segregation region.

[0111] An example of the measurement procedure is to first determine the distance between the internal electrode presence region 311 and the internal electrode separation region 312 from the image obtained using a scanning electron microscope. Next, the internal electrode separation region 312 is observed using a wavelength-dispersive X-ray fluorescence analyzer. Specifically, the internal electrode separation region 312 is observed using a wavelength-dispersive X-ray fluorescence analyzer, and the distance between the magnesium or manganese segregation region 321 or non-segregation region 322 contained in the internal electrode separation region 312 is measured from the obtained mapping image based on the above-mentioned criteria. In this way, the proportions of the segregation region 321 and non-segregation region 322 in the internal electrode separation region 312 can be determined.

[0112] (Examples and Comparative Examples) Referring to Figure 9, examples and comparative examples of the multilayer ceramic capacitor 1 of this embodiment will be described. The samples used for evaluating the examples and comparative examples are as follows.

[0113] (sample) Dimensions of the multilayer ceramic capacitor: Length L 3.15mm, Height T 1.65mm, Width W 1.65mm Ceramic material for the dielectric layer: Barium titanate Capacitance of multilayer ceramic capacitor: 0.01μF Metal material of the internal electrode layer: Nickel

[0114] (Method for evaluating high-temperature load reliability) Applied voltage: 756V (×1.2WV) Temperature and time: 125 degrees Celsius, 2000 hours Number of reviews: 77 Judgment criteria: Samples exhibiting significant defects in appearance were deemed unreliable. ○ (Good): 0 unreliable items, × (Bad): 1 or more unreliable items.

[0115] (Evaluation results) As shown in Figure 9, when the distance B / distance A in the outermost inner electrode layer 301 was between 50% and 75%, the high-temperature load reliability was judged as ○ (good). In contrast, when the distance B / distance A was less than 50% and when the distance B / distance A was greater than 75%, the high-temperature load reliability was judged as × (poor).

[0116] The distance B / distance A mentioned above was measured using a sample different from the 77 samples used for evaluating high-temperature load reliability, but taken from the same manufacturing lot.

[0117] (Manufacturing method for multilayer ceramic capacitors) This document describes a method for manufacturing multilayer ceramic capacitors. However, the manufacturing method is not limited to the method described below.

[0118] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. An example of a paste made of conductive material is a paste in which an organic binder and an organic solvent are added to metal powder.

[0119] A conductive paste for the internal electrode layer 30 is printed onto the dielectric sheet using a printing plate designed to create the shape of the internal electrode layer 30. Examples of printing methods include screen printing and gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 31 formed on it and a dielectric sheet with the pattern of the second internal electrode layer 32 formed on it.

[0120] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the first main surface side outer layer portion 12 on the first main surface 3 side. On top of this, dielectric sheets with the pattern of the first internal electrode layer 31 printed on them and dielectric sheets with the pattern of the second internal electrode layer 32 printed on them are stacked alternately in sequence to form the effective layer portion 10. On top of this effective layer portion 10, a predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the second main surface side outer layer portion 13 on the second main surface 4 side. This results in a laminated sheet.

[0121] Here, the number of dielectric sheets corresponding to the first main surface outer layer 12 and the second main surface outer layer 13 is adjusted so that the thickness of the main surface outer layer 11 increases. This allows magnesium and manganese contained in the dielectric layer of the main surface outer layer 11 to diffuse to the outermost inner electrode layer 301. The thickness of the first main surface outer layer 12 and the second main surface outer layer 13 after firing can be, for example, 50 μm or more and 400 μm or less.

[0122] Furthermore, in order to increase the thickness of the internal electrode layer 30, for example, the thickness of the conductive paste for the internal electrode layer 30 is increased when printing it. This makes it possible to increase the continuity of the internal electrode layer 30, in particular the internal side internal electrode layer 302. In other words, in the internal electrode layer 30, the ratio of the internal electrode separation region 312 to the internal electrode presence region 311 can be reduced.

[0123] Next, the laminated sheets are pressed in the height direction by means of a hydrostatic press or other means to produce a laminated block.

[0124] Next, the laminated block is cut into predetermined sizes to form individual pieces, thereby obtaining multiple laminated chips. After this, the laminated chips may be polished by barrel polishing or other methods to round off the corners and edges.

[0125] Next, the laminated chips are fired. This firing process creates the laminate. The preferred firing temperature is between 900°C and 1400°C. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0126] By shortening the firing time, the continuity of the internal electrode layer 302 can be increased.

[0127] A conductive paste, which will serve as the base electrode layer 50, is applied to both end faces of the laminate 2. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing glass components and metal to the laminate 2, for example by dipping, and then performing a baking treatment. The temperature of the baking treatment at this time is preferably 700 degrees Celsius or more and 900 degrees Celsius or less.

[0128] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 2 with a baked layer.

[0129] Subsequently, a plating layer is formed on the surface of the base electrode layer 50, which consists of a baked layer. In this embodiment, a first plating layer 71 is formed on the surface of the first base electrode layer 51. A second plating layer 72 is formed on the surface of the second base electrode layer 52. In this embodiment, a nickel plating layer and a tin plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The nickel plating layer and the tin plating layer are formed sequentially, for example, by barrel plating.

[0130] When a conductive resin layer is provided, the conductive resin layer may be positioned to cover the baked layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baked layer, and then heat-treated at a temperature of 250 to 550 degrees Celsius or higher. This causes the thermosetting resin to harden and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. To prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0131] Through the above manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0132] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Combining two or more of the individual desirable configurations described in the above embodiments also constitutes the present invention. [Explanation of Symbols]

[0133] 1. Multilayer ceramic capacitor 2 Laminate 3. First main surface 4. Second main surface 5. First Aspect 6. Second Aspect 7. First end face 8. Second end face 10 Effective layer 11 Main surface side outer layer part (outer layer part) 14 Electrode facing part 20 Dielectric layer 21 Inner Dielectric Layer 22 Outer dielectric layer 30 Internal electrode layer 40 External electrode 301 Outermost internal electrode layer 302 Internal internal electrode layer 311 Internal electrode existing area 312 Internal electrode separation region 321 Segregation area 322 Non-segregating region L (Length direction) T (height direction) W (width direction)

Claims

1. Multiple stacked dielectric layers, It includes multiple stacked internal electrode layers, A first principal surface and a second principal surface that are opposite each other in the height direction, A first side and a second side that are perpendicular to the height direction and opposite to each other in the width direction, It further includes a first end face and a second end face that are opposite to each other in the longitudinal direction and perpendicular to the height direction and width direction, An inner layer portion in which the dielectric layer and the internal electrode layer are alternately stacked, A laminate further comprising an outer layer portion arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, A first external electrode disposed on the first end face, A multilayer ceramic capacitor including a second external electrode disposed on the second end face, When the inner electrode layer closest to the outer layer is designated as the outermost inner electrode layer, In a cross-section parallel to the length and height directions, The outermost layer of the internal electrode layer has an internal electrode presence region and an internal electrode separation region. The internal electrode separation region includes a magnesium or manganese segregation region. A multilayer ceramic capacitor in which the ratio (B / A) of the length B of the magnesium or manganese segregation region to the length A of the internal electrode region is 50% or more and 75% or less.

2. The internal electrode separation region includes a non-segregated region where magnesium or manganese is not segregated. The multilayer ceramic capacitor according to claim 1, wherein the length of the segregation region in the internal electrode separation region is longer than the length of the non-segregation region.

Images