Array substrate and method for manufacturing the same, display panel

Abstract

This invention provides an array substrate, a method for manufacturing the same, and a display panel that improve upon the technical challenge of low pixel density. [Solution] The array substrate 100 includes a substrate 110, an active layer 140, a gate insulating layer 150, a conductive layer 160, and a first electrode PE. The active layer includes a channel portion 141, a first conductor portion 142, and a second conductor portion 143. The conductive layer includes a gate 161 and a drain 162. The orthographic projection of the gate in the active layer is located within the channel portion. The drain overlaps and connects with a part of the first conductor portion. The first electrode is connected to the second conductor portion. The drain is connected to the first conductor portion, and the first electrode is directly connected to the second conductor portion. This reduces the placement of the source and source contact holes. Furthermore, in the direction from the first conductor portion to the second conductor portion, the length of the second conductor portion is shorter than the length of the first conductor portion, thereby shortening the length of the active layer and reducing the dimensions of the transistor on the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate, a manufacturing method thereof, and a display panel.

Background Art

[0002] In a conventional display panel, a top gate indium gallium zinc oxide thin film transistor (Top gate IGZO TFT) is used to reduce parasitic capacitance. However, the number of masks required for the thin film transistor forming the top gate structure is more than that required for the thin film transistor forming the bottom gate structure. As a result, the cost increases and the processes increase.

[0003] On the other hand, in order to reduce the number of masks required in the manufacturing process of the thin film transistor with a top gate structure, in a conventional display panel, the gate layer, the source layer, and the drain layer are formed of the same metal layer to reduce the number of masks. However, in this configuration, it is necessary to open vias on both sides of the gate insulating layer so that both the source and the drain are electrically connected to the corresponding conductive active layer. As a result, the size of the thin film transistor increases, and the pixel density of the display panel cannot be further increased.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this application provide an array substrate, a manufacturing method thereof, and a display panel to solve the technical problem that the pixel density of a conventional display panel is relatively small.

Means for Solving the Problems

[0005] Embodiments of this application provide an array substrate, and the array substrate includes a substrate, an active layer provided on one side of the substrate, including a channel portion, and a first conductor portion and a second conductor portion provided on both sides of the channel portion, A gate insulating layer comprising a first insulating portion and a second insulating portion provided at intervals, wherein the first insulating portion is provided on the side of the active layer away from the substrate, and the second insulating portion is provided at one end of the active layer, A conductive layer provided on the side of the gate insulating layer away from the substrate, comprising a gate and a drain provided at a distance, wherein the gate is located on the first insulating portion, the orthographic projection of the gate in the active layer is within the channel portion, the drain is located on the second insulating portion, and the drain overlaps and connects with a part of the first conductor portion, The conductive layer includes a first electrode provided on the side away from the substrate and connected to the second conductor portion.

[0006] Here, in the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length.

[0007] In the array substrate of the present invention, the range of the ratio of the first length to the second length is 1.2 to 2.

[0008] In the array substrate of the present invention, a first via is provided between the first insulating portion and the second insulating portion, and the drain is in contact with the side wall of the second insulating portion and extends along the side wall to the surface of the first conductor portion away from the substrate.

[0009] In the array substrate of the present invention, the drain includes an overlapping surface in contact with the first conductor portion, and the overlapping surface has a length of 2 to 8 microns in the direction from the first conductor portion toward the channel portion.

[0010] In the array substrate of the present invention, the array substrate is A first passivation layer provided on the side of the conductive layer away from the substrate, A flat layer provided on the side of the first passivation layer away from the substrate, A common electrode provided on the side of the flat layer away from the substrate, The system further includes a second passivation layer provided on the side of the common electrode away from the substrate.

[0011] Here, the array substrate is further provided with a second via that penetrates the second passivation layer, the flat layer, and the first passivation layer, and the first electrode is provided on the side of the second passivation layer away from the substrate and is connected to the second conductor portion by passing through the second via.

[0012] In the array substrate of the present invention, the inclination angle of the second via is less than 70°.

[0013] In the array substrate of the present invention, the array substrate is A buffer layer provided between the substrate and the active layer, The present invention further includes at least one transmission line for transmitting a voltage signal, wherein both the transmission line and the active layer are provided on the surface of the buffer layer away from the substrate.

[0014] In the array substrate of the present invention, the material of the transmission line is the same as the material of the first conductor portion and / or the second conductor portion.

[0015] This application further provides a method for manufacturing an array substrate, the method for manufacturing the array substrate is: To provide a substrate, Forming an active layer on the aforementioned substrate, A gate insulating layer is formed on the active layer, and a first via is opened in the gate insulating layer. The first conductive treatment is performed on the active layer that is not covered by the gate insulating layer, The conductive material layer is formed on the gate insulating layer such that the conductive material layer forms a conductive layer including a gate and a drain, the conductive material layer is patterned, and the gate and the drain are provided at a distance from each other. Using a self-aligned process, an etching process is performed on the gate insulating layer not covered by the gate and the drain so as to form a first insulating portion and a second insulating portion provided with a gap therebetween, the first insulating portion is provided on a side of the active layer away from the substrate, the second insulating portion is provided at one end of the active layer, the gate is located on the first insulating portion, the drain is located on the second insulating portion, and the drain overlaps and connects to the active layer corresponding to the first via. A second conductor formation process is performed on the active layer not covered by the gate and the drain so that the active layer corresponding to the gate forms a channel portion, the active layer connected to the channel portion and close to the drain forms a first conductor portion, and the active layer connected to the channel portion and away from the drain forms a second conductor portion. Forming a first electrode connected to the second conductor portion on a side of the conductive layer away from the substrate.

[0016] Here, in a direction from the first conductor portion toward the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length.

[0017] The present application further includes a display panel, and the display panel includes the above-described array substrate.

Brief Description of the Drawings

[0018] Hereinafter, in conjunction with the accompanying drawings, specific embodiments of the present application will be described in detail to clarify the technical solution and other inventive effects of the present application.

[0019] [Figure 1] It is a first type of configuration diagram related to the array substrate provided in the present application. [Figure 2] It is a second type of configuration diagram related to the array substrate provided in the present application. [Figure 3]It is a plan view of an active layer in the array substrate provided in the present application. [Figure 4] It is a configuration diagram of a display panel provided in the present application. [Figure 5] It is a step diagram of a method for manufacturing the array substrate provided in the present application. [Figure 6A-6H] It is a configuration diagram of each step related to the method for manufacturing the array substrate provided in the present application.

Embodiments for Carrying Out the Invention

[0020] Hereinafter, while referring to the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. It is clear that the described embodiments are only a part of the embodiments of the present application and not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application. Furthermore, it should be understood that the specific embodiments described in this specification are only intended to illustrate and explain the present application and are not intended to limit the present application.

[0021] In addition, in the description of the present application, the directions and positional relationships indicated by terms such as "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, and do not imply or suggest that the mentioned devices or elements must have a specific direction and be constructed and operated in a specific direction. It is only for the convenience of the description and simplification of the present application. Therefore, it should be understood that it should not be construed as limiting the present application.

[0022] Furthermore, the terms “first” and “second” are used solely to describe the purpose and should not be understood as indicating or suggesting relative importance, nor as implicitly specifying the number of technical features mentioned. Therefore, features limited to “first” and “second” may explicitly or implicitly include one or more features. In the description of this application, unless explicitly and specifically limited, “multiple” means two or more, and “at least one” means one, two, or more.

[0023] Referring to Figures 1 to 4, an embodiment of the present invention provides an array substrate 100, the array substrate 100 comprising a substrate 110, an active layer 140, a gate insulating layer 150, a conductive layer 160, and a first electrode PE, wherein the active layer 140 is provided on one side of the substrate 110, the gate insulating layer 150 is provided on the side of the active layer 140 away from the substrate 110, the conductive layer 160 is provided on the side of the gate insulating layer 150 away from the substrate 110, and the first electrode PE is provided on the side of the conductive layer 160 away from the substrate 110.

[0024] In this embodiment, the active layer 140 includes a channel portion 141 and a first conductor portion 142 and a second conductor portion 143 provided on both sides of the channel portion 141; the gate insulating layer 150 includes a first insulating portion 151 and a second insulating portion 152 provided at a distance from each other, the first insulating portion 151 being provided on the side of the active layer 140 away from the substrate 110, and the second insulating portion 152 being provided at one end of the active layer 140; the conductive layer 160 includes a gate 161 and a drain 162 provided at a distance from each other, the gate 161 being located on the first insulating portion 151, the orthographic projection of the gate 161 in the active layer 140 being within the channel portion 141, the drain 162 being located on the second insulating portion 152 and overlapping and connected to a part of the first conductor portion 142, and the first electrode PE being connected to the second conductor portion 143.

[0025] In this embodiment, referring to Figure 3, in the direction from the first conductor portion 142 to the second conductor portion 143, the first conductor portion 142 has a first length L1, and the second conductor portion 143 has a second length L2, with the first length L1 being greater than the second length L2.

[0026] In the embodiment, the range of the ratio of the first length L1 to the second length L2 is 1.2 to 2.

[0027] Referring to Figures 1 to 3, since the drain 162 is connected to the first conductor portion 142 and the first electrode PE is directly connected to the second conductor portion 143, the second conductor portion 143 can be multiplexed as a source, thereby reducing the number of sources to be installed. Furthermore, the gate insulating layer 150 does not need to have a source contact hole used to connect the drain 162 within the region where the second conductor portion 143 is located. Additionally, since the second length L2 of the second conductor portion 143 is smaller than the first length L1 of the first conductor portion 142, the length of the active layer 140 is shortened, which corresponds to reducing the size of the transistors on the array substrate 100. This allows more transistors to be placed in the product, increasing the pixel density of the product.

[0028] The technical proposal of this application will be explained below, along with specific examples.

[0029] Referring to Figures 1 and 2, the material of substrate 110 may be a rigid substrate, such as glass or quartz. The material of substrate 110 may also be a flexible substrate, such as polyimide.

[0030] Referring to Figures 1 and 2, the array substrate 100 includes a light-shielding layer 120 provided on one side of the substrate 110, and the orthographic projection of the active layer 140 in the light-shielding layer 120 is located within the light-shielding layer 120, thereby avoiding a decrease in the transistor's device effect due to light incident on the channel portion 141.

[0031] Referring to Figures 1 and 2, the light-shielding layer 120 may be a light-shielding metal or another material having light-shielding properties, such as molybdenum, aluminum, copper, titanium, or an alloy of the above materials or a laminate of the above materials.

[0032] In this embodiment, the thickness of the light-shielding layer 120 is in the range of 1000 angstroms to 8000 angstroms.

[0033] Referring to Figures 1 and 2, the array substrate 100 further includes a buffer layer 130 provided on the side of the light-shielding layer 120 away from the substrate 110, the buffer layer 130 covering the light-shielding layer 120 and laid across the entire array substrate 100, the material of the buffer layer 130 may include a compound structure consisting of nitrogen, silicon and oxygen, a single layer of silicon oxide, a silicon oxide film layer, or a laminated structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0034] In this embodiment, the thickness of the buffer layer 130 is in the range of 6,000 angstroms to 10,000 angstroms.

[0035] Referring to Figures 1 and 2, the array substrate 100 further includes an active layer 140 provided on the side of the buffer layer 130 away from the substrate 110, the active layer 140 including a channel portion 141 and a first conductor portion 142 and a second conductor portion 143 provided on both sides of the channel portion 141.

[0036] In this embodiment, the active layer 140 may be patterned by physical vapor phase growth using a yellow light process and an etching process. The material of the active layer 140 may be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO(InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides. Hereinafter, in the embodiments of this application, IGZO will be described as an example.

[0037] In this embodiment, the thickness of the active layer 140 is in the range of 400 angstroms to 1000 angstroms.

[0038] Referring to Figures 1 and 2, the array substrate 100 further includes a gate insulating layer 150 provided on the side of the active layer 140 away from the substrate 110, the gate insulating layer 150 includes a first insulating portion 151 and a second insulating portion 152 provided at intervals, a first via HL1 provided between the first insulating portion 151 and the second insulating portion 152, and a portion of the first conductor portion 142 is exposed by the first via HL1.

[0039] In this embodiment, the material of the gate insulating layer 150 may include a compound structure consisting of nitrogen, silicon, and oxygen, a single layer of silicon oxide, a silicon oxide film layer, or a laminated structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0040] In this embodiment, the thickness of the gate insulating layer 150 is in the range of 1000 angstroms to 3000 angstroms.

[0041] Referring to Figures 1 and 2, the array substrate 100 further includes a conductive layer 160 provided on the gate insulating layer 150, and the material of the conductive layer 160 may include a single-layer or multi-layer metal structure consisting of metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or at least two of the above-mentioned metals. For example, the material of the conductive layer 160 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0042] In this embodiment, the thickness of the conductive layer 160 is in the range of 2000 angstroms to 8000 angstroms.

[0043] In this embodiment, the conductive layer 160 may be patterned using a yellow light process and an etching process so that it forms a pattern including a gate 161 and a drain 162. Then, a self-aligning process is performed on the gate insulating layer 150 using the pattern of the conductive layer 160 to complete the patterning process for the gate insulating layer 150.

[0044] In this embodiment, the gate 161 is located on the first insulating portion 151, and the drain 162 is located on the second insulating portion 152. The gate 161 corresponds to the channel portion 141, i.e., the orthographic projection of the gate 161 in the active layer 140 overlaps with the channel portion 141. The drain 162 is in contact with the side wall of the second insulating portion 152 and extends along the side wall to the surface of the first conductor portion 142 away from the substrate 110, thereby electrically connecting the drain 162 to the first conductor portion 142.

[0045] Referring to Figures 1 and 2, the array substrate 100 further includes a first passivation layer 170 provided on the side of the conductive layer 160 away from the substrate 110, and the first passivation layer 170 is laid throughout the entire layer. The thickness of the first passivation layer 170 ranges from 1000 angstroms to 5000 angstroms.

[0046] Referring to Figures 1 and 2, the array substrate 100 further includes a flat layer 180 provided on the side of the first passivation layer 170 away from the substrate 110, and the flat layer 180 is laid throughout the entire layer. The material of the flat layer 180 includes a flexible material such as polytetrafluoroethylene, and the thickness of the flat layer 180 ranges from 10,000 angstroms to 30,000 angstroms.

[0047] Referring to Figure 1, the array substrate 100 further includes a common electrode AE ​​provided on the side of the flat layer 180 away from the substrate 110, and the material of the common electrode AE ​​may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0048] Referring to Figure 1, the array substrate 100 further includes a second passivation layer 190 provided on the side away from the common electrode AE ​​substrate 110, and the second passivation layer 190 is laid throughout the entire layer. The thickness of the second passivation layer 190 ranges from 1000 angstroms to 5000 angstroms.

[0049] In this embodiment, the materials of the first passivation layer 170 and the second passivation layer 190 may be the same. The materials of the first passivation layer 170 and the second passivation layer 190 may include a compound structure consisting of nitrogen, silicon, and oxygen, for example, a single layer of silicon oxide, a silicon oxide film layer, or a laminated structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0050] Referring to Figure 1, the array substrate 100 further includes a first electrode PE provided on the side of the second passivation layer 190 away from the substrate 110, and the material of the first electrode PE may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0051] In this embodiment, the array substrate 100 is further provided with a second via HL2 that penetrates the second passivation layer 190, the flat layer 180, and a portion of the first passivation layer 170. The first electrode PE is provided on the side of the second passivation layer 190 away from the substrate 110 and is connected to the second conductor portion 143 by passing through the second via HL2.

[0052] In the configurations shown in Figures 1 and 2, the thickness of the flat layer 180 is relatively large, resulting in a relatively large depth for the second via HL2. On the other hand, to avoid fracture of the first electrode PE at the sidewall of the second via HL2, the inclination angle of the second via HL2 in this invention must not be too large. For example, the inclination angle a of the second via HL2 in this invention may be less than 70°.

[0053] Referring to Figure 2, the first electrode PE may be provided directly on the side of the flat layer 180 away from the substrate 110, and the first electrode PE may be connected to the second conductor portion 143 via the second via HL2.

[0054] The configurations in Figures 1 and 2 can both be applied to liquid crystal display panels. The first electrode PE may be a pixel electrode. The configuration in Figure 2 can be applied to organic light-emitting diode display panels or MiniLEDs, MicroLEDs, etc. When the configuration in Figure 2 is applied to an organic light-emitting diode display panel, the first electrode PE may be an anode.

[0055] Furthermore, since the drain 162 extends into the active layer 140 corresponding to the first via HL1, and in the subsequent conductive treatment, the shielding by the drain 162 prevents the active layer 140 in contact with the drain 162 from undergoing the conductive treatment, in this invention, after opening the first via HL1 in the gate insulating layer 150, it is necessary to perform the first conductive treatment on the active layer 140 corresponding to the first via HL1. At the same time, after completing the patterning process for the conductive layer 160, it is necessary to perform a second conductive treatment on the active layer 140 that is not shielded by the drain 162, gate 161, and gate insulating layer 150.

[0056] In this embodiment, in order to remove oxygen from the active layer 140, both the first and second conduction treatments of this application may be plasma treatments.

[0057] Furthermore, since the region of the first conductor portion 142 that is not shielded by the drain 162 is subjected to two conduction treatments, while the second conductor portion 143 is subjected to only one conduction treatment, the oxygen content of the first conductor portion 142 that is not shielded by the drain 162 may be smaller than the oxygen content of the second conductor portion 143, that is, the resistivity of the first conductor portion 142 is smaller than the resistivity of the second conductor portion 143. In addition, in the configuration shown in Figures 1 and 2, the first conductor portion 142 includes adjacent first portion 142a and second portion 142b, with the first portion 142a corresponding to the first via HL1. Since the first portion 142a is subjected to two conduction treatments, the oxygen content of the first portion 142a in this application is smaller than the oxygen content of the second portion 142b, that is, the resistivity of the first portion 142a is smaller than the resistivity of the second portion 142b.

[0058] In this embodiment, in order to ensure electrical connection between the drain 162 and the first conductor portion 142, the contact area between the drain 162 and the first conductor portion 142 must not be too small. For example, the drain 162 includes an overlapping surface that is in contact with the first conductor portion 142, and the overlapping surface has a length L3 of 2 to 8 microns in the direction from the first conductor portion 142 toward the channel portion 141.

[0059] Since both the gate 161 and the drain 162 are composed of the same metal layer, this process reduces the number of metal layers and the insulating layer that separates the two metal layers. This process reduces the number of photomasks, but a reduction in the number of metal layers limits the wiring space for metal wiring in the product.

[0060] In this embodiment, referring to Figures 1 and 2, the array substrate 100 further includes at least one transmission line 143 for transmitting voltage signals, and both the transmission line 143 and the active layer 140 are provided on the surface of the buffer layer 130, and the material of the transmission line 143 is the same as the material of the first conductor portion 142 and / or the second conductor portion 143. That is, in this application, when manufacturing the active layer 140, the transmission line 143 for transmitting voltage signals in the display panel, such as high-potential lines, low-potential lines, clock signal lines, start signal lines, data signal lines, etc., can be manufactured at the same time using the material of the active layer 140.

[0061] Referring to Figure 4, the present invention further provides a display panel 200 which includes the array substrate 100 described above and a light-emitting element 300 provided on one side of the array substrate 100. If the display panel 200 is a liquid crystal display panel, the light-emitting element 300 is a backlight module, and the side of the display panel 200 away from the light-emitting element 300 may be the light-emitting side. If the display panel 200 is an organic light-emitting diode display panel, the light-emitting element 300 may be an organic light-emitting diode. If the display panel 200 is a direct display type display panel, the light-emitting element 300 may be a MiniLED, MicroLED, etc.

[0062] Referring to Figure 5, the present invention further provides a method for manufacturing an array substrate 100, the method for manufacturing the array substrate 100 comprising the following steps.

[0063] Step S101 provides substrate 110.

[0064] Referring to Figure 6A, the material of substrate 110 may be a rigid substrate, such as glass or quartz. The material of substrate 110 may also be a flexible substrate, such as polyimide.

[0065] This further includes forming a light-shielding layer 120 and a buffer layer 130 on the substrate 110 prior to step S102.

[0066] Referring to Figure 6A, the light-shielding layer 120 may be a light-shielding metal or another material having light-shielding properties. The light-shielding layer 120 is formed by a patterning process to create the configuration shown in Figure 6A, and the buffer layer 130 covers the light-shielding layer 120 and is laid in a full layer on the array substrate 100.

[0067] In step S102, an active layer 140 is formed on the substrate 110.

[0068] Referring to Figure 6B, the active layer 140 may be patterned using physical vapor phase growth by a yellow light process and an etching process. The material of the active layer 140 may be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO(InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides. Hereinafter, in the embodiments of this application, IGZO will be described as an example.

[0069] Referring to Figure 6B, when forming the active layer 140 on the buffer layer 130, at least one active wire 143a is further formed on the buffer layer 130, the material of the active wire 143a is the same as the material of the active layer 140, and the active wire 143a and the active layer 140 are formed in the same photomask process.

[0070] In step S103, a gate insulating layer 150 is formed on the active layer 140, and a first via HL1 is opened in the gate insulating layer 150.

[0071] Referring to Figure 6C, the gate insulating layer 150 is laid in its entirety, completely covering the active layer 140, while the first via HL1 in this step exposes a portion of the active layer 140 for subsequent conductive treatment.

[0072] In step S104, the active layer 140 that is not covered by the gate insulating layer 150 undergoes the first conductive treatment.

[0073] Referring to Figure 6C, the first conductive treatment in the present invention may be a plasma treatment, which removes oxygen from the active layer 140 not covered by the gate insulating layer 150, thereby making the active layer 140 not covered by the gate insulating layer 150 a conductor.

[0074] In step S105, the conductive material layer forms a conductive layer 160 including a gate 161 and a drain 162. Therefore, the conductive material layer is formed on the gate insulating layer 150, and a patterning process is performed on the conductive material layer so that the gate 161 and the drain 162 are separated.

[0075] Referring to Figure 6D, step S105 includes forming a conductive material layer on the gate insulating layer 150 and performing a patterning process on the conductive layer 160 using a yellow light process and an etching process so that the conductive layer 160 forms a pattern including the gate 161 and the drain 162.

[0076] In this embodiment, the material of the conductive layer 160 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0077] In step S106, in order to form a first insulating portion 151 and a second insulating portion 152 of the gate insulating layer 150 which are spaced apart, an etching process is performed on the gate insulating layer 150 that is not covered by the gate 161 and drain 162, the first insulating portion 151 is provided on the side of the active layer 140 away from the substrate 110, the second insulating portion 152 is provided at one end of the active layer 140, the gate 161 is located on the first insulating portion 151, the drain 162 is located on the second insulating portion 152, and the drain 162 overlaps with and connects to the active layer 140 corresponding to the first via HL1.

[0078] Referring to Figure 6E, the gate insulating layer 150 is subjected to a self-alignment process using a photomask of the gate 161 and source 162 patterns in the conductive layer 160, so that the gate insulating layer 150 forms a first insulating portion 151 and a second insulating portion 152 with gaps between them, to remove the gate insulating layer 150 that is not covered by the gate 161 and drain 162.

[0079] In step S107, a second conductor treatment is performed on the active layer 140 that is not covered by the gate 161 and the drain 162, such that the active layer 140 corresponding to the gate 161 forms a channel portion 141, the active layer 140 connected to the channel portion 141 and close to the drain 162 forms a first conductor portion 142, and the active layer 140 connected to the channel portion 141 and far from the drain 162 forms a second conductor portion 143.

[0080] Referring to Figure 6F, the second conducting treatment of the present invention may be a plasma treatment, such that the portion of the active layer 140 close to the drain 162 forms the first conducting portion 142, and the portion of the active layer 140 away from the drain 162 forms the second conducting portion 143, thereby removing oxygen from the active layer 140 that is not shielded by the drain 162, gate 161, and gate insulating layer.

[0081] In this embodiment, the area of ​​the first conductor portion 142 not shielded by the drain 162 is subjected to two conduction treatments, while the second conductor portion 143 is subjected to only one conduction treatment. Therefore, the oxygen content of the first conductor portion 142 not shielded by the drain 162 may be smaller than that of the second conductor portion 143. That is, the resistivity of the first conductor portion 142 is smaller than that of the second conductor portion 143. In addition, in the configuration of Figure 6F, the first conductor portion 142 includes adjacent first portion 142a and second portion 142b, and the first portion 142a corresponds to the first via HL1. Since the first portion 142a underwent both a first and second conduction treatment, while the second portion 142b underwent only the second conduction treatment, the oxygen content of the first portion 142a of the present application is smaller than that of the second portion 142b, that is, the resistivity of the first portion 142a is smaller than that of the second portion 142b.

[0082] In this embodiment, in the direction from the first conductor portion 142 to the second conductor portion 143, the first conductor portion 142 has a first length L1, and the second conductor portion 143 has a second length L2, with the first length L1 being greater than the second length L2.

[0083] In addition, since the drain 162 is connected to the first conductor portion 142 and the first electrode PE is directly connected to the second conductor portion 143, the second conductor portion 143 can be multiplexed as a source, thereby reducing the number of sources to be installed. Furthermore, the gate insulating layer 150 no longer needs to have a source contact hole used to connect the drain 162 within the region where the second conductor portion 143 is located. Moreover, since the second length L2 of the second conductor portion 143 is smaller than the first length L1 of the first conductor portion 142, the length of the active layer 140 can be shortened, which corresponds to reducing the size of the transistors on the array substrate 100. As a result, more transistors can be placed in the product, increasing the pixel density of the product.

[0084] In this embodiment, since the active wire 143a is not shielded by the gate insulating layer 150, the active wire 143a forms a transmission line 143 for transmitting voltage signals through a second conductor treatment, and the transmission line 143 may be, for example, a high-potential line, a low-potential line, a clock signal line, a start signal line, a data signal line, etc.

[0085] In step S108, a first electrode PE connected to the second conductor portion 143 is formed on the side of the conductive layer 160 away from the substrate 110.

[0086] Referring to Figure 6G, before step S108, the procedure further includes forming a first passivation layer 170 on the side of the conductive layer 160 away from the substrate 110, forming a flat layer 180 on the side of the first passivation layer 170 away from the substrate 110, forming a common electrode AE ​​on the side of the flat layer 180 away from the substrate 110, and forming a second passivation layer 190 on the side of the common electrode AE ​​away from the substrate 110.

[0087] In addition, in the processes of the first passivation layer 170, the flat layer 180, and the second passivation layer 190, it is necessary to open vias that expose a part of the second conductor portion 143, and the vias in the first passivation layer 170, the flat layer 180, and the second passivation layer 190 are continuous and form the second via HL2.

[0088] Referring to Figure 6G, the first electrode PE is electrically connected to the second conductor portion 143 by passing through the second via HL2.

[0089] In this embodiment, the materials of the buffer layer 130, gate insulating layer 150, first passivation layer 170, and second passivation layer 190 may include a compound structure consisting of nitrogen, silicon, and oxygen, for example, a single layer of silicon oxide, a silicon oxide film layer, or a laminated structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0090] In this embodiment, the material of the flat layer 180 includes a flexible material such as polytetrafluoroethylene.

[0091] In this embodiment, the materials for the first electrode PE and the common electrode AE ​​may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0092] Referring to Figure 6H, the process further includes forming a first passivation layer 170 on the side of the conductive layer 160 away from the substrate 110, and forming a flat layer 180 on the side of the first passivation layer 170 away from the substrate 110, prior to step S108.

[0093] Referring to Figure 6H, the first electrode PE may be provided directly on the side of the flat layer 180 away from the substrate 110, and the first electrode PE may be connected to the second conductor portion 143 via the second via HL2.

[0094] In the configurations shown in Figures 6G and 6H, the thickness of the flat layer 180 is relatively large, resulting in a relatively large depth for the second via HL2. On the other hand, to avoid fracture of the first electrode PE at the sidewall of the second via HL2, the inclination angle of the second via HL2 in this application must not be too large. For example, the inclination angle a of the second via HL2 in this application may be less than 70°.

[0095] The configurations in Figures 6G and 6H can both be applied to liquid crystal display panels, and the first electrode PE may be a pixel electrode. The configuration in Figure 6H can be further applied to organic light-emitting diode display panels or MiniLEDs, MicroLEDs, etc. When the configuration in Figure 6H is applied to an organic light-emitting diode display panel, the first electrode PE may be an anode.

[0096] The present invention further provides a mobile terminal comprising a terminal body and the display panel 200 described above, wherein the terminal body and the display panel 200 are integrated. The terminal body may be an element such as a circuit board bonded to the display panel 200, or a cover provided on the display panel 200. The mobile terminal may be an electronic device such as a mobile phone, television, or laptop computer.

[0097] In the embodiments described above, each embodiment has its own focus, and for parts of embodiments that are not described in detail, you can refer to the relevant descriptions in other embodiments.

[0098] The embodiments of the present application have been described in detail above. While this specification has described the principles and embodiments of the present application using specific examples, the descriptions of the embodiments are merely intended to aid in understanding the technical proposal and its core concept. Those skilled in the art may modify the technical proposals described in the above-described embodiments or substitute some of their technical features with equivalent ones, but it should be understood that these modifications or substitutions do not cause the essence of the corresponding technical proposal to deviate from the scope of the technical proposals of the various embodiments of the present application.

Claims

1. Substrate and, An active layer provided on one side of the substrate, including a channel portion and a first conductor portion and a second conductor portion provided on both sides of the channel portion, A gate insulating layer comprising a first insulating portion and a second insulating portion provided at intervals, wherein the first insulating portion is provided on the side of the active layer away from the substrate, and the second insulating portion is provided at one end of the active layer, A conductive layer provided on the side of the gate insulating layer away from the substrate, comprising a gate and a drain provided at a distance, wherein the gate is located on the first insulating portion, the orthographic projection of the gate in the active layer is within the channel portion, the drain is located on the second insulating portion, and the drain overlaps and connects with a part of the first conductor portion, The conductive layer includes a first electrode provided on the side away from the substrate and connected to the second conductor portion, Here, in the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length. Array substrate.

2. The range of the ratio of the first length to the second length is 1.2 to 2. The array substrate according to claim 1.

3. A first via is provided between the first insulating portion and the second insulating portion, and the drain is in contact with the side wall of the second insulating portion and extends along the side wall to the surface of the first conductor portion away from the substrate. The array substrate according to claim 1.

4. The drain includes an overlapping surface in contact with the first conductor portion, and the overlapping surface has a length of 2 to 8 microns in the direction from the first conductor portion toward the channel portion. The array substrate according to claim 3.

5. The aforementioned array substrate is A first passivation layer provided on the side of the conductive layer away from the substrate, A flat layer provided on the side of the first passivation layer away from the substrate, A common electrode provided on the side of the flat layer away from the substrate, The present invention further includes a second passivation layer provided on the side of the common electrode away from the substrate, Here, the array substrate is further provided with a second via that penetrates the second passivation layer, the flat layer, and the first passivation layer, and the first electrode is provided on the side of the second passivation layer away from the substrate and is connected to the second conductor portion by passing through the second via. The array substrate according to any one of claims 1 to 4.

6. The inclination angle of the second via is less than 70°. The array substrate according to claim 5.

7. The aforementioned array substrate is A buffer layer provided between the substrate and the active layer, The transmission line further includes at least one transmission line for transmitting a voltage signal, wherein both the transmission line and the active layer are provided on the surface of the buffer layer away from the substrate. The array substrate according to any one of claims 1 to 4.

8. The material of the transmission line is the same as the material of the first conductor portion and / or the second conductor portion. The array substrate according to claim 7.

9. To provide a substrate, Forming an active layer on the aforementioned substrate, A gate insulating layer is formed on the active layer, and a first via is opened in the gate insulating layer. The first conductive treatment is performed on the active layer that is not covered by the gate insulating layer, The conductive material layer is formed on the gate insulating layer such that the conductive material layer forms a conductive layer including a gate and a drain, the conductive material layer is patterned, and the gate and the drain are provided at a distance from each other. The gate insulating layer is etched using a self-aligning process to form a first insulating portion and a second insulating portion that are spaced apart, such that the first insulating portion is provided on the side of the active layer away from the substrate, the second insulating portion is provided at one end of the active layer, the gate is located on the first insulating portion, the drain is located on the second insulating portion, and the drain overlaps and connects to the active layer corresponding to the first via. A second conductive treatment is performed on the active layer not covered by the gate and the drain, such that the active layer corresponding to the gate forms a channel portion, the active layer connected to the channel portion and close to the drain forms a first conductive portion, and the active layer connected to the channel portion and far from the drain forms a second conductive portion. This includes forming a first electrode connected to the second conductor portion on the side of the conductive layer away from the substrate, Here, in the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length. A method for manufacturing array substrates.

10. Includes an array substrate according to any one of claims 1 to 4, Display panel.

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