Circuit equipment and switching power supply equipment

Abstract

To provide a circuit device, etc., in which the boost voltage does not fall below the minimum operating voltage of the pre-driver. [Solution] The circuit device 100 includes a pre-driver 130 that drives the gate of a first N-type MOS transistor TQ1 provided between a power supply node NVDD and a switch node NSWQ, and a bootstrap circuit 160 that generates a boot voltage VBT for the pre-driver 130 from the power supply voltage VDD. A boot capacitor 210 is provided between the switch node NSWQ and the boot node NVBT that supplies the boot voltage VBT to the pre-driver 130. The bootstrap circuit 160 includes a P-type MOS transistor TRP and a Schottky barrier diode SBD provided between the power supply node NVDD and the boot node NVBT. The anode of the Schottky barrier diode SBD is connected to the power supply node NVDD, and the cathode is connected to the boot node NVBT.

Description

Technical Field

[0004] , , , ,

[0005] , , , ,

[0001] The present invention relates to a circuit device, a switching power supply device, and the like.

Background Art

[0002] Patent Document 1 discloses a bootstrap circuit that supplies a boost voltage to a driver. The bootstrap circuit includes a constant current generation circuit that generates a constant voltage, a Schottky barrier diode connected between the constant voltage node and the boost voltage node, and a bootstrap capacitor connected between the boost voltage node and the output node of the switch output stage. The driver drives the output transistor of the switch output stage based on the boost voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, when the bootstrap capacitor is charged, a current flows through the Schottky barrier diode. Since the Schottky barrier diode has a forward voltage, loss occurs in the Schottky barrier diode during the charging of the bootstrap capacitor.

[0005] To reduce losses, one could consider using a MOS transistor instead of a Schottky barrier diode and keeping the MOS transistor on during normal operation. However, since the MOS transistor is off during startup, the boot capacitor is charged through the MOS transistor's body diode. Because the forward voltage of the body diode is greater than the forward voltage of the Schottky barrier diode, the boost voltage may fall below the driver's minimum operating voltage during startup. [Means for solving the problem]

[0006] One aspect of the present disclosure relates to a circuit device for switching control of a first N-type MOS transistor of an output driver of a switching power supply device that generates an output voltage from a power supply voltage, comprising: a pre-driver that drives the gate of the first N-type MOS transistor, which is provided between a power supply node to which the power supply voltage is supplied and a switch node; and a bootstrap circuit that generates a boot voltage for the pre-driver from the power supply voltage, wherein a boot capacitor is provided between the switch node and a boot node that supplies the boot voltage to the pre-driver, and the bootstrap circuit comprises a P-type MOS transistor provided between the power supply node and the boot node, and a Schottky barrier diode whose anode is connected to the power supply node and whose cathode is connected to the boot node.

[0007] Another aspect of the present disclosure relates to a switching power supply device comprising the above-described circuit device, the output driver, the boot capacitor, the switch node, and an inductor provided between the output node and the output node from which the output voltage is output. [Brief explanation of the drawing]

[0008] [Figure 1] An example configuration of a circuit device and a switching power supply unit that includes the circuit device. [Figure 2] Detailed configuration example of a circuit device. [Figure 3]Examples of signal waveforms from a circuit device. [Figure 4] Example of a circuit device configuration for a comparative example. [Figure 5] Detailed configuration example of the comparative circuit device. [Figure 6] An example of a signal waveform from a comparative circuit device. [Figure 7] Example of circuit device layout. [Modes for carrying out the invention]

[0009] Preferred embodiments of this disclosure will be described in detail below. Note that these embodiments are not intended to unduly limit the scope of the claims, and not all configurations described in these embodiments are necessarily essential.

[0010] In this embodiment, the connection includes an electrical connection. An electrical connection is a connection that allows for the transmission of electrical signals, voltages, or currents, and includes connections that enable the transmission of information by electrical signals. The electrical connection may be a connection via a passive element or an active element, etc.

[0011] 1. Example Configuration Figure 1 shows an example configuration of a circuit device 100 and a switching power supply device 200 that includes the circuit device 100. The switching power supply device 200 includes the circuit device 100 and an external circuit. The external circuit includes a boot capacitor 210, an inductor 250, a capacitor 260, and a load 290.

[0012] The circuit device 100 includes an output driver 110, a pre-driver 130, a bootstrap circuit 160, a power terminal TVDD, a boot terminal TBT, a switch terminal TSWQ, and a ground terminal TGND. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. Here, an example is shown in which the output driver 110 is provided inside the circuit device 100, but the output driver 110 may be provided outside the circuit device 100. Similarly, here, an example is shown in which the boot capacitor 210 is provided outside the circuit device 100, but the boot capacitor 210 may be provided inside the circuit device 100.

[0013] The power supply terminal TVDD is supplied with the power supply voltage VDD from an external power supply to the circuit device 100. The power supply node NVDD is a node connected to the power supply terminal TVDD. Note that the power supply voltage VDD may be generated internally within the circuit device 100. The ground terminal TGND is supplied with the ground voltage GND from an external power supply to the circuit device 100. The ground node NGND is a node connected to the ground terminal TGND.

[0014] One end of the boot capacitor 210 is connected to the boot terminal TBT, and the other end is connected to the switch terminal TSWQ. The boot node NVBT is a node connected to the boot terminal TBT, and the switch node NSWQ is a node connected to the switch terminal TSWQ. One end of the inductor 250 is connected to the switch terminal TSWQ, and the other end is connected to the output node NOUT of the switching power supply 200. One end of the capacitor 260 is connected to the output node NOUT, and the other end is connected to the ground node NGND. One end of the load 290 is connected to the output node NOUT, and the other end is connected to the ground node NGND. The load 290 is a circuit or device that is powered by the output voltage VOUT of the switching power supply 200.

[0015] The output driver 110 drives the inductor 250 by outputting a switch voltage SWQ to the switch node NSWQ. The output driver 110 includes a high-side first N-type MOS transistor TQ1 and a low-side second N-type MOS transistor TQ2.

[0016] The source of the first N-type MOS transistor TQ1 is connected to the switch node NSWQ, the drain is connected to the power supply node NVDD, and the gate is connected to the drive node NHDR of the pre-driver 130. The drive signal HDR from the pre-driver 130 is input to the gate. The back gate of the first N-type MOS transistor TQ1 is connected to the source, creating a parasitic body diode BDQ1. The forward direction of the body diode BDQ1 is from the switch node NSWQ to the power supply node NVDD.

[0017] The source of the first N-type MOS transistor TQ1 is connected to the switch node NSWQ, the drain is connected to the power supply node NVDD, and the gate is connected to the drive node NHDR of the pre-driver 130. The back gate of the first N-type MOS transistor TQ1 is connected to the source, creating a parasitic body diode BDQ1. The forward direction of the body diode BDQ1 is from the switch node NSWQ to the power supply node NVDD.

[0018] The source of the second-generation N-type MOS transistor TQ2 is connected to the ground node NGND, and its drain is connected to the switch node NSWQ. The gate is input to the drive signal LDR. The high level of the drive signal LDR is the power supply voltage VDD, and the low level is the ground voltage GND. The back gate of the second-generation N-type MOS transistor TQ2 is connected to the source, creating a parasitic body diode BDQ2. The forward direction of the body diode BDQ2 is from the ground node NGND to the switch node NSWQ. Alternatively, a diode may be provided instead of the second-generation N-type MOS transistor TQ2. The anode of that diode is connected to the ground node NGND, and its cathode is connected to the switch node NSWQ.

[0019] The first N-type MOS transistor TQ1 and the second N-type MOS transistor TQ2 are exclusively turned on. That is, when the first N-type MOS transistor TQ1 is on, the second N-type MOS transistor TQ2 is off, and when the first N-type MOS transistor TQ1 is off, the second N-type MOS transistor TQ2 is on.

[0020] The pre-driver 130 drives the gate of the first N-type MOS transistor TQ1 based on the control signal HCT. The high level of the control signal HCT is the power supply voltage VDD, and the low level is the ground voltage GND. The pre-driver 130 includes a P-type MOS transistor TAP, an N-type MOS transistor TAN, a resistor RAP, a resistor RAN, a resistor REN, and an N-type MOS transistor TEN. Note that the resistors RAP and RAN may be omitted. Also, the resistor REN and the N-type MOS transistor TEN may be omitted.

[0021] The source of the P-type MOS transistor TAP is connected to the boot node NVBT, and the drain is connected to one end of the resistor RAP. The control signal HCT is input to the gate. The other end of the resistor RAP is connected to the drive node NHDR. One end of the resistor RAN is connected to the drive node NHDR, and the other end is connected to the drain of the N-type MOS transistor TAN. The source of the N-type MOS transistor TAN is connected to the switch node NSWQ. The control signal HCT is input to the gate.

[0022] One end of resistor REN is connected to the drive node NHDR, and the other end is connected to the drain of the N-type MOS transistor TEN. The source of the N-type MOS transistor TEN is connected to the ground node NGND. The gate is input to the enable signal ENB. The back gate of the N-type MOS transistor TEN is connected to the source, creating a parasitic body diode BDEN. The forward direction of the body diode BDEN is from the ground node NGND to the other end of resistor REN. When the switching power supply 200 is disabled, the enable signal ENB is high, the N-type MOS transistor TEN is on, and the drive node NHDR is fixed to the ground voltage GND. When the switching power supply 200 is enabled, the enable signal ENB is low, and the N-type MOS transistor TEN is off. Hereafter, we will assume that the N-type MOS transistor TEN is off.

[0023] The bootstrap circuit 160 generates the boot voltage VBT, which is the high-potential side power supply for the pre-driver 130, from the power supply voltage VDD.

[0024] Specifically, when the control signal HCT and the drive signal LDR are at high levels, the first N-type MOS transistor TQ1 is off and the second N-type MOS transistor TQ2 is on. Since the switch voltage SWQ becomes the ground voltage GND, the low-level drive signal HDR becomes the ground voltage GND. At this time, the bootstrap circuit 160 charges the boot capacitor 210 based on the power supply voltage VDD.

[0025] When the control signal HCT and the drive signal LDR are at low levels, the first N-type MOS transistor TQ1 is on and the second N-type MOS transistor TQ2 is off. The switch voltage SWQ becomes the power supply voltage VDD, so the boot voltage VBT is the sum of the power supply voltage VDD and the voltage held by the boot capacitor 210. The high-level drive signal HDR becomes the boot voltage VBT, which is a voltage higher than the power supply voltage VDD.

[0026] The bootstrap circuit 160 includes a P-type MOS transistor TRP and a Schottky barrier diode SBD.

[0027] The source of the P-type MOS transistor TRP is connected to the boot node NVBT, and its drain is connected to the power supply node NVDD. The gate is input to the boot signal BTG. The high level of the boot signal BTG is the power supply voltage VDD, and the low level is the ground voltage GND. The back gate of the P-type MOS transistor TRP is connected to the source, creating a parasitic body diode BDP. The forward direction of the body diode BDP is from the power supply node NVDD to the boot node NVBT.

[0028] The anode of a Schottky barrier diode (SBD) is connected to the power node NVDD, and the cathode is connected to the boot node NVBT. The forward voltage of the Schottky barrier diode (SBD) is lower than the forward voltage of the body diode (BDP). The Schottky barrier diode (SBD) is constructed, for example, by a junction between a diffusion layer of a semiconductor substrate and a metal film.

[0029] When the drive signal LDR is at a high level and the second N-type MOS transistor TQ2 is ON, the boot signal BTG is at a low level and the P-type MOS transistor TRP is ON. That is, the boot capacitor 210 is charged via the ON P-type MOS transistor TRP. However, during the initial charging of the boot capacitor 210 when the circuit device 100 is started up, the P-type MOS transistor TRP is OFF. At this time, the boot capacitor 210 is charged via the Schottky barrier diode SBD. This helps to avoid jamming during startup. Details of this point will be described later in the comparative examples in Figures 4 to 6.

[0030] Figure 2 shows a detailed configuration example of the circuit device 100. Hereafter, explanations of parts similar to those in Figure 1 will be omitted as appropriate. The circuit device 100 further includes a pre-driver 140, a switching control circuit 150, and a terminal TVQ.

[0031] Terminal TVQ is connected to output node NOUT. The output voltage VOUT is input to the switching control circuit 150 via terminal TVQ.

[0032] The switching control circuit 150 pulse-modulates the control signals HCT and LCT based on the clock signal CK and the output voltage VOUT so that the output voltage VOUT becomes a predetermined constant voltage. The clock signal CK is input to the switching control circuit 150 from, for example, an oscillator circuit built into or provided outside the circuit device 100. The pulse modulation control is, for example, Pulse Width Modulation. The switching control circuit 150 also performs startup control based on the drive signals HDR and LDR. The switching control circuit 150 also outputs a boot signal BTG to the gate of the P-type MOS transistor TRP of the bootstrap circuit 160. The switching control circuit 150 may include analog circuits and logic circuits. The analog circuit is, for example, an error amplifier, a triangle wave generation circuit, or a comparator, and is, for example, a circuit that performs pulse modulation control based on the output voltage VOUT. The logic circuit is, for example, a circuit for outputting the control signals HCT, LCT, and the boot signal BTG. A logic circuit is, for example, a circuit that outputs the above-mentioned signals based on signals generated by an analog circuit and driving signals such as HDR.

[0033] The pre-driver 140 drives the second-n type MOS transistor TQ2 by outputting a drive signal LDR to the gate of the second-n type MOS transistor TQ2 based on the control signal LCT. The high level of the drive signal LDR is the power supply voltage VDD, and the low level is the ground voltage GND.

[0034] Figure 3 shows an example of the signal waveform of the circuit device 100. The "ON" and "OFF" labels attached to the signal waveforms indicate the on / off state of the transistors controlled by each signal. Assume that at time t0 after the circuit device 100 is started, the first rising edge of the clock signal CK is input to the switching control circuit 150.

[0035] Before time t0, the switching control circuit 150 outputs a control signal HCT that sets the drive signal HDR to a low level, a control signal LCT that sets the drive signal LDR to a low level, and a high-level boot signal BTG. As a result, the first N-type MOS transistor TQ1, the second N-type MOS transistor TQ2, and the P-type MOS transistor TRP are turned off. At this time, the boot capacitor 210 is charged via the Schottky barrier diode SBD, so the boot voltage VBT is lower than the power supply voltage VDD by the forward voltage VSBD of the Schottky barrier diode SBD.

[0036] When the first rising edge of the clock signal CK is input at time t0, the switching control circuit 150 outputs a control signal HCT that changes the drive signal HDR from a low level to a high level, outputs a control signal LCT that keeps the drive signal LDR at a low level, and keeps the boot signal BTG at a high level. As a result, the first N-type MOS transistor TQ1 turns from off to on, the second N-type MOS transistor TQ2 remains off, and the P-type MOS transistor TRP remains off. Since the switch voltage SWQ changes from the ground voltage GND to the power supply voltage VDD, the boot voltage VBT becomes a voltage that is twice the power supply voltage VDD and then lower by the forward voltage VSBD of the Schottky barrier diode SBD.

[0037] The switching control circuit 150 outputs a control signal HCT that changes the drive signal HDR from a high level to a low level. The switching control circuit 150 also monitors the drive signal HDR and, triggered by the rising edge of the drive signal HDR, outputs a control signal LCT that changes the drive signal LDR from a low level to a high level, and changes the boot signal BTG from a high level to a low level. As a result, the first N-type MOS transistor TQ1 turns from on to off, and the second N-type MOS transistor TQ2 and the P-type MOS transistor TRP turn from off to on. Since the boot capacitor 210 is charged via the on P-type MOS transistor TRP, the boot voltage VBT becomes the power supply voltage VDD.

[0038] When the second rising edge of the clock signal CK is input, the switching control circuit 150 outputs a control signal HCT that changes the drive signal HDR from low level to high level, a control signal LCT that changes the drive signal LDR from high level to low level, and the boot signal BTG from low level to high level. As a result, the first N-type MOS transistor TQ1 turns from off to on, and the second N-type MOS transistor TQ2 and the P-type MOS transistor TRP turn from on to off. Since the switch voltage SWQ changes from the ground voltage GND to the power supply voltage VDD, the boot voltage VBT becomes twice the power supply voltage VDD. The same operation is repeated thereafter.

[0039] According to this embodiment, the only decrease in the boot voltage VBT before time t0 is the forward voltage VSBD of the Schottky barrier diode SBD, which is lower than the body diode BDP. Therefore, the minimum operating voltage of the pre-driver 130, i.e., the boot voltage VBT at which the P-type MOS transistor TAP can be turned on, can be secured, and startup problems can be avoided. This point will be explained using the comparative examples in Figures 4 to 6.

[0040] Figure 4 shows an example configuration of the comparative example circuit device 100. Figure 5 shows a detailed configuration example of the comparative example circuit device 100. In Figures 4 and 5, the Schottky barrier diode (SBD) shown in Figures 1 and 2 is omitted.

[0041] Figure 6 shows an example of the signal waveform of the comparative example circuit device 100. Before time t0, the first N-type MOS transistor TQ1, the second N-type MOS transistor TQ2, and the P-type MOS transistor TRP are off. At this time, the boot capacitor 210 is charged via the body diode BDP of the P-type MOS transistor TRP, so the boot voltage VBT is lower than the power supply voltage VDD by the forward voltage VBD of the body diode BDP. The forward voltage VBD of the body diode BDP is higher than the forward voltage VSBD of the Schottky barrier diode SBD. Therefore, before time t0, the boot voltage VBT = VDD - VBD of the comparative example is lower than the boot voltage VBT = VDD - VSBD of this embodiment.

[0042] When the first rising edge of the clock signal CK is input at time t0, the switching control circuit 150 attempts to change the control signal HCT from high to low, thereby changing the drive signal HDR from low to high. However, if the boot voltage VBT = VDD - VBD is lower than the minimum operating voltage of the pre-driver 130, i.e., the boot voltage at which the P-type MOS transistor TAP can be turned on, the P-type MOS transistor TAP will not turn on. In this case, the drive signal HDR remains at a low level, and no rising edge occurs for the drive signal HDR. Since the switching control circuit 150 controls the drive signal LDR and the boot signal BTG using the rising edge of the drive signal HDR as a trigger, the drive signal LDR remains at a low level, and the boot signal BTG remains at a high level. In this way, the switching power supply 200 becomes stuck in a state where it does not start up.

[0043] For example, when the ambient temperature of the circuit device 100 is low, the forward voltage of the body diode BDP increases, causing the boot voltage VBT = VDD - VBD to decrease during startup. Also, when the ambient temperature of the circuit device 100 is low, the threshold voltage of the P-type MOS transistor TAP of the pre-driver 130 increases, raising the minimum operating voltage of the pre-driver 130. As a result, the above-mentioned stuck state is more likely to occur, especially at low temperatures.

[0044] In the aforementioned Patent Document 1, only a Schottky barrier diode is used in the bootstrap circuit. In this case, even during normal operation after startup, the boot capacitor is charged via the Schottky barrier diode, resulting in losses due to the forward voltage of the Schottky barrier diode. Such losses reduce the power efficiency of the switching power supply. For example, when the power supplied to the load is small, the proportion of losses to power consumption becomes large, and if the losses are large, the power efficiency may decrease significantly. In the comparative examples in Figures 4 to 6, during normal operation after startup, the boot capacitor 210 is charged via the turned-on P-type MOS transistor TRP, thus reducing losses and improving power efficiency compared to Patent Document 1. However, the aforementioned locking problem occurs during startup. According to this embodiment in Figures 1 to 3, during startup, the boot capacitor 210 is charged via the Schottky barrier diode SBD, and during normal operation after startup, the boot capacitor 210 is charged via the turned-on P-type MOS transistor TRP. This solves both the locking problem during startup and the loss problem during normal operation.

[0045] In this embodiment, the circuit device 100 switches and controls the output driver 110 of a switching power supply 200 that generates an output voltage VOUT from a power supply voltage VDD, which is a first N-type MOS transistor TQ1. The circuit device 100 includes a pre-driver 130 that drives the gate of the first N-type MOS transistor TQ1, and a bootstrap circuit 160 that generates a boot voltage VBT of the pre-driver 130 from the power supply voltage VDD. The first N-type MOS transistor TQ1 is provided between the power supply node NVDD, which is supplied with the power supply voltage VDD, and the switch node NSWQ. A boot capacitor 210 is provided between the switch node NSWQ and the boot node NVBT, which supplies the boot voltage VBT to the pre-driver 130. The bootstrap circuit 160 includes a P-type MOS transistor TRP and a Schottky barrier diode SBD, which are provided between the power supply node NVDD and the boot node NVBT. The anode of the Schottky barrier diode SBD is connected to the power supply node NVDD, and the cathode is connected to the boot node NVBT.

[0046] According to this embodiment, the boot capacitor 210 is charged via a Schottky barrier diode (SBD) during startup, and during normal operation after startup, the boot capacitor 210 is charged via an ON P-type MOS transistor (TRP). As a result, as described above, the stuck state in which the switching power supply 200 does not start operating is avoided during startup, and the power efficiency of the switching power supply 200 can be improved by reducing losses in the bootstrap circuit 160 during normal operation.

[0047] In this embodiment, the output driver 110 may also include a second N-type MOS transistor TQ2. The second N-type MOS transistor TQ2 is provided between the switch node NSWQ and the ground node NGND, and may be exclusively turned on with the first N-type MOS transistor TQ1. The P-type MOS transistor TRP may be turned on when the second N-type MOS transistor TQ2 is turned on.

[0048] When the 2N-type MOS transistor TQ2 is in the on state, the boost capacitor 210 is charged. According to the present embodiment, when the 2N-type MOS transistor TQ2 is in the on state, the P-type MOS transistor TRP is in the on state, so the boost capacitor 210 is charged through the on-state P-type MOS transistor TRP. Thereby, during normal operation, the loss in the bootstrap circuit 160 can be reduced.

[0049] Also, in the present embodiment, the power supply voltage may be VDD, the forward voltage of the Schottky barrier diode may be VSBD, and the minimum operating voltage of the pre-driver 130 may be Vmin. At this time, it may be VDD - VSBD > Vmin.

[0050] As described in FIG. 3 and the like, the boost voltage VBT at startup is VDD - VSBD, and when VDD - VSBD < Vmin, there is a possibility of getting stuck. According to the present embodiment, since VDD - VSBD > Vmin, the stuck state at startup can be avoided.

[0051] Note that the minimum operating voltage is the lowest power supply voltage of the pre-driver 130 at which the pre-driver 130 can operate considering variations. The variations include variations due to individual variations of the circuit device 100 or environmental variations. The environmental variations are variations in temperature or the power supply voltage VDD, etc.

[0052] Also, in the present embodiment, the forward voltage VSBD of the Schottky barrier diode SBD may be lower than the forward voltage VBD of the body diode BDP of the P-type MOS transistor TRP.

[0053] According to this embodiment, by providing a Schottky barrier diode SBD in parallel with the P-type MOS transistor TRP, the boot capacitor 210 can be charged via the Schottky barrier diode SBD during startup. Furthermore, since the forward voltage VSBD of the Schottky barrier diode SBD is lower than the forward voltage VBD of the body diode BDP, it is easier to avoid a jammed state compared to when charging via the body diode BDP.

[0054] In this embodiment, the back gate of the P-type MOS transistor TRP may be connected to the boot node NVBT.

[0055] In this embodiment, the anode of the body diode BDP of the P-type MOS transistor TRP is connected to the power node NVDD, and the cathode is connected to the boot node NVBT. During startup, when the difference between the power supply voltage VDD and the boot voltage VBT is greater than the forward voltage VBD of the body diode BDP, the boot capacitor 210 is charged via the body diode BDP and the Schottky barrier diode SBD. When the difference between the power supply voltage VDD and the boot voltage VBT is greater than the forward voltage VBD of the body diode BDP and less than the forward voltage VSBD of the Schottky barrier diode SBD, the boot capacitor 210 is charged via the Schottky barrier diode SBD.

[0056] 2. Layout example Figure 7 shows an example of the layout of the circuit device 100. The direction opposite to the first direction DR1 is the second direction DR2, the direction perpendicular to the first direction DR1 is the third direction DR3, and the direction opposite to the third direction DR3 is the fourth direction DR4. The circuit device 100 is an integrated circuit device, and Figure 7 shows a plan view of its semiconductor substrate. Two intersecting edges of the semiconductor substrate are designated as the first edge HN1 and the second edge HN2. The first edge HN1 is the edge along the first direction DR1, and the second edge HN2 is the edge along the third direction DR3. Note that the arrangement relationship of each circuit with respect to the edges is just an example and is not limited to this.

[0057] Hereinafter, "a circuit is arranged" means that the area on which the circuit elements constituting that circuit are arranged is arranged on the semiconductor substrate. The area is the area that encloses the circuit elements constituting the circuit, and for example, if the circuit is surrounded by a guard bar, it may be the area defined by that guard bar, etc. "Circuit A is arranged on the first direction side of circuit B" is not limited to the case where circuits A and B are arranged along the first direction, but also includes the case where circuits A and B are not arranged along the first direction, but circuit A is on the first direction DR1 side of circuit B. The same applies to other directions. "Terminal" here refers to a pad arranged on the semiconductor substrate.

[0058] The output driver 110 is positioned on the first direction DR1 side of the boot terminal TBT. More specifically, the output driver 110 is positioned near the boot terminal TBT, adjacent to the boot terminal TBT on the first direction DR1 side. For example, the output driver 110 is positioned near the corner where the first side HN1 and the second side HN2 intersect. A switch terminal TSWQ is positioned within the positioning area of ​​the output driver 110. Figure 7 shows an example in which four switch terminals TSWQ are positioned along the first direction DR1, but the number of switch terminals TSWQ can be arbitrary.

[0059] The P-type MOS transistor TRP and Schottky barrier diode SBD of the bootstrap circuit 160 are located on the second direction DR2 side of the boot terminal TBT and are positioned adjacent to the third direction DR3. Figure 7 shows an example where the Schottky barrier diode SBD is positioned in the third direction DR3 of the P-type MOS transistor TRP, but the P-type MOS transistor TRP may also be positioned in the third direction DR3 of the Schottky barrier diode SBD.

[0060] The power terminal TVDD is located on the third direction DR3 side of the boot terminal TBT. Figure 7 shows an example where three power terminals TVDD are arranged along the first side HN1, but the number of power terminals TVDD can be arbitrary.

[0061] The pre-driver 130 is positioned on the second direction DR2 side of the P-type MOS transistor TRP and the Schottky barrier diode SBD. More specifically, the pre-driver 130 is positioned in the vicinity of the P-type MOS transistor TRP and the Schottky barrier diode SBD, adjacent to them on the second direction DR2 side.

[0062] The P-type MOS transistor TRP and Schottky barrier diode SBD are positioned closer to the boot terminal TBT than the switching control circuit 150. Figure 7 shows an example where the switching control circuit 150 is positioned on the second direction DR2 side of the pre-driver 130. In this example, the P-type MOS transistor TRP, Schottky barrier diode SBD, and switching control circuit 150 are positioned in the second direction DR2 side from the boot terminal TBT. However, the position of the switching control circuit 150 is not limited to Figure 7. For example, the P-type MOS transistor TRP and Schottky barrier diode SBD only need to be positioned closer to the boot terminal TBT than at least the logic circuits among the circuits included in the switching control circuit 150. Alternatively, the switching control circuit 150 may be positioned on the fourth direction DR4 side of the P-type MOS transistor TRP and Schottky barrier diode SBD.

[0063] The ground terminal TGND is positioned, for example, along the second side HN2. Figure 7 shows an example where three ground terminals TGND are positioned along the second side HN2, but the number of ground terminals TGND can be arbitrary. The position of the ground terminal TGND can be arbitrary, but from the viewpoint of reducing the wiring parasitic resistance of the output driver 110, it is desirable that the ground terminal TGND be positioned near the output driver 110. Figure 7 shows an example where the ground terminal TGND is positioned near the output driver 110, on the first direction DR1 side and the fourth direction DR4 side.

[0064] In this embodiment, the circuit device 100 includes a boot terminal TBT connected to the boot node NVBT. The output driver 110 is positioned on the first direction DR1 side of the boot terminal TBT. The P-type MOS transistor TRP and Schottky barrier diode SBD are positioned on the second direction DR2 side of the boot terminal TBT, when the direction opposite to the first direction DR1 is defined as the second direction DR2.

[0065] In this embodiment, the output driver 110 and the P-type MOS transistor TRP and Schottky barrier diode SBD are arranged in different directions relative to the boot terminal TBT. This allows the boot terminal TBT and the P-type MOS transistor TRP and Schottky barrier diode SBD to be placed close together. As a result, the wiring length between the boot terminal TBT and the P-type MOS transistor TRP and Schottky barrier diode SBD is shortened, thereby reducing losses due to wiring resistance when charging the boot capacitor 210.

[0066] In this embodiment, the circuit device 100 may also include a power terminal TVDD connected to the power node NVDD. The power terminal TVDD may be located on the third direction DR3 side of the boot terminal TBT, where the direction perpendicular to the first direction DR1 is defined as the third direction DR3.

[0067] According to this embodiment, the output driver 110, the P-type MOS transistor TRP and Schottky barrier diode SBD, and the power supply terminal TVDD are arranged in different directions relative to the boot terminal TBT. This allows the boot terminal TBT, the P-type MOS transistor TRP and Schottky barrier diode SBD, and the power supply terminal TVDD to be placed close together. In other words, the P-type MOS transistor TRP and Schottky barrier diode SBD can be placed close together to the power supply terminal TVDD. As a result, the wiring length between the power supply terminal TVDD and the P-type MOS transistor TRP and Schottky barrier diode SBD is shortened, thereby reducing losses due to wiring resistance when charging the boot capacitor 210.

[0068] In this embodiment, the pre-driver 130 may be arranged adjacent to the P-type MOS transistor TRP and the Schottky barrier diode SBD on the second direction DR2 side.

[0069] As described above, the boot terminal TBT and the P-type MOS transistor TRP and Schottky barrier diode SBD can be placed close together. The pre-driver 130 is then positioned adjacent to the P-type MOS transistor TRP and Schottky barrier diode SBD on the second direction DR2 side. This allows the boot terminal TBT and the pre-driver 130 to be placed close together. As a result, the wiring length between the boot terminal TBT and the pre-driver 130 is shortened, reducing losses due to wiring resistance when current flows from the boot capacitor 210 to the pre-driver 130.

[0070] In this embodiment, the circuit device 100 may also include a switching control circuit 150 that controls the pre-driver 130. The P-type MOS transistor TRP and Schottky barrier diode SBD may be positioned closer to the boot terminal TBT than the logic circuits included in the switching control circuit 150.

[0071] According to this embodiment, the boot terminal TBT, the P-type MOS transistor TRP, and the Schottky barrier diode SBD can be placed close together. Furthermore, by separating the logic circuit of the switching control circuit 150 from the boot terminal TBT, the logic circuit becomes less susceptible to noise generated by the operation of the bootstrap circuit 160.

[0072] In this embodiment, the P-type MOS transistor TRP and the Schottky barrier diode SBD may be arranged adjacent to each other along the third direction DR3, when the direction orthogonal to the first direction DR1 is defined as the third direction DR3.

[0073] According to this embodiment, the P-type MOS transistor TRP and the Schottky barrier diode SBD are arranged on the second direction DR2 side of the boot terminal TBT and adjacent to each other along the third direction DR3. This makes it possible to reduce the distance between the boot terminal TBT and the P-type MOS transistor TRP, and the distance between the boot terminal TBT and the Schottky barrier diode SBD.

[0074] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of the output driver, pre-driver, bootstrap circuit, circuit device, external circuit, and switching power supply, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of Symbols]

[0075] 100...Circuit device, 110...Output driver, 130,140...Pre-driver, 150...Switching control circuit, 160...Bootstrap circuit, 200...Switching power supply, 210...Boot capacitor, 250...Inductor, 260...Capacitor, 290...Load, BDP...Body diode, DR1...First direction, DR2...Second direction, DR3...Third direction, DR4...Fourth direction, GND...Ground voltage, NGND...Ground node, NHDR...Drive node, NOUT...Output node, NSWQ...Switch node, NVBT...Boot node, NVDD...Power node, SWQ...Switch voltage, TBT...Boot terminal, TGND...Ground terminal, TQ1...First N-type MOS transistor, TQ2...Second N-type MOS transistor, TRP...P-type MOS transistor, TSWQ...Switch terminal, TVDD...Power terminal, VBT...Boot voltage, VDD...Power supply voltage, VOUT...Output voltage, SBD...Schottky barrier diode

Claims

1. A circuit device for switching control of a first N-type MOS transistor in the output driver of a switching power supply that generates an output voltage from a power supply voltage, A pre-driver for driving the gate of the first N-type MOS transistor, which is provided between the power supply node and the switch node to which the power supply voltage is supplied, A bootstrap circuit that generates the boot voltage of the pre-driver from the power supply voltage, Includes, A boot capacitor is provided between the switch node and the boot node that supplies the boot voltage to the pre-driver. The bootstrap circuit described above is A P-type MOS transistor is provided between the power supply node and the boot node, A Schottky barrier diode whose anode is connected to the power supply node and whose cathode is connected to the boot node, A circuit device characterized by including the following.

2. In the circuit device described in claim 1, The aforementioned output driver is A second N-type MOS transistor is provided between the switch node and the ground node and is exclusively turned on with the first N-type MOS transistor, The aforementioned P-type MOS transistor is A circuit device characterized in that it turns on when the second N-type MOS transistor is in the ON state.

3. In the circuit device described in claim 1, A circuit device characterized in that, when the power supply voltage is VDD, the forward voltage of the Schottky barrier diode is VSBD, and the minimum operating voltage of the pre-driver is Vmin, VDD - VSBD > Vmin.

4. In the circuit device described in claim 1, The forward voltage of the Schottky barrier diode is A circuit device characterized by having a voltage lower than the forward voltage of the body diode of the P-type MOS transistor.

5. In the circuit device described in claim 1, The back gate of the aforementioned P-type MOS transistor is A circuit device characterized by being connected to the boot node.

6. In the circuit device described in claim 1, Includes a boot terminal connected to the boot node, The aforementioned output driver is The boot terminal is located on the first direction side, The P-type MOS transistor and the Schottky barrier diode are, A circuit device characterized in that, when the direction opposite to the first direction is defined as the second direction, the boot terminal is positioned on the side of the second direction.

7. In the circuit device described in claim 6, Includes a power terminal connected to the aforementioned power node, The aforementioned power terminals are A circuit device characterized in that, when the direction perpendicular to the first direction is defined as the third direction, the boot terminal is positioned on the side of the third direction.

8. In the circuit device described in claim 6, The aforementioned pre-driver is A circuit device characterized in that the P-type MOS transistor and the Schottky barrier diode are arranged adjacent to each other on the second direction side.

9. In the circuit device described in claim 6, Includes a switching control circuit for controlling the pre-driver, The P-type MOS transistor and the Schottky barrier diode are, A circuit device characterized by being positioned closer to the boot terminal than the logic circuits included in the switching control circuit.

10. In the circuit device described in claim 6, The P-type MOS transistor and the Schottky barrier diode are, A circuit device characterized by being arranged adjacent to each other along the third direction, where the direction perpendicular to the first direction is defined as the third direction.

11. A circuit device according to any one of claims 1 to 10, The output driver and, The aforementioned boot capacitor, An inductor is provided between the switch node and the output node from which the output voltage is output, A switching power supply device characterized by including the following.

Images