Semiconductor devices and semiconductor memory devices

Abstract

The present invention provides a semiconductor device and a semiconductor memory device that can suppress the interfacial resistance between electrodes and channels. [Solution] The semiconductor device of the embodiment comprises a channel containing an oxide semiconductor and an electrode in contact with the channel. The electrode of the semiconductor device of the embodiment contains a conductive oxide containing a first element, which is an alkaline earth metal element, and a second element, which is a transition metal element, as cations.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and semiconductor memory devices. [Background technology]

[0002] A semiconductor device is known that comprises a transistor element with a channel made of an oxide semiconductor (In-Ga-Zn-O: IGZO) between a source and drain made of indium tin oxide (ITO). In recent years, with the scaling down of oxide semiconductor RAM (Oxide Semiconductor-Random Access Memory), securing on-current has become a challenge. To secure on-current, it is necessary to reduce the interfacial resistance between the electrodes and the channel. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-035171 [Patent Document 2] Japanese Patent Publication No. 2023-179982 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, in a combination of an electrode made of ITO and a channel made of IGZO, a Schottky barrier may be formed at the interface between ITO and IGZO. This causes increased resistance between the electrode and channel layers. The semiconductor memory device of this embodiment was made to solve this problem, and aims to provide a semiconductor device and a semiconductor memory device that can suppress the interfacial resistance between the electrode and channel. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a channel containing an oxide semiconductor and an electrode in contact with the channel. The electrode of the semiconductor device of the embodiment contains a conductive oxide containing a first element, which is an alkaline earth metal element, and a second element, which is a transition metal element, as cations. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing a cross-section of the semiconductor device according to the embodiment. [Figure 2] This diagram illustrates the required properties for the electrode material in the semiconductor device of the embodiment. [Figure 3] This diagram illustrates the required properties for the electrode material in the semiconductor device of the embodiment. [Figure 4] This figure shows a perovskite-type crystal structure applicable to the electrode material of the semiconductor device according to the embodiment. [Figure 5] This figure shows a crystal structure applicable to the electrode material of the semiconductor device according to the embodiment. [Figure 6] This figure illustrates the crystal structure and work function applicable to the electrode material of the semiconductor device according to the embodiment. [Figure 7] This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to an embodiment. [Figure 8] This is a schematic cross-sectional diagram illustrating an example of the structure of a memory cell array in an embodiment. [Figure 9] This is a block diagram showing an example configuration of a semiconductor memory device according to the embodiment. [Modes for carrying out the invention]

[0007] (Configuration of the embodiment) The semiconductor device of the embodiment will be described below with reference to the drawings. In the embodiment, substantially identical components are denoted by the same reference numerals, and their descriptions may be partially omitted. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each part, etc., may differ from those of reality.

[0008] Figure 1 is a cross-sectional view showing the basic configuration of a semiconductor device of an embodiment. The semiconductor device 1 of the embodiment is, for example, a semiconductor memory. The semiconductor device 1 shown in Figure 1 has a source electrode 15a and a drain electrode 15b, an insulating layer 16 disposed between the source electrode 15a and the drain electrode 15b, a channel 17 whose both ends are joined to the source electrode 15a and the drain electrode 15b, and a gate electrode 18 disposed near the channel 17 between the source electrode 15a and the drain electrode 15b.

[0009] The source electrode 15a, drain electrode 15b, and gate electrode 18 are electrodes corresponding to the source, drain, and gate of the transistor element formed by the semiconductor element 1. The source electrode 15a and drain electrode 15b are made of conductive oxide. The gate electrode 18 is made of, for example, a metal, a metal compound, or a semiconductor. The insulating layer 16 is made of, for example, silicon dioxide (SiO2). The channel 17 contains an oxide semiconductor. An example of the oxide semiconductor for the channel 17 is In-Ga-Zn-O (IGZO), which consists of indium, gallium, zinc, and oxygen. The source electrode 15a, drain electrode 15b, channel 17, and gate electrode 18 can constitute a memory transistor.

[0010] Here, the electrode materials forming the source electrode 15a and the drain electrode 15b will be described. It is preferable that these electrode materials do not form a Schottky barrier at the junction interface when bonded to the channel 17 containing an oxide semiconductor.

[0011] (Work function of electrodes) When joining an electrode made of ITO and a channel made of IGZO, a Schottky barrier can be formed. This is due to the work function of the electrode and the electron affinity of the channel being very close values. Due to factors such as the atomic arrangement and composition of the interface, the effective magnitude relationship between the two is likely to change, leading to the formation of a Schottky barrier. The Schottky barrier formed at the joining interface acts to increase the electrical resistance. To suppress the formation of the Schottky barrier, as the electrode material, an electrode material having a work function sufficiently lower than the electron affinity (about 4.5 eV) of the IGZO forming the channel 17 is selected.

[0012] Figures 2 and 3 are diagrams for explaining the characteristics required for the electrode material in the semiconductor device of the embodiment.

[0013] As shown in FIG. 2, when the work function φ of the electrode M is greater than the electron affinity χ of the semiconductor S when the electrode and the semiconductor are laminated and brought into contact, a Schottky barrier is formed at the interface. This acts to increase the resistance at the interface between the electrode and the semiconductor.

[0014] On the other hand, as shown in FIG. 3, when the work function φ of the electrode M is less than the electron affinity χ of the semiconductor S when the electrode and the semiconductor are brought into contact, the interface becomes an ohmic junction and a Schottky barrier is not formed. Therefore, in order to suppress the electrical resistance related to the electrode-semiconductor interface, it is preferable to select an electrode material with a small work function φ of the electrode. M

[0015] (Perovskite crystal) Generally, metals with a low work function have unstable properties. However, among oxides with a perovskite crystal structure, there are materials having a small work function and stable properties. FIG. 4 is a diagram showing an example of a perovskite crystal structure applicable to the electrode material of the semiconductor device of the embodiment.

[0016] A perovskite crystal structure is a structure in which three different atoms or ions are arranged in a specific positional relationship within a cubic lattice. Figure 4 shows an example of the oxide ABO3, in which atom A is located at the corner of the cube, atom B is at the center of the cube, and oxygen atoms are located at the center of the faces of the cube. In the structure shown in Figure 4, atom A (cation A) is slightly larger and has 12 coordination, while atom B (cation B) has 6 coordination. A structure with such a 1:1:3 composition ratio is called an ABX3 type perovskite structure.

[0017] Perovskite oxide materials exhibit a low work function and metallic properties by, for example, assigning a specific cation such as strontium to the position of atom A. Therefore, by using perovskite oxide materials for the source electrode 15a and drain electrode 15b, it is possible to realize electrodes that do not generate a barrier at the interface. Since perovskite oxides are oxides, it is also possible to suppress the effect of heat resistance (the phenomenon of extracting oxygen from IGZO).

[0018] Figure 5 shows a crystal structure applicable to the electrode material of the semiconductor device according to the embodiment. The structure shown in Figure 5 is an example in which atom A is strontium and atom B is molybdenum (cubic-SrMoO3). Figure 6 is a diagram illustrating the crystal structure and work function applicable to the electrode material of the semiconductor device according to the embodiment. Figure 6 shows the work function of the perovskite oxide with the structure shown in Figure 5, calculated based on density functional theory.

[0019] As shown in Figure 6, the work function on the low-index plane of the perovskite oxide with the structure shown in Figure 5 ranged from 1.5 to 4.2 eV. These values ​​are smaller than the electron affinity of the IGZO forming the channel 17 (approximately 4.5 eV) in all orientations (planes), and thus the formation of an interface barrier can be suppressed. In other words, it can be said to be suitable as an electrode material for the source electrode 15a and the drain electrode 15b.

[0020] (Selection of cations in perovskite oxides) The tolerance factor t is known as an indicator of the stability and distortion of a crystal structure. The tolerance factor t is a dimensionless number calculated from the ratio of ionic radii and is given by the following equation 1.

[0021]

number

[0022] Therefore, the tolerance factor t was calculated using alkaline earth metals as atom A and transition metals as atom B. As a result, when magnesium, calcium, strontium, and barium were selected as atom A, and vanadium, niobium, tantalum, chromium, molybdenum, tungsten, titanium, zirconium, and hafnium were selected as atom B, the tolerance factor t ranged from 0.76 to 1.084. Furthermore, for titanium, zirconium, and hafnium, which are transition metals of Group 4, vanadium, niobium, and tantalum, which are transition metals of Group 5, or chromium, molybdenum, and tungsten, which are transition metals of Group 6, were added (doped). In other words, these combinations constitute a cubic perovskite structure, and it is expected that an ohmic bond will be formed when bonded to a channel made of IGZO.

[0023] Thus, as the electrode material in the semiconductor device of the embodiment, it is preferable to select a perovskite oxide of general formula: ABO3, in which atom A is an alkaline earth metal and atom B is a transition metal of group 5 or group 6, or a transition metal of group 4 doped with a transition metal element of group 5 or group 6 to form an n+ metal.

[0024] (Semiconductor devices as memory devices) Next, a semiconductor memory device having a semiconductor device 1 according to an embodiment will be described with reference to Figures 1, 7, and 8. Figure 7 is a circuit diagram illustrating an example of the circuit configuration of a memory cell array 2 as a semiconductor memory device according to an embodiment. Figure 7 shows a plurality of memory cells MC, a plurality of word lines WL (word line WLn, word line WLn+1, word line WLn+2, where n is an integer), a plurality of bit lines BL (bit line BLm, bit line BLm+1, bit line BLm+2, where m is an integer), and a power line VPL.

[0025] Multiple memory cells MC are arranged in a matrix direction to form a memory cell array 2. Each memory cell MC comprises a memory transistor MTR, which is a field-effect transistor (FET), and a memory capacitor MCP. The memory transistor MTR corresponds to the semiconductor device 1 of the embodiment. The gate (gate electrode 18) of the memory transistor MTR is connected to the corresponding word line WL, and either the source (source electrode 15a) or the drain (drain electrode 15b) is connected to the corresponding bit line BL. The word line WL is connected to, for example, a row decoder. The bit line BL is connected to, for example, a sense amplifier. The first electrode of the memory capacitor MCP is connected to the other of the source or drain of the memory transistor MTR, and the second electrode is connected to a power line VPL that supplies a specific potential. The power line VPL is connected to, for example, a power supply circuit. The memory cell MC can store data by accumulating charge in the memory capacitor MCP from the bit line BL through switching of the memory transistor MTR by the word line WL. The memory cell MC can also read data based on the charge accumulated in the memory capacitor MCP to the bit line BL through switching of the memory transistor MTR by the word line WL. The number of memory cells (MCs) is not limited to the number shown in Figure 7.

[0026] Figure 8 is a schematic cross-sectional diagram illustrating an example of the structure of a memory cell array 2. Figure 8 shows a portion of the XZ cross-section, which consists of the X, Y, and Z axes that are perpendicular to each other. As shown in Figure 8, the memory cell array 2 comprises a conductor 21, a conductive layer 22, an electrical conductor 23, an insulator 24, a conductive layer 31, a conductive oxide layer 32, an oxide semiconductor layer 41, a conductive layer 42, an insulating film 43, a conductive oxide layer 51, a conductive layer 52, and a conductive layer 71.

[0027] As shown in Figure 8, the memory transistor (MTR) and memory capacitor (MCP) are provided above the insulating layer (11) on the semiconductor substrate (10). Peripheral circuits such as a low decoder, sense amplifier, and power supply circuit are formed on the semiconductor substrate (10). The peripheral circuits include field-effect transistors, such as P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs). Field-effect transistors can be formed using a semiconductor substrate (10) such as a single-crystal silicon substrate, and Pch-FETs and Nch-FETs have a channel region, a source region, and a drain region on the semiconductor substrate (10). The semiconductor substrate (10) may have a P-type conductivity. The insulating layer (11) is provided on the semiconductor substrate (10) and includes, for example, silicon (Si) and oxygen (O) or nitrogen (N). The insulating layer (11) may be a multilayer film.

[0028] The conductor 21, the conductive layer 22, the electrical conductor 23, and the insulator 24 form a memory capacitor MCP. The memory capacitor MCP is a three-dimensional capacitor, such as a pillar-type capacitor or a cylinder-type capacitor.

[0029] The conductor 21 is provided above the semiconductor substrate 10, with the insulating layer 11 in between. The conductive layer 22 is provided on a portion of the conductor 21. The conductor 21 and the conductive layer 22 form the second electrode of the memory capacitor MCP. The conductor 21 extends so as to overlap with a plurality of electrical conductors 23 when viewed from the Z-axis direction. The conductor 21 is also called a plate electrode. The electrical conductor 23 is provided above the conductor 21, with the insulator 24 in between, extends in the Z-axis direction, and forms the first electrode of the memory capacitor MCP. The insulator 24 is provided between the conductor 21 and the conductive layer 22 and the electrical conductor 23, and forms the dielectric of the memory capacitor MCP.

[0030] The conductor 21 and the conductive layer 22 include materials such as tungsten and titanium nitride. The electrical conductor 23 includes materials such as tungsten, titanium nitride, and amorphous silicon. The insulator 24 includes materials such as hafnium oxide, zirconium oxide, and aluminum oxide.

[0031] The conductive layer 31 is provided on the electrical conductor 23 and is electrically connected to the electrical conductor 23. The conductive layer 31 contains, for example, copper. Note that the conductive layer 31 is not necessarily required to be formed.

[0032] The conductive oxide layer 32 is provided on the conductive layer 31. The conductive oxide layer 32 contains the conductive oxide of the embodiment.

[0033] The conductive layer 31 and the conductive oxide layer 32 form a conductor 30. Multiple conductors 30 are provided for multiple electrical conductors 23. An insulating layer 33 is formed between the multiple conductors 30. The insulating layer 33 includes, for example, silicon and oxygen or nitrogen.

[0034] The oxide semiconductor layer 41, the conductive layer 42, and the insulating film 43 form a memory transistor MTR. The memory transistor MTR is, for example, an N-channel field effect transistor. The memory transistor MTR is provided above the memory capacitor MCP. A plurality of memory transistors MTR are provided corresponding to a plurality of memory capacitors MCP. An insulating layer 44 and an insulating layer 45 are formed between the plurality of memory transistors MTR. The insulating layer 44 and the insulating layer 45 contain, for example, silicon and oxygen or nitrogen.

[0035] The oxide semiconductor layer 41 is, for example, a columnar body extending in the Z-axis direction. The oxide semiconductor layer 41 penetrates the conductive layer 42 in the Z-axis direction. The oxide semiconductor layer 41 forms a channel (channel 17 in the semiconductor device 1 of the embodiment) of the memory transistor MTR. The oxide semiconductor layer 41 contains, for example, indium (In). The oxide semiconductor layer 41 contains, for example, indium oxide and gallium oxide, indium oxide and zinc oxide, or indium oxide and tin oxide. As an example, it contains an oxide containing indium, gallium, and zinc (indium-gallium-zinc-oxide), so-called IGZO (InGaZnO).

[0036] One end of the oxide semiconductor layer 41 in the Z-axis direction is connected to the conductive layer 31 via the conductive oxide layer 32 and functions as the other source or drain of the memory transistor MTR. The conductive oxide layer 32 is provided between the electric conductor 23 of the memory capacitor MCP and the oxide semiconductor layer 41 of the memory transistor MTR and functions as the other source electrode 15a or drain electrode 15b of the memory transistor MTR.

[0037] The work function φ of the conductive oxide layer 32 is the same as that of the semiconductor device of the embodiment. M is the electron affinity χ of the oxide semiconductor layer 41. SA material with a smaller relationship can be selected. That is, as the material for the conductive oxide layer 32, a perovskite oxide of general formula: ABO3 can be selected in which atom A is an alkaline earth metal and atom B is a transition metal of group 5 or group 6, or a transition metal of group 4 doped with a transition metal element of group 5 or group 6 to form an n+ metal. This reduces the connection resistance between the memory transistor MTR and the memory capacitor MCP.

[0038] The conductive layer 42 includes a portion facing the oxide semiconductor layer 41 in the X-Y plane, with the insulating film 43 in between. The conductive layer 42 forms the gate electrode 18 of the memory transistor MTR and also forms the word line WL as wiring. The conductive layer 42 includes, for example, a metal, a metal compound, or a semiconductor. The conductive layer 42 includes, for example, at least one material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0039] Multiple conductive layers 42 extend in the X-axis direction and are arranged parallel to each other. Each conductive layer 42 overlaps and connects to multiple memory cells MC in the X-axis direction.

[0040] The insulating film 43 is provided between the oxide semiconductor layer 41 and the conductive layer 42 in the X-Y plane. The insulating film 43 forms the gate insulating film of the memory transistor MTR. The insulating film 43 includes, for example, silicon and oxygen or nitrogen. The insulating film 43 may be a laminated film of multiple insulating films.

[0041] The memory transistor (MTR) is a so-called Surrounding Gate Transistor (SGT), in which the gate electrode 18 is arranged to surround the channel 17. The SGT allows for a reduction in the area of ​​the semiconductor device.

[0042] A field-effect transistor having a channel layer containing an oxide semiconductor has a lower off-leak current than a field-effect transistor provided on a semiconductor substrate 10. Therefore, for example, data held in a memory cell MC can be retained for a longer period, thus reducing the number of refresh operations. In addition, since a field-effect transistor having a channel layer containing an oxide semiconductor can be formed using a low-temperature process, thermal stress on the memory capacitor MCP can be suppressed.

[0043] The conductive oxide layer 51 is provided on the oxide semiconductor layer 41. The conductive oxide layer 51 contains the conductive oxide of the embodiment.

[0044] The conductive layer 52 is provided on the conductive oxide layer 51 and is electrically connected to the conductive oxide layer 51. The conductive layer 52 contains, for example, copper.

[0045] The conductive oxide layer 51 and the conductive layer 52 form a conductor 50. The conductor 50 is electrically connected to the sense amplifier via a bit line BL. The conductor 50 functions as a conductive pad for connecting, for example, a memory transistor MTR to the bit line BL. Multiple conductors 50 are provided to correspond to multiple memory transistors MTR. An insulating layer 53 is formed between the multiple conductors 50. The insulating layer 53 includes, for example, silicon and oxygen or nitrogen.

[0046] The other end of the oxide semiconductor layer 41 in the Z-axis direction is connected to the conductive layer 52 via the conductive oxide layer 51 and functions as either the source or the drain of the memory transistor MTR. The conductive oxide layer 51 functions as either the source electrode 15a or the drain electrode 15b of the memory transistor MTR.

[0047] The conductive oxide layer 51 has a work function φ M The electron affinity χ of the oxide semiconductor layer 41 SA material with a smaller relationship can be selected. That is, as the material for the conductive oxide layer 51, a perovskite oxide of general formula: ABO3 can be selected in which atom A is an alkaline earth metal and atom B is a transition metal of group 5 or group 6, or a transition metal of group 4 doped with a transition metal element of group 5 or group 6 to form an n+ metal. This reduces the connection resistance between the memory transistor MTR and the memory capacitor MCP.

[0048] The conductive layer 71 is provided on the conductive layer 52 and connected to the conductor 50. The conductive layer 71 forms bit lines BL as wiring. An insulating layer 72 is formed between the multiple conductive layers 71. The insulating layer 72 includes, for example, silicon and oxygen or nitrogen.

[0049] Multiple memory cells (MCs) may form a staggered arrangement in the XY plane. A memory cell MC connected to one of multiple word lines (WLs) is positioned offset in the X-axis direction relative to memory cell MCs connected to adjacent word lines (WLs). This increases the integration density of memory cells (MCs).

[0050] Figure 9 is a block diagram showing an example configuration of a semiconductor memory device. The memory device 100 includes a memory cell array 110, a load driver 111, a column driver 112, a write circuit 113, a read circuit 114, a voltage generation circuit 115, and a control circuit 116. The memory cell array 110 includes the semiconductor memory device of the embodiment described above.

[0051] The low driver 111 controls multiple rows of the memory cell array 110. The low driver 111 receives a low address signal from the control circuit 116 based on the decoding result of an externally input address signal ADR. The low driver 111 sets the word line WL of the row selected by the low address signal to a selected state. The low driver 111 includes circuits such as a multiplexer (word line selection circuit) and a word line driver.

[0052] The column driver 112 controls multiple columns of the memory cell array 110. The column driver 112 receives a column address signal from the control circuit 116 based on the decoding result of the address signal ADR. The column driver 112 sets the bit line BL of the column selected by the column address signal to the selected state. The column driver 112 includes circuits such as a multiplexer (bit line selection circuit) and a bit line driver.

[0053] The writing circuit 113 performs various controls for the data writing operation. The writing circuit 113 receives a data signal DT input from an external source. During the writing operation, the writing circuit 113 supplies a write pulse formed by current and / or voltage to the memory cell array 110. This allows data to be written to the memory cell MC. The writing circuit 113 is electrically connected to the memory cell array 110 via the load driver 111. The writing circuit 113 includes circuits such as a voltage source and / or a current source, a pulse generation circuit, and a latch circuit.

[0054] The read circuit 114 performs various controls for the data read operation. During the read operation, the read circuit 114 supplies a read pulse (e.g., read voltage) to the memory cell array 110. The read circuit 114 senses the potential or current value of the bit line BL. Based on this sensing result, data in the memory cell MC can be read. The read circuit 114 transfers the read data signal to the outside. The read circuit 114 is connected to the memory cell array 110 via the column driver 112. The read circuit 114 includes circuits such as a voltage source and / or a current source, a pulse generation circuit, a latch circuit, and a sense amplifier circuit.

[0055] The write circuit 113 and the read circuit 114 are not limited to being independent circuits. For example, the write circuit 113 and the read circuit 114 may have common components that can be used together and may be arranged in the storage device 100 as a single integrated circuit.

[0056] The voltage generation circuit 115 uses an externally supplied power supply voltage to generate voltages for various operations of the memory cell array 110. The voltage generation circuit 115 supplies the generated voltages to the load driver 111, the column driver 112, the write circuit 113, and the read circuit 114, respectively.

[0057] The control circuit 116 includes, for example, a command register and an address register. Based on, for example, an externally input command signal CMD, an address signal ADR, and a control signal CNT, the control circuit 116 controls the load driver 111, a column driver 112, a write circuit 113, a read circuit 114, and a voltage generation circuit 115 to perform operations such as read operations, write operations, and erase operations.

[0058] The command signal CMD is a signal indicating the operation that the storage device 100 should perform. For example, the address signal ADR is a signal indicating the coordinates of one or more memory cells MC (called selected cells) to be operated on within the memory cell array 110. The address signal ADR includes the low address signal and column address signal of the memory cell MC. The control signal CNT is a signal for controlling, for example, the operation timing between the storage device 100 and an external device and the operation timing within the storage device 100.

[0059] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0060] 1... Semiconductor device, 15a... Source electrode, 15b... Drain electrode, 16... Insulating layer, 17... Channel, 18... Electrode gate 2…Memory cell array, 10…Semiconductor substrate, 11…Insulating layer, 21…Conductor, 22…Conductive layer, 23…Electrical conductor, 24…Insulator, 30…Conductor, 31…Conductive layer, 32…Conductive oxide layer, 33…Insulating layer, 41…Oxide semiconductor layer, 42…Conductive layer, 43…Insulating film, 44…Insulating layer, 45…Insulating layer, 50…Conductor, 51…Conductive oxide layer, 52…Conductive layer, 53…Insulating layer, 71…Conductive layer, 72…Insulating layer 100...Memory device, 110...Memory cell array, 111...Row driver, 112...Column driver, 113...Write circuit, 114...Read circuit, 115...Voltage generation circuit, 116...Control circuit

Claims

1. A semiconductor device comprising a channel containing an oxide semiconductor and an electrode in contact with the channel, The electrode comprises a conductive oxide containing a first element, which is an alkaline earth metal element, and a second element, which is a transition metal element, as cations in a semiconductor device.

2. The semiconductor device according to claim 1, wherein the composition ratio of the first element, the second element, and oxygen in the conductive oxide is 1:1:

3.

3. The semiconductor device according to claim 1, wherein the conductive oxide has a propskite-type crystal structure.

4. The aforementioned conductive oxide is General form: ABO ３ Here, A is the first element, B is the second element, A semiconductor device according to claim 1, having a composition represented by the above.

5. The semiconductor device according to claim 1, wherein the second element is at least one element selected from the group of transition line metal elements belonging to Group 4, Group 5, and Group 6.

6. The first element is at least one alkaline earth metal element selected from the group consisting of magnesium, calcium, strontium, and barium. The semiconductor device according to claim 1, wherein the second element is at least one transition metal element selected from the group consisting of vanadium, niobium, tantalum, chromium, molybdenum, tungsten, titanium, zirconium, and hafnium.

7. The semiconductor device according to claim 6, wherein the second element comprises at least one transition metal element selected from the group consisting of titanium, zirconium, and hafnium, and at least one transition metal element selected from the group consisting of vanadium, niobium, tantalum, chromium, molybdenum, and tungsten.

8. A semiconductor memory device comprising a channel containing an oxide semiconductor, an electrode in contact with the channel, and a capacitor electrically connected to the electrode, The electrode contains a conductive oxide comprising a first element, which is an alkaline earth metal element, and a second element, which is a transition metal element, as cations. Semiconductor memory device.

9. The semiconductor memory device according to claim 8, wherein the composition ratio of the first element, the second element, and oxygen in the conductive oxide is 1:1:

3.

10. The semiconductor memory device according to claim 8, wherein the conductive oxide has a propskite-type crystal structure.

11. The aforementioned conductive oxide is General form: ABO ３ Here, A is the first element, B is the second element, A semiconductor memory device according to claim 8, having a composition represented by the above.

12. The semiconductor memory device according to claim 8, wherein the second element is at least one element selected from the group of transition line metal elements belonging to Group 4, Group 5, and Group 6.

13. The first element is at least one alkaline earth metal element selected from the group consisting of magnesium, calcium, strontium, and barium. The semiconductor memory device according to claim 8, wherein the second element is at least one transition metal element selected from the group consisting of vanadium, niobium, tantalum, chromium, molybdenum, tungsten, titanium, zirconium, and hafnium.

14. The semiconductor memory device according to claim 13, wherein the second element comprises at least one transition metal element selected from the group consisting of titanium, zirconium, and hafnium, and at least one transition metal element selected from the group consisting of vanadium, niobium, tantalum, chromium, molybdenum, and tungsten.

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