Method and apparatus for power supply through a package substrate with a stack of glass layers having different coefficients of thermal expansion

Abstract

Systems, apparatus, products, and methods for supplying power through a package substrate comprising a stack of glass layers having different coefficients of thermal expansion are disclosed. [Solution] An exemplary substrate for an integrated circuit package comprises: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE being different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between the inner wall of the first hole and the conductive material.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are often connected to larger circuit boards, such as motherboards and other types of printed circuit boards (PCBs), via a package substrate. As the size of IC chips and / or dies decreases and the interconnect density increases, alternatives to conventional substrate layers have been developed to provide stable transmission of high-frequency data signals between different circuits and / or an increase in power supply. One option being pursued is the implementation of a package substrate with a glass core. Generally, glass core implementation provides a number of advantages, including a higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation, compared to implementation with a conventional epoxy core.

Brief Description of the Drawings

[0002] [Figure 1] An exemplary integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown.

[0003] [Figure 2A] An exemplary substrate core that can be used to implement the exemplary substrate core of FIG. 1 is shown.

[0004] [Figure 2B] Another exemplary substrate core that can be used to implement the exemplary substrate core of FIG. 1 is shown.

[0005] [Figure 3] Different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2A are shown. [[ID= [Figure 4] Different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2A are shown. [Figure 5] Different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2A are shown. [Figure 6]Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 7] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 8] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 9] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 10] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 11] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 12] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 13] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 14] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 15] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 16] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 17] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core. [Figure 18] Figure 2A shows different stages in an exemplary manufacturing process for producing the exemplary substrate core.

[0006] [Figure 19]Shows different stages in another exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2A. [Figure 20] Shows different stages in another exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2A.

[0007] [Figure 21] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B. [Figure 22] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B. [Figure 23] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B. [Figure 24] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B. [Figure 25] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B. [Figure 26] Shows different stages in an exemplary manufacturing process for manufacturing the exemplary substrate core of FIG. 2B.

[0008] [Figure 27A] Shows another exemplary substrate core that can be used to implement the exemplary substrate core of FIG. 1.

[0009] [Figure 27B] Shows another exemplary substrate core that can be used to implement the exemplary substrate core of FIG. 1.

[0010] [Figure 28] Shows another exemplary substrate core that can be used to implement the exemplary substrate core of FIG. 1.

[0011] [Figure 29]Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 30] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 31] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 32] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 33] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 34] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 35] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 36] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 37] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 38] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 39] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 40] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 41] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 42] Figure 28 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core.

[0012] [Figure 43] Another exemplary substrate core that could be used to mount the exemplary substrate core in Figure 1 is shown.

[0013] [Figure 44] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 45] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 46] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 47] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 48] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core. [Figure 49] Figure 43 shows different stages in an exemplary manufacturing process for producing an exemplary substrate core.

[0014] [Figure 50] This flowchart illustrates an exemplary method that may be performed to manufacture one of the exemplary package substrate cores shown in Figures 1-49. [Figure 51] This flowchart illustrates an exemplary method that may be performed to manufacture one of the exemplary package substrate cores shown in Figures 1-49. [Figure 52] This flowchart illustrates an exemplary method that may be performed to manufacture one of the exemplary package substrate cores shown in Figures 1-49.

[0015] [Figure 53] This is a top view of a wafer containing a die that may be included in an IC package constructed according to the teachings disclosed herein.

[0016] [Figure 54] This is a side cross-sectional view of an IC device that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0017] [Figure 55] This is a side cross-sectional view of an IC device assembly which may include an IC package constructed in accordance with the teachings disclosed herein.

[0018] [Figure 56] This is a block diagram of an exemplary electrical device, which may include an IC package constructed in accordance with the teachings disclosed herein.

[0019] Generally, the same reference number is used throughout the drawings and accompanying specifications to refer to the same or similar parts. The drawings are not necessarily to exact scale. Instead, the thickness of layers or areas may be enlarged in the drawings. Layers and areas with clear lines and boundaries are shown in the drawings, but some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be invisible, blended, and / or irregular. [Modes for carrying out the invention]

[0020] Figure 1 illustrates an exemplary integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contact pads or lands 104 on the mounting surface 105 of the package (e.g., the bottom surface). In some examples, the IC package 100 may include balls, pins, and / or pads in addition to, or instead of, the contact pads 104, to enable the electrical coupling of the package 100 to the circuit board 102. In this example, the package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (sometimes also referred to as chips or chipsets) mounted on a package substrate 110 and surrounded by a package lid or mold compound 112. Thus, the package substrate 110 is an exemplary means for supporting the semiconductor dies. The exemplary IC package 100 in Figure 1 includes two dies 106, 108, but in other examples, the package 100 may have only one die or more than two dies. In some examples, one of the dies 106, 108 (or isolated dies) is incorporated into the package substrate 110. Dies 106, 108 can provide any preferred type of function (e.g., data processing, memory storage, etc.).

[0021] As shown in the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the substrate 110 via a corresponding array of interconnects 114. In Figure 1, the interconnects are shown as bumps. However, the interconnects 114 may be any other type of electrical connection (e.g., balls, pins, pads, wire bonding, etc.) in addition to or instead of the bumps shown. The electrical connection between the dies 106, 108 and the substrate 110 (e.g., interconnect 114) is sometimes referred to as a first-level interconnect. In contrast, the electrical connection between the IC package 100 and the circuit board 102 (e.g., pad 104) is sometimes referred to as a second-level interconnect. In some examples, one or both of the dies 106, 108 may be stacked on top of one or more other dies and / or interposers. In such an example, dies 106, 108 may be coupled to a lower die and / or interposer through a first set of first-level interconnects, and the lower die and / or interposer may be connected to the package substrate 110 through a separate set of first-level interconnects associated with the lower die and / or interposer. Thus, as used herein, a first-level interconnect refers to an interconnect between a die and a package substrate, or between a die and a lower die and / or interposer (e.g., balls, bumps, pins, pads, wire bonding, etc.).

[0022] As shown in Figure 1, the interconnect 114 of the first level interconnect includes two different types of bumps corresponding to core bumps 116 and bridge bumps 118. As used herein, core bumps 116 are bumps on dies 106, 108 through which electrical signals pass between dies 106, 108 and external components of the IC package 100. More specifically, as shown in the illustrated example, when dies 106, 108 are mounted on the package substrate 110, core bumps 116 are physically connected and electrically coupled to contact pads 120 on the internal surface 122 of the substrate 110. The contact pads 120 on the internal surface 122 of the package substrate 110 are electrically coupled to landing pads 104 on the bottom (external) surface 105 of the substrate 110 (e.g., the surface opposite the internal surface 122) via an internal interconnect 124 within the substrate 110. As a result, between the core bumps 116 of dies 106 and 108 and the landing pads 104 mounted on the circuit board 102, there is a continuous electrical signal path passing through contact pads 120 and an interconnect 124 provided between them.

[0023] As used herein, a bridge bump 118 is a bump on dies 106, 108 that an electrical signal passes through when passing between different dies 106, 108 within a package 100. Thus, as shown in the illustrated example, the bridge bump 118 of the first die 106 is electrically coupled to the bridge bump 118 of the second die 108 via a silicon-based interconnect die 126 (e.g., interconnect bridge) incorporated into the package substrate 110. As shown in Figure 1, the core bump 116 is typically larger than the bridge bump 118. In some examples, the interconnect bridge 126 and its associated bridge bump 118 are omitted.

[0024] In some examples, the underfill material 119 is placed between the dies 106, 108 and the package substrate 110, around and / or between the first level interconnect 114 (for example, around and / or between the core bump 116 and / or bridge bump 118). In the illustrated example, only the first die 106 is associated with the underfill material 119. However, in other examples, both dies 106 and 108 are associated with the underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, the mold compound 112 is used as the underfill material surrounding the first level interconnect 114.

[0025] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, which are located on the bottom (external) surface 105 and / or the top (internal) surface 122 of the package substrate 110.

[0026] In Figure 1, the substrate 110 of an exemplary IC package 100 includes a substrate core 128 (e.g., main core, overall core) between two separate build-up regions 130 (e.g., build-up layer, redistribution layer). As shown in the illustrated example, the substrate core 128 includes a plurality of different types of glass cores 132, 134, 136 (e.g., subcore, glass substrate, glass layer, glass sheet) stacked on top of each other. In some examples, the cores 132, 134, 136 include at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, cores 132, 134, and 136 contain one or more additives, including aluminum oxide (Al2O3), boron trioxide (B2O3), magnesia oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, cores 132, 134, and 136 contain silicon and oxygen. In some examples, cores 132, 134, and 136 contain silicon, oxygen, and / or one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, glass cores 132, 134, and 136 are separate layers of glass containing silicon, oxygen, and aluminum. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.In some examples, as will be further explained below, the different glass cores 132, 134, and 136 contain different materials or materials of different compositions, and as a result, the different glass cores 132, 134, and 136 are associated with different coefficients of thermal expansion (CTE). In some examples, the CTE is modified among the different glass cores 132, 134, and 136 by changing the amount of alkali dopant (e.g., Na2O, K2O, etc.) contained in the glass. Generally, the lower the alkali content, the lower the CTE. Thus, for a CTE of 3 ppm / °C, the alkali content may be less than 0.1%. In contrast, for a CTE of 9 ppm / °C, the alkali content may be up to 20%.

[0027] In some examples, cores 132, 134, and 136 are amorphous solid glass layers. In some examples, cores 132, 134, and 136 are glass layers that do not contain organic adhesives or organic materials. In some examples, cores 132, 134, and 136 are solid glass layers having a rectangular shape in plan view. In some examples, cores 132, 134, and 136 as glass substrates contain at least one glass layer, do not contain epoxy, and do not contain glass fibers (e.g., do not contain an epoxy prepreg layer with glass cloth). In some examples, cores 132, 134, and 136 correspond to a single piece of glass extending across the overall height / thickness of each corresponding core.

[0028] In some examples, cores 132, 134, and 136 have a rectangular shape with substantially the same extent in plan view, with layers above and / or below the core. In some examples, cores 132, 134, and 136 have a thickness ranging from about 25 micrometers (μm) to about 400 μm (the overall thickness of substrate core 128 ranges from about 50 μm to about 1.4 millimeters (mm)). In some examples, cores 132, 134, and 136 may have dimensions ranging from about 10 mm to about 250 mm on each side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, cores 132, 134, and 136 correspond to a rectangular volume in which sections (e.g., vias) are removed and filled with other material (e.g., metal).

[0029] In Figure 1, the build-up region 130 is represented as a mass / block through which the internal interconnect 124 extends linearly through the build-up region 130 (and the glass cores 132, 134, 136). However, Figure 1 is simplified for clarity and illustrative purposes. In reality, interconnects are not necessarily linear. More specifically, in some examples, the build-up region 130 is defined by alternating layers of dielectric material and layers of conductive material (e.g., metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnect 124, which is represented in a simplified form by straight lines as shown in Figure 1. In some examples, the metal layers are patterned to define electrical routing or conductive traces that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through the intervening dielectric layers. Furthermore, electrical routing or traces on either side of the substrate core 128 may be electrically coupled by through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass cores 132, 134, and 136.

[0030] In particular, glass cores are advantageous over epoxy-based cores because glass is harder and therefore provides greater mechanical support or strength to the package substrate. Thus, the substrate core 128, and more specifically, the individual glass cores 132, 134, and 136, are exemplary means for reinforcing the package substrate. In addition to the mechanical advantages, glass cores also offer other features, including higher plated through-hole (PTH) density, lower signal loss, and lower overall thickness variation. However, glass cores also present challenges due to the brittle (e.g., fragile) nature of glass and the potential for defects that can cause cracks to propagate through the glass.

[0031] A common type of glass core fracture known to exist is called seware fracture. Seware fracture results in the separation of the glass core along a crack that propagates from the edge of the glass core along its length and width between the main outer surfaces of the glass core (e.g., the top and bottom surfaces, the front and back surfaces). In other words, seware fracture is characterized by the glass core splitting into two separate pieces of glass along a line that generally extends parallel to the main plane of the glass core.

[0032] Factors contributing to back cracking failure include internal stress induced by a mismatch in the coefficients of thermal expansion (CTE) between the glass core (e.g., CTE of approximately 3 ppm / °C to 10 ppm / °C) and the materials in the build-up region (e.g., approximately 39 ppm / °C for the organic dielectric layer, approximately 17 ppm / °C for copper, and approximately 2.6 ppm / °C for silicon) during the thermal cycling of the package substrate 110, and defects at the edges of the glass core resulting from fragmentation. More specifically, package substrates such as the package substrate 110 in Figure 1 are often manufactured on large panels that are subsequently fragmented or cut into individual units using a saw. Thus, in the illustrated example in Figure 1, the package substrate 110, including the substrate core 128 (and associated subcores 132, 134, 136) and the build-up region 130, includes the opposite edge 138 created by cutting with a saw. Cutting with such a saw can result in defects at the edges of the glass core (e.g., edges 138 of glass cores 132, 134, and 136 in Figure 1), which can cause cracks to propagate laterally beyond the middle of the glass core, potentially splitting the glass core into two or more pieces. Such crack formation and propagation are exacerbated by temperature fluctuations and stresses induced by the difference in CTE between the glass core and the build-up region. Generally, the material in the build-up region 130 has a higher CTE than the glass. As a result, the material in the build-up region 130 expands and contracts more than the glass core in response to thermal fluctuations, thereby creating internal stresses within the glass core that can promote crack propagation.

[0033] Examples disclosed herein reduce (minimize) concerns about back cracking by mounting the substrate core 128 using multiple different types (e.g., disaggregated) glass cores 132, 134, 136 stacked on each other's tops as shown in Figure 1. More specifically, in the examples disclosed herein, the different stacked cores 132, 134, 136 are mounted by different materials (or different compositions of the same material) associated with different CTEs. In some examples, glass cores closer to the build-up region 130 are manufactured with a CTE closer to the CTE of the build-up region 130 than glass cores further away from the build-up region 130 (e.g., closer to the middle of the stack of glass cores). In this manner, the substrate core 128 is defined by a gradient or gradual change in CTE (between each stacked glass core 132, 134, 136) that provides transitions between different layers in the package substrate 110 to reduce stress at any given location. Therefore, in some examples, the intermediate glass core 134 has a lower CTE than the top glass core 132 and a lower CTE than the bottom glass core 136. In some examples, the CTEs of the top glass core 132 and the bottom glass core 136 are identical. Therefore, in some examples, the different CTEs of the glass cores 132, 134, and 136 are symmetrical across the entire thickness of the substrate core 128. That is, the arrangement or order of the stack of glass cores 132, 134, and 136, and their associated CTEs, define a symmetrical sequence of CTEs from the bottom glass core (e.g., the third glass core 136) to the top glass core (e.g., the first glass core 132). In other examples, the different CTEs may not be symmetrical. For example, in some cases, the top glass core 132 (e.g., the glass core closest to dies 106 and 108) has the highest CTE in the stack (e.g., about 7 ppm / °C to 9 ppm / °C), the bottom glass core 136 (e.g., the glass core furthest from dies 106 and 108) has the lowest CTE (e.g., about 3 ppm / °C to 5 ppm / °C), and the middle glass core 134 has a CTE somewhere between the other two (e.g., about 5 ppm / °C to 7 ppm / °C).In other examples, the top glass core 132 (e.g., the glass core closest to dies 106, 108) has the lowest CTE in the stack, and the bottom glass core 136 has the highest CTE in the stack. In some examples, when there are more than three glass cores, the CTE of each core is more precisely tuned than in the above examples to provide a gradual change in CTE value between each consecutive glass core in the stack corresponding to any preferred CTE gradient. That is, any preferred sequence of different CTE values ​​across any preferred number of stacked glass cores can be implemented, additionally or alternatively, to achieve any preferred CTE gradient across the overall substrate core 128.

[0034] In addition to reducing stress by mounting multiple glass cores with different CTEs, in some examples, a buffer material 140 (e.g., adhesive material) is placed between adjacent glass cores 132, 134, and 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity and absorbs the stress resulting from the different CTEs and thermal fluctuations of the different glass cores 132, 134, and 136, thereby further reducing the stress inside the substrate core 128. In some examples, the buffer material is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the buffer material is an inorganic dielectric material (e.g., silicon dioxide (SiO₂)). x ), silicon nitride (SiN x )) In some examples, the buffer material comprises carbon-doped oxide (CDO). In some examples, one or more layers of the buffer material 140 may be omitted so that different of the glass cores 132, 134, and 136 are in direct contact. In some examples, the layers of the buffer material 140 comprise a conductive material that facilitates the rewiring of electrical paths between the glass cores 132, 134, and 136. Thus, the material between the glass cores is also referred to herein as a rewiring material that defines one or more rewiring layers in the package substrate 100.

[0035] In the exemplary substrate core 128 in Figure 1, three different glass cores 132, 134, and 136 are shown, but any other suitable number of glass cores may be mounted with corresponding CTEs, defining a specific CTE gradient across the entire thickness of the substrate core 128. Thus, in some examples, only two glass cores, each with a different CTE, are used. In other examples, more than three glass cores are used. In some such examples, each glass core is different from all other glass cores in the core stack. In other examples, two or more of the glass cores may have the same CTE (e.g., made from the same material with the same composition), and at least one glass core has a different CTE from the others.

[0036] In the illustrated example in Figure 1, the glass cores 132, 134, and 136 are shown as having the same thickness. However, in some examples, the thicknesses of the glass cores 132, 134, and 136 may differ from one another. For example, in some examples, the intermediate glass core 134 is thicker than the top glass core 132 and thicker than the bottom glass core 136. In other examples, the intermediate glass core 134 is thinner than the top glass core 132 and thinner than the bottom glass core 136. Any preferred thickness of the glass core can be implemented to achieve a suitable CTE gradient that reduces stress to mitigate back cracking failure while also providing sufficient rigidity for the package substrate.

[0037] A stack of multiple glass cores 132, 134, and 136 with different CTEs disclosed herein may function to reduce stresses that could otherwise lead to back splitting failure. However, a stack of glass cores 132, 134, and 136 also presents challenges in the manufacturing of portions of interconnect 124 extending through the glass cores 132, 134, and 136. Examples disclosed herein overcome some of these challenges. More specifically, the following description and associated figures disclose exemplary structures and associated manufacturing processes for implementing electrical wiring for power supply (e.g., coaxial magnetic inductor loops (CMILs) and plated magnetic vias (PMVs)) through a stack of glass cores 132, 134, and 136. As used herein, CMILs and PMVs are different types of power supply interconnects.

[0038] Figure 2A shows an exemplary substrate core 200 that may be used to mount the exemplary substrate core 128 of Figure 1. Similar to Figure 1, the substrate core 200 of Figure 2A includes a first glass core 202, a second glass core 204, and a third glass core 206 that are stacked on top of each other. In this example, the different glass cores 202, 204, and 206 correspond to the glass cores 132, 134, and 136 of Figure 1. Thus, the glass cores 202, 204, and 206 have different CTEs as described above. For example, in some examples, the second glass core 204 (e.g., an intermediate glass core) has a lower CTE than either the first glass core 202 or the third glass core 206. In this example, each of the glass cores 202, 204, and 206 has approximately the same thickness. In some examples, the thickness is about 350 micrometers (μm). In other examples, the thickness may be greater than or less than 350 μm. Furthermore, in some examples, different glass cores 202, 204, and 206 may have different thicknesses. Additionally, while three glass cores are shown, in some examples, any other suitable number of glass cores (e.g., 2, 4, 5, 6, 7, etc.) may be used. In such examples, a stack of glass cores may define any suitable CTE gradient based on the CTE differences for each glass core in the stack. In some examples, the CTE gradient is symmetrical across the entire thickness of the substrate core 200. In other examples, the CTE gradient may not be symmetrical.

[0039] In the illustrated example, the different glass cores 202, 204, and 206 are separated by an intervening layer of dielectric material 208 (e.g., buffering material, adhesive material). In some examples, the dielectric material 208 includes an organic epoxy-based dielectric. However, any other suitable dielectric may be used additionally or alternatively. In this example, in addition to being between the glass cores 202, 204, and 206, the dielectric material 208 is on the outermost surface of the outermost glass core (e.g., the first and third glass cores 202, 206). Thus, in this example, the dielectric material 208 defines the first and second outer surfaces 210, 212 of the overall substrate core 200. However, in some examples, the outermost layer of dielectric material 208 shown in Figure 2A may be omitted and / or may correspond to the first layer of a build-up region on either side of the substrate core 200 (e.g., build-up region 130 in Figure 1). In such an example, the outer surfaces of the first and third glass cores 202 and 206 define the first and second outer surfaces 210 and 212 of the overall substrate core 200.

[0040] In the illustrated example in Figure 2A, the CMIL 214 (e.g., power supply interconnect) extends through the substrate core 200 between the first and second outer surfaces 210, 212. The CMIL 214 functions to enhance power supply through the package substrate (e.g., package substrate 110 in Figure 1) including the substrate core 200. As shown in Figure 2A, the CMIL 214 extends continuously through the first opening 216 (e.g., first cavity) in the first glass core 202, the second opening 218 (e.g., second cavity) in the second glass core 204, and the third opening 220 (e.g., third cavity) in the third glass core 206. In this example, the dielectric material 208 also extends through the openings 216, 218, and 220 in the different glass cores 202, 204, and 206. The CMIL 214, defined by two plated through-holes extending through the dielectric material 208 (and through openings 216, 218, 220 in the glass cores 202, 204, 206), includes first and second portions 222, 224 extending through adjacent through-holes in the dielectric material 208. In this example, each of the first and second portions 222, 224 of the CMIL 214 includes a non-magnetic plug 226 (e.g., a non-magnetic core) that defines the central region of each portion 222, 224, which is surrounded by a conductive material 228 that itself is surrounded by a magnetic material 230 (e.g., a magnetic lining). In some examples, the non-magnetic plug 226 includes a dielectric material (e.g., epoxy). In some examples, the conductive material 228 includes copper. In other examples, any other suitable conductive material may be used. In some examples, the magnetic material 230 is any suitable material with magnetic properties (e.g., iron, iron-containing alloys (e.g., silicon steel), ferrite materials (e.g., nickel-zinc ferrite (e.g., Ni a Zn (1-a) Fe2O4), manganese ferrite (e.g., Mn a Zn (1-a) This could be Fe2O4, cobalt ferrite (e.g., CoFe2O4, CoO·Fe2O3), other ferromagnetic particles or elements, etc.

[0041] In the illustrated example in Figure 2A, the first and second portions of the CMIL 214 are capped onto the first outer surface 210 of the substrate core 200, each accompanied by first and second conductive pads 232 and 234, respectively. In this example, the conductive pads 232 and 234 contain the same material as the conductive material 228 (e.g., copper) extending along the axial length of the two portions of the CMIL 214. Furthermore, as shown in Figure 2A, the first and second portions of the CMIL 214 are electrically coupled along the second outer surface 212 of the substrate core 200 by conductive pads 236 (e.g., traces, wires).

[0042] In addition to the CMIL 214 extending through the large openings 216, 218, and 220 in the glass cores 202, 204, and 206, the glass cores 202, 204, and 206 also include through-glass vias (TGVs) 238 that are electrically coupled by an additional conductive material 240 extending through an intervening layer of dielectric material 208. In some examples, the TGVs 238 are plated with the same material used in the additional conductive material 240 (e.g., copper). In some examples, at least some of the additional conductive material 240 may be made of a different material from the TGVs 238. Furthermore, as shown in the illustrated example, conductive pads 242 are located on the outer surfaces 210, 212 of the substrate core 200 and are electrically coupled to the TGVs 238 and the additional conductive material 240. In this example, the conductive pads 242 define the opposite end of an interconnect that extends across the entire thickness of the substrate core 200 (e.g., portion of interconnect 124 in Figure 1).

[0043] Figure 2B shows another exemplary substrate core 244 that may be used to mount the exemplary substrate core 128 of Figure 1. The exemplary substrate core 244 of Figure 2B is substantially identical to the exemplary substrate core 200 of Figure 2A, except that it is described below and / or otherwise evident from the context. Accordingly, features shown in Figure 2B that are identical or similar to the corresponding features in Figure 2A are identified by the same reference number. Furthermore, the description of such features described above in relation to Figure 2A applies similarly with respect to the corresponding features in Figure 2B. Specifically, the exemplary substrate core 244 includes first, second, and third glass cores 202, 204, and 206 containing TGV 238 extending through it. The glass cores 202, 204, and 206 are separated by intercalation layers of dielectric material 208 deposited on opposite surfaces of each of the glass cores 202, 204, and 206. Therefore, the outermost layer of the dielectric material 208 defines the first and second outer surfaces 210 and 212 of the substrate core 244. Furthermore, the dielectric material 208 extends through corresponding openings 216, 218, and 220 that pass through the glass cores 202, 204, and 206. The openings 216, 218, and 220 provide space for the exemplary CMIL 246 to extend through the substrate core 244.

[0044] Figure 2B differs from Figure 2A in that different glass cores 202, 204, and 206 are stacked together, resulting in a difference in how different segments of CMIL 246 are bonded together. Specifically, in this example, the adhesive dielectric 248 is located between adjacent portions of the dielectric material 208 on the facing surfaces of adjacent glass cores 202, 204, and 206. In this example, the adhesive dielectric 248 (e.g., buffer material) is a different material from the dielectric material 208. More specifically, in some examples, the adhesive dielectric 248 is mounted by a material having a lower modulus of elasticity than the dielectric material 208, providing greater stress reduction between the glass cores 202, 204, and 206 compared to the exemplary substrate core 200 in Figure 2A, where the adhesive dielectric 248 is omitted. In other examples, the adhesive dielectric 248 may be the same material as the dielectric material 208.

[0045] In the illustrated example of Figure 2B, the adhesive dielectric 248 is also positioned between adjacent ends of different segments of the CMIL 246. Thus, unlike in Figure 2A, the non-magnetic plug 226, conductive material 228, and magnetic material 230 in the separate first and second parts 250, 252 of the CMIL 246 do not extend continuously along the entire length of the CMIL 246. Rather, as shown in Figure 2B, the non-magnetic plug 226, conductive material 228, and magnetic material 230 are divided into separate segments spaced apart from each other. However, in this example, the different segments of the conductive material 228 are still electrically coupled together by conductive vias 254 extending through the adhesive dielectric 248. Furthermore, similar conductive vias 256 extend through the adhesive dielectric 248 and are electrically coupled to the TGV 238 extending through the glass cores 202, 204, and 206. In some examples, conductive vias 254 and 256 contain the same material as conductive material 228 in CMIL 246 and TGV 238 (e.g., plated copper). In other examples, conductive vias 254 and 256 contain different conductive materials (e.g., sintered copper paste, liquid metal (e.g., gallium-based alloy)).

[0046] Figures 3–18 show different stages in an exemplary manufacturing process for producing the exemplary substrate core 200 of Figure 2A. Figure 3 represents a glass panel 300 corresponding to one of the initial states of the glass cores 202, 204, and 206. For illustrative purposes, the glass panel 300 is shown and described as corresponding to the second glass core 204 (e.g., the intermediate glass core in the substrate core 200 of Figure 2A). In some examples, the glass panel 300 is manufactured to a thickness corresponding to the final thickness of the glass core 204. However, in some examples, the glass panel 300 is initially made slightly thicker than the final thickness of the glass core 204, allowing some amount of glass to be removed during the subsequent polishing or planarization process, as will be further described below.

[0047] Figure 4 illustrates the manufacturing stage after the glass core 204 has been exposed to a laser as part of a laser-induced deep etching (LIDE) process. The laser is focused on defined regions 402 of the glass core 204 to modify the optical and chemical properties of the glass core 204 in those regions 402. Figure 5 illustrates the manufacturing stage following a chemical etching process to remove material from the modified regions 402 of the glass core 204 shown in Figure 3 to define the larger second aperture 218 shown in Figure 2A, and an additional aperture 502 (e.g., via) for the TGV 238 shown in Figure 2A. In this example, the apertures 218, 502 generally have a cross-sectional profile corresponding to an hourglass shape, with narrower aperture widths (e.g., diameters) near the midpoint of the apertures between the opposite first and second surfaces 504, 506 of the glass core 204. In other examples, one or more of the apertures 218, 502 may have different cross-sectional shapes. For example, in some cases, one or more of the openings 218, 502 may have a generally conical or tapered shape, with a minimum width (e.g., diameter) on one of the two surfaces 504, 506 of the glass core 204 and a maximum width (e.g., diameter) on the opposite surface 504, 506. In other cases, the width (e.g., diameter) of one or more of the openings 218, 502 is approximately consistent along the entire length of the openings 218, 502 between the opposite surfaces 506, 508 of the glass core 204.

[0048] Figure 6 shows a manufacturing stage after the glass core 204 has been attached to the conductive carrier 602. In this example, the conductive carrier includes a conductive layer 604 (e.g., a copper layer) and a release layer 606 (e.g., an adhesive dielectric layer). Figure 7 shows a manufacturing stage after the openings 218 in the glass core 204 have been filled with dielectric material 208. In some examples, the dielectric material 208 is distributed to the openings as a liquid or paste and then cured. In some examples, any excess dielectric material 208 extending beyond the first surface 504 of the glass core 204 is removed by a polishing process (e.g., chemical mechanical planarization (CMP)). In some examples, this polishing process slightly thins the glass core 204.

[0049] Figure 8 illustrates the manufacturing stage following the application of a mask 802 (e.g., via photolithography) that covers the assembly except for the opening 502 in the glass core. Furthermore, the manufacturing stage shown in Figure 8 is after an etching process (e.g., plasma etching, dry etching) to remove the portion of the release layer 606 exposed within the opening 502 in the glass core 204, thereby exposing the underlying conductive layer 604. The mask 802 protects the dielectric material 208 during the etching process.

[0050] Figure 9 illustrates the manufacturing stage after the mask 802 has been removed (e.g., stripped) and subsequently plated with copper within the opening 502 to define the TGV238 extending through the glass core 204. In this example, the TGV238 is plated from the exposed portion of the conductive layer 604 upwards. Therefore, in this example, no seed layer is deposited along the walls of the opening 502 before the plating process. However, in other examples, a seed layer may be used to facilitate the plating of the TGV238. In some examples, a low modulus material (e.g., silicon dioxide (SiO₂)) may be used. xA liner (such as carbon-doped oxide (CDO), polyimide, parylene, etc.) may be added to the glass surface before depositing the metal over TGV238 (including any seed layer, if present) to reduce stress. In some examples, the liner extends along the entire length of TGV238. In other examples, the liner extends along a limited portion of TGV238 (e.g., near the ends of TGV238) (e.g., a high-stress area). In some examples, the liner is added before depositing the dielectric material 208 at the second opening 218, so that the liner is between the dielectric material 208 and the glass core 204. In other examples, the liner is omitted. The manufacturing stage shown in Figure 9 is also after a subsequent polishing process (e.g., a CMP process) to remove excess copper extending over the first surface 504 of the glass core 204. Thus, in some examples, both the dielectric material 208 and TGV238 are coplane with the first surface 504.

[0051] Figure 10 shows the manufacturing stage after the conductive carrier 602 has been removed, including both the conductive layer 604 and the release layer 606. In some examples, the second surface 506 of the glass core undergoes a polishing process (e.g., CMP) to make both the dielectric material 208 and TGV 238 flush with the second surface 506. In some examples, the assembly also undergoes a cleaning process to remove any residual material.

[0052] Figure 11 shows the manufacturing stages after applying first and second buffer layers (e.g., adhesive layer, dielectric layer) 1102, 1104 to the first and second surfaces 504, 506 of the glass core 204, respectively. In some examples, the buffer layers 1102, 1104 are applied through a lamination process. In some examples, the buffer layers 1102, 1104 are made of the same material as the dielectric material 208 located in the large second opening 218 of the glass core 204. In other examples, the buffer layers 1102, 1104 are made of a different material from the dielectric material 208 in the second opening 218. Figure 11 also shows the result of adding conductive vias 1106 through the buffer layers 1102, 1104 to electrically couple the underlying TGV 238 to the associated conductive pad 1108. More specifically, holes (e.g., vias) are drilled through buffer layers 1102 and 1104 to expose the ends of TGV238, then the holes are filled to define the material of the conductive via 1106 and generate the conductive pad 1108.

[0053] Figure 12 shows the manufacturing stages after applying additional dielectric layers 1202, 1204 to the first and second buffer layers 1102, 1104, respectively. In some examples, the additional dielectric layers 1202, 1204 are applied through a lamination process. In some examples, the additional dielectric layers 1202, 1204 are made of the same material as the dielectric material 208 located in the large second opening 218, and / or the same material as the buffer layers 1102, 1104. In other examples, the additional dielectric layers 1202, 1204 are made of a different material than the dielectric material 208 in the second opening 218, and / or a different material than the material used for the buffer layers 1102, 1104. Furthermore, in this example, an additional conductive via 1206 is provided through the additional dielectric layers 1202, 1204 and electrically coupled to conductive blankets 1208, 1210 on the outer surfaces on both sides of the assembly. In some examples, conductive material added within and / or on the dielectric material 208 and / or additional dielectric layers 1202, 1204 functions to redistribute signal paths. Thus, the dielectric material 208, the additional dielectric layers 1202, 1204, and the associated conductive material are referred herein, optionally, to redistributing materials defining one or more redistributing layers in the package substrate 200 of Figure 2.

[0054] Figure 13 shows a subsequent manufacturing stage in which the hole 1302 is drilled through the dielectric material 208, buffer layers 1102, 1104, and additional dielectric layers 1202, 1204. Furthermore, in the manufacturing stage shown in Figure 13, the through-hole 1302 is filled with magnetic material 230 used in CMIL 214. In this example, the hole 1302 defines the outer extent of the first and second parts 222, 224 of CMIL 214 shown in Figure 2A. In some examples, the magnetic material 230 is deposited in the hole 1302 as a paste or resin which is then cured. Subsequently, grinding and / or polishing processes (e.g., CMP process) may be utilized on both sides of the assembly to remove excess material.

[0055] Figure 14 illustrates the manufacturing stage after drilling the internal through-hole 1402 through the middle of different parts of the magnetic material 230. Furthermore, in the manufacturing stage represented in Figure 14, the walls of the internal through-hole 1402 (e.g., the inner walls of the magnetic material 230) are plated with the conductive material 228. In some examples, this is achieved through a bottom-up plating process. In other examples, this is achieved by directly plating the magnetic material 230 and / or a seed layer on top of the magnetic material 230.

[0056] As shown in Figure 14, the remaining central region of the internal through-hole 1402 (inside the conductive material 228) is filled with a non-magnetic plug 226. In some examples, the non-magnetic plug 226 is deposited within the central region of the conductive material 228 as a paste or resin that is subsequently cured. A grinding and / or polishing process (e.g., a CMP process) may then be utilized on both sides of the assembly to remove excess material.

[0057] Figure 15 represents a manufacturing stage following a grinding and / or polishing process (e.g., a CMP process) to make the edges of the constructed segments of CMIL 214 flush with the additional dielectric layers 1202, 1204. In some examples, the manufacturing stage represented by Figure 15 corresponds to a complete glass core assembly 1500 at the end of processing of the second glass core 204 before it is stacked with other glass cores 202, 206 (which have been processed to include other segments of CMIL 214). In some examples, the first and third glass cores 202, 206 are processed in a similar manner to the second glass core 204 as outlined above. Thus, Figure 16 represents a complete glass core assembly 1600 after the completion of processing of the first glass core 202, and Figure 17 represents a complete glass core assembly 1700 after the completion of processing of the third glass core 206. As shown, the final result shown in Figure 16 is substantially identical to the final result shown in Figure 15, except that Figure 16 follows an additional operation to provide a conductive pad 1602 on one of the outer surfaces 1604 of the assembly (e.g., the top surface). In this example, the outer surface 1604 corresponds to the first surface 210 of the substrate core 200 in Figure 2A, and the conductive pad 1602 corresponds to the conductive pads 232, 234, and 242 along the first surface 210 of the substrate core 200 in Figure 2A. Similarly, the final result shown in Figure 17 is substantially identical to the final result shown in Figure 15, except that Figure 17 follows an additional operation to provide a conductive pad 1702 on one of the outer surfaces 1704 of the assembly (e.g., the bottom surface). In this example, the outer surface 1704 corresponds to the second surface 212 of the substrate core 200 in Figure 2A, and the conductive pad 1702 corresponds to the conductive pads 236 and 242 along the second surface 212 of the substrate core 200 in Figure 2A.

[0058] Figure 18 illustrates the manufacturing stages when three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the associated glass core assemblies 1500, 1600, and 1700 shown in Figures 15-17. In some examples, an adhesive resin is used to join the different glass core assemblies 1500, 1600, and 1700 together on their boundary surfaces. More specifically, in some examples, the adhesive is a dielectric adhesive applied to areas of dielectric material on the boundary surfaces of the glass core assemblies 1500, 1600, and 1700. In some such examples, a liquid metal or copper paste is deposited between the boundary surface portions defined by conductive material (e.g., via 1206 and conductive material 228 of CMIL 214) to electrically bond the conductive material in the stack. Additionally or alternatively, in some examples, additional conductive pads (similar to the conductive pad 1108 described in relation to Figure 11) may be added to the boundary surfaces of the glass core assemblies 1500, 1600, and 1700 to facilitate the electrical coupling of conductive materials. Furthermore, in some examples, additional non-magnetic plugs 226 and magnetic material 230 may also be placed in corresponding locations to connect the associated portions of the CMIL 214. In other examples, no additional material is added between the boundary surfaces of the glass core assemblies 1500, 1600, and 1700. Instead, the material on the boundary surfaces is directly bonded (e.g., by fusion bonding). Combining or bonding different glass core assemblies 1500, 1600, and 1700 results in the substrate core 200 shown in Figure 2A.

[0059] Figures 19 and 20 show different stages in another exemplary manufacturing process for producing the exemplary substrate core 200 of Figure 2A. In this example, no components of CMIL 214 are added until the glass cores 202, 204, and 206 have already been assembled and stacked together. Specifically, Figure 19 represents a post-manufacturing stage in which three separate glass core assemblies 1902, 1904, and 1906 are assembled or joined together as an assembly. In this example, the glass core assemblies 1902, 1904, and 1906 in Figure 19 are similar to the glass core assembly 1500 in Figure 15, except that they do not include a non-magnetic plug 226, a conductive material 228 surrounding such a non-magnetic plug 226, and a magnetic material 230 surrounding such a conductive material 228. In other words, in some examples, the glass core assemblies 1902, 1904, and 1906 in Figure 19 are manufactured after the same process described above in detail in relation to Figures 3-15, except that the process described in detail in relation to Figures 13 and 14 is omitted.

[0060] After the glass core assemblies 1902, 1904, and 1906 are joined together, through-holes are drilled throughout the entire stack and then filled with magnetic material 230 as shown in Figure 20 (and similar to that described above in relation to Figure 13). Subsequently, internal through-holes are drilled through the magnetic material 230, and following the process described in detail above in relation to Figure 14, room may be made for conductive material 228 and non-magnetic plugs 226. Conductive pads may then be added to both sides of the stack to produce the final substrate core 200 shown in Figure 2A.

[0061] Figures 21–26 show different stages in an exemplary manufacturing process for producing the exemplary substrate core 244 of Figure 2B. The process for producing the exemplary substrate core 244 of Figure 2B may follow the same or similar process described above in relation to the different stages of manufacturing represented by Figures 3–18 described above, except that it is described below and / or that it is otherwise evident from the context. More specifically, the process may be the same or identical up to the stage of manufacturing represented in Figure 10. Figure 21 represents a stage of manufacturing similar to that shown in Figure 11, except that a complete layer of metal 2102 is held on the outer surfaces of the buffer layers 1102, 1104. That is, unlike those described in relation to Figure 11, the conductive pad 1108 is not defined in the stage of manufacturing represented in Figure 21.

[0062] Figure 22 represents a manufacturing stage similar to that shown and described in relation to Figures 13-14 above. That is, the hole 1302 is drilled through the assembly and then filled with magnetic material 230 similar to that in Figure 13. Furthermore, conductive material 228 is plated onto the walls of the internal through-hole 1402 within the magnetic material 230, and then the remaining central region of the internal through-hole 1402 is filled with non-magnetic plug 226. Figure 22 differs from those shown in Figures 13 and 14 in that the additional dielectric layers 1202, 1204 (added in Figure 12) are omitted.

[0063] Figure 23 shows a manufacturing stage after an additional amount of conductive material 228 has been deposited (e.g., plated) and extended across the ends of the constructed segments of CMIL 246. Thus, in this example, the non-magnetic plugs 226 in each segment of CMIL 246 are surrounded by the conductive material 228. Furthermore, as shown in the illustrated example, the thickness of the metal layer 2102 (added in Figure 21) becomes thicker in the manufacturing stage shown in Figure 23 because the additional amount of conductive material 228 has been added.

[0064] Figure 24 illustrates the manufacturing stage after the outer layer of metal has been removed (e.g., via etching) to define the conductive pad 2402 for TGV238 and the constructed segment of CMIL246. The conductive pad 2402 is similar to the conductive pad 1602 described above in relation to Figure 16. However, unlike that shown in Figure 16, in the illustrated example of Figure 24, the conductive pad 2402 is added to both sides of the assembly (e.g., both ends of TGV238 and both ends of the segment of CMIL246).

[0065] Figure 25 shows the manufacturing stage after the adhesive dielectric 248 has been deposited (e.g., laminated), and then perforated and filled to provide conductive vias 254, 256. Figure 25 shows the complete glass core assembly after the processing of the second glass core 204 has been completed and it has been stacked or bonded together with the first and third glass cores 202, 206. In some examples, the first and third glass cores 202, 206 are combined or bonded together to produce corresponding glass core assemblies, and a similar process is described in detail in Figures 22-25 to define the glass core stack shown in Figure 2B.

[0066] Figure 26 illustrates the manufacturing stages when the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining their respective glass core assemblies 2602, 2604, and 2606. In this example, each of the glass core assemblies 2602, 2604, and 2606 in Figure 11 is the result of processing the corresponding glass cores 202, 204, and 206 through the manufacturing stages shown in Figures 3-10 and 22-25. That is, the second glass core 204 processed up to the point shown in Figure 25 corresponds to the second glass core assembly 2604 shown in Figure 26. Furthermore, as shown in Figure 26, the third glass core assembly 2606 is substantially identical to the second glass core assembly 2604, except for a different glass core with a different CTE (e.g., a third glass core 206 instead of the second glass core 204). A further difference between the second glass core assembly 2404 and the third glass core assembly 2406 is the inclusion of an exemplary conductive pad 2608 that electrically couples the corresponding segments of the CMIL 246. The exemplary conductive pad 2608 is similar to the conductive pad 1702 described above in relation to Figure 17. The first glass core assembly 2602 is similar to the other two glass core assemblies 2604 and 2606, except that it does not have a different glass core 202 (with a different CTE) and an adhesive dielectric 248 in which conductive vias 254 are placed. That is, in some examples, the first glass core assembly 2602 in Figure 26 is completed by the manufacturing stages shown in Figure 24 without proceeding to the operations described above in relation to Figure 25. In some examples, once the different glass core assemblies 2602, 2604 and 2606 are assembled together (as shown in Figure 26), the stack is pressed (e.g., subjected to compression) and undergoes a curing process to bond the assemblies. The final result of combining or joining the different glass core assemblies 2602, 2604, and 2606 is the substrate core 244 shown in Figure 2B.

[0067] Figure 27A shows another exemplary substrate core 2700 that may be used to mount the exemplary substrate core 128 of Figure 1. The exemplary substrate core 2700 of Figure 27A is substantially identical to the exemplary substrate core 200 of Figure 2A, except that it is described below and / or otherwise evident from the context. Accordingly, features shown in Figure 27A that are identical or similar to the corresponding features in Figure 2A (and associated Figures 3-18) are identified by the same reference number. Furthermore, the description of such features described above in relation to Figure 2A (and associated Figures 3-18) applies similarly with respect to the corresponding features in Figure 27.

[0068] Figure 27A differs from Figure 2A in the construction of an exemplary CMIL 2702 extending through an exemplary substrate core 2700. Specifically, in Figure 2A, the central region of the two parts 222, 224 of CMIL 214 is defined by a non-magnetic plug 226. In contrast, in the illustrated example of Figure 27A, the first and second parts 2704, 2706 of CMIL 2702 do not have a non-magnetic plug. Instead, the central region of the two parts 2704, 2706 is defined by a conductive material 228 (e.g., copper) that fills the entire space inside the magnetic material 230. That is, the conductive material 228 in the first and second parts 2704, 2706 is a solid mass that extends continuously from the internal surface of the magnetic material 230 to the center of the longitudinal length of parts 2704, 2706 (e.g., the central axis). In other words, in the illustrated example of Figure 27, each portion 2704, 2706 includes a solid metal core that extends continuously across the cross-section of the metal core.

[0069] The process for manufacturing the exemplary substrate core 2700 in Figure 27A may follow the same or similar process detailed above in relation to the different stages of manufacturing represented by Figures 3-18 described above in relation to Figure 2A, except that the non-magnetic plug 226 (described in relation to Figure 14) is omitted. That is, instead of simply plating the walls of the internal through-hole 1402 with conductive material 228 and then filling the remaining central area with non-magnetic plug 226, the entire area within the internal through-hole 1402 is filled with conductive material 228 (e.g., via a plating process), producing the substrate core 2700 of Figure 27A. The subsequent manufacturing process described above in relation to Figures 15-18 may proceed in the same or similar manner described above to produce different glass core assemblies that do not include the non-magnetic plug in the corresponding CMIL 2702 segment. When such glass core assemblies are assembled (in accordance with the process described above in relation to Figure 18, except that the non-magnetic plug is absent), the final result is the exemplary substrate core 2700 of Figure 27A.

[0070] Figure 27B shows another exemplary substrate core 2708 that may be used to mount the exemplary substrate core 128 of Figure 1. The exemplary substrate core 2708 of Figure 27B is substantially identical to the exemplary substrate core 244 of Figure 2B, except that it is described below and / or otherwise evident from the context. Accordingly, features shown in Figure 27B that are identical or similar to the corresponding features in Figure 2B (and associated Figures 3-18) are identified by the same reference number. Furthermore, the descriptions of such features described above in relation to Figure 2B (and associated Figures 3-18) apply similarly with respect to the corresponding features in Figure 27B.

[0071] Figure 27B differs from Figure 2B in the construction of an exemplary CMIL 2710 extending through an exemplary substrate core 2708. Specifically, in Figure 2B, the central region of the two portions 250, 252 of CMIL 214 is defined by a non-magnetic plug 226. In contrast, in the illustrated example of Figure 27B, the first and second portions 2712, 2714 of CMIL 2710 do not have a non-magnetic plug. Instead, the central region of the two portions 2712, 2714 is defined by a conductive material 228 (e.g., copper) that fills the entire space inside the magnetic material 230. That is, the conductive material 228 in the first and second portions 2712, 2714 is a solid mass that extends continuously from the internal surface of the magnetic material 230 to the center of the longitudinal length of portions 2712, 2714 (e.g., the central axis). In other words, in the illustrated example of Figure 27B, each portion 2712, 2714 includes a solid metal core that extends continuously across the cross-section of the metal core.

[0072] The process for manufacturing the exemplary substrate core 2708 in Figure 27B may follow the same or similar process detailed above in relation to the different stages of manufacturing represented by Figures 3-10 and 21-26 described above in relation to Figure 2B, except that the non-magnetic plug 226 (described in relation to Figure 22) is omitted. That is, instead of simply plating the walls of the internal through-hole 1402 with conductive material 228 and then filling the remaining central area with non-magnetic plug 226, the entire area within the internal through-hole 1402 is filled with conductive material 228 (e.g., via a plating process) to produce the substrate core 2708 in Figure 27B. The subsequent manufacturing process described above in relation to Figures 23-26 may proceed in the same or similar manner described above to produce different glass core assemblies that do not include the non-magnetic plug in the corresponding segment of CMIL 2710. When such glass core assemblies are assembled (in accordance with the process described above in relation to Figure 26, except that the non-magnetic plug is absent), the final result is the exemplary substrate core 2708 in Figure 27B.

[0073] Figure 28 shows another exemplary substrate core 2800 that may be used to mount the exemplary substrate core 128 of Figure 1. Features shown in Figure 28 that are identical or similar to the corresponding features in Figures 2A, 2B, 27A, and 27B (and associated Figures 3-18 and 21-26) are identified by the same reference number. Furthermore, the descriptions of such features described above in relation to Figures 2A, 2B, 27A, and 27B (and associated Figures 3-18 and 21-26) apply similarly with respect to the corresponding features in Figure 28. Specifically, the exemplary substrate core 2800 includes first, second, and third glass cores 202, 204, and 206 containing TGV 238 extending through it. The glass cores 202, 204, and 205 are separated by intervening layers of dielectric material 208 on opposite surfaces of each of the glass cores 202, 204, and 206. Therefore, the outermost layer of the dielectric material 208 defines the first and second outer surfaces 210 and 212 of the substrate core 2800. Similar to that shown in Figure 2A, the TGV 238 in the glass cores 202, 204, and 206 are electrically coupled by an additional conductive material 240 extending through the intervening layer of the dielectric material 208.

[0074] Unlike the above examples, which include CMIL214, 246, 2702, and 2710, the exemplary substrate core 2800 in Figure 28 includes a set of plated magnetic vias (PMVs) 2802, 2804 (e.g., power supply interconnects) extending throughout the entire thickness of the substrate core 2800. The PMVs 2802, 2804 may perform a similar function to CMIL214, 246, 2702, and 2710, enhancing the power supply through the package substrate containing the substrate core 2800 (e.g., package substrate 110 in Figure 1). As shown in Figure 28, the PMVs 2802, 2804 include a seed layer 2808 covering the sidewalls of the openings 2806 (e.g., vias) extending through their respective glass cores 202, 204, and 206. In this example, the seed layer 2808 may include ruthenium, titanium, copper, and / or any combination thereof. In some examples, PMVs 2802 and 2804 include a magnetic material 2810 covering the inner wall of the seed layer 2808 (e.g., a seed layer surrounding the magnetic material 2810). In some examples, the magnetic material 2810 in Figure 28 is made of an electroplated Ni, Fe, or Co alloy exhibiting high magnetic permeability (e.g., above 20). That is, in some examples, the magnetic material 2810 in Figure 28 is identical or similar to the magnetic material 230 described above in relation to Figure 2A. Additionally, PMVs 2802 and 2804 include a central region filled with a conductive material 2812. In some examples, the conductive material 2812 in Figure 28 is identical or similar to the conductive material 228 (e.g., copper) described above in relation to Figure 2A.

[0075] In the illustrated example in Figure 28, the PMVs 2802 and 2804 are capped onto the first outer surface 210 of the substrate core 2800 by first and second conductive pads 2814 and 2816, respectively. In this example, the conductive pads 2814 and 2816 contain the same material (e.g., copper) as the conductive material 2812 extending along the axial length of the PMVs 2802 and 2804. Furthermore, as shown in Figures 2A and 2B, the PMVs 2802 and 2804 are electrically coupled along the second outer surface 212 of the substrate core 2800 by a conductive pad 2818 (e.g., trace, wire).

[0076] Figures 29–42 show different stages in an exemplary manufacturing process for producing the exemplary substrate core 2800 of Figure 28. The manufacturing stages represented by Figures 29–35 are substantially identical to those outlined above in relation to Figures 3–6 and 8–10, except that they are described below and / or that are otherwise evident from the context. That is, the process begins with the glass panel 2900 shown in Figure 29 (corresponding in this example to the initial state of the second glass core 204). The glass core 204 is exposed to a laser as part of the LIDE process (Figure 30), and then the laser-exposed portion of the glass core 204 is removed (Figure 31), defining the aperture 3102 for TGV 238 and defining the aperture 2806 for PMV 2802, 2804. Unlike that shown in Figure 5, in the illustrated example of Figure 31, the aperture 3102 is substantially the same size as the aperture 2806. As shown in Figure 32, the glass core 204 is mounted on a conductive carrier. In some examples, the conductive carrier may be similar to or identical to the conductive carrier 602 shown and described in relation to Figure 6. Accordingly, the same reference number is used to identify similar features, and the details provided above for such features apply similarly to this example. Figure 33 shows the application (e.g., via photolithography) of the mask 3302 covering the assembly except for the opening 3102 of the glass core 204. That is, the opening 2806 for PMV 2802, 2804 is covered but remains empty at this stage of the process. Figure 33 further shows the result of the etching process to remove the release layer 606 exposed within the opening 3102. Figure 34 shows the manufacturing stage after the mask 802 has been removed (e.g., stripped) and then copper has been plated into the opening 3102 to define TGV 238. Figure 35 shows the manufacturing stage after the conductive carrier 602 has been removed, including both the conductive layer 604 and the release layer 606. In some cases, a polishing (e.g., CMP) process may be implemented to make the metal of TGV238 substantially flush with the outer surface of the glass core 204.

[0077] Figure 36 illustrates the manufacturing stages after adding dielectric material 208 to both outer surfaces of the glass core 204 (e.g., lamination), then drilling holes, and then filling such holes (e.g., by plating) to define metal vias electrically coupled to the TGV 238. In some examples, a polishing (e.g., CMP) process is implemented to remove excess metal and make the vias 3602 substantially flush with the dielectric material 208.

[0078] Figure 37 illustrates a manufacturing stage after another drilling process through the dielectric material 208 to expose the opening 2806 for PMVs 2802 and 2804. Figure 38 illustrates a manufacturing stage after the deposition of the seed layer 2808. In some examples, the seed layer 2808 is deposited to cover the inner wall of the opening 2806 through any suitable deposition process (e.g., physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, etc.). Furthermore, Figure 38 illustrates the subsequent application (e.g., through plating) of the magnetic material 2810 onto the seed layer 2808. In some examples, the seed layer 2808 and the magnetic material 2810 are also applied to the outer surface of the assembly (e.g., on the dielectric material 208 and via 3602). Accordingly, in some examples, any excess material deposited outside the opening 2806 is removed (e.g., through etching, polishing, etc.).

[0079] Figure 39 illustrates the manufacturing stage after plating with conductive material 2812 (e.g., copper) to fill the opening 2806 and complete the structure of the associated segments of PMV 2802, 2804. In some examples, excess conductive material 2812 is removed through a polishing process (e.g., a CMP process) to make the outer surfaces of the different materials substantially identical to each other. In some examples, the manufacturing stage represented by Figure 39 corresponds to the complete glass core assembly 3900 at the end of processing of the second glass core 204 before it is stacked with other glass cores 202, 206 (processed to contain the other segments of PMV 2802, 2804). In some examples, the first and third glass cores 202, 206 are processed in a similar manner to the second glass core 204 as outlined above. Therefore, Figure 40 represents the complete glass core assembly 4000 after the processing of the first glass core 202 is complete, and Figure 41 represents the complete glass core assembly 4100 after the processing of the third glass core 206 is complete. As shown, the final result shown in Figure 40 is substantially identical to the final result shown in Figure 39, except that Figure 40 is followed by an additional operation to provide conductive pads 2814, 2816 on one of the outer surfaces (e.g., top surface) of the assembly 4000. In this example, the outer surface corresponds to the first surface 210 of the substrate core 2800 in Figure 28. Similarly, the final result shown in Figure 41 is substantially identical to the final result shown in Figure 39, except that Figure 41 is after an additional operation to provide a conductive pad 2818 on one of the outer surfaces (e.g., bottom surface) of the assembly 4100. In this example, the outer surface corresponds to the second surface 212 of the substrate core 2800 in Figure 28.

[0080] Figure 42 illustrates the manufacturing stages when the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the associated glass core assemblies 3900, 4000, and 4100 from Figures 39-41. In some examples, the same process used to join the glass core assemblies 3900, 4000, and 4100 from Figures 39-41, as described above in relation to Figure 18, is used to join the glass core assemblies 3900, 4000, and 4100 from Figures 39-41. The result of combining or joining the different glass core assemblies 3900, 4000, and 4100 is the substrate core 2800 shown in Figure 28.

[0081] Figure 43 shows another exemplary substrate core 4300 that may be used to mount the exemplary substrate core 128 of Figure 1. The exemplary substrate core 4300 of Figure 43 is substantially identical to the exemplary substrate core 2800 of Figure 28, except for the points described below. Accordingly, features shown in Figure 28 that are identical or similar to the corresponding features in Figure 43 (and associated Figures 29-42) are identified by the same reference number. Furthermore, the descriptions of such features described above in relation to Figure 28 (and associated Figures 29-42) apply similarly with respect to the corresponding features in Figure 43.

[0082] Figure 43 differs from Figure 28 in that the dielectric material 208 on the outer surfaces of each of the glass cores 202, 204, and 206 is omitted. Furthermore, Figure 43 differs from Figure 28 in the manner in which the different glass cores 202, 204, and 206 are combined or joined together, and in the resulting means for electrically coupling the different segments of the different TGV238 and PMV2802, 2804. Specifically, as shown in the illustrated example of Figure 43, the different cores 202, 204, and 206 are joined together by an adhesive dielectric 4302 extending between the facing surfaces of adjacent glass cores 202, 204, and 206. In some examples, the adhesive dielectric 4302 is substantially identical or similar to the adhesive dielectric 248 in Figure 2B. Furthermore, in this example, the TGV 238 extending through the glass cores 202, 204, and 206 is electrically coupled by conductive vias 4304 extending through the adhesive dielectric 4302. Similar conductive vias 4306 extend through the adhesive dielectric 4302 and electrically couple the conductive material 2812 associated with different segments of the PMV 2802, 2804. In some examples, the conductive vias 4304, 4306 are substantially identical or similar to the conductive vias 254, 256 in Figure 2B.

[0083] Figures 44–49 show different stages in an exemplary manufacturing process for producing the exemplary substrate core 4300 of Figure 43. The process for producing the exemplary substrate core 4300 of Figure 43 may follow the same or similar process described above in relation to the different stages of manufacturing represented by Figures 29–35, which are described above in relation to Figure 28. More specifically, Figure 44 shows a stage of manufacturing after the stage shown in Figure 35 and after the deposition of the seed layer 2808 and the magnetic material 2810. In some examples, these layers are added using the same technique described above in relation to Figure 38, except that the layer of dielectric material 208 in Figure 44 is absent.

[0084] Figure 45 represents a manufacturing stage after plating with a conductive material 2812 (e.g., copper), similar to the process described above in relation to Figure 39. Figure 46 represents a manufacturing stage after adding conductive pads 4602 (e.g., copper pads) to both ends of TGV238 and conductive pads 4604 (e.g., copper pads) to both ends of segments PMV2802,2804. In some examples, the manufacturing stage represented by Figure 46 corresponds to the complete glass core assembly 4600 at the end of processing of the second glass core 204 before it is stacked with other glass cores 202,206 (which have been processed to include other segments of PMV2802,2804).

[0085] In some examples, the first and third glass cores 202, 206 are processed in a similar manner to the second glass core 204 as outlined above. Thus, Figure 47 represents the complete glass core assembly 4700 after the processing of the first glass core 202 is complete, and Figure 48 represents the complete glass core assembly 4800 after the processing of the third glass core 206 is complete. As shown, the final result shown in Figure 47 is substantially identical to the final result shown in Figure 46, except that Figure 47 is after additional operations for adding the adhesive dielectric 4302 and subsequent drilling and filling of holes to provide conductive vias 4304, 4306. The final result shown in Figure 48 is substantially identical to the final result shown in Figure 47, except that the conductive pads at the bottom ends of the segments of PMV 2802, 2804 are combined into a single conductive pad corresponding to conductive pad 2818.

[0086] Figure 49 illustrates the manufacturing stages when the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the associated glass core assemblies 4600, 4700, and 4800 shown in Figures 46-48. In some examples, the same process used to join the glass core assemblies 4600, 4700, and 4800 of Figures 46-48, as described above in relation to Figure 18, is used to join the glass core assemblies 4600, 4700, and 4800 of Figures 46-48. The result of combining or joining the different glass core assemblies 4600, 4700, and 4800 is the substrate core 4300 shown in Figure 43.

[0087] Figure 50 is a flowchart illustrating an exemplary method that may be performed to manufacture one of the exemplary package substrate cores 128, 200, 244, 2700, 2708, 2800, and 4300 shown in Figures 1-49. In some examples, some or all of the operations outlined in the exemplary method of Figure 50 are performed automatically by equipment programmed to perform the operations. The exemplary method is described with reference to the flowchart shown in Figure 50, but many other methods may be used as alternatives. For example, the order of execution of blocks may be changed, and / or some of the blocks described may be combined, divided, rearranged, omitted, excluded, and / or implemented in any other manner. Furthermore, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated example.

[0088] The exemplary method in Figure 50 begins in block 5002 by preparing glass cores (e.g., glass panels 300, 2900 corresponding to any one of glass cores 202, 204, 206) with a given coefficient of thermal expansion (CTE). In some examples, the composition of the material used in the glass cores is selected to achieve the intended CTE for a particular layer of glass in an overall substrate core, which includes multiple glass cores stacked together. In block 5004, the exemplary method includes the step of adding openings through the glass cores (e.g., as shown in Figures 4-5 and 30-31). The openings may include openings for TGV (e.g., TGV238), CMIL (e.g., CMIL214, 246, 2702, 2710), and / or PMV (e.g., PMV2802, 2804).

[0089] In block 5006, the exemplary method involves determining whether at least one of the openings contains CMIL. If so, the process proceeds to block 5008. Otherwise, the process proceeds to block 5012. In block 5008, the exemplary process involves depositing a dielectric material (e.g., dielectric material 208) into at least one CMIL opening (e.g., as shown in Figure 7). In block 5010, the exemplary process involves covering at least one CMIL opening with a mask (e.g., mask 802 as shown in Figure 8).

[0090] In block 5012, the exemplary method involves determining whether at least one of the openings (added in block 5004) contains a PMV. If so, the process proceeds to block 5014. Otherwise, the process proceeds to block 5016. In block 5014, the exemplary process involves covering at least one PMV opening with a mask (e.g., mask 3302 shown in Figure 33).

[0091] In block 5016, the exemplary method involves depositing a conductive material in the remaining openings to define the TGV (e.g., TGV 238) through the glass core (as shown, for example, in Figures 9 and 34). In block 5018, the exemplary method involves removing a mask (added in block 5010 and / or block 5014) from the glass core. In block 5020, the exemplary method involves depositing dielectric layers (e.g., buffer layers 1102, 1104 in Figure 11, dielectric material 208 in Figure 36) on the outer surface of the glass core. In some examples, block 5022 is omitted (e.g., when manufacturing the exemplary substrate core 4300 in Figure 43). In block 5022, the exemplary method involves adding conductive vias (e.g., conductive via 3602) aligned with the TGV through the dielectric layers (as shown, for example, in Figures 11 and 36). In block 5024, the exemplary method involves adding material for additional redistribution layers (e.g., conductive pad 1108, additional dielectric layer 1202, conductive blanket 1208, as shown in Figure 12). In some examples (e.g., when manufacturing the exemplary substrate cores 244, 2708, 2800, 4300 in Figures 2B, 27B, 28, and 43), block 5024 is omitted.

[0092] In block 5026, the exemplary method involves fabricating a segment of CMIL in a CMIL opening prepared for that purpose. Further details regarding the implementation of block 5026 are provided below in relation to Figure 51. In cases where there is no CMIL opening (e.g., the result of block 5006 is no), block 5026 may be omitted. In block 5028, the exemplary method involves fabricating a segment of PMV in a PMV opening prepared for that purpose. Further details regarding the implementation of block 5028 are provided below in relation to Figure 52. In cases where there is no PMV opening (e.g., the result of block 5012 is no), block 5028 may be omitted.

[0093] In block 5030, the exemplary method involves determining whether to manufacture another glass core assembly (e.g., glass core assemblies 1500, 1600, 1700, 1902, 1904, 1906, 2300, 2400, 2500, 3900, 4000, 4100, 4600, 4700, 4800). If so, the process returns to block 5002 and repeats the process for the different glass core. In some examples, the different glass cores may be constructed with different CTEs. In some examples, separate iterations through the exemplary process may be performed in parallel rather than sequentially. When there are no further glass core assemblies to manufacture, the exemplary process proceeds to block 5032, which involves assembling the glass core assemblies. In some examples, the glass core assemblies completed up to block 5028 are assembled (as shown in Figures 18 and 42) so that the CMIL segments and / or PMVs are in direct contact with each other. In other examples, dielectric adhesives (e.g., adhesive dielectrics 248, 4302) may be added to at least one side of the boundary surface of adjacent glass core assemblies (as shown in Figures 25, 26 and 47-49) to facilitate the connection of the glass core assemblies. In some such examples, additional conductive vias (e.g., conductive vias 254, 256, 4304, 4306) extending through the dielectric adhesive are provided.

[0094] In some examples, blocks 5026 and / or 5028 (further details of which are described below in relation to Figures 51 and 52) may be implemented after block 5032. That is, in some examples, the glass core assembly is manufactured and assembled (as shown in Figure 19) before the inclusion of the CMIL and / or PMV, which are then added. The result of the exemplary process in Figure 50 is a finished substrate core (e.g., one of substrate cores 128, 200, 244, 2700, 2708, 2800, or 4300). The finished substrate core can then undergo any preferred subsequent processing (e.g., adding build-up layers, mounting one or more dies, and implementing other packaging processes).

[0095] Figure 51 is a flowchart illustrating an exemplary method for implementing block 5026 of Figure 50. In some examples, some or all of the operations outlined in the exemplary method of Figure 51 are performed automatically by a device programmed to perform the operations. The exemplary method is described with reference to the flowchart shown in Figure 51, but many other methods may be used as alternatives. For example, the order of execution of blocks may be changed, and / or parts of the described blocks may be combined, divided, rearranged, omitted, excluded, and / or implemented in any other way. Furthermore, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated example.

[0096] The exemplary method in Figure 51 begins in block 5102 by drilling a hole (e.g., hole 1302) through a dielectric material (e.g., dielectric material 208) extending through openings (e.g., openings 216, 218, 220) in the glass core. In block 5104, the exemplary method involves filling the hole with a magnetic material (e.g., magnetic material 230). In block 5106, the exemplary method involves drilling an internal through-hole (e.g., internal through-hole 1402) through the magnetic material. In block 5108, the exemplary method involves determining whether to include a non-magnetic plug in the CMIL. If so, the process proceeds to block 5110. Otherwise, the exemplary process proceeds to block 5114.

[0097] In block 5110, the exemplary method involves plating the walls of the internal through-holes with a conductive material (e.g., conductive material 228) while leaving the central region open. In block 5112, the exemplary method involves filling the central region with a non-magnetic plug (e.g., non-magnetic plug 226). The exemplary process then proceeds to block 5116. Returning to block 5114, the exemplary process involves filling the internal through-holes with a conductive material. The exemplary process then proceeds to block 5116, which involves determining whether a segment of the CMIL being manufactured is in direct contact with another segment of the CMIL (as shown in the exemplary substrate core in Figures 18 and 42, in contrast to an example where the segments are spaced apart by adhesive dielectrics 248, 4302, as shown in Figures 26 and 49, for example). If so, the process proceeds to block 5118.

[0098] In block 5118, the exemplary method involves polishing the glass core assembly to produce a flat outer surface. In block 5120, the exemplary method involves adding conductive pads (e.g., conductive pads 232, 234, 236, 1602, 1702, 2814, 2816, 2818, 4602, 4604) to the resulting outer surface of the glass core assembly. In some examples, the conductive pads are added to only one of the two surfaces (as shown in Figures 16 and 17). In some examples, no conductive pads are added (as shown in Figures 15 and 19). In some examples, whether conductive pads are added to both outer surfaces of the glass core, to one, or not depends on where the glass cores are located in the stack of glass cores and how different glass cores are combined or joined in the stack. The exemplary process in Figure 51 is then completed, and we return to completing the exemplary process in Figure 50.

[0099] Returning to block 5116, if the segment of CMIL to be manufactured does not directly contact another segment of CMIL, the exemplary method proceeds to block 5122. In block 5122, the exemplary method involves depositing an additional amount of conductive material 228 and extending it across the ends of the CMIL segments. In block 5124, the exemplary method involves removing portions of the outer metal layer to define conductive pads (e.g., conductive pads 232, 234, 236, 1602, 1702, 2814, 2816, 2818, 4602, 4604). In this example, the conductive pads are added to both sides of the glass core assembly (e.g., capping and closing both ends of the CMIL as shown in Figure 24). The exemplary process in Figure 51 is then completed, and we return to completing the exemplary process in Figure 50.

[0100] Figure 52 is a flowchart illustrating an exemplary method for implementing block 5028 of Figure 50. In some examples, some or all of the operations outlined in the exemplary method of Figure 52 are performed automatically by a device programmed to perform the operations. The exemplary method is described with reference to the flowchart shown in Figure 52, but many other methods may be used as alternatives. For example, the order of execution of blocks may be changed, and / or parts of the described blocks may be combined, divided, rearranged, omitted, excluded, and / or implemented in any other way. Furthermore, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated example.

[0101] The exemplary method in Figure 52 begins in block 5202 by drilling a hole through the dielectric layer (added in block 5020 in Figure 50) to expose the PMV opening (as shown in Figure 37). In block 5204, the exemplary method involves depositing a seed layer (e.g., seed layer 2808) on the sidewall of the opening (as shown in Figures 38 and 44). In block 5206, the exemplary method involves adding a magnetic material (e.g., magnetic material 2810) to cover the inner wall of the seed layer (as shown in Figures 38 and 44). In block 5208, the exemplary method involves filling the internal through-hole with a conductive material (e.g., conductive material 2812 as shown in Figures 39 and 45). In block 5210, the exemplary method involves adding conductive pads (e.g., conductive pads 232, 234, 236, 1602, 1702, 2814, 2816, 2818, 4602, 4604) to the outer surface of the resulting glass core assembly. In some examples, the conductive pads are added to only one of the two surfaces (as shown in Figures 40 and 41). In some examples, the conductive pads are added to both surfaces (as shown in Figures 46-48). In some examples, no conductive pads are added (as shown in Figure 39). In some examples, whether the conductive pads are added to both outer surfaces of the glass core, to one, or not depends on where the glass cores are located in the stack of glass cores and how the different glass cores are combined or joined in the stack. The exemplary process in Figure 52 is then completed, and we return to completing the exemplary process in Figure 50.

[0102] The exemplary IC package 100 shown in Figure 1 (with any of the exemplary substrate cores 128, 200, 244, 2700, 2708, 2800, or 4300) disclosed herein may be included in any suitable electronic component. Figures 53–56 show various exemplary devices that may include, or could be included in, the IC package 100 disclosed herein.

[0103] Figure 53 is a top view of a wafer 5300 and die 5302 that may be contained in the IC package 100 of Figure 1 (for example, preferably one of dies 106 or 108). The wafer 5300 includes semiconductor material and one or more dies 5302 having circuits. Each die 5302 may be a repeating unit of a semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 5300 may undergo a fragmentation process in which the dies 5302 are separated from each other to provide separate “chips”. The die 5302 includes one or more transistors (for example, some of the transistors 5440 in Figure 54 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some examples, die 5302 may include and / or implement memory devices (random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuits or electronic devices. Multiple of these devices may be combined on a single die 5302. For example, a memory array of multiple memory circuits may be formed on the same die 5302 as a programmable circuit (e.g., processor circuit 5602 in Figure 56) and / or other logic circuits. Such memory may store information for use by the programmable circuit. The exemplary IC package 100 disclosed herein may be manufactured using a die-wafer assembly technique in which several dies are mounted on a wafer 5300 containing other dies, and the wafer 5300 is subsequently pulverized.

[0104] Figure 54 is a side cross-sectional view of an IC device 2000 that may be contained in an exemplary IC package 100 (for example, in one of dies 106, 108). One or more of the IC devices 5400 may be contained in one or more dies 5302 (Figure 53). The IC devices 5400 may be formed on a die substrate 5402 (for example, wafer 5300 in Figure 53) and may be contained in a die (for example, die 5302 in Figure 53). The die substrate 5402 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination thereof). The die substrate 5402 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) base structure. In some examples, the die substrate 5402 may be formed using alternative materials. The material may, but is not limited to, be combined with silicon containing germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, or may not be combined with it. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 5402. A few examples of materials on which the die substrate 5402 may be formed are described here, but any material that can function as the basis for the IC device 5400 may be used. The die substrate 5402 may be part of a flaked die (e.g., die 5302 in Figure 53) or a wafer (e.g., wafer 5300 in Figure 53).

[0105] The IC device 5400 may include one or more device layers 5404 disposed on and / or on the die substrate 5402. The device layer 5404 may include features of one or more transistors 5440 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 5402. The device layer 5404 may include, for example, one or more source and / or drain (S / D) regions 5420, a gate 5422 for controlling the current between the S / D regions 5420, and one or more S / D contacts 5424 for routing electrical signals to and from the S / D regions 5420. The transistor 5440 may include additional features, such as device isolation regions and gate contacts, which are not shown for clarity. The transistor 5440 is not limited to the types and configurations shown in Figure 54 and may include a variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around gate transistors or all-around gate transistors such as nanoribbon transistors and nanowire transistors.

[0106] Each transistor 5440 may include a gate 5422 comprising a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and / or zinc. Examples of high-dielectric materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and / or lead zinc niobium oxide. In some cases, when high dielectric constant materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0107] The gate electrode may be formed on a gate dielectric, and the gate electrode may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 5440 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a filler metal layer. Further metal layers, such as barrier layers, may be included. In the case of a PMOS transistor, the metals that can be used for the gate electrode are, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or (e.g., for work function tuning) any of the metals described later with reference to an NMOS transistor. In the case of NMOS transistors, the metals that can be used for the gate electrode are not limited to, but include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and / or aluminum carbide), and / or (e.g., for work function tuning) any of the metals mentioned above with reference to PMOS transistors.

[0108] In some examples, when viewed as a cross-section of transistor 5440 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom portion substantially parallel to the surface of the die substrate 5402 and two sidewall portions substantially perpendicular to the top surface of the die substrate 5402. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of the die substrate 5402 and not comprising sidewall portions substantially perpendicular to the top surface of the die substrate 5402. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar-type non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar-type non-U-shaped layers.

[0109] In some examples, pairs of sidewall spacers may be formed on the opposite side of the gate stack so as to surround the gate stack. Sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally involve deposition and etching process operations. In some examples, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on the opposite side of the gate stack.

[0110] The S / D region 5420 may be formed within the die substrate 5402 adjacent to the gate 5422 of the corresponding transistor 5440. The S / D region 5420 may be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic are ion-implanted into the die substrate 5402 to form the S / D region 5420. An annealing process may follow the ion implantation process to activate the dopants and diffuse them further into the die substrate 5402. In the latter process, the die substrate 5402 is first etched to form a recess at the location of the S / D region 5420. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 5420. In some implementations, the S / D region 5420 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some examples, epitaxially deposited silicon alloys may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 5420 may be formed using one or more alternative semiconductor materials such as germanium or III-V materials or alloys. In further examples, one or more layers of metal and / or metallic alloys may be used to form the S / D region 5420.

[0111] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and from a device on device layer 5404 (e.g., transistor 5440) through one or more interconnect layers (shown as interconnect layers 5406-5410 in Figure 54). For example, conductive features on device layer 5404 (e.g., gate 5422 and S / D contact 5424) can be electrically coupled to the interconnect structure 5428 of interconnect layers 5406-5410. One or more interconnect layers 5406-5410 can form a metallization stack (also referred to as the "ILD stack") 5419 of the IC device 5400.

[0112] The interconnect structure 5428 may be arranged within interconnect layers 5406-5410 to route electrical signals according to a variety of designs (in particular, such arrangements are not limited to the specific configuration of interconnect structure 5428 shown in Figure 54). While a certain number of interconnect layers 5406-5410 are shown in Figure 54, examples of the present disclosure include IC devices having more or fewer interconnect layers than those shown.

[0113] In some examples, the interconnect structure 5428 may include wires 5428a and / or vias 5428b filled with a conductive material such as metal. The wires 5428a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 5402 on which the device layer 5404 is formed. For example, the wires 5428a may route electrical signals in an inward and / or outward direction from the viewpoint of Figure 54. The vias 5428b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 5402 on which the device layer 5404 is formed. In some examples, the vias 5428b may electrically couple wires 5428a of different interconnect layers 5406-5410 together.

[0114] As shown in Figure 54, interconnect layers 5406-5410 may include dielectric material 5426 disposed between interconnect structures 5428. In some examples, the dielectric material 5426 disposed between interconnect structures 5428 in different interconnect layers 5406-5410 may have different compositions; in other examples, the composition of the dielectric material 5426 between different interconnect layers 5406-5410 may be the same.

[0115] A first interconnect layer 5406 (referred to as metal 1 or "M1") may be formed directly on the device layer 5404. In some examples, the first interconnect layer 5406 may include lines 5428a and / or vias 5428b, as shown. Lines 5428a of the first interconnect layer 5406 may be coupled to contacts of the device layer 5404 (e.g., S / D contacts 5424).

[0116] A second interconnect layer 5408 (referred to as metal 2 or "M2") may be formed directly above the first interconnect layer 5406. In some examples, the second interconnect layer 5408 may include vias 5428b for connecting lines 5428a of the second interconnect layer 5408 to lines 5428a of the first interconnect layer 5406. For clarity, lines 5428a and vias 5428b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 5408), but in some examples, lines 5428a and vias 5428b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0117] The third interconnect layer 5410 (referred to as Metal 3 or "M3") (and additional interconnect layers as desired) may be formed continuously on the second interconnect layer 5408 according to techniques and / or configurations similar to those described in relation to the second interconnect layer 5408 or the first interconnect layer 5406. In some examples, "higher" interconnect layers (i.e., further away from the device layer 5404) in the metallization stack 5419 within the IC device 5400 may be thicker.

[0118] The IC device 5400 may include a solder resist material 5434 (e.g., polyimide or similar material) formed on interconnect layers 5406-5410 and one or more conductive contacts 5436. In Figure 54, the conductive contacts 5436 are illustrated as being in the form of bonding pads. The conductive contacts 5436 may be electrically coupled to an interconnect structure 5428 and may be configured to route electrical signals from transistor 5440 to other external devices. For example, solder joints may be formed on one or more conductive contacts 5436 to mechanically and / or electrically couple a chip containing the IC device 5400 to another component (e.g., a circuit board). The IC device 5400 may include additional or alternative structures for routing electrical signals from interconnect layers 5406-5410. For example, the conductive contacts 5436 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0119] Figure 55 is a side cross-sectional view of an IC device assembly 5500 which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 5500 includes a number of components arranged on a circuit board 5502 (which may be, for example, a motherboard). The IC device assembly 5500 includes a number of components arranged on a first surface 5540 of the circuit board 5502 and on a second opposite surface 5542 of the circuit board 5502, and generally the components may be arranged on one or both of surfaces 5540 and 5542. Any of the IC packages described below with reference to the IC device assembly 2200 may take the form of the exemplary IC package 100 in Figure 1.

[0120] In some examples, the circuit board 5502 may be a printed circuit board (PCB) comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed (optionally, in conjunction with other metal layers) to route electrical signals between components coupled to the circuit board 5502 in a desired circuit pattern. In other examples, the circuit board 5502 may be a non-PCB substrate.

[0121] The IC device assembly 5500 shown in Figure 55 includes a package-on-interposer structure 5536 coupled to the first surface 5540 of a circuit board 5502 by a coupling component 5516. The coupling component 5516 may electrically and mechanically couple the package-on-interposer structure 5536 to the circuit board 5502 and may include solder balls (shown in Figure 55), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0122] The package-on-interposer structure 5536 may include an IC package 5520 coupled to an interposer 5504 by a coupling component 5518. The coupling component 5518 can take any suitable form for the application, such as the form described above with reference to the coupling component 5516. Although a single IC package 5520 is shown in Figure 55, multiple IC packages may be coupled to the interposer 5504, and in fact, additional interposers may be coupled to the interposer 5504. The interposer 5504 may provide an intervening substrate used to bridge the circuit board 5502 and the IC package 5520. The IC package 5520 may be, for example, a die (die 5302 in Figure 53), an IC device (e.g., IC device 5400 in Figure 54), or any other suitable component, or may include them. Generally, the interposer 5504 may spread connections to a wider pitch, or reroute some connections to different connections. For example, the interposer 5504 may couple an IC package 5520 (e.g., a die) to a set of BGA conductive contacts of a coupling component 5516 for coupling to a circuit board 5502. In the example shown in Figure 55, the IC package 5520 and the circuit board 5502 are mounted on opposite sides of the interposer 5504; in other examples, the IC package 5520 and the circuit board 5502 may be mounted on the same side of the interposer 5504. In some examples, three or more components may be interconnected by the interposer 5504.

[0123] In some examples, the interposer 5504 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 5504 may be formed of polymer materials such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polyimide. In some examples, the interposer 5504 may be formed of alternative rigid or flexible materials. Such materials may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 5504 may include metal interconnects 5508 and vias 5510 including, but not limited to, through-silicon vias (TSVs) 5506. The interposer 5504 may further include embedded devices 5514, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 5504. The package-on-interposer structure 5536 may take any form of package-on-interposer structure known in the art.

[0124] The IC device assembly 5500 may include an IC package 5524 that is coupled to the first surface 5540 of the circuit board 5502 by a coupling component 5522. The coupling component 5522 may take any form of the examples described above with reference to coupling component 5516, and the IC package 5524 may take any form of the examples described above with reference to IC package 5520.

[0125] The IC device assembly 5500 illustrated in Figure 55 includes a package-on-package structure 5534 coupled to a second surface 5542 of a circuit board 5502 by a coupling component 5528. The package-on-package structure 5534 may include a first IC package 5526 and a second IC package 5532, coupled together by a coupling component 5530 so that the first IC package 5526 is positioned between the circuit board 5502 and the second IC package 5532. The coupling components 5528, 5530 may take any form of the examples of coupling components 5516 described above, and the IC packages 5526, 5532 may take any form of the examples of IC packages 5520 described above. The package-on-package structure 5534 may be configured according to any package-on-package structure known in the art.

[0126] Figure 56 is a block diagram of an exemplary electrical device 5600, which may include one or more exemplary IC packages 100. For example, any preferred components of the electrical device 5600 may include one or more of the device assemblies 5500, IC devices 5400, or dies 5302 disclosed herein, which may be arranged in the exemplary IC package 100. Although numerous components are shown in Figure 56 as being included in the electrical device 5600, one or more of these components may be omitted or duplicated if appropriate for the application. In some examples, some or all of the components included in the electrical device 5600 may be mounted on one or more motherboards. In some examples, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0127] Additionally, in various examples, the electrical device 5600 may not include one or more of the components shown in Figure 56, but may include interface circuits for connecting one or more components. For example, the electrical device 5600 may not include the display 5606, but may include a display interface circuit (e.g., a connector and driver circuit) to which the display 5606 can be connected. In another set of examples, the electrical device 5600 may not include an audio input device 5618 (e.g., a microphone) or an audio output device 5608 (e.g., a speaker, headset, earbuds, etc.), but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 5618 or audio output device 5608 can be connected.

[0128] The electrical device 5600 may include a programmable circuit 5602 (e.g., one or more processing devices). The programmable circuit 5602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 5600 may include a memory 5604. The memory 5604 may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some examples, the memory 5604 may include memory that shares a die with the programmable circuit 5602. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0129] In some examples, the electrical device 5600 may include a communication chip 5612 (e.g., one or more communication chips). For example, the communication chip 5612 may be configured to manage wireless communication for data transfer to and from the electrical device 5600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. While the relevant devices may not include wiring in some examples, the term does not imply that the relevant devices are not included in any wiring.

[0130] The 5612 communication chip may implement any of the numerous wireless standards or protocols, including, but is not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2")), and other Institute of Electrical and Electronics Engineers (IEEE) standards. Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and it is a certification mark for products that have passed compliance and interoperability tests for the IEEE 802.16 standard. The communication chip 5612 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), and Evolved HSPA (E-HSPA or LTE networks). The communication chip 5612 may operate in accordance with GSM® Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 5612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other examples, the communication chip 5612 may operate in accordance with other radio protocols. The electrical device 5600 may include an antenna 5622 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0131] In some examples, the communication chip 5612 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 5612 may include multiple communication chips. For example, the first communication chip 5612 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and the second communication chip 5612 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, or others. In some examples, the first communication chip 5612 may be dedicated to wireless communications, and the second communication chip 5612 may be dedicated to wired communications.

[0132] The electrical device 5600 may include a battery / power supply circuit 5614. The battery / power supply circuit 5614 may include a circuit for connecting components of the electrical device 5600 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical device 5600 (e.g., AC line power).

[0133] The electrical device 5600 may include a display 5606 (or the corresponding interface circuit described above). The display 5606 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0134] The electrical device 5600 may include an audio output device 5608 (or the corresponding interface circuit described above). The audio output device 5608 may include any device that generates an audible indicator, such as a speaker, headset, or earbuds.

[0135] The electrical device 5600 may include an audio input device 5618 (or the corresponding interface circuit described above). The audio input device 5618 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0136] The electrical device 5600 may include a GPS circuit 5616. The GPS circuit 5616 may communicate with a satellite-based system and receive the position of the electrical device 5600 in a manner known in the art.

[0137] The electrical device 5600 may include any other output device 5610 (or the corresponding interface circuit described above). Examples of other output devices 5610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0138] The electrical device 5600 may include any other input device 5620 (or the corresponding interface circuit described above). Examples of other input devices 5620 may include an accelerometer, gyroscope, compass, imaging device, cursor control device such as a keyboard or mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0139] The electrical device 5600 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA®), ultramobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some examples, the electrical device 5600 may be any other electronic device that processes data.

[0140] The terms “including” and “comprising” (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of “include” or “comprise” (e.g., “comprises,” “includes,” “comprising,” “including,” “having,” etc.) as a preamble or in any type of enumeration of claims, it should be understood that additional elements, terms, etc., may exist without falling outside the scope of the corresponding claim or enumeration. Where used herein, the phrase “at least” is open-ended in the same way that the terms “include” and “comprising” are open-ended, for example, when used as a transitional clause in the preamble of a claim. For example, when used in the form of A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. When used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in a context describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to mean an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in a context describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to mean an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0141] Where used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. Where used herein, the term “a” or “an” object refers to one or more of those objects. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably herein. Furthermore, multiple means, elements, or actions, though listed individually, may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and their inclusion in different examples or claims does not imply that the combination of features is unfeasible and / or unfavorable.

[0142] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. If the second part has at least one part between the Earth and the first part, the first part is above the second part. Similarly, as used herein, if the first part is closer to the Earth than the second part, the first part is “below” the second part. As described above, the first part may be above or below the second part, with or without other parts between them, with the first and second parts in contact, or without the first and second parts in direct contact with each other.

[0143] Notwithstanding the foregoing, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies during manufacturing or production, “on top of” does not refer to the earth, but rather to the substrate on which the relevant components are manufactured, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise specified or suggested by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “on top of” a second component in the semiconductor die if, during manufacturing / production, the first component is further away than the second component from the substrate (e.g., a semiconductor wafer) on which the two components are manufactured or otherwise provided. Similarly, unless otherwise specified or suggested by the context, a first component in an IC package (e.g., a semiconductor die) is “on top of” a second component in the IC package if, during manufacturing, the first component is further away from the printed circuit board (PCB) on which the IC package will be mounted or attached. It is often understood that semiconductor devices are used in a orientation different from their orientation during manufacturing. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of "on top of" in the previous paragraph (i.e., the term "on top of" describes the relationship between two parts relative to the Earth) may be determined based on the context of use.

[0144] As used in this patent, the description that any part (e.g., a layer, film, area, region, or plate) is located on another part in any way (e.g., positioned on, situated on, placed on, or formed on) indicates that the referenced part is in contact with the other part, or that the referenced part is on the other part and is accompanied by one or more intermediate parts positioned between them.

[0145] Where used herein, unless otherwise stated, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to connections, and / or relative movement between those elements. Thus, references to connections do not necessarily imply that two elements are directly connected and / or are in a fixed relationship with one another. Where used herein, any statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0146] Unless otherwise specified, descriptors such as “first,” “second,” and “third” are used herein without prejudice or otherwise indicating any meaning of priority, physical order, placement in a list, and / or ordering in any way, but merely as labels and / or arbitrary names to distinguish elements for the sake of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in a detailed description, while the same element may be referred to in a claim using a different descriptor such as “second” or “third.” In such cases, it should be understood that such descriptors are simply used to distinguish those elements in the context of the description (for example, in a claim) (otherwise, those elements may share, for example, the same name).

[0147] Where used herein, “approximately” and “about” modify their subject / value to acknowledge the existence of potential variations that occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified herein.

[0148] As used herein, "substantially real-time" means occurring almost instantaneously, but it is acknowledged that there may be real-world delays such as computing time and transmission delays. Therefore, unless otherwise specified, "substantially real-time" means real-time plus 1 second.

[0149] As used herein, the term “communicate” (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, without requiring direct physical (e.g., wired) communication and / or regular communication, and additionally includes periodic intervals, scheduled intervals, aperiodic intervals, and / or selective communication for a single event.

[0150] As used herein, “programmable circuit configuration” is defined as comprising (i) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) having a structure for performing a particular operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions for performing a particular function and / or operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit configurations include a central processor unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) whose configuration and / or structure can be programmed with a second instruction to instantiate one or more operations and / or functions corresponding to a first instruction; a graphics processor unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing a first instruction to perform one or more operations and / or functions; one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions; and / or a programmable microprocessor such as an integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system comprising multiple types of programmable circuit configurations (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof), and by orchestration techniques (e.g., an Application Programming Interface (API)) that can assign computing tasks to any of the multiple types of programmable circuit configurations that are suitable for or available for performing computing tasks.

[0151] As used herein, an integrated circuit / circuit configuration is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit may be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit configuration, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0152] From the above, it is understood that exemplary systems, apparatus, products, and methods are disclosed that enable the manufacture of CMIL and / or PMV for enhanced power supply within a substrate core, including a stack of multiple isolated glass cores with different CTEs. The different CTEs define a CTE gradient that reduces stress within the package substrate, specifically mitigating back cracking failure known to occur in substrates having a single solid glass core with a single CTE. As a result, the examples disclosed herein improve yield losses in the manufacture of package substrates and improve the reliability and / or service life of IC packages compared to known techniques.

[0153] Further examples and combinations thereof include the following:

[0154] Example 1 is a substrate for an integrated circuit package comprising: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE being different from the first CTE, and a conductive material extending at least partially through the first pore in the first glass layer and the second pore in the second glass layer; and a magnetic material between the inner wall of the first pore and the conductive material. Includes a substrate equipped with the following features.

[0155] Example 2 includes the substrate of Example 1, and the conductive material and magnetic material define a coaxial magnetic inductor loop (CMIL).

[0156] Example 3 includes the substrate of Example 2, further comprising a non-magnetic plug within the CMIL, wherein the conductive material surrounds the non-magnetic plug and the magnetic material surrounds the conductive material.

[0157] Example 4 includes a substrate of either Example 2 or 3, wherein the CMIL is a first CMIL, the substrate includes a second CMIL adjacent to the first CMIL, and both the first and second CMILs extend through the first and second perforations of their respective first and second glass layers.

[0158] Example 5 includes one of the substrates from Examples 1 to 4, and further includes a dielectric material between the first glass layer and the second glass layer.

[0159] Example 6 includes the substrate of Example 5, and the dielectric material has a lower elastic modulus than the first glass layer.

[0160] Example 7 includes a substrate from either Example 5 or 6, and the dielectric material includes an organic dielectric.

[0161] Example 8 includes the substrate of Example 7, and the dielectric material includes at least one of parylene or polyimide.

[0162] Example 9 includes one of the substrates from Examples 5 to 8, and the dielectric material includes an inorganic dielectric.

[0163] Example 10 includes the substrate of Example 9, wherein the dielectric material includes at least one of silicon, oxygen, or nitrogen.

[0164] Example 11 includes an integrated circuit (IC) package comprising: a first build-up region; a second build-up region; a stack of multiple glass layers between the first and second build-up regions, the different glass layers having different coefficients of thermal expansion (CTE); and a power supply interconnect passing through the stack of multiple glass layers, the power supply interconnect comprising at least one of nickel, iron, or cobalt.

[0165] Example 12 includes the IC package of Example 11, wherein the glass layer includes a first glass layer having a first CTE, a second glass layer having a second CTE, and a third glass layer having a third CTE, the second glass layer being of a different type from the first glass layer, the third glass layer being of a different type from the first glass layer, and the second glass layer being of a different type from the second glass layer.

[0166] Example 13 includes the IC package of Example 12, wherein the first glass layer is adjacent to the first build-up region, the second glass layer is adjacent to the second build-up region, and the third glass layer is between the first and second glass layers, the first build-up region has a fifth CTE, the second build-up region has a sixth CTE, the first CTE is closer to the fifth CTE than the third CTE is closer to the fifth CTE, and the second CTE is closer to the sixth CTE than the third CTE is closer to the sixth CTE.

[0167] Example 14 includes the IC package of Example 13, further comprising a fourth glass layer between the first and third glass layers, the fourth glass layer having a seventh CTE between the first and third CTEs.

[0168] Example 15 includes one of the IC packages from Examples 12-14, where the second CTE corresponds to the first CTE, and the first CTE is higher than the third CTE.

[0169] Example 16 includes one of the IC packages from Examples 12 to 15, wherein the third glass layer has a third CTE that is different from the first CTE and different from the second CTE.

[0170] Example 17 includes one of the IC packages from Examples 12-16, where different CTEs of the glass layers define symmetrical CTE gradients.

[0171] Example 18 includes a device comprising: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate comprising a stack of glass layers, the first of which has a different coefficient of thermal expansion (CTE) than the second of which; and a magnetic inductor extending through the stack of glass layers, the magnetic inductor comprising a non-magnetic core.

[0172] Example 19 includes the apparatus of Example 18, wherein a first segment of the non-magnetic core extends through a first hole in a first glass layer, and a second segment of the non-magnetic core extends through a second hole in a second glass layer.

[0173] Example 20 includes the apparatus of Example 19, further comprising a magnetic material surrounding a non-magnetic core, wherein the magnetic material extends continuously from a first pore in the first glass layer to a second pore in the second glass layer.

[0174] Example 21 includes a package substrate comprising: a first glass layer, the first glass layer having a first coefficient of thermal expansion (CTE) and a first opening extending through it; a second glass layer, the second glass layer having a second CTE different from the first CTE and a second opening extending through it; a first metal segment extending at least partially through the first opening; a second metal segment extending at least partially through the second opening; the first metal segment being electrically coupled to the second metal segment; a first magnetic lining at the first opening, the first magnetic lining surrounding the first metal segment; and a second magnetic lining at the second opening, the second magnetic lining surrounding the second metal segment.

[0175] Example 22 includes the package substrate of Example 21, wherein the first and second metal segments and the first and second magnetic linings define a coaxial magnetic inductor loop (CMIL).

[0176] Example 23 includes the package substrate of Example 22, wherein the first metal segment extends continuously from the inner surface of the first magnetic lining along the central axis of the longitudinal length of the first metal segment.

[0177] Example 24 includes a package substrate of either Example 22 or 23, wherein the CMIL is a first CMIL, and the substrate includes a second CMIL adjacent to the first CMIL, and both the first and second CMILs extend through the first and second glass layers, respectively.

[0178] Example 25 includes any one of Examples 21 to 24, further comprising a dielectric material between the first glass layer and the second glass layer.

[0179] Example 26 includes the package substrate of Example 25, and the dielectric material includes epoxy.

[0180] Example 27 includes an integrated circuit (IC) package comprising a package core including a first glass sheet and a second glass sheet of a different type from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) than the second glass sheet, a first redistribution layer on a first surface of the package core, a second redistribution layer on a second surface of the package core, the second surface being opposite to the first surface, and an interconnect extending through the package core, the interconnect comprising a magnetic material.

[0181] Example 28 includes the IC package of Example 27, wherein the first glass sheet includes a first opening, the second glass sheet includes a second opening, the interconnect extends through the first and second openings, and the IC package further includes a dielectric material within the first opening, the dielectric material surrounding the magnetic material.

[0182] Example 29 includes the IC package of Example 28, and further includes a buffering material between the first glass sheet and the second glass sheet.

[0183] Example 30 includes the IC package of Example 29, and the buffer material differs from the dielectric material in that the buffer material has a lower modulus of elasticity than the dielectric material.

[0184] Example 31 includes one of the IC packages from Examples 27-30, wherein the magnetic material extends through a first opening in a first glass sheet and through a second opening in a second glass sheet, and the magnetic material in the first opening is separated from the magnetic material in the second opening by a different material.

[0185] Example 32 includes one of the IC packages from Examples 27 to 30, wherein the magnetic material extends continuously from the first surface of the first glass sheet to the second surface of the second glass sheet, with the first surface of the first glass sheet oriented away from the second glass sheet and the second surface of the second glass sheet oriented away from the first glass sheet.

[0186] Example 33 includes a semiconductor chip, a substrate on which the semiconductor chip is mounted, the substrate including a substrate core defined by a first glass layer and a second glass layer, the first glass layer being between the semiconductor chip and the second glass layer, the first glass layer having a different coefficient of thermal expansion (CTE) than the second glass layer, and a magnetic inductor passing through the first and second glass layers of the substrate core, the magnetic inductor including a solid metal core across the cross-section of the metal core.

[0187] Example 34 includes the substrate of Example 33 and further includes a dielectric material between the first glass layer and the second glass layer.

[0188] Example 35 includes the substrate of Example 34, wherein the dielectric material is a first dielectric material, and the substrate further includes a second dielectric material between the first and second glass layers, the second dielectric material being different from the first dielectric material.

[0189] Example 36 includes the substrate of Example 35, wherein the first layer of the first dielectric material is adjacent to the first glass layer, the second layer of the first dielectric material is adjacent to the second glass layer, and the second dielectric material is located between the first layer of the first dielectric material and the second layer of the first dielectric material.

[0190] Example 37 includes a substrate of either Example 35 or 36, wherein the first segment of the magnetic inductor is located in a first hole in the first glass layer, the second segment of the magnetic inductor is located in a second hole in the second glass layer, and the first segment of the magnetic inductor is separated from the second segment of the magnetic inductor by a second dielectric material.

[0191] Example 38 includes the substrate of Example 37, wherein the second dielectric material is in contact with the first segment of the magnetic inductor and the second segment of the magnetic inductor.

[0192] Example 39 includes a substrate which is either Example 37 or 38, and further comprises a first conductive pad at the first end of a first segment of a magnetic inductor, and a second conductive pad at the second end of a segment of the magnetic inductor, wherein the first and second ends of the first and second segments of the magnetic inductor are oriented toward each other, the first conductive pad is spaced apart from the second conductive pad, and the first conductive pad is electrically coupled to the second conductive pad.

[0193] Example 40 includes one of the substrates from Examples 34 to 39, wherein the magnetic inductor includes magnetic material in a first pore in the first glass layer, and the dielectric material separates the magnetic material from the inner wall of the first pore.

[0194] Example 41 includes a substrate for an integrated circuit package, the substrate comprising a first glass layer having a first coefficient of thermal expansion (CTE), a second glass layer having a second CTE, the second CTE being different from the first CTE, and a magnetic material covering the first wall of a first opening in the first glass layer and covering the second wall of a second opening in the second glass layer.

[0195] Example 42 includes the substrate of Example 41, wherein the magnetic material extends continuously from within the first opening of the first glass layer to within the second opening of the second glass layer.

[0196] Example 43 includes the substrate of Example 41, wherein the magnetic material in the first aperture is spaced apart from the magnetic material in the second aperture.

[0197] Example 44 includes any one of the substrates from Examples 41 to 43, and further comprises conductive material in the first and second openings.

[0198] Example 45 includes the substrate of Example 44, wherein the conductive material defines a first pad at the first end of the magnetic material in the first opening and a second pad at the second end of the magnetic material in the second opening, the first and second ends of the magnetic material in the first and second openings respectively oriented toward each other, and the first pad is spaced apart from and electrically coupled to the second pad.

[0199] Example 46 includes a substrate of either Example 44 or 45, wherein a conductive material and a magnetic material define a first plated magnetic via (PMV) passing at least partially through the first glass layer and a second PMV passing at least partially through the second glass layer, and the first PMV is electrically coupled to the second PMV.

[0200] Example 47 includes any one of the substrates from Examples 44 to 46, further comprising a metal layer covering the first wall of the first opening, wherein the metal layer is different from the conductive material and the magnetic material separates the metal layer from the conductive material.

[0201] Example 48 includes any one of the substrates from Examples 41 to 47, and further comprises a dielectric material between the first glass layer and the second glass layer.

[0202] Example 49 includes the substrate of Example 48, further comprising a buffering material between the first glass layer and the second glass layer, wherein the buffering material is different from the dielectric material.

[0203] Example 50 includes the substrate of Example 49, wherein the buffer material has a lower modulus of elasticity than the dielectric material.

[0204] Example 51 includes one of the substrates from Examples 48 to 50, wherein the dielectric material extends along the first wall of the first opening, separating the magnetic material from the first wall of the first opening.

[0205] Example 52 includes one of the substrates from Examples 41 to 51, wherein the first and second glass layers are in a stack of glass layers, and the different glass layers have different CTEs, and the different CTEs in the stack of glass layers define a symmetric sequence of CTEs from the bottom glass layer in the stack to the top glass layer in the stack.

[0206] Example 53 includes an integrated circuit (IC) package comprising a semiconductor die, a first glass layer having a first coefficient of thermal expansion (CTE), a second glass layer of a different type from the first glass layer, the second glass layer having a second CTE, and a build-up region having a third CTE, the build-up region being between the semiconductor die and the first glass layer, the first glass layer being between the build-up region and the second glass layer, the first CTE being closer to the third CTE than the second CTE relative to the third CTE, and a power supply interconnect extending through the first and second glass layers, the power supply interconnect comprising a magnetic material.

[0207] Example 54 includes the IC package of Example 53, further comprising an adhesive material between a first glass layer and a second glass layer, the adhesive material in contact with a first surface of the first glass layer and a second surface of the second glass layer.

[0208] Example 55 includes the IC package of Example 54, further comprising a first conductive pad and a second conductive pad, with an adhesive material located between the first and second conductive pads.

[0209] Example 56 includes the IC package of Example 55 and further comprises conductive vias that electrically connect the first and second conductive pads.

[0210] Example 57 includes a device comprising a package substrate comprising a semiconductor chip mounted on a package substrate, the stack of glass layers, the adjacent glass layers having different compositions of materials associated with different coefficients of thermal expansion (CTE), and plated magnetic vias, the plated magnetic vias comprising a magnetic material, passing at least partially through the stack of glass layers.

[0211] Example 58 includes the apparatus of Example 57, wherein the glass layer in the stack defines a CTE gradient that is symmetrical across the stack.

[0212] Example 59 includes the apparatus of either Example 57 or 58, further comprising a dielectric material between adjacent glass layers.

[0213] Example 60 includes any one of the devices from Examples 57 to 59, further comprising at least one of a keyboard or a display.

[0214] The following claims are incorporated herein by reference. Certain exemplary systems, apparatus, products, and methods are disclosed herein, but the scope of this patent is not limited thereto. Conversely, this patent encompasses all systems, apparatus, products, and methods that fall in any way within the scope of these claims. Other possible items (Item 1) A substrate for integrated circuit packages: A first glass layer having a first coefficient of thermal expansion (CTE); A second glass layer having a second CTE, wherein the second CTE is different from the first CTE. A conductive material extending at least partially through the first hole in the first glass layer and the second hole in the second glass layer; and Magnetic material between the inner wall of the first hole and the conductive material A circuit board equipped with the following features. (Item 2) The conductive material and the magnetic material define a coaxial magnetic inductor loop (CMIL), as described in item 1. (Item 3) The substrate according to item 2, further comprising a non-magnetic plug within the CMIL, wherein the conductive material surrounds the non-magnetic plug and the magnetic material surrounds the conductive material. (Item 4) The substrate according to item 2, wherein the CMIL is a first CMIL, the substrate includes a second CMIL adjacent to the first CMIL, and both the first and second CMILs extend through the first and second holes of their respective first and second glass layers. (Item 5) The substrate according to item 1, further comprising a dielectric material between the first glass layer and the second glass layer. (Item 6) The dielectric material has a lower elastic modulus than the first glass layer, as described in item 5. (Item 7) The dielectric material includes an organic dielectric, as described in item 5. (Item 8) The dielectric material is the substrate according to item 7, comprising at least one of parylene or polyimide. (Item 9) The dielectric material includes an inorganic dielectric, as described in item 5. (Item 10) The dielectric material is the substrate according to item 9, comprising at least one of silicon, oxygen, or nitrogen. (Item 11) First build-up area; Second build-up area; A stack of multiple glass layers between the first and second build-up regions, the different glass layers having different coefficients of thermal expansion (CTE); and A power supply interconnect passing through the stack of the plurality of glass layers, the power supply interconnect comprising at least one of nickel, iron, or cobalt, An integrated circuit (IC) package that includes [a specific feature / feature]. (Item 12) The IC package according to item 11, wherein the glass layer comprises a first glass layer having a first CTE, a second glass layer having a second CTE, and a third glass layer having a third CTE, wherein the second glass layer is of a different type from the first glass layer, and the third glass layer is of a different type from both the first and second glass layers. (Item 13) The IC package according to item 12, wherein the first glass layer is adjacent to the first build-up region, the second glass layer is adjacent to the second build-up region, the third glass layer is between the first and second glass layers, the first build-up region has a fifth CTE, the second build-up region has a sixth CTE, the first CTE is closer to the fifth CTE than the third CTE is closer to the fifth CTE, and the second CTE is closer to the sixth CTE than the third CTE is closer to the sixth CTE. (Item 14) The IC package according to item 13, further comprising a fourth glass layer between the first glass layer and the third glass layer, wherein the fourth glass layer has a seventh CTE between the first CTE and the third CTE. (Item 15) The IC package described in item 12, wherein the second CTE corresponds to the first CTE, and the first CTE is higher than the third CTE. (Item 16) The IC package according to item 12, wherein the third glass layer has a third CTE that is different from the first CTE and different from the second CTE. (Item 17) The IC package according to item 12, wherein the different CTEs of the glass layer define a symmetrical CTE gradient. (Item 18) Semiconductor die; A package substrate supporting the semiconductor die, the package substrate comprising a stack of glass layers, wherein the first of the glass layers has a different coefficient of thermal expansion (CTE) than the second of the glass layers; and A magnetic inductor extending through the stack of glass layers, the magnetic inductor including a non-magnetic core, A device equipped with the following features. (Item 19) The apparatus according to item 18, wherein the first segment of the non-magnetic core extends through a first hole passing through the first glass layer, and the second segment of the non-magnetic core extends through a second hole passing through the second glass layer. (Item 20) The apparatus according to item 19, further comprising a magnetic material surrounding the non-magnetic core, wherein the magnetic material extends continuously from within the first hole in the first glass layer to within the second hole in the second glass layer.

Claims

1. A substrate for integrated circuit packages: A first glass layer having a first coefficient of thermal expansion (CTE); A second glass layer having a second CTE, wherein the second CTE is different from the first CTE; A conductive material extending at least partially through the first hole in the first glass layer and the second hole in the second glass layer; and Magnetic material between the inner wall of the first hole and the conductive material A circuit board equipped with the following features.

2. The substrate according to claim 1, wherein the conductive material and the magnetic material define a coaxial magnetic inductor loop (CMIL).

3. The substrate according to claim 2, further comprising a non-magnetic plug within the CMIL, wherein the conductive material surrounds the non-magnetic plug and the magnetic material surrounds the conductive material.

4. The substrate according to claim 2 or 3, wherein the CMIL is a first CMIL, the substrate includes a second CMIL adjacent to the first CMIL, and both the first CMIL and the second CMIL extend through the first and second holes of the respective first and second glass layers.

5. The substrate according to claim 1 or 2, further comprising a dielectric material between the first glass layer and the second glass layer.

6. The substrate according to claim 5, wherein the dielectric material has a lower elastic modulus than the first glass layer.

7. The substrate according to claim 5, wherein the dielectric material includes an organic dielectric.

8. The substrate according to claim 7, wherein the dielectric material comprises at least one of parylene or polyimide.

9. The substrate according to claim 5, wherein the dielectric material includes an inorganic dielectric.

10. The substrate according to claim 9, wherein the dielectric material comprises at least one of silicon, oxygen, or nitrogen.

11. An integrated circuit (IC) package, First build-up area; Second build-up area; A stack of multiple glass layers between the first build-up region and the second build-up region, the different glass layers having different coefficients of thermal expansion (CTE); and A power supply interconnect passing through the stack of the plurality of glass layers, the power supply interconnect comprising at least one of nickel, iron, or cobalt, An IC package equipped with the following features.

12. The IC package according to claim 11, wherein the glass layer comprises a first glass layer having a first CTE, a second glass layer having a second CTE, and a third glass layer having a third CTE, wherein the second glass layer is of a different type from the first glass layer, the third glass layer is of a different type from the first glass layer, and the third glass layer is of a different type from the second glass layer.

13. The IC package according to claim 12, wherein the first glass layer is adjacent to the first build-up region, the second glass layer is adjacent to the second build-up region, the third glass layer is between the first glass layer and the second glass layer, the first build-up region has a fifth CTE, the second build-up region has a sixth CTE, the first CTE is closer to the fifth CTE than the third CTE is closer to the fifth CTE, and the second CTE is closer to the sixth CTE than the third CTE is closer to the sixth CTE.

14. The IC package according to claim 13, further comprising a fourth glass layer between the first glass layer and the third glass layer, wherein the fourth glass layer has a seventh CTE between the first CTE and the third CTE.

15. The IC package according to any one of claims 12 to 14, wherein the second CTE corresponds to the first CTE, and the first CTE is higher than the third CTE.

16. The IC package according to any one of claims 12 to 14, wherein the third CTE differs from the first CTE and the second CTE.

17. The IC package according to any one of claims 12 to 14, wherein the different CTEs of the glass layer define a symmetrical CTE gradient.

18. Semiconductor die; A package substrate supporting the semiconductor die, the package substrate comprising a stack of glass layers, wherein the first of the glass layers has a different coefficient of thermal expansion (CTE) than the second of the glass layers; and A magnetic inductor extending through the stack of glass layers, the magnetic inductor including a non-magnetic core, A device equipped with the following features.

19. The apparatus according to claim 18, wherein the first segment of the non-magnetic core extends through a first hole passing through the first glass layer, and the second segment of the non-magnetic core extends through a second hole passing through the second glass layer.

20. The apparatus according to claim 19, further comprising a magnetic material surrounding the non-magnetic core, wherein the magnetic material extends continuously from within the first hole in the first glass layer to within the second hole in the second glass layer.

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