Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can avoid the effects of variations in the gate resistance of multiple gate structures without incurring losses. [Solution] The semiconductor device 1 includes a chip 2 having a first main surface 3 including an active region 6, an n-type drift region 9 formed on the chip 2, a p-type body region 41 formed on the surface of the drift region 9, an n-type source region 42 formed on the surface of the body region 41, a plurality of gate structures 45 formed opposite the body region 41 and forming channels in the body region 41, an interlayer film 13 covering the plurality of gate structures 45, gate wiring 25 formed on the interlayer film 13, and a plurality of resistive film portions 81 embedded in the interlayer film 13. The resistive film portions 81 are connected to both the gate structures 45 and the gate wiring 25.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising a chip having a first main surface on one side and a second main surface on the other side, a plurality of trench gate structures formed on the first main surface, a main surface insulating film covering the first main surface, a top inorganic film covering the main surface insulating film and the plurality of trench gate structures, and gate wiring electrodes. The gate wiring electrodes are electrodes drawn out from the gate main surface electrodes. The gate wiring electrodes are connected to the plurality of gate structures through gate openings formed in the top inorganic film. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2022 / 024813

[0004] [overview] One embodiment of the present disclosure provides a semiconductor device comprising: a chip having a first main surface including an active region; a first impurity region of a first conductivity type formed on the chip; a second impurity region of a second conductivity type formed on the surface of the first impurity region; a third impurity region of a first conductivity type formed on the surface of the second impurity region; a plurality of gate structures formed in the active region opposite to the second impurity region and forming channels in the second impurity region; an interlayer film covering the plurality of gate structures; a gate electrode film formed on the interlayer film; and a plurality of resistive film portions embedded in the interlayer film. The resistive film portions may be connected to both the gate structures and the gate electrode film. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a plan view of a semiconductor device according to the first embodiment of this disclosure. [Figure 2] Figure 2 is a cross-sectional view of the semiconductor device. [Figure 3] Figure 3 is a plan view showing the layout of the main surface electrode film. [Figure 4] Figure 4 is a plan view showing the layout of the first main surface of the semiconductor device. [Figure 5] Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 4. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5. [Figure 7] Figure 7 is an enlarged view of the area enclosed by the dashed line VII in Figure 4. [Figure 8] Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. [Figure 9] Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 7. [Figure 10] Figure 10 is a cross-sectional view along the line XX shown in Figure 7. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 7. [Figure 12] Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 7. [Figure 13] Figure 13 is a schematic diagram showing a wafer used in the manufacture of the semiconductor device. [Figure 14A] Figure 14A is a cross-sectional view showing the manufacturing method of the semiconductor device. [Figure 14B] Figure 14B is a cross-sectional view showing a process after Figure 14A. [Figure 14C] Figure 14C is a cross-sectional view showing a process after Figure 14B. [Figure 14D] Figure 14D is a cross-sectional view showing a process after Figure 14C. [Figure 14E] Figure 14E is a cross-sectional view showing a process after Figure 14D. [Figure 14F] Figure 14F is a cross-sectional view showing a process after Figure 14E. [Figure 14G] Figure 14G is a cross-sectional view showing a process after Figure 14F. [Figure 14H] FIG. 14H is a cross-sectional view showing the process after FIG. 14G. [Figure 14I] FIG. 14I is a cross-sectional view showing the process after FIG. 14H. [Figure 14J] FIG. 14J is a cross-sectional view showing the process after FIG. 14I. [Figure 14K] FIG. 14K is a cross-sectional view showing the process after FIG. 14J. [Figure 15] FIG. 15 is a cross-sectional view showing a main part of the semiconductor device according to the second embodiment of the present disclosure. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device according to a second exemplary form in which the number of second contact openings is changed. [Figure 18] FIG. 18 is a cross-sectional view of a semiconductor device according to a modified example in which the configuration of a plurality of resistor film portions is changed.

[0006] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] All of the accompanying drawings are schematic diagrams, not strictly illustrated, and scales, ratios, angles, etc. do not necessarily match. The same reference numerals are assigned to corresponding structures among the accompanying drawings, and duplicate explanations are omitted or simplified. For structures with explanations omitted or simplified, the explanations made before the omission or simplification apply.

[0008] When the term "substantially" is used in this specification, this term includes not only a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, but also a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first", "second", "third", etc. are used, but these are symbols attached to the names of each structure for clarifying the order of explanation and are not attached for the purpose of limiting the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is the conductivity type due to pentavalent elements, and "p-type" is the conductivity type due to trivalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] Figure 1 is a plan view of a semiconductor device 1 according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view of the semiconductor device 1. Figure 3 is a plan view showing the layout of the main surface electrode film 14. Figure 4 is a plan view showing the layout of the first main surface 3 of the semiconductor device 1. Figure 2 shows a cross-section along the line II-II in Figure 3. In Figure 2, the surface insulating film 34 is not shown.

[0011] The semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr (Figures 2 and 4) as an example of a device structure. The transistor structure Tr has a trench gate type vertical structure (trench structure).

[0012] Referring to Figures 1 to 4, the semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1 is a "wide-bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0013] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1 is a "SiC semiconductor device".

[0014] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side (Figure 2), and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first principal surface 3 and the second principal surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first principal surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second principal surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal. The first principal surface 3 and the second principal surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and 10° or less. The off-angle is preferably 5° or less.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this configuration, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0019] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0020] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0021] Referring to Figure 2, the semiconductor device 1 (chip 2) includes an n-type first semiconductor layer 6 formed on the surface layer of the second main surface 4. The first semiconductor layer 6 is given a drain potential as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)", "base region (layer)", "drain region (layer)", etc.

[0022] The first semiconductor layer 6 extends in layers along the second main surface 4, forming the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 consists of a SiC substrate (substrate) containing a SiC single crystal (semiconductor single crystal), and has a second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 consists of a substrate made of a SiC single crystal (i.e., a SiC substrate).

[0023] The first semiconductor layer 6 is 1 × 10 18 cm -3 The above 1 x 10 21 cm -3 The following n-type impurity concentrations may be present as peak values. Preferably, the first semiconductor layer 6 has a nearly constant n-type impurity concentration in the thickness direction.

[0024] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or more and 500 μm or less.

[0025] The semiconductor device 1 includes a drain pad electrode 7 that covers the second main surface 4. The drain pad electrode 7 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 7 forms ohmic contact with the first semiconductor layer 6.

[0026] The drain pad electrode 7 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). Alternatively, the drain pad electrode 7 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0027] Referring to Figure 2, the semiconductor device 1 (chip 2) includes an n-type second semiconductor layer 8 formed on the surface layer of the first main surface 3. The second semiconductor layer 8 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor layer 8 extends in layers along the first main surface 3 and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0028] In this configuration, the second semiconductor layer 8 consists of an n-type semiconductor layer. The second semiconductor layer 8 may also consist of an epitaxial layer containing a SiC single crystal (semiconductor single crystal) (i.e., a SiC epitaxial layer). The second semiconductor layer 8 consists of an epitaxial layer (SiC epitaxial layer) that has been crystallized starting from the first semiconductor layer 6.

[0029] The second semiconductor layer 8 has a lower end and an upper end. The lower end of the second semiconductor layer 8 is the crystal growth starting point, and the upper end of the second semiconductor layer 8 is the crystal growth ending point. The lower end of the second semiconductor layer 8 is also the bottom of the second semiconductor layer 8. Since the second semiconductor layer 8 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 8 coincides with the upper end of the first semiconductor layer 6.

[0030] The second semiconductor layer 8 includes an n-type drift region 9 as an example of a first impurity region. In this embodiment, the drift region 9 is formed by a part (n-type portion) of the second semiconductor layer 8. Preferably, the second semiconductor layer 8 has a substantially constant n-type impurity concentration in the thickness direction. The second semiconductor layer 8 may have a lower n-type impurity concentration than the first semiconductor layer 6.

[0031] The second semiconductor layer 8 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 8 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor layer 8 may have a value that falls within at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0032] Referring to Figures 2 to 4, the semiconductor device 1 includes an active region 10 and an outer peripheral region 11 set on the first main surface 3 of the chip 2.

[0033] Referring to Figures 2 and 4, the active region 10 is a region (element region) that includes the device structure (i.e., the transistor structure Tr) and generates an output current (drain current). In a plan view, the active region 10 is set in the inner part of the chip 2, spaced apart from the periphery of the chip 2 (first to fourth sides 5A to 5D). In a plan view, the active region 10 is formed in a polygonal shape with sides parallel to the periphery of the chip 2. In this embodiment, in a plan view, the active region 10 is formed in a polygonal shape with recesses along the gate pad electrodes 24 (described later). The active region 10 may also be formed in a quadrilateral shape in a plan view. Preferably, the planar area of ​​the active region 10 is 50% to 90% of the planar area of ​​the first main surface 3.

[0034] The outer peripheral region 11 is a region that does not include the device structure (transistor structure Tr). In a plan view, the outer peripheral region 11 is located in the region between the periphery of the chip 2 and the active region 10. In a plan view, the outer peripheral region 11 extends in a band shape along the active region 10 and is set up as a polygonal ring (a quadrilateral ring in this form) surrounding the active region 10.

[0035] Referring to Figure 3, the semiconductor device 1 includes a plurality of gate structures 45 formed on the first main surface 3 in the active region 10. A gate potential is applied to the plurality of gate structures 45 as a control potential. In this embodiment, the plurality of gate structures 45 are arranged at intervals in the second direction Y (m-axis direction) and are formed in a strip shape extending in the first direction X (a-axis direction). In this embodiment, the plurality of gate structures 45 are arranged in a stripe shape extending in the a-axis direction (first direction X). The direction of extension of the plurality of gate structures 45 coincides with the off direction of the chip 2.

[0036] Referring to Figure 3, the semiconductor device 1 includes an interlayer film 13 covering the first main surface 3. In Figure 3, the interlayer film 13 is shown as a white area. The interlayer film 13 may, for example, be formed over the entire first main surface 3. The interlayer film 13 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 13 may be referred to as an "insulating film," "interlayer insulating film," "insulating layer," "intermediate insulating film," etc.

[0037] Referring to Figure 3, the semiconductor device 1 includes a main surface electrode film 14 disposed on the interlayer film 13. In Figure 3, the main surface electrode film 14 is shown as a hatched area. To clarify the positional relationship between the plan view of the semiconductor device 1, the layout of the first main surface 3, and the main surface electrode film 14, the outline of the main surface electrode film 14 is shown as a dashed line in Figures 1 and 4.

[0038] Referring to Figure 3, the main surface electrode film 14 includes a source electrode film 15 and a gate electrode film 16.

[0039] The source electrode film 15 is a film that is physically and electrically isolated from the gate electrode film 16. The source electrode film 15 is positioned on the interlayer film 13 at a distance from the gate electrode film 16.

[0040] The source electrode film 15 includes a source pad electrode 17 and a source wiring 18. The source pad electrode 17 is an electrode to which a source potential is applied from the outside. The source pad electrode 17 may also be referred to as the "first main surface electrode," "source pad electrode," "source metal," "first pad electrode," etc.

[0041] The source pad electrode 17 is formed from a metallic material containing Al (aluminum). The source pad electrode 17 contains an Al-based metal film. The source pad electrode 17 may contain at least one of the following: a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0042] In this embodiment, the source pad electrode 17 is positioned on the active region 10 in a plan view. The source pad electrode 17 is formed in a polygonal shape in a plan view. The source pad electrode 17 includes a first source electrode 19 and a second source electrode 20 that are separated from each other.

[0043] In this embodiment, the source pad electrode 17 includes a first source electrode 19 positioned in a region on the third side surface 5C side of the center position in the first direction X of the active region 10 (first main surface 3), and a second source electrode 20 positioned in a region on the fourth side surface 5D side of the center position. The first source electrode 19 and the second source electrode 20 may be connected to each other at their ends on the second side surface 5B side.

[0044] The source wiring 18 is supplied with the same potential (source potential) as the potential supplied to the source pad electrode 17. The source pad electrode 17 may also be referred to as a "termination electrode (wiring)", "finger electrode", "source finger", etc.

[0045] The source wiring 18 has a wiring width less than the electrode width of the source pad electrode 17 and is selectively routed on the interlayer film 13. In this configuration, the source wiring 18 is led out from the source pad electrode 17 towards the second side surface 5B. The source wiring 18 is led out from the active region 10 to the outer peripheral region 11. In order to secure the area for arranging the source wiring 18, the width of the outer peripheral region 11 is wider than in the case of the semiconductor device 1 shown in Figure 2.

[0046] The source wiring 18 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 10). In this embodiment, the source wiring 18 is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 10). The source wiring 18 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The source wiring 18 may be end-bound or endless.

[0047] Referring to Figure 3, the gate electrode film 16 is an electrode to which a gate potential is applied from the outside. The gate electrode film 16 may also be referred to as the "second main surface electrode," "gate pad electrode," "gate metal," "second pad electrode," etc.

[0048] The gate electrode film 16 is formed from a metallic material containing Al (aluminum). The gate electrode film 16 includes an Al-based metal film. The gate electrode film 16 may also include at least one of the following: a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0049] The gate electrode film 16 includes a gate pad electrode 24 and gate wiring 25. In this embodiment, the gate pad electrode 24 is located on the outer peripheral region 11. Specifically, the gate pad electrode 24 is located in a region adjacent to the center of one side (first side surface 5A in this embodiment) of the first main surface 3 in a plan view. The gate pad electrode 24 is located in a recess formed in the source pad electrode 17. The gate pad electrode 24 may be located in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 24 may be located at any corner C of the chip 2 on the first main surface 3 in a plan view. The gate pad electrode 24 may be located in the center of the first main surface 3 in a plan view. The gate pad electrode 24 may be located on the active region 10. In this embodiment, the gate pad electrode 24 is formed in a square shape in a plan view.

[0050] The gate wiring 25 is routed from the gate pad electrode 24 around the active region 10, encircling the active region 10. The gate wiring 25 transmits the gate potential applied to the gate pad electrode 24 to the multiple gate structures 45.

[0051] The gate wiring 25 includes a base wiring 26 and finger wiring 27. The base wiring 26 surrounds the gate pad electrode 24 in a plan view. In this embodiment, the base wiring 26 is a rectangular annular shape extending in a first direction X and a second direction Y.

[0052] The finger wiring 27 extends outward in a strip shape from the outer edge of the annular base wiring 26. The semiconductor device 1 includes a plurality of finger wirings 28-30 extending outward in strip shapes from the outer edge of the base wiring 26 in different directions. The plurality of finger wirings 28-30 are arranged in a non-parallel relationship with respect to each other. The plurality of finger wirings 28-30 may include a first finger wiring 28, a second finger wiring 29, and a third finger wiring 30.

[0053] The first finger wiring 28 and the second finger wiring 29 extend from the base wiring 26 in opposite directions along the periphery of the chip 2, collectively surrounding the source pad electrode 17. The first finger wiring 28 and the second finger wiring 29 are examples of gate periphery wiring.

[0054] In this configuration, the first finger wiring 28 extends from the base wiring 26 along the first side 5A, third side 5C, and second side 5B in the first direction X, and has a first tip 31 in the center of the fourth side 5D in the first direction X. The second finger wiring 29 extends from the base wiring 26 along the first side 5A, fourth side 5D, and second side 5B in the first direction X, and has a second tip 32 in the center of the fourth side 5D in the first direction X. The first tip 31 and the second tip 32 face each other with space between them in the first direction X.

[0055] The first finger wiring 28 is formed in a substantially U shape and has a corner at a position corresponding to the corner C of the chip 2. The first finger wiring 28 may also be referred to as, for example, "first outer peripheral wiring," "first outer peripheral electrode," "first outer peripheral finger wiring," or "first outer peripheral finger electrode." The second finger wiring 29 is formed in a substantially U shape and has a corner at a position corresponding to the corner C of the chip 2. The second finger wiring 29 may also be referred to as, for example, "second outer peripheral wiring," "second outer peripheral electrode," "second outer peripheral finger wiring," or "second outer peripheral finger electrode." The first finger wiring 28 and the second finger wiring 29 may be collectively referred to as "outer peripheral wiring," "outer peripheral electrode," "outer peripheral finger wiring," or "outer peripheral finger electrode" surrounding the active region 10.

[0056] The third finger wiring 30 extends from the base wiring 26 toward the center of the chip 2 and crosses the source pad electrode 17. In other words, the third finger wiring 30 extends toward the center of the chip 2 and crosses the active region 10. The third finger wiring 30 is an example of gate central wiring. The third finger wiring 30 extends from the base wiring 26 toward the second side 5B and may divide the source pad electrode 17 into a first source electrode 19 and a second source electrode 20. The third finger wiring 30 has a third tip portion 33 inside the region enclosed by the first finger wiring 28 and the second finger wiring 29. The third finger wiring 30 may be referred to, for example, "central wiring," "central electrode," "central finger wiring," "central finger electrode," etc.

[0057] Referring to Figure 1, the semiconductor device 1 includes a surface insulating film 34 that selectively covers the main surface electrode film 14 and the interlayer film 13 on the first main surface 3. The surface insulating film 34 includes a gate pad opening 36 that exposes a portion of the gate pad electrode 24 as a gate pad 35. The surface insulating film 34 covers the periphery of the gate pad electrode 24 and the entire area of ​​the gate wiring 25. The gate pad opening 36 is formed in a rectangular shape in plan view.

[0058] The surface insulating film 34 includes a first source pad opening 38 that exposes a portion of the first source electrode 19 as a first source pad 37, and a second source pad opening 40 that exposes a portion of the second source electrode 20 as a second source pad 39. The surface insulating film 34 covers the peripheral edges of the first source electrode 19 and the second source electrode 20.

[0059] The first source pad opening 38 is formed in a polygonal shape that follows the periphery of the first source electrode 19 in a plan view. The second source pad opening 40 is formed in a polygonal shape that follows the periphery of the second source electrode 20 in a plan view. Preferably, the planar area of ​​the first source pad opening 38 and the second source pad opening 40 is larger than the planar area of ​​the gate pad opening 36.

[0060] The surface insulating film 34 may have a laminated structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side. The surface insulating film 34 only needs to include at least one of the inorganic insulating film and the organic insulating film, and does not necessarily need to include both simultaneously. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the inorganic insulating film includes an insulating material different from the interlayer film 13. The organic insulating film is preferably a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0061] Referring to Figure 2, an outer well region 70 is formed in the outer peripheral region 11 of the first main surface 3. The outer well region 70 includes a first outer well region 71 and a plurality of second outer well regions 72. The first outer well region 71 and the plurality of second outer well regions 72 may be referred to as "termination regions" and "field regions," respectively. Alternatively, the first outer well region 71 and the plurality of second outer well regions 72 may be collectively referred to as the "outer well region." The first outer well region 71 may be referred to as the "termination well region," "JTE region (Junction Termination Extension region)," etc. The second outer well regions 72 may be referred to as the "guard region," "field limit region," etc. In Figure 4, the outer well region 70 is omitted from the illustration for illustrative purposes.

[0062] In this configuration, the first outer well region 71 is formed as a polygonal ring (quadrilateral ring) with four sides parallel to the periphery of the chip 2. In this configuration, the first outer well region 71 is formed in the outer peripheral region 11 and surrounds the active region 10. A source potential is applied to the first outer well region 71. When a reverse bias voltage is applied, the first outer well region 71 expands a depletion layer in the second semiconductor layer 8. The depletion layer, originating from the first outer well region 71, expands in the horizontal and thickness directions, mitigating the electric field near the boundary between the active region 10 and the outer peripheral region 11.

[0063] In this configuration, the multiple second outer well regions 72 are formed in a polygonal ring (quadrilateral ring) shape with four sides parallel to the periphery of the chip 2. The multiple second outer well regions 72 surround the first outer well region 71. The multiple second outer well regions 72 are formed in an electrically floating state. The multiple second outer well regions 72 extend the depletion layer, which originates from the first outer well region 71, toward the periphery of the first main surface 3, thereby mitigating the electric field at the periphery (outer outer region 11) of the first main surface 3.

[0064] Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 4. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5.

[0065] Referring to Figure 6, the semiconductor device 1 includes a p-type body region 41 formed on the surface of the first main surface 3 in the active region 10. The body region 41 is an example of a second impurity region. The body region 41 may also be called an "impurity region," "channel region," etc. A source potential may be applied to the body region 41. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be the ground potential. The body region 41 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 8. The body region 41 has, for example, 1 × 10 17 cm -3 The above 1 x 10 18 cm -3 The following p-type impurity concentrations may be present as peak values.

[0066] The body region 41 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this configuration, the body region 41 is formed over the entire area of ​​the active region 10. The body region 41 is formed on the surface of the second semiconductor layer 8 and extends in layers along the first main surface 3. The body region 41 does not necessarily have to be formed in the outer peripheral region 11.

[0067] The body region 41 is formed with a gap from the bottom of the second semiconductor layer 8 (first semiconductor layer 6) toward the first main surface 3, and faces the first semiconductor layer 6 with a portion of the second semiconductor layer 8 in between. The body region 41 is formed with a gap from the depth position of the middle part of the second semiconductor layer 8 toward the first main surface 3.

[0068] The body region 41 is formed in the region on the first main surface 3 side of the second semiconductor layer 8 in a cross-sectional view and is electrically connected to the second semiconductor layer 8. The body region 41 forms a pn junction (body diode) with the second semiconductor layer 8. When a reverse bias voltage is applied, the body region 41 expands a depletion layer in the second semiconductor layer 8. The depletion layer, starting from the body region 41, expands horizontally and in the thickness direction within the second semiconductor layer 8.

[0069] Referring to Figures 5 and 6, the semiconductor device 1 includes an n-type source region 42 formed on the surface of the first main surface 3 in the active region 10. The source region 42 is an example of a third impurity region. A source potential is applied to the source region 42. The source region 42 has an n-type impurity concentration higher than the p-type impurity concentration of the second semiconductor layer 8. The n-type impurity concentration of the source region 42 is higher than the p-type impurity concentration of the body region 41.

[0070] The source region 42 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 11. The source region 42 may also be formed inward from the periphery of the body region 41, spaced apart. The source region 42 is formed in the surface layer of the body region 41 and extends in layers along the first main surface 3.

[0071] The source region 42 is formed at a distance from the bottom of the body region 41 toward the first main surface 3, and faces the second semiconductor layer 8 across a portion of the body region 41. In a cross-sectional view, the source region 42 is formed in the region on the first main surface 3 side of the body region 41 and is electrically connected to the body region 41.

[0072] Referring to Figures 5 and 6, as described above, the semiconductor device 1 includes a plurality of trench-type gate structures 45 formed on the first main surface 3 in the active region 10. A gate potential is applied to the plurality of gate structures 45 as a control potential. The plurality of gate structures 45 control the inversion and non-inversion of the channel within the body region 41 in response to the gate potential.

[0073] As shown in Figure 5, the multiple gate structures 45 are arranged on the first main surface 3 at intervals extending inward from the periphery of the first main surface 3. Each gate structure 45 extends in a strip-like shape in the first direction X in a plan view. The multiple gate structures 45 are arranged at intervals in the second direction Y. In other words, the multiple gate structures 45 are arranged in a stripe-like pattern extending in the first direction X in a plan view.

[0074] As shown in Figure 6, the multiple gate structures 45 penetrate the body region 41 and the source region 42 so as to reach the second semiconductor layer 8. In other words, the body region 41 and the source region 42 are located on both sides of each gate structure 45. Each gate structure 45 is formed with a gap from the bottom of the second semiconductor layer 8 toward the first main surface 3, and faces the first semiconductor layer 6 with a portion of the second semiconductor layer 8 in between.

[0075] The sidewalls of each gate structure 45 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The sidewalls of each gate structure 45 are formed substantially perpendicular to the first main surface 3. The bottom wall of each gate structure 45 is formed by the c-plane (Si plane) of the SiC single crystal. Preferably, the bottom wall of each gate structure 45 extends substantially flat along the horizontal direction.

[0076] One gate structure 45 comprises a gate trench 46, a first trench insulating film 47, and a gate embedded electrode 48. The gate trench 46 is formed on the first main surface 3 and defines the wall surface (side wall and bottom wall) of the gate structure 45. The first trench insulating film 47 covers the wall surface of the gate trench 46. The first trench insulating film 47 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first trench insulating film 47 contains a silicon oxide film made of the oxide of the chip 2.

[0077] The gate embedded electrode 48 is embedded in the gate trench 46 with the first trench insulating film 47 in between. The gate embedded electrode 48 faces the channel region 44 with the first trench insulating film 47 in between. In other words, the gate embedded electrode 48 faces the second semiconductor layer 8, the body region 41, and the source region 42 with the first trench insulating film 47 in between.

[0078] The gate-embedded electrode 48 is made of conductive polysilicon (polysilicon). The gate-embedded electrode 48 includes either or both p-type conductive polysilicon and n-type conductive polysilicon. In this embodiment, the gate-embedded electrode 48 has p-type. The gate-embedded electrode 48 is formed by a deposit layer of doped polysilicon.

[0079] Each gate structure 45 includes a channel region 44 (Figure 6) formed between the source region 42 and the drift region 9 within the body region 41. The inversion and non-inversion of this channel region 44 are controlled by the gate structure 45. Multiple channel regions 44 are provided. Each of the multiple channel regions 44 forms a current path connecting the source region 42 and the drift region 9 along the side surface of each gate structure 45 within the body region 41.

[0080] The semiconductor device 1 includes a plurality of first trench source structures 50 formed on the first main surface 3 in the active region 10. A source potential is applied to the plurality of first trench source structures 50.

[0081] Multiple first trench source structures 50 are formed on the first main surface 3 in the active region 10 so as to be adjacent to multiple gate structures 45 in the second direction Y. Specifically, each first trench source structure 50 is located in the regions between adjacent gate structures 45. Multiple first trench source structures 50 face multiple gate structures 45 in the second direction Y. In other words, in this configuration, multiple first trench source structures 50 are arranged alternately with multiple gate structures 45 in the second direction Y.

[0082] As shown in Figure 5, each first trench source structure 50 extends in a strip shape in the first direction X in a plan view. Each first trench source structure 50 faces the gate structure 45 in the second direction Y in the active region 10. As shown in Figures 6 and 7, each first trench source structure 50 penetrates the body region 41 and the source region 42 to reach the second semiconductor layer 8. In other words, the body region 41 and the source region 42 are located on both sides of each first trench source structure 50.

[0083] A first trench source structure 50 comprises a first source trench 51, a second trench insulating film 52, and a first source embedded electrode 53. The first source trench 51 is formed on the first main surface 3 and defines the walls (side walls and bottom walls) of the first trench source structure 50. The second trench insulating film 52 covers the walls of the first source trench 51. The second trench insulating film 52 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0084] The first source embedded electrode 53 is embedded in the first source trench 51 with the second trench insulating film 52 in between. The first source embedded electrode 53 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the first source embedded electrode 53 contains the same conductive material as the gate embedded electrode 48. The first source embedded electrode 53 faces the second semiconductor layer 8, the body region 41, and the source region 42 with the second trench insulating film 52 in between.

[0085] The ends of the multiple first trench source structures 50 are led out from the active region 10 to the outer peripheral region 11. The ends of the multiple first trench source structures 50 are connected to source underlayment wiring (not shown) formed below the portion of the source wiring 18 (Figure 3) that extends along the third side 5C and the fourth side 5D. The multiple first trench source structures 50 are electrically connected to the source wiring 18 (Figure 3) via the source underlayment wiring.

[0086] Referring to Figures 5 and 6, the semiconductor device 1 includes a plurality of p-type first well regions 55 formed in the surface layer of the first main surface 3 of the active region 10, along the plurality of gate structures 45. The p-type impurity concentration in the first well regions 55 is higher than the p-type impurity concentration in the body region 41.

[0087] Each first well region 55 is formed along the side and bottom walls of the corresponding gate structure 45 and is electrically connected to the body region 41 at the surface of the first main surface 3. Multiple first well regions 55 are formed at intervals from the bottom of the second semiconductor layer 8 toward the first main surface 3 and face the first semiconductor layer 6 with a portion of the second semiconductor layer 8 in between. Multiple first well regions 55 form a pn junction with the second semiconductor layer 8.

[0088] Referring to Figures 5 and 6, the semiconductor device 1 includes a plurality of p-type second well regions 56 formed in the surface layer of the first main surface 3 of the active region 10, along the plurality of first trench source structures 50. The p-type impurity concentration in the second well regions 56 is higher than that in the body region 41. The plurality of second well regions 56 are formed in a one-to-one correspondence with the plurality of first trench source structures 50. Each second well region 56 is formed in a region along the corresponding first trench source structure 50, spaced apart from the plurality of gate structures 45. Each second well region 56 is formed along the side and bottom walls of the corresponding first trench source structure 50 and is electrically connected to the body region 41 in the surface layer of the first main surface 3. Each second well region 56 extends along the wall surface of the first trench source structure 50.

[0089] Multiple second well regions 56 are formed at intervals from the bottom of the second semiconductor layer 8 toward the first main surface 3, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 8 in between. The bottoms of the multiple second well regions 56 are located on the bottom side of the second semiconductor layer 8 with respect to the depth position of the bottoms of the multiple first well regions 55. The multiple second well regions 56 form a pn junction with the second semiconductor layer 8.

[0090] Referring to Figures 5 and 6, the semiconductor device 1 includes a plurality of p-type body contact regions 57 formed in the surface layer of the first main surface 3 of the active region 10, along a plurality of second well regions 56. The body contact regions 57 have a higher p-type impurity concentration than the body region 41. The p-type impurity concentration of the body contact regions 57 is higher than the p-type impurity concentration of the second well region 56 (first well region 55).

[0091] Each body contact region 57 is formed within a second well region 56. Each body contact region 57 extends along the wall surface of the corresponding first trench source structure 50 within the corresponding second well region 56. Each body contact region 57 is formed in a one-to-many correspondence with one corresponding first trench source structure 50. Each body contact region 57 is formed spaced apart in a first direction X along the corresponding first trench source structure 50. Each body contact region 57 is drawn out to the surface of the body region 41 along the wall surface of the corresponding first trench source structure 50 within the corresponding second well region 56 and is exposed from the first main surface 3.

[0092] In this embodiment, each body contact region 57 extends in a strip-like shape in a first direction X in a plan view. Multiple body contact regions 57 along one first trench source structure 50 are opposite to multiple body contact regions 57 along other first trench source structures 50 in a second direction Y.

[0093] Referring to Figures 5 and 6, the semiconductor device 1 includes an insulating main surface insulating layer 77 that selectively covers the first main surface 3, as described above. The main surface insulating layer 77 is connected to the first trench insulating film 47, the second trench insulating film 52, and the third trench insulating film 62 (described later) on the first main surface 3, and exposes the gate embedded electrode 48, the first source embedded electrode 53, and the second source embedded electrode 63 (described later). The main surface insulating layer 77 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the main surface insulating layer 77 contains the same type of insulating material as the insulating material of the first insulating layer 21, etc. In this embodiment, the main surface insulating layer 77 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating layer 77 contains a silicon oxide film made of the oxide of the chip 2. The main surface insulating layer 77 may be referred to as an "underlying insulating film," "underlying inorganic film," etc.

[0094] Referring to Figures 5 and 6, as described above, the semiconductor device 1 includes an insulating interlayer film 13 that selectively covers the first main surface 3. The interlayer film 13 may also be called an "inorganic film," "inorganic insulating film," etc. In this embodiment, the interlayer film 13 has a laminated structure consisting of a first insulating layer 21 on the first main surface 3 side and a second insulating layer 22 on the main surface electrode film 14 (Figure 3) side.

[0095] The first insulating layer 21 is laminated on the main surface insulating layer 77 and selectively covers the first main surface 3 with the main surface insulating layer 77 in between. Specifically, the first insulating layer 21 selectively covers the active region 10. The first insulating layer 21 may also selectively cover the outer peripheral region 11. The first insulating layer 21 may be referred to as the "first intermediate insulating film," "lower intermediate insulating film," "first interlayer film," "lower interlayer film," "first upper ground insulating film," etc. On the first main surface 3, the first insulating layer 21 covers a plurality of gate structures 45, a plurality of first trench source structures 50, and a plurality of second trench source structures 60 (described later).

[0096] The first insulating layer 21 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the first insulating layer 21 contains a silicon oxide film. Preferably, the first insulating layer 21 contains an insulating material having different properties from the insulating material of the main surface insulating layer 77. For example, preferably, the first insulating layer 21 has a single-layer structure or a laminated structure containing at least one of a silicon oxide film containing phosphorus (PSG film), a silicon oxide film containing phosphorus and boron (BPSG film), an impurity-free silicon oxide film (NSG film), and a tetraethyl orthosilicate film (TEOS film). For example, the first insulating layer 21 may have a laminated structure containing an NSG film and a PSG film (or BPSG film) laminated on top of the NSG film.

[0097] The first insulating layer 21 has a first film thickness T1 (Figure 6). The first film thickness T1 is, for example, 0.05 μm or more and 0.6 μm or less. The first film thickness T1 may have a value that falls within at least one of the following ranges: 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, and 0.5 μm or more and 0.6 μm or less.

[0098] The second insulating layer 22 is laminated on the first insulating layer 21 and selectively covers the first main surface 3, sandwiching the first insulating layer 21 and the main surface insulating layer 77. Specifically, the second insulating layer 22 selectively covers the active region 10. The second insulating layer 22 may also selectively cover the outer peripheral region 11. The second insulating layer 22 may be referred to as the "second intermediate insulating film," "upper intermediate insulating film," "second interlayer film," "upper interlayer film," "second upper ground insulating film," etc. The second insulating layer 22, sandwiching the first insulating layer 21, covers a plurality of gate structures 45, a plurality of first trench source structures 50, and a plurality of second trench source structures 60 (described later) on the first main surface 3.

[0099] The second insulating layer 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating layer 22 preferably includes a silicon oxide film. The second insulating layer 22 preferably includes an insulating material having properties different from those of the insulating material of the main surface insulating layer 77. For example, the second insulating layer 22 preferably has a single-layer structure or a stacked structure including at least one of a phosphorous-containing silicon oxide film (PSG film), a silicon oxide film containing phosphorous and boron (BPSG film), an impurity-free silicon oxide film (NSG film), and a tetraethyl orthosilicate film (TEOS film). For example, the second insulating layer 22 may have a single-layer structure of an NSG film stacked on the first insulating layer 21. The thickness of the second insulating layer 22 may be thinner than the thickness of the first insulating layer 21.

[0100] The second insulating layer 22 has a second film thickness T2 (FIG. 6). The second film thickness T2 is, for example, 0.05 μm or more and 0.4 μm or less. The second film thickness T2 may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, and 0.3 μm or more and 0.4 μm or less. In this form, the second film thickness T2 of the second insulating layer 22 is smaller than the first film thickness T1 of the first insulating layer 21 (T2 < T1). The second film thickness T2 may be the same as the first film thickness T1 (T2 = T1), or may be larger than the first film thickness T1 (T2 > T1).

[0101] FIG. 7 is an enlarged view of the portion surrounded by the dashed-dotted line VII in FIG. 4. FIG. 8 is a cross-sectional view taken along the line VIII-VIII shown in FIG. 7. FIG. 9 is a cross-sectional view taken along the line IX-IX shown in FIG. 7. FIG. 10 is a cross-sectional view taken along the line X-X shown in FIG. 7. FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG. 7. FIG. 12 is a cross-sectional view taken along the line XII-XII shown in FIG. 7. For clarification of the positional relationship in the second direction Y of the gate connection electrode 78 (described later), the first contact opening 79 (described later), the resistance wiring film 80 (described later), the resistance film portion 81 (described later), and the second contact opening 85 (described later), the positions in the second direction Y of these components are indicated by dashed-dotted lines in FIG. 7.

[0102] Referring to Figures 7 and 12, the semiconductor device 1 includes a plurality of trench-type second trench source structures 60 formed in the outer peripheral region 11. Source potentials are applied to the plurality of second trench source structures 60.

[0103] Each second trench source structure 60 is located in the region between the periphery of the first main surface 3 and the multiple gate structures 45. The multiple second trench source structures 60 are formed aligned with the multiple gate structures 45 in the first direction X. One gate structure 45 is sandwiched in the first direction X by two second trench source structures 60.

[0104] Each second trench source structure 60 is positioned in regions between adjacent first trench source structures 50 and faces multiple first trench source structures 50 in the second direction Y. In other words, multiple second trench source structures 60 are arranged alternately with multiple first trench source structures 50 in the second direction Y.

[0105] A single second trench source structure 60 comprises a second source trench 61, a third trench insulating film 62, and a second source embedded electrode 63. The second source trench 61 is formed on the first main surface 3 and defines the walls (side walls and bottom walls) of the second trench source structure 60. The third trench insulating film 62 covers the walls of the second source trench 61. The second source embedded electrode 63 is embedded in the second source trench 61, sandwiching the third trench insulating film 62. The second source embedded electrode 63 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon.

[0106] The end of each second trench source structure 60 on the active region 10 side is formed with a gap in the first direction X from the gate structure 45. In other words, the second trench source structure 60 is insulated from the gate structure 45. The ends of each second trench source structure 60 on the side surfaces 5C and 5D are connected to source underlay wiring (not shown) formed below the portion of the source wiring 18 (Figure 3) that extends along the third side surface 5C and the fourth side surface 5D. Multiple second trench source structures 60 are electrically connected to the source wiring 18 (Figure 3) via the source underlay wiring.

[0107] Referring to Figures 7 and 12, the semiconductor device 1 includes a plurality of p-type third well regions 64 formed along the third side surface 5C and the fourth side surface 5D of the outer peripheral region 11, in the region along the plurality of second trench source structures 60. The third well regions 64 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 41.

[0108] Multiple third well regions 64 are formed in a one-to-one correspondence with multiple second trench source structures 60. Each third well region 64 is formed in a region along the corresponding second trench source structure 60, spaced apart from the multiple first well regions 55 and multiple second well regions 56. Each third well region 64 is formed along the side and bottom walls of the corresponding second trench source structure 60. Each third well region 64 is electrically connected to the body region 41 at the surface layer of the first main surface 3. Multiple third well regions 64 form a pn junction with the second semiconductor layer 8.

[0109] Referring to Figures 3 and 7, in the active region 10, the portion of the gate wiring 25 extending along the second direction Y overlaps with multiple gate structures 45 in a plan view. Specifically, in this embodiment, the portion of the base wiring 26 extending in the second direction Y, and multiple (e.g., three) finger wirings 27 overlap with multiple gate structures 45 in a plan view.

[0110] Referring to Figure 7, the region on the active region 10 that is perpendicular in a plan view to the portion of the gate wiring 25 that extends along the second direction Y is called the wiring overlap region 90. The wiring overlap region 90 is covered by the gate wiring 25 (the portion of the base wiring 26 that extends in the second direction Y, and the finger wiring 27). The wiring overlap region 90 may also be called the "wiring covering region," "wiring covering region," etc.

[0111] Referring to Figures 8 to 12, the multiple gate structures 45 include multiple gate connection electrodes 78. Each gate connection electrode 78 selectively covers the gate embedded electrode 48. The gate connection electrodes 78 may also be referred to as "connection electrodes," "connection electrode films," "gate connection electrode films," etc. The gate connection electrodes 78 are considered to be a component of the gate structure 45. The gate connection electrodes 78 may also be a separate element from the gate structure 45. In this embodiment, the multiple gate connection electrodes 78 are formed in the wiring overlap region 90.

[0112] The multiple gate connection electrodes 78 are made of conductive polysilicon (polysilicon). The multiple gate connection electrodes 78 include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The multiple gate connection electrodes 78 have the same conductivity type as the gate embedded electrode 48, and in this embodiment, they are p-type. The multiple gate connection electrodes 78 have the same p-type impurity concentration as the gate embedded electrode 48. The multiple gate connection electrodes 78 are formed by a doped polysilicon deposit layer. Each gate connection electrode 78 is formed integrally (simultaneously) with the corresponding gate embedded electrode 48.

[0113] Each gate connection electrode 78 is interposed between the gate structure 45 and the resistive wiring film 80 (described later). In other words, multiple gate connection electrodes 78 are arranged on multiple gate structures 45 and covered by the resistive wiring film 80. In this embodiment, each gate connection electrode 78 covers both ends of the corresponding gate structure 45 in the second direction Y in a film-like manner and extends in a strip-like manner in the first direction X.

[0114] Multiple gate connection electrodes 78 are formed to protrude from the first main surface 3 toward the gate wiring 25. Each of the multiple gate connection electrodes 78 has an electrode surface 78a that extends along the first main surface 3. In this embodiment, the multiple gate connection electrodes 78 are formed in a tapered shape (frustoconical shape) toward the electrode surface 78a in cross-sectional view. Preferably, the electrode surface 78a is formed to be wider than the gate structure 45 with respect to the second direction Y.

[0115] The third film thickness T3 (Figure 9) of the gate connection electrode 78 may be less than the depth of the first trench source structure 50, or greater than the depth of the first trench source structure 50. The third film thickness T3 (Figure 9) of the gate connection electrode 78 may be less than the depth of the gate structure 45, or greater than the depth of the gate structure 45. The thickness of the gate connection electrode 78 may be 0.05 μm or more and 3 μm or less.

[0116] Referring to Figures 7 to 12, the semiconductor device 1 includes a plurality of first contact openings 79 formed in the first insulating layer 21 in the active region 10. The plurality of first contact openings 79 penetrate the first insulating layer 21 and selectively expose a plurality of gate structures 45. Specifically, the plurality of first contact openings 79 are formed in the portion of the first insulating layer 21 that covers a plurality of gate connection electrodes 78. Each first contact opening 79 exposes a plurality of gate connection electrodes 78.

[0117] Referring to Figure 12, in this embodiment, the multiple first contact openings 79 are formed in a one-to-one correspondence with the multiple gate connection electrodes 78. Each first contact opening 79 extends in a strip shape in a first direction X in a plan view. The multiple first contact openings 79 are arranged at intervals in a second direction Y. In other words, the multiple first contact openings 79 are arranged in a stripe shape extending in the first direction X in a plan view. Each first contact opening 79 has a first opening length L1 (Figure 12) that is longer in the first direction X.

[0118] Referring to Figures 3 and 12, the semiconductor device 1 includes a resistive wiring film 80 formed below the portion of the gate wiring 25 that extends along the second direction Y (the portion of the base wiring 26 that extends in the second direction Y, and the plurality of finger wirings 27). The resistive wiring film 80 has a constant wiring width W2 (Figure 12) and extends in the second direction Y.

[0119] The wiring width W2 (Figure 12) is narrower than the wiring width W1 (Figures 3 and 12). In this configuration, both sides of the resistive wiring film 80 are set back inward from both sides of the gate wiring 25 (part of the finger wiring 27 and base wiring 26) in a plan view. Both sides of the resistive wiring film 80 may be aligned with both sides of the gate wiring 25 in a plan view, or they may protrude outward from both sides of the finger wiring 27.

[0120] Referring to Figure 12, the resistive wiring film 80 is formed on the first insulating layer 21. The resistive wiring film 80 is covered by the second insulating layer 22. In other words, the resistive wiring film 80 is embedded in the interlayer film 13. The resistive wiring film 80 covers a plurality of gate embedded electrodes 48 and a plurality of gate connecting electrodes 78, with the first insulating layer 21 in between. The resistive wiring film 80 covers a plurality of first trench source structures 50, with the first insulating layer 21 in between.

[0121] The resistive wiring film 80 is interposed between the multiple gate connection electrodes 78 and the first insulating layer 21. In other words, the resistive wiring film 80 covers the multiple gate connection electrodes 78 collectively and is covered by the first insulating layer 21. The resistive wiring film 80 has a higher resistivity than the gate embedded electrodes 48 of the gate structure 45.

[0122] The resistive wiring film 80 is made of conductive polysilicon (polysilicon). The resistive wiring film 80 includes either one or both of p-type conductive polysilicon and n-type conductive polysilicon. The resistive wiring film 80 has the same conductivity type as the gate buried electrode 48, and in this form, it has a p-type. The p-type impurity concentration of the resistive wiring film 80 is higher than the p-type impurity concentration of the gate buried electrode 48 (the plurality of gate connection electrodes 78). The resistive wiring film 80 has a p-type impurity concentration of 1.0×10 19 cm -3 or more and 1.0×10 21 cm -3 or less as a peak value.

[0123] The resistive wiring film 80 consists of a diffusion layer in which p-type impurities are diffused by ion implantation. The resistive wiring film 80 contains p-type impurities throughout its entire area with respect to both the first direction X and the second direction Y. The p-type impurity concentration of the resistive wiring film 80 may have a concentration gradient (concentration profile) that gradually decreases from the surface of the resistive wiring film 80 to a predetermined depth.

[0124] The fourth film thickness T4 (FIG. 9) of the resistive wiring film 80 may be smaller than the first film thickness T1 (FIG. 9) of the first insulating layer 21 (T4 < T1). The fourth film thickness T4 may be equal to the first film thickness T1 (T4 = T1). The fourth film thickness T4 may be larger than the first film thickness Tl (T4 > T1). The fourth film thickness T4 is preferably larger than the second film thickness T2 (FIG. 9) of the second insulating layer 22 (T4 > T2).

[0125] The fourth film thickness T4 (FIG. 9) of the resistive wiring film 80 may be smaller than the third film thickness T3 (FIG. 9) of the plurality of gate connection electrodes 78 (T4 < T3). The fourth film thickness T4 may be equal to the third film thickness T3 (T4 = T3). The fourth film thickness T4 may be larger than the third film thickness T3 (T4 > T3).

[0126] The resistive wiring film 80 penetrates the multiple first contact openings 79 from above the first insulating layer 21 and is mechanically and electrically connected to the electrode surface 78a of the gate connection electrode 78 within the multiple first contact openings 79. As a result, the resistive wiring film 80 is electrically connected to the multiple gate structures 45 via the multiple gate connection electrodes 78.

[0127] The resistive wiring film 80 includes a plurality of resistive film portions 81 extending in a first direction X. The plurality of resistive film portions 81 refer to the portions of the resistive wiring film 80 that are perpendicular to the plurality of gate structures 45 in the direction Z. The plurality of resistive film portions 81 are formed so as to be aligned in the second direction Y without any gaps between them, thereby forming the resistive wiring film 80 extending in the second direction Y. In other words, in this embodiment, a plurality (many) of resistive film portions 81 are included in the resistive wiring film 80.

[0128] Multiple resistive film portions 81 are formed on the first insulating layer 21. Multiple resistive film portions 81 are covered by the second insulating layer 22. In other words, multiple resistive film portions 81 are embedded in the interlayer film 13.

[0129] Multiple resistive film portions 81 are arranged on multiple gate connection electrodes 78. Multiple resistive film portions 81 are covered by a first insulating layer 21. Multiple resistive film portions 81 cover multiple gate embedded electrodes 48 and multiple gate connection electrodes 78 with the first insulating layer 21 in between. In this embodiment, multiple resistive film portions 81 are formed in a one-to-one correspondence with multiple gate connection electrodes 78 and multiple gate embedded electrodes 48. Multiple resistive film portions 81 have a higher resistivity than the gate embedded electrodes 48 and gate connection electrodes 78.

[0130] Each resistive film portion 81 includes one central portion 82, two raised portions 83, and two end portions 84. Each central portion 82 is the portion that fits into the corresponding first contact opening 79 and contacts the corresponding gate connection electrode 78. Each central portion 82 is formed on the corresponding gate connection electrode 78. Each central portion 82 has a flat upper surface 82a.

[0131] The two raised portions 83 cover the portion (raised portion) of the first insulating layer 21 that covers the end of the gate connection electrode 78 in the first direction X. The upper surface of each raised portion 83 is located above the upper surface 82a of the corresponding central portion 82. The lower surface of each raised portion 83 is located above the lower surface of the corresponding central portion 82. The two raised portions 83 are formed so as to sandwich the central portion 82 in the first direction X.

[0132] The two ends 84 cover the portion of the first insulating layer 21 that does not cover the gate connection electrode 78. Each end 84 has a flat upper surface 84a (Figure 16). The upper surface of each end 84 is located below the upper surface 82a of the corresponding central portion 82. The lower surface of each end 84 is located below the lower surface of the corresponding central portion 82. The two ends 84 are formed to sandwich the central portion 82 and the two raised portions 83 in the first direction X.

[0133] The multiple resistive film portions 81 are made of conductive polysilicon (polysilicon). Each of the multiple resistive film portions 81 contains either p-type conductive polysilicon or n-type conductive polysilicon, or both. The multiple resistive film portions 81 have the same conductivity type as the gate embedded electrode 48, and in this embodiment, they are p-type. The concentration of p-type impurities in the multiple resistive film portions 81 is higher than the concentration of p-type impurities in the gate embedded electrode 48 (multiple gate connecting electrodes 78).

[0134] Each of the multiple resistive film portions 81 consists of a diffusion layer of p-type impurities. The concentration of p-type impurities in the multiple resistive film portions 81 may have a concentration gradient (concentration profile) that gradually decreases from the surface of the resistive wiring film 80 to a predetermined depth.

[0135] Referring to Figure 12, the ends 81b on both sides of each resistive film portion 81 in the first direction X are the sides of the resistive wiring film 80. The ends 81b on both sides are set back inward from the side edges 25b on both sides of the gate wiring 25. The ends 81b on both sides protrude outward from the ends 78b on both sides of the multiple gate connection electrodes 78 in the first direction X.

[0136] Each resistive film portion 81 penetrates a plurality of first contact openings 79 from above the first insulating layer 21 and is mechanically and electrically connected to the electrode surface 78a of the gate connection electrode 78 within the first contact openings 79. As a result, one resistive film portion 81 is electrically connected to the gate structure 45 via the gate connection electrode 78.

[0137] Referring to Figures 8 and 12, the semiconductor device 1 includes a plurality of second contact openings 85 formed in the first insulating layer 21 in the active region 10. The plurality of second contact openings 85 penetrate the second insulating layer 22 and selectively expose a plurality of resistive film portions 81.

[0138] Referring to Figure 12, the multiple second contact openings 85 are formed in the portion of the second insulating layer 22 that covers the multiple resistive film portions 81. The multiple second contact openings 85 expose the multiple resistive film portions 81. In this configuration, the multiple second contact openings 85 are formed in a one-to-one correspondence with the multiple resistive film portions 81. Each second contact opening 85 extends in a strip shape in the first direction X in a plan view. The multiple second contact openings 85 are arranged with spacing in the second direction Y. In other words, the multiple second contact openings 85 are arranged in a stripe shape extending in the first direction X in a plan view.

[0139] The second contact opening 85 has a second opening length L2 (Figure 12) that is longer in the first direction X. In this configuration, the second opening length L2 is smaller than the first opening length L1 (L1 > L2).

[0140] The gate wiring 25 enters through a plurality of second contact openings 85 from above the second insulating layer 22 and is mechanically and electrically connected to the upper surfaces 81a (Figure 12) of a plurality of resistive film portions 81 within the plurality of second contact openings 85. As a result, the gate wiring 25 is electrically connected to a plurality of gate structures 45 via a plurality of resistive film portions 81 (resistive wiring films 80) and a plurality of gate connection electrodes 78. Consequently, the gate potential applied to the gate wiring 25 is applied to the plurality of gate structures 45 via a plurality of resistive film portions 81 (resistive wiring films 80).

[0141] Referring to Figure 12, the multiple second contact openings 85 are formed in a one-to-one correspondence with the multiple first contact openings 79. Each second contact opening 85 is formed in the portion of the second insulating layer 22 that covers the central portion 82 of the corresponding resistive film portion 81. The second contact openings 85 expose the central portion 82. Therefore, the gate wiring 25 is mechanically and electrically connected to the upper surface 82a (Figure 12) of the central portion 82 of the multiple resistive film portions 81 within the multiple second contact openings 85.

[0142] Each second contact opening 85 is formed to overlap the corresponding gate connection electrode 78 in a plan view. In other words, each second contact opening 85 is formed to overlap the corresponding gate structure 45 in a plan view. Each second contact opening 85 overlaps the corresponding first contact opening 79 in a plan view. Both ends of the second contact opening 85 in the first direction X are set back inward compared to both ends of the first contact opening 79 in the first direction X.

[0143] Figure 13 is a schematic diagram showing a wafer 150 used in the manufacture of semiconductor device 1. Referring to Figure 13, the wafer 150 is the substrate for chip 2 and contains a SiC single crystal. The wafer 150 is formed in the shape of a flat disc. Of course, the wafer 150 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0144] The first wafer main surface 151 corresponds to the first main surface 3 of chip 2 (Figure 2, etc.), and the second wafer main surface 152 corresponds to the second main surface 4 of chip 2 (Figure 2, etc.). The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of a SiC single crystal. The first wafer main surface 151 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon plane of the SiC single crystal. The wafer 150 (first wafer main surface 151 and second wafer main surface 152) has the aforementioned off-direction and off-angle.

[0145] The wafer 150 has markings 154 on the wafer side surface 153 that indicate the crystal orientation of the SiC single crystal. The markings 154 may include either an orientation flat or an orientation notch, or both. An orientation flat consists of a notch that is cut out in a straight line in a plan view. An orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 151 in a plan view.

[0146] Marker 154 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. Marker 154 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0147] The wafer 150 includes a second semiconductor layer 8 (as shown in Figure 14A, described later) in the region (surface layer) on the first wafer main surface 151 side. The second semiconductor layer 8 is formed in a layered manner extending along the first wafer main surface 151. In this configuration, the second semiconductor layer 8 consists of an epitaxial layer (specifically, a SiC epitaxial layer). A drift region 9 (as shown in Figure 14A, described later) is formed in the second semiconductor layer 8.

[0148] The wafer 150 includes a first semiconductor layer 6 (as shown in Figure 14A, described later) in the region (surface layer) on the second wafer main surface 152 side. The first semiconductor layer 6 is formed in a layered manner extending along the second main surface 4 and is electrically connected to the first semiconductor layer 6. In this configuration, the first semiconductor layer 6 consists of the wafer body (specifically, a SiC wafer). In other words, in this configuration, the wafer 150 consists of an epitaxial wafer (a so-called epi-wafer) having a stacked structure including the wafer body and an epitaxial layer.

[0149] For example, multiple device regions 155 and multiple cutting lines 156 are set on the wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. The multiple device regions 155 are each set in a rectangular shape when viewed from above.

[0150] In this configuration, the multiple device regions 155 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are each spaced inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are arranged in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0151] Figures 14A to 14K are cross-sectional views showing the manufacturing method of the semiconductor device 1. Figures 14A to 14K show a cross-section of a portion of the active region 10 of one device region 155 (Figure 13). In Figures 14A to 14K, the left figure corresponds to a portion of the cross-section in Figure 9, and the right figure corresponds to a portion of the cross-section in Figure 8.

[0152] Referring to Figure 14A, first, the aforementioned wafer 150 is prepared. Next, referring to Figure 14B, a body region 41 is formed on the surface of the second semiconductor layer 8. The body region 41 is formed by introducing p-type impurities into the first wafer main surface 151 of the wafer 150. Subsequently, a source region 42 is formed on the surface of the body region 41. The source region 42 is formed by introducing n-type impurities into the surface of the body region 41.

[0153] Next, referring to Figure 14C, a body contact region 57 is formed on the surface of the body region 41. The body contact region 57 is formed by introducing p-type impurities to the surface of the body region 41. Next, a gate trench 46 and a first source trench 51 are formed. The gate trench 46 and the first source trench 51 may be formed by an etching method through a mask (e.g., wet etching). Next, a plurality of first well regions 55 are formed along the inner walls of the plurality of gate trenches 46, and a plurality of second well regions 56 are formed along the inner walls of the plurality of first source trenches 51. After that, annealing may be performed.

[0154] Next, referring to Figure 14D, the first trench insulating film 47, the second trench insulating film 52, and the main surface insulating layer 77 are formed. These may be formed by the CVD (chemical vapor deposition) method.

[0155] Next, referring to Figure 14E, the gate embedded electrode 48, the first source embedded electrode 53, and the gate connection electrode 78 are formed. A base conductive layer 100, which will serve as the base for these electrodes 48, 53, and 78, is deposited on the first wafer main surface 151, and then any unnecessary portions are removed by etching. The base conductive layer 100 is a deposited layer of p-type doped polysilicon. This forms these electrodes 48, 53, and 78. These electrodes 48, 53, and 78 may be formed by the CVD method. The CVD method may be the LP-CVD (Low Pressure-CVD) method.

[0156] Next, referring to Figure 14F, a first insulating layer 21 is formed on the first wafer main surface 151. This forms a first insulating layer 21 having portions that directly cover the first source embedded electrode 53 and the gate connection electrode 78. The first insulating layer 21 may be formed by the CVD method. After the formation of the first insulating layer 21, a reflow process (heat treatment process) may be performed on the first insulating layer 21.

[0157] Next, referring to Figure 14G, a first mask 101 having a predetermined layout is placed on the first insulating layer 21. The first mask 101 has mask openings 102 for exposing areas where multiple first contact openings 79 are to be formed, and covers the remaining areas. Next, unnecessary portions of the first insulating layer 21 are removed by etching through the first mask 101. This forms multiple first contact openings 79 in the first insulating layer 21. After that, the first mask 101 is removed.

[0158] Next, referring to Figure 14H, a polysilicon film 103 is formed on the main surface 151 of the first wafer. The polysilicon film 103 is an undoped polysilicon film that does not contain impurities.

[0159] Next, referring to Figure 14I, p-type impurities are introduced into the polysilicon film 103 by ion implantation. This impurities create a p-type diffusion layer throughout the polysilicon film 103. This forms a resistive wiring film 80 made of conductive polysilicon. The resistive wiring film 80 comprises a plurality of resistive film portions 81 aligned in the second direction Y. These resistive film portions 81 are mechanically and electrically connected to a plurality of gate connection electrodes 78 within a plurality of first contact openings 79.

[0160] Next, referring to Figure 14J, a second insulating layer 22 is formed on the main surface 151 of the first wafer. This forms a second insulating layer 22 having a portion that directly covers the resistive wiring film 80 (multiple resistive film portions 81). The second insulating layer 22 may be formed by the CVD method. After the formation of the second insulating layer 22, a reflow process (heat treatment process) may be performed on the second insulating layer 22.

[0161] Subsequently, a second mask (not shown) having a predetermined layout is placed on the second insulating layer 22. The second mask exposes the area where multiple second contact openings 85 (see also Figure 12) are to be formed, and covers the other areas. Next, unnecessary portions of the second insulating layer 22 are removed by etching through the second mask. This forms multiple second contact openings 85 in the second insulating layer 22. After that, the second mask is removed.

[0162] Next, referring to Figure 14K, a main surface electrode film 14 (Figure 3) including gate wiring 25 is formed on the first wafer main surface 151. Then, the gate wiring 25 is formed on the second insulating layer 22. The gate wiring 25 is formed by sputtering. The gate wiring 25 is mechanically and electrically connected to a plurality of resistive film portions 81 within a plurality of second contact openings 85.

[0163] Next, a surface insulating film 34 (Figure 1) is selectively formed on the surface of the main surface electrode film 14 (Figure 3). Then, a drain pad electrode 7 (Figure 2) is formed on the second wafer main surface 152. The drain pad electrode 7 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the planned cutting line 156, and a plurality of semiconductor devices 1 are cut out. A semiconductor device 1 is manufactured through the above process.

[0164] In the semiconductor device 1, multiple resistive film portions 81 are embedded in the interlayer film 13. The multiple resistive film portions 81 are mechanically and electrically connected to both the multiple gate structures 45 formed in the active region 10 and the gate wiring 25 (gate electrode film 16). In other words, one resistive film portion 81 is mechanically and electrically connected to both the gate structure 45 and the gate wiring 25 (gate electrode film 16).

[0165] Conventionally, semiconductor devices (MISFETs) are sometimes used in parallel connections. If there is a large variation in the characteristics of the individual gate elements contained in each transistor within an individual MISFET, parasitic oscillation may occur in each of the multiple MISFETs connected in parallel. One example of a case where there is a large variation in the characteristics of the individual gate elements contained in the device structure is when there is a large variation in the gate resistance of the multiple gate structures contained in the device structure.

[0166] To suppress parasitic oscillations, it is conceivable to interpose (add) another gate resistor between the device structure (transistor) and the gate electrode film in a semiconductor device (MISFET). By adding a gate resistor, the effects of variations in the gate resistance of individual gate structures can be avoided.

[0167] However, in this case, the active area on the first main surface of the chip becomes smaller due to the installation of the additional gate, reducing the effective area (area of ​​the active region) on the first main surface of the chip. In this case, losses may occur in the chip, potentially increasing the on-resistance of the chip.

[0168] Therefore, there is a need to provide a semiconductor device that can avoid the effects of variations in the gate resistance of multiple gate structures without incurring losses.

[0169] As described above, in the semiconductor device 1, a plurality of resistive film portions 81 are embedded in the interlayer film 13. The plurality of resistive film portions 81 are connected to both a plurality of gate structures 45 formed in the active region 10 and the gate wiring 25 (gate electrode film 16).

[0170] Since multiple resistive film sections 81 are interposed between the transistor structure Tr and the gate electrode film 16, the effects of variations in the gate resistance of individual gate structures 45 can be avoided. Furthermore, because the multiple resistive film sections 81 are formed between the multiple gate structures 45 formed in the active region 10 and the gate wiring 25, the area of ​​the active region 10 (effective area on the first main surface 3 of the chip 2) does not decrease even when the resistive film sections 81 are added (the active region 10 does not become narrower). Therefore, no loss occurs in the chip 2. In this way, the effects of variations in the gate resistance of multiple gate structures 45 can be avoided without causing loss.

[0171] In particular, in this configuration, multiple resistive film portions 81 are formed in the wiring overlap region 90 where multiple gate structures 45 overlap with the gate wiring 25 in a plan view. Therefore, the resistive film portions 81 can be added without affecting the area of ​​the active region 10.

[0172] Furthermore, in this configuration, the multiple resistive film sections 81 have a higher resistivity than the gate structure 45. Specifically, the p-type impurity concentration of the multiple resistive film sections 81 is higher than the p-type impurity concentration of the gate embedded electrode 48 (gate connecting electrode 78). Therefore, the influence of variations in the gate resistance of the multiple gate structures 45 can be avoided.

[0173] For example, when the gate resistance of multiple gate structures 45 is set to 1Ω, the variation in resistance values ​​is about 0.1Ω. In this configuration, if the resistance value of each resistive film portion 81 is set to, for example, 4Ω, the total resistance value becomes 5Ω. On the other hand, the variation in resistance values ​​remains 0.1Ω. This makes it possible to avoid the effects of variations in the gate resistance of multiple gate structures 45.

[0174] Furthermore, in this configuration, the resistive film portion 81 consists of a diffusion layer in which p-type impurities are diffused by ion implantation. Therefore, compared to the case where it is formed by a deposited layer of doped polysilicon, variations in the amount of diffusion of p-type impurities can be suppressed. This makes it possible to more effectively avoid the effects of variations in the gate resistance of the multiple gate structures 45.

[0175] In this configuration, multiple resistive film portions 81 are formed on a first insulating layer 21 that covers multiple gate structures 45. The multiple resistive film portions 81 are connected to the multiple gate structures 45 via multiple first contact openings 79 formed in the first insulating layer 21. The gate wiring 25 is formed on a second insulating layer 22 that covers the first insulating layer 21 and the multiple resistive film portions 81, and is connected to the multiple resistive film portions 81 via multiple second contact openings 85 formed in the second insulating layer 22. Therefore, a configuration in which multiple resistive film portions 81 embedded in the interlayer film 13 are connected to multiple gate structures 45 and gate wiring 25 can be realized with a relatively simple configuration.

[0176] Figure 15 is a cross-sectional view showing the main parts of the semiconductor device 201 according to the second embodiment of this disclosure. Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 15. Figures 15 and 16 show a first embodiment of the semiconductor device 201 according to the second embodiment. In the semiconductor device 201, components common to the semiconductor device 1 according to the first embodiment are given the same reference numerals and their descriptions are omitted.

[0177] The difference between semiconductor device 201 and semiconductor device 1 is that instead of multiple second contact openings 85, it has multiple second contact openings 85A and multiple second contact openings 85B. Each second contact opening 85A and each second contact opening 85B are formed offset in a first direction X from the corresponding gate connection electrode 78 in a plan view. In other words, each second contact opening 85A and each second contact opening 85B are formed offset in a first direction X from the corresponding gate structure 45 in a plan view.

[0178] Multiple second contact openings 85A and 85B are formed in a 2:1 correspondence relationship with multiple resistive film portions 81. Multiple second contact openings 85A penetrate the second insulating layer 22 and selectively expose multiple resistive film portions 81. Multiple second contact openings 85B penetrate the second insulating layer 22 and selectively expose multiple resistive film portions 81.

[0179] As described above, each first contact opening 79 is formed in the portion of the first insulating layer 21 that covers the multiple gate connection electrodes 78. Therefore, the multiple second contact openings 85A and 85B are formed in a 2:1 correspondence relationship with the multiple first contact openings 79. In a plan view, each second contact opening 85A and each second contact opening 85B do not overlap with the corresponding first contact opening 79.

[0180] Multiple second contact openings 85A are formed in a one-to-one correspondence with multiple resistive film portions 81. Each second contact opening 85A is formed in the portion of the second insulating layer 22 that covers the end portion 84 (outer end portion 84) of the corresponding resistive film portion 81. Each second contact opening 85A extends in a strip shape in the first direction X in a plan view. Multiple second contact openings 85A are arranged at intervals in the second direction Y. In other words, multiple second contact openings 85A are arranged in a stripe shape extending in the first direction X in a plan view.

[0181] The second contact opening 85A has its end 84 (outer end 84) exposed. Therefore, the gate wiring 25 is mechanically and electrically connected to the upper surface 84a of the end 84 (outer end 84) of the multiple resistive film portions 81 within the multiple second contact openings 85A. The second contact opening 85A has a second opening length L12 that is longer in the first direction X. In this embodiment, the second opening length L12 is equivalent to the first opening length L11 of the first contact opening 79 (L11=L12). The second opening length L2 may be greater than or less than the first opening length L11 (L11>L12, L11 <L12)。

[0182] Multiple second contact openings 85B are formed in the portion of the second insulating layer 22 that covers the ends 84 (inner ends 84) of multiple resistive film portions 81. Multiple second contact openings 85B expose multiple ends 84 (inner ends 84). Therefore, the gate wiring 25 is mechanically and electrically connected to the upper surfaces 84a of the ends 84 (inner ends 84) of the multiple resistive film portions 81 within the multiple second contact openings 85B. The second contact openings 85B have a second opening length L12 that is longer in the first direction X. In this embodiment, the second opening length L2 is equal to the first opening length L11 of the first contact opening 79 (L11=L12). The second opening length L2 may be greater than or less than the first opening length L11 (L11>L12, L11 <L12)。

[0183] Each second contact opening 85B is formed in the portion of the second insulating layer 22 that covers the end 84 (inner end 84) of the corresponding resistive film portion 81. Multiple second contact openings 85B are formed in a one-to-one correspondence with multiple resistive film portions 81. Each second contact opening 85B extends in a strip shape in the first direction X in a plan view. Multiple second contact openings 85B are arranged with intervals in the second direction Y. In other words, multiple second contact openings 85B are arranged in a stripe shape extending in the first direction X in a plan view.

[0184] The second contact opening 85B exposes its end 84 (inner end 84). Therefore, the gate wiring 25 is mechanically and electrically connected to the upper surface 84a of the end 84 (inner end 84) of the multiple resistive film portions 81 within the multiple second contact openings 85B. The second contact opening 85B has a second opening length L12 that is longer in the first direction X. In this configuration, the second opening length L2 is equal to the first opening length L11 of the first contact opening 79 (L11=L12). The second opening length L2 may be greater than or less than the first opening length L11 (L11>L12, L11 <L12)。

[0185] In the semiconductor device 201 (second embodiment), the length of each end 84 in the first direction X is formed to be larger than that of each end 84 in the semiconductor device 1 (first embodiment) (see Figure 12). This is because the second contact openings 85A and 85B are formed at the end 84.

[0186] Since there is a constraint on the length of the wiring overlap region 90 in the first direction X, if the length of the end portion 84 in the first direction X becomes longer, the length of the central portion 82 in the first direction X becomes smaller. For this reason, in the second embodiment, the length of the first contact opening 79 in the first direction X is set to be smaller compared to the semiconductor device 1 (first embodiment).

[0187] According to semiconductor device 201 (second embodiment), the same effects and advantages as those described in semiconductor device 1 (first embodiment) are achieved.

[0188] Furthermore, in this configuration, the second contact openings 85A and 85B are formed at the end 84 of the resistive film portion 81. The electrode surface 78a of the gate connection electrode 78 may have irregularities. In this case, the upper surface of the central portion 82 of the resistive film portion 81 may not be flat. On the other hand, the end 84 of the resistive film portion 81 is not affected by the flatness of the electrode surface 78a. Therefore, the upper surface 84a of the end 84 of the resistive film portion 81 is flat regardless of the condition of the electrode surface 78a. Since the second contact openings 85A and 85B are formed on the flat end 84, the gate wiring 25 and the resistive film portion 81 can be connected well.

[0189] Figure 17 is a cross-sectional view of a semiconductor device 201 according to a second embodiment in which the number of second contact apertures has been changed.

[0190] In the second embodiment shown in Figure 17, the multiple second contact openings 85B are omitted from the first embodiment shown in Figures 15 and 16. The semiconductor device 201 is provided with only multiple second contact openings 85A as second contact openings. The multiple second contact openings 85A are formed in a one-to-one correspondence with the multiple first contact openings 79. As described above, each second contact opening 85A is formed offset in the first direction X from the corresponding gate connection electrode 78 in a plan view.

[0191] In the second embodiment shown in Figure 17, the semiconductor device 201 may have only a plurality of second contact openings 85B as the second contact openings. In this case, a configuration in which the plurality of second contact openings 85A are omitted from the first embodiment shown in Figures 15 and 16 may be adopted.

[0192] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0193] For example, in the semiconductor device 1 (first embodiment), as shown in the modified example in Figure 18, a plurality of resistive film portions 81 may be arranged at intervals in the second direction Y. In other words, a plurality of resistive film portions 81 may be formed in a stripe shape extending in the first direction X. In this case, the resistive wiring film 80 composed of the plurality of resistive film portions 81 will extend intermittently along the second direction Y.

[0194] The modified form shown in Figure 18 may be combined with the semiconductor device 201 (second embodiment).

[0195] In this disclosure, Figure 7 illustrates a second finger wiring 29 as an example of a finger wiring 27 electrically connected to a plurality of gate structures 45 via a plurality of resistive film portions 81. This finger wiring 27 may also be a first finger wiring 28 (Figure 3) or a third finger wiring 30 (Figure 3).

[0196] In Figure 7, finger wiring 27 is used as an example to illustrate the gate wiring 25 that is electrically connected to multiple gate structures 45 via multiple resistive film portions 81. This gate wiring 25 may also be base wiring 26 (Figure 3, the portion of base wiring 26 that extends in the second direction Y).

[0197] In Figure 7, gate wiring 25 is used as an example to illustrate the gate electrode film 16 (Figure 3) that is electrically connected to multiple gate structures 45 via multiple resistive film portions 81. This gate wiring 25 may also be a gate pad electrode 24 (Figure 3).

[0198] In each embodiment, a trench gate type vertical structure (trench structure) was given as an example of the transistor structure Tr, but a planar gate type vertical structure (planar structure) may be used instead.

[0199] Furthermore, in the embodiments described above, a first semiconductor layer 6 and a second semiconductor layer 8, each containing a SiC single crystal, were employed. However, at least one or all of the first semiconductor layer 6 and the second semiconductor layer 8 may contain a single crystal of a wide-bandgap semiconductor other than a SiC single crystal.

[0200] The first semiconductor layer 6 and the second semiconductor layer 8 may be made of the same type of single crystal, or they may be made of different types of single crystals. Furthermore, at least one or all of the first semiconductor layer 6 and the second semiconductor layer 8 may be made of silicon (Si).

[0201] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0202] In each of the above-described embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0203] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0204] [Note 1-1] A tip (2) having a first main surface (3) including an active region (10), A first impurity region (9) of the first conductivity type formed on the chip (2), A second impurity region (41) of the second conductivity type formed on the surface of the first impurity region, A third impurity region (42) of the first conductivity type formed on the surface of the second impurity region, In the active region (10), a plurality of gate structures (45) are formed opposite the second impurity region and form channels in the second impurity region, An interlayer film (13) covering multiple gate structures, A gate electrode film (16) formed on the interlayer film (13), It includes a resistive film portion (81) embedded within the interlayer film (13), A semiconductor device (1,201) in which the resistive film portion (81) is connected to both the gate structure (45) and the gate electrode film (16).

[0205] [Appendix 1-2] The semiconductor device (1,201) according to Appendix 1-1, wherein the resistive film portion (81) has a higher resistivity than the gate structure (45).

[0206] [Appendix 1-3] The semiconductor device (1,201) described in Appendix 1-1 or Appendix 1-2, wherein the resistive film portion (81) is made of polysilicon.

[0207] [Appendix 1-4] The gate structure (45) is made of polysilicon, The semiconductor device (1,201) according to Appendix 1-3, wherein the resistive film portion (81) has a lower impurity concentration than the gate structure (45).

[0208] [Appendix 1-5] The semiconductor device (1,201) described in Appendix 1-4, wherein the resistive film portion (81) consists of a diffusion layer in which impurities are diffused.

[0209] [Appendix 1-6] Multiple gate structures (45) are formed in a stripe shape extending in the first direction (X), The gate electrode film (16) includes gate wiring (25) formed to extend in a line shape in a second direction (Y) intersecting the first direction (X), A semiconductor device (1,201) according to any one of claims 1 to 5, wherein a plurality of the resistive film portions (81) are embedded in the interlayer film (13) in a wiring overlap region (90) where the plurality of the gate structures (45) overlap with the gate wiring (25) in a plan view.

[0210] [Appendix 1-7] The semiconductor device (1,201) described in Appendix 1-6, wherein a plurality of the resistive film portions (81) are included in a resistive wiring film (80) that extends in a line in the second direction (Y) below the gate wiring (25).

[0211] [Appendix 1-8] A semiconductor device (1,201) as described in Appendix 1-6 or Appendix 1-7, wherein the ends (81b) of the plurality of resistive film portions (81) in the second direction (Y) are set back inward from the side edges (25b) of the gate wiring (25) in a plan view.

[0212] [Appendix 1-9] The plurality of gate structures (45) include a plurality of trench gate structures (45) formed in a stripe shape extending in the first direction (X) in the active region (10), The trench gate structure (45) includes a trench (46) that extends from the first main surface (3) through the third impurity region (42) and the second impurity region (41) to the first impurity region (9), a trench insulating film (47) formed on the inner surface of the trench (46), a gate embedded electrode (48) embedded in the trench (46) via the trench insulating film (47), and a gate connecting electrode (78) formed in the wiring overlap region (90) that protrudes from the first main surface (3) towards the gate wiring (25) and is in contact with the gate embedded electrode (48). A semiconductor device (1,201) according to any one of the appendices 1-6 to 1-8, wherein the resistive film portion (81) is formed on the gate connection electrode (78) with a part of the interlayer insulating layer (13) in between, and is connected to the gate connection electrode (78).

[0213] [Appendix 1-10] The semiconductor device (1,201) as described in Appendix 1-9, wherein the ends (81b) of the resistive film portion (81) in the first direction (X) protrude outward more than the ends (78b) of the gate connection electrode (78) in the first direction.

[0214] [Appendix 1-11] The first main surface (3) further includes a plurality of first trench source structures (50) formed in a stripe shape extending in the first direction (X), The first trench source structure (50) is formed between a plurality of adjacent trench gate structures (45), and the plurality of resistive film portions (81) are included in a resistive wiring film (80) that extends in a line in the second direction (Y) below the gate wiring (25). The semiconductor device (1,201) according to Appendix 1-9 or Appendix 1-10, wherein the resistive wiring film (80) covers the first trench source structure (50) with a portion of the interlayer insulating layer (13) in between.

[0215] [Appendix 1-12] The interlayer insulating layer (13) includes a first insulating layer (21) that covers a plurality of gate structures (45), The resistive film portion (81) is formed on the first insulating layer (21) and connected to the gate structure (45) via a first contact opening (79) formed in the first insulating layer (21). The interlayer insulating layer (13) further includes a second insulating layer (22) that covers the first insulating layer (21) and the plurality of resistive film portions (81), A semiconductor device (1,201) according to any one of the appendices 1-6 to 1-11, wherein the gate wiring (25) is connected to the resistive film portion (81) via second contact openings (85, 85A, 85B) formed in the second insulating layer (22).

[0216] [Appendix 1-13] A semiconductor device (1,201) according to Appendix 1-12, wherein a plurality of the first contact openings (79) and a plurality of the second contact openings (85, 85A, 85B) are arranged in a stripe shape extending in the first direction (X).

[0217] [Appendix 1-14] The semiconductor device (1) according to Appendix 1-12 or Appendix 1-13, wherein the second contact opening (85) is formed overlapping the gate structure (45) in a plan view.

[0218] [Appendix 1-15] A semiconductor device (1) according to any one of the appendices 1-12 to 1-14, wherein the second contact opening (85) is formed to overlap the first contact opening (79) in a plan view.

[0219] [Appendix 1-16] The semiconductor device (201) according to Appendix 1-12 or Appendix 1-13, wherein the second contact openings (85A, 85B) are formed offset in the first direction (X) on the gate structure (45) in a plan view.

[0220] [Appendix 1-17] The semiconductor device (201) according to Appendix 1-12 or Appendix 1-16, wherein the second contact opening (85A, 85B) is formed offset from the first contact opening (79) in the first direction (X) when viewed in plan.

[0221] [Appendix 1-18] Multiple second contact openings (85A, 85B) are formed in a 2:1 relationship with respect to multiple first contact openings (79). The semiconductor device (201) described in Appendix 1-17, wherein the two second contact openings (85A, 85B) sandwich the corresponding first contact opening (79) in the second direction (Y) in a plan view.

[0222] [Appendix 1-19] The semiconductor device (201) described in Appendix 1-17, wherein a plurality of the second contact openings (85A) are formed in a one-to-one relationship with a plurality of the first contact openings (79).

[0223] [Appendix 1-20] The chip (2) is a semiconductor device (1,201) as described in any one of the appendices 1-1 to 1-19, including a SiC chip. [Explanation of Symbols]

[0224] 1: Semiconductor device 2: Tip 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: First semiconductor layer 7: Drain pad electrode 8: Second semiconductor layer 9: Drift region (first impurity region) 10: Active area 11: Outer area 13: Interlayer insulating layer 14: Main surface electrode film 15: Source electrode film 16: Gate film 17: Source pad electrode 18: Source Wiring 19: First source electrode 20: Second source electrode 21: First insulating layer 22: Second insulating layer 24: Gate pad electrode 25: Gate wiring 25b: Side edge 26: Base wiring 27: Finger wiring 28: First finger wiring 29: Second finger wiring 30: Third finger wiring 31: 1st tip 32:Second tip 33:Third tip 34: Surface insulating film 35: Gate pad 36: Gate pad opening 37: First Sourcepad 38: First source pad opening 39: Second Sourcepad 40: Second source pad opening 41: Body region (second impurity region) 42: Source region (third impurity region) 44: Channel area 45: Gate structure 46: Gate Trench 47: First trench insulating film 48: Gate-embedded electrode 50: First trench source structure 51: First Source Trench 52: Second trench insulating film 53: Source embedded electrode 53: First source embedded electrode 55: First well area 56: Second well area 57: Body contact area 60: Second trench source structure 61: Second Source Trench 62: Second source trench insulating film 63: Second source embedded electrode 64: Third well area 70: Outer Well Region 71: First Outer Well Region 72: Second Outer Well Region 77: Main surface insulating layer 78: Gate connection electrode 78a: Electrode surface 78b: End 79: First contact opening 80: Resistance wiring film 81: Resistive film portion 81a:Top surface 81b: End 82: Central part 82a:Top surface 83: Protuberance 84: End 84a:Top surface 85: Second contact opening 85A: Second contact opening 85B: Second contact opening 90: Wiring overlap area 100: Base conductive layer 101: First Mask 102: Mask opening 103: Polysilicon film 150: Wafer 151: Main surface of the first wafer 152: Main surface of the second wafer 153: Wafer side 154: Landmark 155: Device area 156: Cutting line 201: Semiconductor equipment C: Corner T1: First film thickness T2: Second film thickness T3: Third film thickness T4: 4th film thickness Tr: Transistor structure W1: Wiring width W2: Wiring width X: 1st direction Y: Second direction Z: Vertical direction

Claims

1. A chip having a first main surface including an active region, A first impurity region of the first conductivity type formed on the chip, A second impurity region of a second conductivity type formed on the surface of the first impurity region, A third impurity region of the first conductivity type formed on the surface of the second impurity region, A plurality of gate structures are formed in the active region opposite to the second impurity region and form channels in the second impurity region, An interlayer film covering multiple gate structures, A gate electrode film formed on the interlayer film, It includes a plurality of resistive film portions embedded within the interlayer film, A semiconductor device in which the resistive film portion is connected to both the gate structure and the gate electrode film.

2. The semiconductor device according to claim 1, wherein the resistive film portion has a higher resistivity than the gate structure.

3. The semiconductor device according to claim 2, wherein the resistive film portion is made of polysilicon.

4. The gate structure is made of polysilicon. The semiconductor device according to claim 3, wherein the resistive film portion has a lower impurity concentration than the gate structure.

5. The semiconductor device according to claim 4, wherein the resistive film portion comprises a diffusion layer in which impurities have been diffused.

6. Multiple gate structures are formed in a stripe shape extending in the first direction, The gate electrode film includes gate wiring formed to extend in a line shape in a second direction intersecting the first direction, The semiconductor device according to claim 1, wherein a plurality of the resistive film portions are embedded in the interlayer film in a wiring overlap region where a plurality of the gate structures overlap with the gate wiring in a plan view.

7. The semiconductor device according to claim 6, wherein a plurality of the resistive film portions are included in a resistive wiring film that extends in a line shape in the second direction below the gate wiring.

8. The semiconductor device according to claim 6 or 7, wherein the ends on both sides in the first direction of the plurality of resistive film portions are set back inward from the side edges on both sides of the gate wiring in a plan view.

9. The plurality of gate structures include a plurality of trench gate structures, The trench gate structure includes a trench extending from the first main surface through the third impurity region and the second impurity region to the first impurity region, a trench insulating film formed on the inner surface of the trench, a gate embedded electrode embedded in the trench via the trench insulating film, and a gate connecting electrode formed in the wiring overlap region so as to protrude from the first main surface toward the gate wiring side and in contact with the gate embedded electrode. The semiconductor device according to claim 6, wherein the resistive film portion is formed on the gate connection electrode with a part of the interlayer film in between, and is connected to the gate connection electrode.

10. The semiconductor device according to claim 9, wherein both ends of the resistive film portion in the first direction are located outward from both ends of the gate connection electrode in the first direction.

11. The first main surface further includes a plurality of first trench source structures formed in a stripe shape extending in the first direction, The first trench source structure is formed between a plurality of adjacent trench gate structures, Multiple of the aforementioned resistive film portions are included in a resistive wiring film that extends linearly in the second direction. The semiconductor device according to claim 9 or 10, wherein the resistive wiring film covers the first trench source structure, sandwiching a portion of the interlayer film.

12. The interlayer film includes a first insulating layer that covers a plurality of gate electrode films, The resistive film portion is formed on the first insulating layer and connected to the gate structure via a first contact opening formed in the first insulating layer. The interlayer film further includes a second insulating layer that covers the first insulating layer and the plurality of resistive film portions, The semiconductor device according to any one of claims 6, 7, 9, and 10, wherein the gate wiring is connected to the resistive film portion through a second contact opening formed in the second insulating layer.

13. The semiconductor device according to claim 12, wherein a plurality of the first contact openings and a plurality of the second contact openings are arranged in a stripe shape extending in the first direction.

14. The semiconductor device according to claim 12, wherein the second contact opening is formed overlapping the gate structure in a plan view.

15. The semiconductor device according to claim 12, wherein the second contact opening is formed to overlap the first contact opening in a plan view.

16. The semiconductor device according to claim 12, wherein the second contact opening is formed in a plan view, overlapping the gate structure with an offset in the first direction.

17. The semiconductor device according to claim 12, wherein the second contact opening is formed offset from the first contact opening in the first direction in a plan view.

18. Multiple second contact openings are formed in a 2:1 relationship with respect to multiple first contact openings. The semiconductor device according to claim 17, wherein the two second contact openings, in a plan view, sandwich the corresponding first contact opening in the second direction.

19. The semiconductor device according to claim 17, wherein a plurality of the second contact openings are formed in a one-to-one relationship with respect to a plurality of the first contact openings.

20. The semiconductor device according to any one of claims 1 to 7, 9, and 10, wherein the chip includes a SiC chip.

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