Semiconductor equipment

Abstract

We provide a semiconductor device that suppresses gate signal delay. [Solution] The semiconductor device 100 according to the present disclosure comprises a semiconductor substrate 60 on which a trench 20 is formed, a gate pad, a first gate wiring 11a, a second gate wiring 11b, a finger wiring 12, a first main electrode 50a, a second main electrode 50b, a lower electrode 31 provided inside the trench 20, and an upper electrode 30 provided inside the trench 20 on the lower electrode 31 via an insulating film 35, wherein the lower electrode 31 is in contact with the first gate wiring 11a or the second gate wiring 11b and the finger wiring 12, and the upper electrode 30 is in contact with the first gate wiring 11a or the second gate wiring 11b and the finger wiring 12.

Description

Technical Field

[0006] , , ,

[0001] This disclosure relates to semiconductor devices.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including an active trench having a gate insulating film provided along a trench of a semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to a gate electrode. The active portion is divided into two upper and lower portions via an intermediate insulating film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device such as that of Patent Document 1, the electrodes in the trench are divided vertically. Therefore, the area of the electrodes in the trench becomes small, resulting in an increase in wiring resistance and a possible delay in the gate signal.

[0005] This disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of suppressing a delay in a gate signal.

Means for Solving the Problems

[0006] The semiconductor device according to the first disclosure comprises a semiconductor substrate in which a first trench is formed, a gate pad provided on the semiconductor substrate, a first gate wiring provided on the semiconductor substrate and electrically connected to the gate pad, a second gate wiring provided on the semiconductor substrate and electrically connected to the gate pad, a finger wiring provided on the semiconductor substrate between the first gate wiring and the second gate wiring and electrically connected to the gate pad, a first main electrode provided on the semiconductor substrate between the first gate wiring and the finger wiring, a second main electrode provided on the semiconductor substrate between the second gate wiring and the finger wiring, a first lower electrode provided inside the first trench, and a first upper electrode provided inside the first trench on the first lower electrode via an insulating film, wherein the first lower electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring, and the first upper electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring.

[0007] The semiconductor device according to the second disclosure includes a semiconductor substrate in which a first trench is formed, an upper gate pad provided on the semiconductor substrate, a lower gate pad provided on the semiconductor substrate, a first lower gate wiring provided on the semiconductor substrate and electrically connected to the lower gate pad, a second lower gate wiring provided on the semiconductor substrate and electrically connected to the lower gate pad, a finger wiring provided on the semiconductor substrate between the first lower gate wiring and the second lower gate wiring and electrically connected to the lower gate pad, and a first main gate wiring provided on the semiconductor substrate between the first lower gate wiring and the finger wiring. The device comprises an electrode, a second main electrode provided on the semiconductor substrate between the second lower gate wiring and the finger wiring, an upper gate wiring provided on the semiconductor substrate between the first lower gate wiring or the second lower gate wiring and the finger wiring and electrically connected to the upper gate pad, a first lower electrode provided inside the first trench, and a first upper electrode provided inside the first trench on the first lower electrode via an insulating film, wherein the first lower electrode is in contact with the first lower gate wiring or the second lower gate wiring and the finger wiring, and the first upper electrode is in contact with the upper gate wiring. [Effects of the Invention]

[0008] In the semiconductor device according to the first disclosure, the first lower electrode and the first upper electrode each contact the first gate wiring or the second gate wiring and the finger wiring. This makes it possible to suppress wiring resistance and suppress gate signal delay. In the semiconductor device according to the second disclosure, the first lower electrode contacts the first lower gate wiring or the second lower gate wiring and the finger wiring. This makes it possible to suppress wiring resistance and suppress gate signal delay. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of the semiconductor device according to Embodiment 1, taken in a direction perpendicular to the direction in which the trench extends. [Figure 3] This is a cross-sectional view of the semiconductor device according to Embodiment 1, taken in a direction along the trench. [Figure 4] This is a cross-sectional view of the semiconductor device according to Embodiment 2, taken in a direction along the trench. [Figure 5] This is a plan view of the semiconductor device according to Embodiment 3. [Figure 6] This is a cross-sectional view of the semiconductor device according to Embodiment 4, taken in a direction perpendicular to the direction in which the trench extends. [Figure 7] This is a cross-sectional view of the semiconductor device according to Embodiment 4, taken in a direction along the trench. [Figure 8] This is a plan view of the semiconductor device according to Embodiment 5. [Figure 9] This is a cross-sectional view of the semiconductor device according to Embodiment 5, taken in a direction perpendicular to the direction in which the trench extends. [Figure 10] This is a cross-sectional view of the semiconductor device according to Embodiment 5, taken in a direction along the trench. [Figure 11] This is a plan view of the semiconductor device according to Embodiment 6. [Figure 12] This is a plan view of the semiconductor device according to Embodiment 7. [Figure 13] This is a plan view of the semiconductor device according to Embodiment 8. [Figure 14] This is a cross-sectional view of the semiconductor device according to Embodiment 9, taken in a direction perpendicular to the direction in which the trench extends. [Figure 15] This is a cross-sectional view of the semiconductor device according to Embodiment 9, taken in a direction along the trench. [Figure 16] This is a cross-sectional view of the semiconductor device according to Embodiment 10, taken in a direction perpendicular to the direction in which the trench extends. [Figure 17] This is a plan view of the semiconductor device according to Embodiment 10. [Modes for carrying out the invention]

[0010] The semiconductor device according to this embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repetitive description may be omitted.

[0011] Embodiment 1. FIG. 1 is a plan view of a semiconductor device 100 according to Embodiment 1. FIG. 2 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1 in a direction perpendicular to the direction in which the trench 20 extends. FIG. 3 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1 in the direction along the trench 20. That is, FIG. 3 is a cross-sectional view taken along the line A - B in FIG. 1. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 includes a semiconductor substrate 60. In the cross-sectional view, the semiconductor layer formed on the semiconductor substrate 60 and the collector electrode provided on the back surface of the semiconductor substrate 60 are omitted.

[0012] The semiconductor substrate 60 is, for example, a silicon substrate. A plurality of trenches 20 are formed in the semiconductor substrate 60. The plurality of trenches 20 extend along the straight line A - B in FIG. 1. A gate pad 10 is provided on the semiconductor substrate 60. A gate signal is input to the gate pad 10 from the outside. Gate wirings 11a, 11b and finger wirings 12 electrically connected to the gate pad 10 are provided on the semiconductor substrate 60. The finger wirings 12 are provided between the gate wirings 11a, 11b. The gate wirings 11a, 11b and the finger wirings 12 constitute the gate wiring 11. The gate wiring 11 may be a metal wiring and is formed, for example, of aluminum.

[0013] On the semiconductor substrate 60, a main electrode 50a is provided between the gate wiring 11a and the finger wiring 12. Also, on the semiconductor substrate 60, a main electrode 50b is provided between the gate wiring 11b and the finger wiring 12. In FIG. 2, the main electrode 50a or the main electrode 50b is shown as the main electrode 50. The main electrodes 50a and 50b are emitter electrodes and are electrically connected to an emitter pad (not shown). In plan view, the main electrodes 50a and 50b are surrounded by the gate wiring 11 including the gate wirings 11a and 11b and the finger wiring 12. The finger wiring 12 is arranged so as to divide the main electrode 50.

[0014] Inside the trench 20, an upper electrode 30 and a lower electrode 31 which are gate electrodes are provided. The upper electrode 30 and the lower electrode 31 are formed of, for example, polysilicon. The upper electrode 30 is provided on the lower electrode 31 via an insulating film 35. That is, the insulating film 35 divides the upper electrode 30 and the lower electrode 31. As shown in FIG. 2, the insulating film 35 is provided so as to surround both sides and the top and bottom of the lower electrode 31 and the upper electrode 30. The insulating film 35 is formed of, for example, SiO2.

[0015] As shown in FIG. 3, the upper electrode 30 contacts the gate wiring 11a, the gate wiring 11b, and the finger wiring 12. Specifically, an upper contact 40a is formed by forming an opening in the insulating film 35. In the upper contact 40a, the upper electrode 30 and the gate wiring 11 contact each other. Also, the lower electrode 31 contacts the gate wiring 11a, the gate wiring 11b, and the finger wiring 12. Specifically, a lower contact 40b is formed by forming an opening in the insulating film 35. In the lower contact 40b, the lower electrode 31 and the gate wiring 11 contact each other.

[0016] Note that the trench 20 extending in the A - B direction is divided directly below the finger wiring 12. In the present embodiment and the following embodiments, a plurality of portions divided in the A - B direction may be collectively regarded as one trench 20.

[0017] Next, the effects of this embodiment will be described. In this embodiment, the main electrode 50 is divided by the finger wiring 12. The upper electrode 30 and the lower electrode 31 are electrically connected to the gate wiring 11 by contacting the gate wiring 11a, 11b and the finger wiring 12, respectively. In this case, compared to the case without the finger wiring 12, the length of the trench 20 in the A-B direction is shortened by providing the finger wiring 12. Also, the wiring resistance of the gate wiring 11 is generally lower than that of the electrodes in the trench 20. Therefore, in this embodiment, wiring resistance can be suppressed, and the delay of the gate signal can be suppressed. In particular, even when the area of ​​the gate electrode is reduced by dividing the gate electrode into the upper electrode 30 and the lower electrode 31, the delay of the gate signal can be suppressed. Furthermore, by suppressing the delay of the gate signal, it is possible to increase the chip size, for example.

[0018] Furthermore, in this embodiment, the trench 20 is interrupted directly below the finger wiring 12 in the direction from gate wiring 11a to gate wiring 11b. As a result, the trench 20 becomes even shorter, and the delay of the gate signal can be suppressed.

[0019] The upper electrode 30 may contact only one of the gate wiring 11a or gate wiring 11b. Similarly, the lower electrode 31 may contact only one of the gate wiring 11a or gate wiring 11b. In the example in Figure 3, the gate electrode on the left side of the trench 20, which is divided into left and right sections, contacts the gate wiring 11a and the finger wiring 12, while the gate electrode on the right side contacts the gate wiring 11b and the finger wiring 12. In this case as well, the effect of suppressing gate signal delay can be obtained.

[0020] The shape of the gate wiring 11 is not limited to that shown in Figure 1. Furthermore, the semiconductor substrate 60 may be formed from a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond.

[0021] The modifications described above can be appropriately applied to the semiconductor device according to the following embodiments. Since the semiconductor device according to the following embodiments has many similarities with Embodiment 1, the explanation will focus on the differences from Embodiment 1.

[0022] Embodiment 2. Figure 4 is a cross-sectional view of the semiconductor device 200 according to Embodiment 2, taken along the trench 20. In the semiconductor device 200, the trench 20 is not interrupted directly below the finger wiring 12. Even with this structure, as in Embodiment 1, wiring resistance can be suppressed and gate signal delay can be suppressed.

[0023] Embodiment 3. Figure 5 is a plan view of the semiconductor device 300 according to Embodiment 3. The semiconductor device 300 differs from the semiconductor device 100 of Embodiment 1 in that it has a plurality of finger wirings 12a and 12b. The other configurations are the same as those of the semiconductor device 100. In the example of Figure 4, the main electrode 50 is divided into three main electrodes 50a, 50b, and 50c by the finger wirings 12a and 12b. The number of finger wirings 12 is not limited.

[0024] Similar to Embodiment 1, the trench 20 may be divided directly below the finger wirings 12a and 12b. If there are two finger wirings 12, the trench 20 is divided into three sections in the A-B direction. According to this embodiment, the trench 20 can be made even shorter, and the gate signal delay can be suppressed more effectively than in Embodiment 1. Note that, similar to Embodiment 2, the trench 20 does not necessarily have to be divided directly below the finger wirings 12a and 12b.

[0025] Embodiment 4. Figure 6 is a cross-sectional view of the semiconductor device 400 according to Embodiment 4, taken perpendicular to the direction in which the trench 20 extends. Figure 7 is a cross-sectional view of the semiconductor device 400 according to Embodiment 4, taken along the trench 20. In this embodiment, two types of trenches 20a and 20b are formed in the semiconductor substrate 60. The structure of trench 20a is the same as that of trench 20 in Embodiment 1. Inside trench 20b, a lower electrode 31 and an upper electrode 32 provided on the lower electrode 31 via an insulating film 35 are provided. The other structures are the same as those in Embodiment 1.

[0026] As shown in Figure 7, the lower electrode 31 of trench 20b contacts the gate wiring 11a, gate wiring 11b, and finger wiring 12. The upper electrode 32 of trench 20b contacts the main electrodes 50a and 50b. In other words, the upper electrode 30 and lower electrode 31 of trench 20a, and the lower electrode 31 of trench 20b are active electrodes electrically connected to the gate pad 10. The upper electrode 32 of trench 20b is a dummy electrode.

[0027] In this embodiment, the input capacitance can be adjusted by the upper electrode 32 connected to the main electrode 50.

[0028] The lower electrode 31 of the trench 20b may contact only one of the gate wiring 11a and gate wiring 11b. Similarly, the upper electrode 32 of the trench 20b may contact only one of the main electrode 50a or main electrode 50b. In the example shown in Figure 7, the lower electrode 31 of the left portion of the trench 20b, which is divided into left and right sections, contacts the gate wiring 11a and finger wiring 12, while the lower electrode 31 of the right portion contacts the gate wiring 11b and finger wiring 12. Furthermore, the upper electrode 32 of the left portion of the trench 20b, which is divided into left and right sections, contacts the main electrode 50a, while the upper electrode 32 of the right portion contacts the main electrode 50b.

[0029] The arrangement of trenches 20b is not limited. For example, trenches 20a and 20b may be arranged alternately. It is sufficient if some of the multiple trenches 20 shown in Figure 1 are replaced with trenches 20b.

[0030] Embodiment 5. Figure 8 is a plan view of the semiconductor device 500 according to Embodiment 5. Figure 9 is a cross-sectional view of the semiconductor device 500 according to Embodiment 5 in a direction perpendicular to the direction in which the trench 20 extends. Figure 10 is a cross-sectional view of the semiconductor device 500 according to Embodiment 5 in a direction along the trench 20. In other words, Figure 10 is a cross-sectional view of line C in Figure 8. The semiconductor device 500 is, for example, an IGBT. The semiconductor device 500 includes a semiconductor substrate 60. Note that in the cross-sectional view, the semiconductor layer formed on the semiconductor substrate 60 and the collector electrode provided on the back surface of the semiconductor substrate 60 are omitted.

[0031] An upper gate pad 513, a lower gate pad 515, an upper gate wiring 514 electrically connected to the upper gate pad 513, and a lower gate wiring 516 electrically connected to the lower gate pad 515 are provided on the semiconductor substrate 60. Gate signals are input to the upper gate pad 513 and the lower gate pad 515 from an external source. The upper gate pad 513 and the lower gate pad 515 are, for example, adjacent to each other.

[0032] The lower gate wiring 516 includes lower gate wirings 516a and 516b that are electrically connected to the lower gate pad 515. On the semiconductor substrate 60, finger wiring 12 is provided between the lower gate wirings 516a and 516b that are electrically connected to the lower gate pad 515.

[0033] On the semiconductor substrate 60, a main electrode 50a is provided between the lower gate wiring 516a and the finger wiring 12. On the semiconductor substrate 60, a main electrode 50b is provided between the lower gate wiring 516b and the finger wiring 12. In Figure 9, either the main electrode 50a or the main electrode 50b is shown as the main electrode 50. The main electrodes 50a and 50b are emitter electrodes and are electrically connected to an emitter pad (not shown).

[0034] The upper gate wiring 514 includes upper gate wirings 514a to 514d that are electrically connected to the upper gate pad 513. Upper gate wiring 514a is provided between the lower gate wiring 516a and the main electrode 50a. Upper gate wiring 514b is provided between the lower gate wiring 516b and the main electrode 50a. Upper gate wiring 514c is provided between the finger wiring 12 and the main electrode 50a. Upper gate wiring 514d is provided between the finger wiring 12 and the main electrode 50b. In plan view, the main electrodes 50a and 50b are surrounded by the upper gate wiring 514.

[0035] The semiconductor device 500 includes a lower electrode 531 provided inside the trench 20 and an upper electrode 530 provided inside the trench 20 on the lower electrode 531 via an insulating film 35. The upper electrode 530 is in contact with the upper gate wiring 514a, upper gate wiring 514b, upper gate wiring 514c, and upper gate wiring 514d. Specifically, an upper contact 40a is formed by the formation of an opening in the insulating film 35. At the upper contact 40a, the upper electrode 530 and the upper gate wiring 514 are in contact. The lower electrode 531 is in contact with the lower gate wiring 516a, lower gate wiring 516b, and finger wiring 12. Specifically, a lower contact 40b is formed by the formation of an opening in the insulating film 35. At the lower contact 40b, the lower electrode 531 and the lower gate wiring 516 are in contact.

[0036] In the example shown in Figure 10, the upper electrode 530 of the left portion of the trench 20, which is divided into left and right sections, is in contact with the upper gate wirings 514a and 514c, while the upper electrode 530 of the right portion is in contact with the upper gate wirings 514b and 514d. Additionally, the lower electrode 531 of the left portion of the trench 20, which is divided into left and right sections, is in contact with the lower gate wiring 516a and the finger wiring 12, while the lower electrode 531 of the right portion is in contact with the lower gate wiring 516b and the finger wiring 12.

[0037] In this embodiment as well, wiring resistance can be suppressed to reduce gate signal delay. Furthermore, by connecting the lower gate pad 515 to the upper gate pad 513, for example, the upper electrode 530 and the lower electrode 531 can be brought to the same potential. For example, a wire can be used for the connection. In addition, by connecting the lower gate pad 515 to the main electrode 50, the lower electrode 531 can be brought to the emitter potential. In this way, multiple states can be realized for the electrodes in the trench 20. Moreover, the potential of the lower electrode 531 can be changed depending on the connection, and capacitance adjustment can be easily performed.

[0038] Furthermore, separate gate signals can be input to the upper electrode 530 and the lower electrode 531. For example, the timing of the gate signals can be changed for the upper electrode 530 and the lower electrode 531. This makes it easier to adjust the carrier near the trench 20 and reduces losses during switching operation.

[0039] The shapes of the upper gate wiring 514 and the lower gate wiring 516 are not limited to those shown in Figure 8. The upper gate wiring 514 may be provided on the semiconductor substrate 60 between the lower gate wiring 516a or the lower gate wiring 516b and the finger wiring 12. The upper electrode 530 may contact any part of the upper gate wiring 514. For example, the upper electrode 530 may contact one or more of the upper gate wirings 514a, 514b, 514c, and 514d. Similarly, the lower electrode 531 may contact only one of the lower gate wirings 516a or the lower gate wiring 516b.

[0040] In this embodiment as well, the trench 20 is divided directly below the finger wiring 12 in the direction from the lower gate wiring 516a to the lower gate wiring 516b. Similar to Embodiment 2, the trench 20 does not necessarily have to be divided.

[0041] Embodiment 6. Figure 11 is a plan view of a semiconductor device 600 according to Embodiment 6. In this embodiment, the upper gate pad 513 and the lower gate pad 515 are provided on one side and the other side of the semiconductor substrate 60, respectively. Finger wiring 12 is provided between the upper gate pad 513 and the lower gate pad 515. The other configurations are the same as those of Embodiment 5.

[0042] Embodiment 7. Figure 12 is a plan view of the semiconductor device 700 according to Embodiment 7. The semiconductor device 700 includes a plurality of finger wirings 12a and 12b. The other configurations are the same as those of Embodiment 5.

[0043] The lower gate wiring 716 includes lower gate wirings 716a and 716b that are electrically connected to the lower gate pad 515. On the semiconductor substrate 60, finger wirings 12a and 12b are provided between the lower gate wirings 716a and 716b that are electrically connected to the lower gate pad 515.

[0044] On the semiconductor substrate 60, a main electrode 50a is provided between the lower gate wiring 716a and the finger wiring 12a. On the semiconductor substrate 60, a main electrode 50b is provided between the lower gate wiring 716b and the finger wiring 12b. On the semiconductor substrate 60, a main electrode 50c is provided between the finger wirings 12a and 12b.

[0045] The upper gate wiring 714 includes upper gate wirings 714a to 714f that are electrically connected to the upper gate pad 513. Upper gate wiring 714a is provided between the lower gate wiring 716a and the main electrode 50a. Upper gate wiring 714b is provided between the lower gate wiring 716b and the main electrode 50a. Upper gate wiring 714c is provided between the finger wiring 12a and the main electrode 50a. Upper gate wiring 714d is provided between the finger wiring 12b and the main electrode 50b. Upper gate wiring 714e is provided between the finger wiring 12a and the main electrode 50c. Upper gate wiring 714f is provided between the finger wiring 12b and the main electrode 50c.

[0046] In the example shown in Figure 12, the main electrode 50 is divided into three main electrodes 50a, 50b, and 50c by the finger wirings 12a and 12b. The number of finger wirings 12 is not limited. Similar to Embodiment 1, the trench 20 may be divided directly below the finger wirings 12a and 12b. Similar to Embodiment 2, the trench 20 does not have to be divided directly below the finger wirings 12a and 12b.

[0047] Embodiment 8. Figure 13 is a plan view of the semiconductor device 800 according to Embodiment 8. The semiconductor device 800 differs from Embodiment 5 in that, in addition to the IGBT region, a diode region 870 is formed on the semiconductor substrate 60. The other configurations are the same as those of Embodiment 5. In other words, the semiconductor device 800 may be an RC (Reverse Conducting) IGBT. Note that the semiconductor device 100 of Embodiment 1 may also be an RC IGBT.

[0048] Embodiment 9. Figure 14 is a cross-sectional view of the semiconductor device 900 according to Embodiment 9, taken perpendicular to the direction in which the trench 20 extends. Figure 15 is a cross-sectional view of the semiconductor device 900 according to Embodiment 9, taken along the trench 20. In this embodiment, two types of trenches 20c and 20d are formed in the semiconductor substrate 60. The structure of trench 20c is the same as that of trench 20 in Embodiment 5. Inside trench 20d, a lower electrode 531 and an upper electrode 532 provided on the lower electrode 531 via an insulating film 35 are provided. The other structures are the same as those in Embodiment 5.

[0049] As shown in Figure 15, the lower electrode 531 of trench 20d contacts the lower gate wiring 516a, the lower gate wiring 516b, and the finger wiring 12. The upper electrode 532 of trench 20d contacts the main electrodes 50a and 50b. The upper electrode 530 of trench 20c is an active electrode electrically connected to the gate pad 10. The upper electrode 532 of trench 20d is a dummy electrode.

[0050] In the example shown in Figure 15, the lower electrode 531 of the left portion of the trench 20d, which is divided into left and right sections, is in contact with the lower gate wiring 516a and the finger wiring 12, while the lower electrode 531 of the right portion is in contact with the lower gate wiring 516b and the finger wiring 12. Additionally, the upper electrode 532 of the left portion of the trench 20d, which is divided into left and right sections, is in contact with the main electrode 50a, while the upper electrode 532 of the right portion is in contact with the main electrode 50b.

[0051] In this embodiment, the capacitance can be adjusted by the upper electrode 532 connected to the main electrode 50. Furthermore, by changing the connection of the lower gate pad 515, the potential of the lower electrode 531 can be changed, making capacitance adjustment even easier.

[0052] In this embodiment as well, the lower electrode 531 of the trench 20d may contact only one of the lower gate wiring 516a and the lower gate wiring 516b. Also, the upper electrode 532 of the trench 20d may contact only one of the main electrode 50a or the main electrode 50b.

[0053] Embodiment 10. Figure 16 is a cross-sectional view of the semiconductor device 1000 according to Embodiment 10, taken in a direction perpendicular to the direction in which the trench 20 extends. Figure 17 is a plan view of the semiconductor device 1000 according to Embodiment 10. This embodiment differs from Embodiment 9 in that a trench 20e is provided instead of a trench 20d. The other configurations are the same as those of Embodiment 9.

[0054] Inside the trench 20e, there is a lower electrode 531 and an upper electrode 1032 which is provided above the lower electrode 531 via an insulating film 35. The lower electrode 531 of the trench 20e is in contact with the lower gate wiring 516a, the lower gate wiring 516b and the finger wiring 12. The upper electrode 1032 of the trench 20e is in contact with the lower gate wiring 516a, the lower gate wiring 516b and the finger wiring 12.

[0055] As shown in Figure 17, the lower electrode 531 of trench 20c is electrically connected to the lower gate wiring 516 via the lower contact 40b in the lower lifting region 41. The upper electrode 530 of trench 20c is electrically connected to the upper gate wiring 514 via the upper contact 40a. The upper electrode 1032 of trench 20e is electrically connected to the lower gate wiring 516 via the upper contact 40a. The lower electrode 531 of trench 20e is electrically connected to the lower gate wiring 516 via the lower contact 40b in the lower lifting region 41.

[0056] In this embodiment as well, the potential of the lower electrode 531 and the upper electrode 1032 can be changed by changing the connection of the gate pads, making it easy to adjust the capacitance.

[0057] Furthermore, each of the lower electrode 531 and the upper electrode 1032 only needs to be in contact with either the lower gate wiring 516a or the lower gate wiring 516b.

[0058] The various aspects of this disclosure are summarized below as an appendix. (Note 1) A semiconductor substrate in which the first trench is formed, A gate pad provided on the semiconductor substrate, A first gate wiring is provided on the semiconductor substrate and electrically connected to the gate pad, A second gate wiring is provided on the semiconductor substrate and electrically connected to the gate pad, On the semiconductor substrate, a finger wiring is provided between the first gate wiring and the second gate wiring, and is electrically connected to the gate pad, On the semiconductor substrate, a first main electrode is provided between the first gate wiring and the finger wiring, On the semiconductor substrate, a second main electrode is provided between the second gate wiring and the finger wiring, The first lower electrode is provided inside the first trench, Inside the first trench, a first upper electrode is provided on the first lower electrode via an insulating film, Equipped with, The first lower electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring. The semiconductor device is characterized in that the first upper electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring. (Note 2) The semiconductor device according to Appendix 1, characterized in that, in a plan view, the first main electrode and the second main electrode are surrounded by gate wiring including the first gate wiring, the second gate wiring, and the finger wiring. (Note 3) The semiconductor device according to Appendix 1 or 2, characterized in that the first trench is interrupted directly below the finger wiring in the direction from the first gate wiring to the second gate wiring. (Note 4) A semiconductor device according to any one of the appendices 1 to 3, characterized by comprising a plurality of the aforementioned finger wirings. (Note 5) A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first gate wiring or the second gate wiring and the finger wiring. The semiconductor device according to any one of the appendices 1 to 4, characterized in that the second upper electrode is in contact with the first main electrode or the second main electrode. (Note 6) A semiconductor substrate in which the first trench is formed, An upper gate pad provided on the semiconductor substrate, A lower gate pad provided on the semiconductor substrate, A first lower gate wiring is provided on the semiconductor substrate and is electrically connected to the lower gate pad, A second lower gate wiring is provided on the semiconductor substrate and is electrically connected to the lower gate pad, On the semiconductor substrate, a finger wiring is provided between the first lower gate wiring and the second lower gate wiring, and is electrically connected to the lower gate pad, On the semiconductor substrate, a first main electrode is provided between the first lower gate wiring and the finger wiring, On the semiconductor substrate, a second main electrode is provided between the second lower gate wiring and the finger wiring, On the semiconductor substrate, an upper gate wiring is provided between the first lower gate wiring or the second lower gate wiring and the finger wiring, and is electrically connected to the upper gate pad, The first lower electrode is provided inside the first trench, Inside the first trench, a first upper electrode is provided on the first lower electrode via an insulating film, Equipped with, The first lower electrode contacts the first lower gate wiring or the second lower gate wiring, and the finger wiring. A semiconductor device characterized in that the first upper electrode is in contact with the upper gate wiring. (Note 7) The aforementioned upper gate wiring is, A second upper gate wiring is provided between the first lower gate wiring and the first main electrode and is electrically connected to the upper gate pad, A second upper gate wiring is provided between the second lower gate wiring and the second main electrode and is electrically connected to the upper gate pad, A third upper gate wiring is provided between the finger wiring and the first main electrode and is electrically connected to the upper gate pad, A fourth upper gate wiring is provided between the finger wiring and the second main electrode and is electrically connected to the upper gate pad, Equipped with, The semiconductor device according to Appendix 6, characterized in that the first upper electrode is in contact with the first upper gate wiring, the second upper gate wiring, the third upper gate wiring, and the fourth upper gate wiring. (Note 8) The semiconductor device according to appendix 6 or 7, characterized in that, in a plan view, the first main electrode and the second main electrode are surrounded by the upper gate wiring. (Note 9) The semiconductor device according to any one of appendices 6 to 8, characterized in that the first trench is interrupted directly below the finger wiring in the direction from the first lower gate wiring to the second lower gate wiring. (Note 10) The semiconductor device according to any one of appendices 6 to 9, characterized in that the upper gate pad and the lower gate pad are adjacent to each other. (Note 11) A semiconductor device according to any one of appendices 6 to 9, characterized in that the finger wiring is provided between the upper gate pad and the lower gate pad. (Note 12) A semiconductor device according to any one of the appendices 6 to 11, characterized by comprising a plurality of the aforementioned finger wirings. (Note 13) A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first lower gate wiring or the second lower gate wiring and the finger wiring. The semiconductor device according to any one of appendices 6 to 12, characterized in that the second upper electrode is in contact with the first main electrode or the second main electrode. (Note 14) A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first lower gate wiring or the second lower gate wiring and the finger wiring. The semiconductor device according to any one of appendices 6 to 12, characterized in that the second upper electrode is in contact with the first lower gate wiring or the second lower gate wiring and the finger wiring. (Note 15) The semiconductor device according to any one of appendices 1 to 14, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor. (Note 16) The semiconductor device according to Appendix 15, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. [Explanation of symbols]

[0059] 10 Gate pad, 11, 11a, 11b Gate wiring, 12, 12a, 12b Finger wiring, 20, 20a-20e Trench, 30 Upper electrode, 31 Lower electrode, 32 Upper electrode, 35 Insulating film, 40a Upper contact, 40b Lower contact, 41 Lower pull-up region, 50, 50a-50c Main electrode, 60 Semiconductor substrate, 100, 200, 300, 400, 500 Semiconductor device, 513 Upper gate pad, 514, 514a-514d: Upper gate wiring, 515 Lower gate pad, 516, 516a, 516b Lower gate wiring, 530 Upper electrode, 531 Lower electrode, 532 Upper electrode, 600, 700 Semiconductor device, 714, 714a-714f Upper gate wiring: 716, 716a, 716b Lower gate wiring: 800 Semiconductor device: 870 Diode region: 900, 1000 Semiconductor device: 1032 Upper electrode

Claims

1. A semiconductor substrate in which the first trench is formed, A gate pad provided on the semiconductor substrate, A first gate wiring is provided on the semiconductor substrate and electrically connected to the gate pad, A second gate wiring is provided on the semiconductor substrate and electrically connected to the gate pad, On the semiconductor substrate, a finger wiring is provided between the first gate wiring and the second gate wiring, and is electrically connected to the gate pad, On the semiconductor substrate, a first main electrode is provided between the first gate wiring and the finger wiring, On the semiconductor substrate, a second main electrode is provided between the second gate wiring and the finger wiring, A first lower electrode is provided inside the first trench, Inside the first trench, a first upper electrode is provided on the first lower electrode via an insulating film, Equipped with, The first lower electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring. A semiconductor device characterized in that the first upper electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring.

2. The semiconductor device according to claim 1, characterized in that, in a plan view, the first main electrode and the second main electrode are surrounded by gate wiring including the first gate wiring, the second gate wiring, and the finger wiring.

3. The semiconductor device according to claim 1 or 2, characterized in that the first trench is divided directly below the finger wiring in the direction from the first gate wiring to the second gate wiring.

4. The semiconductor device according to claim 1 or 2, characterized by comprising a plurality of the aforementioned finger wirings.

5. A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first gate wiring or the second gate wiring and the finger wiring. The semiconductor device according to claim 1 or 2, characterized in that the second upper electrode is in contact with the first main electrode or the second main electrode.

6. A semiconductor substrate in which the first trench is formed, An upper gate pad provided on the semiconductor substrate, A lower gate pad provided on the semiconductor substrate, A first lower gate wiring is provided on the semiconductor substrate and is electrically connected to the lower gate pad, A second lower gate wiring is provided on the semiconductor substrate and is electrically connected to the lower gate pad, On the semiconductor substrate, a finger wiring is provided between the first lower gate wiring and the second lower gate wiring, and is electrically connected to the lower gate pad, On the semiconductor substrate, a first main electrode is provided between the first lower gate wiring and the finger wiring, On the semiconductor substrate, a second main electrode is provided between the second lower gate wiring and the finger wiring, On the semiconductor substrate, an upper gate wiring is provided between the first lower gate wiring or the second lower gate wiring and the finger wiring, and is electrically connected to the upper gate pad, A first lower electrode is provided inside the first trench, Inside the first trench, a first upper electrode is provided on the first lower electrode via an insulating film, Equipped with, The first lower electrode contacts the first lower gate wiring or the second lower gate wiring, and the finger wiring. A semiconductor device characterized in that the first upper electrode is in contact with the upper gate wiring.

7. The aforementioned upper gate wiring is, A first upper gate wiring is provided between the first lower gate wiring and the first main electrode and is electrically connected to the upper gate pad, A second upper gate wiring is provided between the second lower gate wiring and the second main electrode and is electrically connected to the upper gate pad, A third upper gate wiring is provided between the finger wiring and the first main electrode and is electrically connected to the upper gate pad, A fourth upper gate wiring is provided between the finger wiring and the second main electrode and is electrically connected to the upper gate pad, Equipped with, The semiconductor device according to claim 6, characterized in that the first upper electrode is in contact with the first upper gate wiring, the second upper gate wiring, the third upper gate wiring, and the fourth upper gate wiring.

8. The semiconductor device according to claim 6 or 7, characterized in that, in a plan view, the first main electrode and the second main electrode are surrounded by the upper gate wiring.

9. The semiconductor device according to claim 6 or 7, characterized in that the first trench is divided directly below the finger wiring in the direction from the first lower gate wiring to the second lower gate wiring.

10. The semiconductor device according to claim 6 or 7, characterized in that the upper gate pad and the lower gate pad are adjacent to each other.

11. The semiconductor device according to claim 6 or 7, characterized in that the finger wiring is provided between the upper gate pad and the lower gate pad.

12. The semiconductor device according to claim 6 or 7, characterized by comprising a plurality of the aforementioned finger wirings.

13. A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first lower gate wiring or the second lower gate wiring and the finger wiring. The semiconductor device according to claim 6 or 7, characterized in that the second upper electrode is in contact with the first main electrode or the second main electrode.

14. A second lower electrode is provided inside the second trench formed in the semiconductor substrate, Inside the second trench, a second upper electrode is provided on the second lower electrode via an insulating film, Equipped with, The second lower electrode contacts the first lower gate wiring or the second lower gate wiring and the finger wiring. The semiconductor device according to claim 6 or 7, characterized in that the second upper electrode is in contact with the first lower gate wiring or the second lower gate wiring and the finger wiring.

15. The semiconductor device according to claim 1 or 6, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor.

16. The semiconductor device according to claim 15, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

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