Semiconductor memory devices and semiconductor devices

Abstract

To provide semiconductor memory devices and semiconductor devices capable of manufacturing high-quality semiconductor devices. [Solution] The semiconductor memory device comprises an oxide semiconductor stretched in the vertical direction, a first electrode including a first conductor containing a first oxide conductive material and connected to the upper end of the oxide semiconductor, a gate electrode facing the oxide semiconductor via a gate insulating film, a second electrode provided below the oxide semiconductor and extending in the vertical direction, a dielectric layer provided on the outer circumferential surface of the second electrode, and a third electrode provided on the outer circumferential surface of the dielectric layer, wherein the second electrode includes a second conductor containing a second oxide conductive material, connected to the lower end of the oxide semiconductor, and having a facing surface that faces the inner circumferential surface of the third electrode across the dielectric layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a semiconductor device.

Background Art

[0002] Among semiconductor elements, there are some that use a metal oxide containing indium and tin as an electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the manufacturing process of a semiconductor element in which a metal oxide is used as an electrode, a technique for manufacturing a high-quality semiconductor device is required.

[0005] The present disclosure aims to provide a semiconductor memory device and a semiconductor device capable of manufacturing a high-quality semiconductor device.

Means for Solving the Problems

[0006] The semiconductor memory device according to the present disclosure includes an oxide semiconductor extending in the vertical direction, a first electrode including a first oxide conductive material and including a first conductor connected to the upper end of the oxide semiconductor, a gate electrode facing the oxide semiconductor through a gate insulating film, a second electrode provided below the oxide semiconductor and extending in the vertical direction, a dielectric layer provided on the outer peripheral surface of the second electrode, and a third electrode provided on the outer peripheral surface of the dielectric layer. The second electrode includes a second oxide conductive material, is connected to the lower end of the oxide semiconductor, and includes a second conductor having an opposing surface facing the inner peripheral surface of the third electrode with the dielectric layer interposed therebetween.

[0007] The semiconductor device according to this disclosure comprises an oxide semiconductor stretched in the vertical direction, a first electrode including a first conductor connected to the upper end of the oxide semiconductor and containing a first oxide conductive material, a gate electrode facing the oxide semiconductor via a gate insulating film, and a second electrode connected to the lower end of the oxide semiconductor and containing a second oxide conductive material, wherein the first contact portion between the oxide semiconductor and the second electrode does not contact the seam included in the second electrode.

[0008] The semiconductor memory device according to this disclosure comprises a semiconductor device, a first capacitor electrode connected to the second electrode, a second capacitor electrode facing the first capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array according to the first embodiment. [Figure 2] This is a schematic cross-sectional diagram illustrating an example of the structure of a semiconductor memory device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane. [Figure 3] This shows a detailed cross-sectional view of the semiconductor memory device 101 as seen from a cross-section 70ZX that is parallel to the ZX plane and is contained within the oxide semiconductor layer 70. [Figure 4] This shows a detailed cross-sectional view of the semiconductor memory device 101 as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the oxide semiconductor layer 70. [Figure 5] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device according to the first embodiment. [Figure 6] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device according to the first embodiment. [Figure 7] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device according to the first embodiment. [Figure 8] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device according to the first embodiment. [Figure 9] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 10] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 11] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 12] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 13] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 14] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 15] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 16] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 17] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 18] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 19] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 20] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 21] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 22] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 23] It is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device of the first embodiment. [Figure 24]This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device according to the first embodiment. [Figure 25] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor according to the first embodiment. [Figure 26] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor according to the first embodiment. [Figure 27] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor according to the first embodiment. [Figure 28] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor according to the first embodiment. [Figure 29] This is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor according to the first embodiment. [Figure 30] This shows a detailed cross-sectional view of a modified semiconductor memory device 101, as seen from a cross-section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70. [Figure 31] This shows a detailed cross-sectional view of a modified semiconductor memory device 101, specifically a cross-section 70YZ parallel to the YZ plane, as viewed from the cross-section 70YZ contained within the oxide semiconductor layer 70. [Figure 32] This shows a cross-sectional view of the semiconductor memory device 102 as seen from a cross-section 70ZX that is parallel to the ZX plane and is contained within the oxide semiconductor layer 70. [Figure 33] This is a plan view of capacitor 120 as seen from above. [Figure 34] This is a schematic diagram to explain Seam 301. [Figure 35] This is a plan view of the metal oxide layer 50a as seen from below. [Figure 36] This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of a comparative semiconductor device. [Figure 37] This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of a comparative semiconductor device. [Figure 38] This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of a comparative semiconductor device. [Figure 39]This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of a comparative semiconductor device. [Figure 40] This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of a comparative semiconductor device. [Figure 41] This is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device according to the second embodiment. [Figure 42] This is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device according to the second embodiment. [Figure 43] This is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device according to the second embodiment. [Figure 44] This is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device according to the second embodiment. [Figure 45] This is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device according to the second embodiment. [Figure 46] This is a diagram illustrating seam 302, which is a modified version of seam 301. [Figure 47] This is a diagram illustrating seam 303, which is a modified version of seam 301. [Figure 48] This is a diagram illustrating seam 304, which is a modified version of seam 301. [Figure 49] This is a diagram illustrating seam 305, a modified version of seam 301. [Modes for carrying out the invention]

[0010] This embodiment will now be described with reference to the attached drawings. To facilitate understanding of the explanation, the same reference numerals are used for identical components in each drawing whenever possible, and redundant explanations are omitted.

[0011] [First Embodiment] The configuration of the semiconductor memory device according to the first embodiment will now be described. Each drawing may show the X, Y, and Z axes. The X, Y, and Z axes form a three-dimensional Cartesian coordinate system in a right-handed system. Hereinafter, the direction of the arrow on the X axis may be called the X-axis+ direction, and the direction opposite to the arrow may be called the X-axis- direction, and the same applies to the other axes. The Z-axis+ direction and Z-axis- direction may also be called "up" and "down," respectively. Furthermore, the planes perpendicular to the X, Y, or Z axes may be called the YZ plane, ZX plane, or XY plane. The direction in the Z axis direction may also be called the "up and down direction." "Up," "down," and "up and down direction" are terms that indicate relative positional relationships within the drawings and do not define orientations based on the vertical direction.

[0012] Furthermore, unless otherwise specifically stated, the dimensions of the components shown in each drawing may differ from the actual dimensions in order to facilitate understanding of the explanation.

[0013] In this specification, “connection” includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0014] In this specification, "formed above" includes not only cases where it is formed in contact with what is above, but also cases where it is formed above through another object, unless otherwise specified. The same applies to cases such as "formed below."

[0015] The semiconductor memory device 101 according to the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) and includes a memory cell array.

[0016] As shown in Figure 1, the memory cell array includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0017] Figure 1 shows an example of multiple word lines WL, n Word line WL n+1 and word line WL n+2This is shown (where n is a positive integer). Also, Figure 1 shows an example of a bit line BL. m , bit line BL m+1 and bit line BL m+2 This is shown (where m is a positive integer). Note that the number of memory cells MC is not limited to the number shown in Figure 1.

[0018] Multiple memory cells (MCs) are arranged, for example, in a matrix to form a memory cell array. A memory cell MC includes a memory transistor (MTR), which is a field-effect transistor (FET), and a memory capacitor (MCP).

[0019] A series of memory cells MC arranged along the row direction have a word line WL (e.g., word line WL) corresponding to the row to which they belong (e.g., row n). n A series of memory cells MCs arranged along the column direction are connected to the bit line BL (e.g., bit line BL) corresponding to the column to which they belong (e.g., the m+2th column). m+2 It connects to ).

[0020] More specifically, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs. Either the source or the drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0021] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to the other electrode of the source or drain of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power line (not shown) that supplies a specific potential.

[0022] The memory cell MC is configured to retain data by accumulating charge in the memory capacitor MCP through the current flowing through the corresponding bit line BL, which is achieved by switching the memory transistor MTR based on the potential of the corresponding word line WL.

[0023] As shown in Figure 2, the semiconductor memory device 101 comprises a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, and 63.

[0024] The capacitor 20 includes a dielectric layer 22 (an example of a "dielectric film"), a conductor 23, an electrode 24 ("second electrode"), and an electrode 25 (an example of a "third electrode" and "second capacitor electrode").

[0025] The semiconductor device 30 includes a field-effect transistor 40 (an example of a "semiconductor element"), an electrode 50 (an example of a "first electrode") provided above the field-effect transistor 40, and an electrode 24 (an example of a "second electrode") provided below the field-effect transistor 40.

[0026] The field-effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of a "gate electrode"), and an insulating layer 45. The field-effect transistor 40 corresponds to the memory transistor MTR of a memory cell MC (see Figure 1).

[0027] The oxide semiconductor layer 70 is formed within the insulating layer 45 and has an upper end 70a and a lower end 70b. The oxide semiconductor layer 70 is a columnar body that extends along the vertical direction. The oxide semiconductor layer 70 has a central axis 70d (an example of a "second central axis") that is substantially parallel to the Z-axis. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0028] The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies act as donors. The oxide semiconductor layer 70 contains at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), iridium (Ir), ruthenium (Ru), and titanium (Ti), as well as oxygen.

[0029] In this embodiment, the oxide semiconductor layer 70 contains indium, zinc, and gallium as metallic elements. More specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, i.e., IGZO (InGaZnO). However, the oxide semiconductor layer 70 may be made of other types of oxide semiconductors.

[0030] The field-effect transistor 40 is a so-called vertical transistor having a channel that extends in the Z-axis direction (up and down direction) approximately perpendicular to the surface of the semiconductor substrate 10.

[0031] The conductive layer 42 faces the oxide semiconductor layer 70 via a gate insulating film 43. More specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40 and surrounds the oxide semiconductor layer 70 via the gate insulating film 43 between its upper end 70a and lower end 70b. The conductive layer 42 contains, for example, tungsten (W).

[0032] The conductive layer 42 is made up of multiple electrodes that extend approximately parallel to the Y-axis and are repeatedly provided in the X-axis direction. These electrodes correspond to the word line WL (see Figure 1).

[0033] The gate insulating film 43 includes, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen. The gate insulating film 43 is formed to cover the entire circumference of the side surface of the oxide semiconductor layer 70.

[0034] The electrode 50 is formed above the oxide semiconductor layer 70 and connected to the upper end 70a of the oxide semiconductor layer 70. The electrode 50 includes a metal oxide layer 50a (an example of the "first conductor"), a barrier metal layer 50b, and a metal film 50c.

[0035] The metal oxide layer 50a is connected to the upper end 70a of the oxide semiconductor layer 70. In this embodiment, the metal oxide layer 50a is in contact with the upper end 70a of the oxide semiconductor layer 70. The metal oxide layer 50a contains a first oxide conductive material. Specifically, the first oxide conductive material is an oxide conductive material containing indium and tin as metal elements. More specifically, the first oxide conductive material is indium-tin oxide (ITO).

[0036] The metal film 50c is provided above the metal oxide layer 50a and contains tungsten. The barrier metal layer 50b is formed between the metal oxide layer 50a and the metal film 50c. The barrier metal layer 50b contains, for example, titanium and nitrogen. In this embodiment, the barrier metal layer 50b is formed of titanium nitride (TiN).

[0037] Circuit 11 comprises peripheral circuits such as a decoder for selecting a predetermined memory cell MC from among multiple memory cells MC of the semiconductor memory device 101, i.e., capacitors 20 and field-effect transistors 40, a sense amplifier connected to the bit line BL, and a register composed of SRAM. Circuit 11 may include a CMOS circuit having field-effect transistors, specifically P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs), formed using a CMOS process.

[0038] The field-effect transistor of circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon substrate. Pch-FETs and Nch-FETs are so-called lateral field-effect transistors that have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have a channel for flowing carriers in the X-axis direction or Y-axis direction substantially parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a P-type to N-type conductivity. For convenience, Figure 2 shows an example of the field-effect transistor of circuit 11.

[0039] Capacitor 20 is a memory capacitor MCP included in the memory cell MC (see Figure 1). Figure 2 shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0040] Figure 3 shows a detailed cross-sectional view of the semiconductor memory device 101 as seen from the cross-section 70ZX, which is parallel to the ZX plane and is contained within the oxide semiconductor layer 70. Figure 4 shows a detailed cross-sectional view of the semiconductor memory device 101 as seen from the cross-section 70YZ, which is parallel to the YZ plane and is contained within the oxide semiconductor layer 70.

[0041] As shown in Figures 3 and 4, the capacitor 20 is located below the oxide semiconductor layer 70 and above the semiconductor substrate 10. The electrodes 24 in the capacitor 20 are located below the oxide semiconductor layer 70 and have a columnar shape extending in the vertical direction. The upper end of the electrodes 24 is connected to the lower end 70b of the oxide semiconductor layer 70.

[0042] The dielectric layer 22 is provided on the outer circumferential surface 24o of the electrode 24. The electrode 25 is provided on the outer circumferential surface 22o of the dielectric layer 22.

[0043] In detail, the electrode 24 includes a conductive film 21 (an example of a "third conductor") and a metal oxide layer 32 (an example of a "second conductor").

[0044] The metal oxide layer 32 contains a secondary oxide conductive material. The secondary oxide conductive material contains at least one of indium (In), zinc (Zn), tin (Sn), iridium (Ir), ruthenium (Ru), titanium (Ti), and tungsten (W), and oxygen.

[0045] In this embodiment, the second oxide conductive material comprises indium, tin, and oxygen. Specifically, the second oxide conductive material is indium-tin oxide (ITO) similar to that of the metal oxide layer 50a.

[0046] The upper end of the metal oxide layer 32 is in contact with the lower end 70b of the oxide semiconductor layer 70. The metal oxide layer 32 has a columnar shape extending in the vertical direction. The metal oxide layer 32 has a central axis 32d (an example of a "first central axis") that is approximately parallel to the Z axis. The central axis 32d is aligned with the central axis 70d.

[0047] A portion of the lower part of the outer circumferential surface of the metal oxide layer 32 is a facing surface 32a that faces the inner circumferential surface 25i of the electrode 25, with the dielectric layer 22 in between.

[0048] The conductive film 21 in the electrode 24 is provided between the metal oxide layer 32 and the dielectric layer 22. Specifically, the conductive film 21 is provided on the outer circumferential surface of the metal oxide layer 32. The conductive film 21 has a cup shape with an open top, and the metal oxide layer 32 is housed within this cup.

[0049] The conductive film 21 contains, for example, titanium and nitrogen. In this embodiment, the conductive film 21 is formed of titanium nitride. The outer surface of the conductive film 21 is the outer surface 24o of the electrode 24.

[0050] The dielectric layer 22 includes insulating films 22a and 22b. The insulating film 22a is provided on the outer circumferential surface 24o of the electrode 24. The insulating film 22a has a cup shape with an open top, and the electrode 24 is housed within the cup.

[0051] The insulating film 22b is provided on the outer circumferential surface of the insulating film 22a. The insulating film 22b has a cup shape with an opening at the top, and the insulating film 22a is housed within this cup.

[0052] The upper end of the metal oxide layer 32, the upper open end of the conductive film 21, the upper open end of the insulating film 22a, and the upper open end of the insulating film 22b are aligned in the Z direction.

[0053] The insulating films 22a and 22b are formed from materials with high dielectric constants. Specifically, insulating film 22a may contain materials such as ZrO containing zirconium and oxygen. Insulating film 22b may contain materials such as ZrAlO containing zirconium, aluminum, and oxygen. The outer surface of insulating film 22b is the outer surface 22o of the dielectric layer 22.

[0054] The electrode 25 is provided on a portion of the lower part of the outer peripheral surface 22o of the dielectric layer 22. The electrode 25 has a cup shape with an open top, and a portion of the lower part of the dielectric layer 22 is housed within the cup. The electrode 25 also has a lower end that contacts the upper surface of the conductor 23.

[0055] The electrode 25 contains, for example, titanium and nitrogen. In this embodiment, the electrode 25 is formed of titanium nitride. The upper open end of the electrode 25 is located below the upper end of the metal oxide layer 32. The inner circumferential surface 25i of the electrode 25 faces a portion of the lower part of the outer circumferential surface 24o of the electrode 24, with the dielectric layer 22 in between.

[0056] The conductor 23 contacts the lower ends of the multiple electrodes 25 contained in each of the multiple capacitors 20. The conductor 23 functions, for example, as a ground electrode that is grounded. The conductor 23 may contain a material such as tungsten or titanium nitride.

[0057] As shown in Figure 2, the conductor 33 includes wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 may include via wiring, for example, that extends in the Z-axis direction and has via wiring that connects the word line WL to the circuit 11 provided on the semiconductor substrate 10. The conductor 33 is made of, for example, copper.

[0058] The insulating layer 34 is provided between multiple capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0059] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen. The upper surface of the insulating layer 35 is aligned in the Z direction with the upper end of the electrode 24 and the upper end of the dielectric layer 22.

[0060] [Method for manufacturing a semiconductor memory device] The following describes a method for manufacturing a semiconductor memory device 101 as an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0061] First, as shown in Figure 5, insulating layers 34 and 35 are formed in this order above the conductor 23. Each of the conductor 23, insulating layer 34, and insulating layer 35 extends along a plane substantially parallel to the XY plane.

[0062] Next, as shown in Figure 6, a hard mask layer 36 and a resist layer 37 are formed above the insulating layer 35 in that order. Each of the hard mask layer 36 and the resist layer 37 extends along a plane substantially parallel to the XY plane. Then, exposure, development, and peeling are performed on the surface of the resist layer 37 by lithography, and a plurality of openings 37a are formed in the resist layer 37.

[0063] Next, as shown in Figure 7, the hard mask layer 36 exposed through the opening 37a of the resist layer 37 is removed by reactive ion etching. This forms an opening 36a in the hard mask layer 36 that is continuous with the opening 37a.

[0064] Next, as shown in Figure 8, reactive ion etching removes a portion of the insulating layer 35 and a portion of the insulating layer 34 through openings 37a and 36a. This forms a capacitor hole CH whose bottom reaches the conductive material 23.

[0065] Next, as shown in Figure 9, the electrode 25 is formed on the inner surface of the capacitor hole CH and on the surface above the insulating layer 35.

[0066] Next, as shown in Figure 10, an insulating layer 134 is formed above the electrode 25. The insulating layer 134 is, for example, a silicon oxide film containing silicon and oxygen. Then, a portion of the upper part of the insulating layer 134 is removed by reactive ion etching. This forms an insulating layer 134 that fills a portion of the lower part of the capacitor hole CH.

[0067] Next, as shown in Figure 11, the electrode 25 exposed above the upper edge of the insulating layer 134 is removed by etching. This forms the electrode 25 that will be provided on the inner surface of the capacitor hole CH. The upper edge of the electrode 25 is then located below the upper surface of the insulating layer 35.

[0068] Next, as shown in Figure 12, the insulating layer 134 inside the capacitor hole CH is removed by etching.

[0069] Next, as shown in Figure 13, insulating film 22b, insulating film 22a, and conductive film 21 are deposited in this order on the inner surface of the capacitor hole CH and on the surface above the insulating layer 35.

[0070] Next, as shown in Figure 14, a metal oxide layer 32 is deposited on the upper surface of the conductive film 21. The metal oxide layer 32 is deposited inside the capacitor hole CH by, for example, ALD (Atomic Layer Deposition).

[0071] Next, as shown in Figure 15, a portion of the upper parts of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b is removed by chemical mechanical polishing, exposing the insulating layer 35. This forms the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b separated for each capacitor hole CH. The upper edges of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z direction.

[0072] Next, as shown in Figure 16, an insulating film 45b, a conductive layer 42, and an insulating film 45a are provided above the insulating layer 35 in this order. Each of the insulating film 45b, the conductive layer 42, and the insulating film 45a extends along a plane substantially parallel to the XY plane.

[0073] Next, as shown in Figure 17, a mask is formed above the insulating film 45a by, for example, lithography, and then transistor holes TH are formed by reactive ion etching. The transistor holes TH extend approximately parallel to the Z-axis and penetrate the insulating film 45a, the conductive layer 42, and the insulating film 45b. At the bottom of the transistor holes TH, the upper surface of the metal oxide layer 32 is exposed. The transistor holes TH have a tapered shape, with the cross-section becoming smaller towards the bottom.

[0074] Next, as shown in Figure 18, a gate insulating film 43 is formed so as to cover the upper surface of the insulating film 45a and the inner surface of the transistor hole TH.

[0075] Next, as shown in Figure 19, a portion of the gate insulating film 43 is etched by reactive ion etching. As a result, the upper surface of the metal oxide layer 32 is exposed at the bottom of the transistor hole TH.

[0076] Next, as shown in Figure 20, an oxide semiconductor layer 70 is formed on the upper surface of the insulating film 45a and on the transistor hole TH. The lower end 70b of the oxide semiconductor layer 70 contacts the upper surface of the metal oxide layer 32 exposed at the bottom of the transistor hole TH. As a result, the transistor hole TH is filled with the oxide semiconductor layer 70.

[0077] Next, as shown in Figure 21, a portion of the oxide semiconductor layer 70 is removed, exposing the upper surface of the insulating film 45a. At this time, the upper surface 70a of the oxide semiconductor layer 70 is aligned in the Z direction with the upper edge of the gate insulating film 43 and the upper surface of the insulating film 45a.

[0078] Next, as shown in Figure 22, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed in this order above the oxide semiconductor layer 70 and the insulating film 45a. Each of the metal oxide layer 50a, barrier metal layer 50b, and metal film 50c extends along a plane substantially parallel to the XY plane.

[0079] Next, as shown in Figure 23, electrodes 50 are formed for each oxide semiconductor layer 70 by etching a portion of each of the metal film 50c, barrier metal layer 50b, and metal oxide layer 50a. The electrodes 50 function as landing pads.

[0080] Next, as shown in Figure 24, an insulating layer 63 is formed to cover the electrode 50. The insulating layer 63 contains, for example, a silicon oxide. Then, a portion of the insulating layer 63 is chemically and mechanically polished, exposing the upper surface of the electrode 50.

[0081] [Manufacturing method for capacitor 120] The following describes a method for manufacturing a capacitor 120 having a structure different from that of capacitor 20.

[0082] First, as shown in Figure 25, the manufacturing method of capacitor 120 differs from that of capacitor 20 shown in Figure 15 in that an electrode 124 is deposited on the upper surface of the conductive film 21 instead of the metal oxide layer 32. The electrode 124 contains, for example, SiGe containing silicon and germanium. The electrode 124 is deposited inside the capacitor hole CH by, for example, CVD (Chemical Vapor Deposition).

[0083] Next, as shown in Figure 26, chemical mechanical polishing removes a portion of the upper parts of each electrode 124, conductive film 21, insulating film 22a, and insulating film 22b, exposing the insulating layer 35. This forms electrodes 124, conductive film 21, insulating film 22a, and insulating film 22b separated for each capacitor hole CH. The upper edges of each electrode 124, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z direction.

[0084] Next, as shown in Figure 27, a portion of the upper part of electrode 124 is removed by etching. This forms an electrode 124 (an example of a "first capacitor electrode") that fills a portion of the lower part of capacitor hole CH.

[0085] Next, as shown in Figure 28, a barrier metal layer 224 and a metal oxide layer 132 are deposited in this order above the capacitor hole CH. The barrier metal layer 224 contains, for example, titanium nitride containing nitrogen and titanium. The metal oxide layer 132 contains, for example, ITO.

[0086] Next, as shown in Figure 29, a portion of the upper parts of the metal oxide layer 132 and the barrier metal layer 224 is removed by chemical mechanical polishing, exposing the insulating layer 35. The upper edges of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224, and metal oxide layer 132 are aligned in the Z direction.

[0087] (effect) As shown in Figures 25 to 29, the manufacturing method for the capacitor 120 includes the steps of chemical mechanical polishing, recess formation by removing a portion above the electrode 124, deposition of the barrier metal layer 224 and the metal oxide layer 132, and chemical mechanical polishing, from the deposition of the electrode 124 until the capacitor 120 is completed.

[0088] In contrast, in the manufacturing method for the capacitor 20, as shown in Figures 14 and 15, the capacitor 20 is completed by depositing a metal oxide layer 32 and then performing chemical mechanical polishing. In other words, the capacitor 20 can be manufactured using a simple process.

[0089] Furthermore, in the capacitor 120, the resistance value becomes high due to the contact resistance between the metal oxide layer 132 and the barrier metal layer 224, and between the barrier metal layer 224 and the electrode 124.

[0090] In contrast, the capacitor 20 has a configuration in which a metal oxide layer 32 is provided instead of the metal oxide layer 132, electrode 124, and barrier metal layer 224, so that the above-mentioned contact resistance does not occur and the resistance value can be lowered.

[0091] Furthermore, the metal oxide layer 132 in capacitor 120 has a smaller volume than the metal oxide layer 32 in capacitor 20. For this reason, the metal oxide layer 132 may disappear during the gate insulating film formation process (see Figure 18) and the etching process (see Figure 19).

[0092] In contrast, the capacitor 20 has a configuration in which the volume of the metal oxide layer 32 is large, which makes it possible to suppress the disappearance of the metal oxide layer 132 during the gate insulating film formation process (see Figure 18) and the etching process (see Figure 19).

[0093] It is also conceivable to have an electrode 124 (see Figure 26) provided in place of the metal oxide layer 32 in contact with the lower end 70b of the oxide semiconductor layer 70, but since the work functions of SiGe and IGZO do not match well, the resistance value will be high.

[0094] In contrast, the semiconductor memory device 101 can lower its resistance by bringing the metal oxide layer 32 (ITO), which has a good work function match, into contact with the lower end 70b of the oxide semiconductor layer 70 (IGZO).

[0095] (Variable example of semiconductor memory device 101) Figure 30 shows a detailed cross-sectional view of a modified semiconductor memory device 101, specifically a cross-section 70ZX parallel to the ZX plane, as viewed from the cross-section 70ZX contained within the oxide semiconductor layer 70. Figure 31 shows a detailed cross-sectional view of a modified semiconductor memory device 101, specifically a cross-section 70YZ parallel to the YZ plane, as viewed from the cross-section 70YZ contained within the oxide semiconductor layer 70.

[0096] As shown in Figures 30 and 31, a modified version of the semiconductor memory device 101, compared to the semiconductor memory device 101 shown in Figures 3 and 4, includes a capacitor 20a instead of capacitor 20.

[0097] The electrode 24 in capacitor 20a does not contain the conductive film 21, unlike the electrode 24 in capacitor 20. In other words, the outer surface of the metal oxide layer 32 becomes the outer surface 24o of the electrode 24.

[0098] In this way, by omitting the conductive film 21, the step of depositing the conductive film 21 can be omitted. In other words, the capacitor 20a can be manufactured using a simple process.

[0099] [Second Embodiment] The semiconductor memory device 102 according to the second embodiment will now be described. In the second embodiment and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects and advantages due to similar configurations will not be mentioned sequentially for each embodiment.

[0100] Figure 32 shows a cross-sectional view of the semiconductor memory device 102 as seen from a cross-section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70.

[0101] As shown in Figure 32, the semiconductor memory device 102 according to the second embodiment includes a semiconductor device 30B and a capacitor 120 instead of the semiconductor device 30 and capacitor 20 shown in Figures 3 and 4.

[0102] Compared to capacitor 20, capacitor 120 includes electrodes 124, a metal oxide layer 132, and a barrier metal layer 224 instead of the metal oxide layer 32.

[0103] Figure 33 is a plan view of the capacitor 120 as seen from above. As shown in Figures 32 and 33, in the semiconductor device 30B, the barrier metal layer 224 forms a recessed area 224a that is indented downwards.

[0104] In detail, the barrier metal layer 224 has a cup shape with an upward opening. The lower surface of the barrier metal layer 224 is in contact with the upper surface of the electrode 124. The side surface of the barrier metal layer 224 is in contact with the upper inner surface of the conductive film 21.

[0105] The metal oxide layer 132 (an example of a "second electrode") is embedded in the recess 224a. The upper edges of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224, and metal oxide layer 132 are aligned in the Z direction.

[0106] Furthermore, the metal oxide layer 132 is connected to the lower end 70b of the oxide semiconductor layer 70 and contains a second oxide conductive material. In this embodiment, the upper surface 211 of the metal oxide layer 132 is in contact with the lower end 70b of the oxide semiconductor layer 70.

[0107] The contact portion 201 (an example of the "first contact portion") between the metal oxide layer 132 and the oxide semiconductor layer 70 is approximately circular. The metal oxide layer 132 is a cylinder having a central axis extending in the vertical direction.

[0108] Figure 34 is a schematic diagram illustrating the seam 301. As shown in Figures 32 to 34, the metal oxide layer 132 includes the seam 301. When the metal oxide layer 132 is viewed along the vertical direction, the centroid 211cg of the upper surface 211 of the metal oxide layer 132 coincides with the seam 301.

[0109] For example, when ITO is filled into a recess 224a by sputtering, the outer peripheral portion 211o, which is close to the side surface of the recess 224a, is filled with ITO, but the central portion 211c, which is further away from the side surface and closer to the center of gravity 211cg, may not be filled sufficiently.

[0110] The portion of the cavity that is not filled with ITO is the seam 301. In this embodiment, the seam 301 has a spindle shape that is elongated in the vertical direction.

[0111] Furthermore, the metal oxide layer 132 filled in the recess 224a includes a transverse orientation portion 132L and a longitudinal orientation portion 132V. The transverse orientation portion 132L is close to the side surface of the recess 224a, and the ITO is oriented along a plane parallel to the XY plane. The longitudinal orientation portion 132V is located closer to the center of gravity 211cg than the transverse orientation portion 132L, and the ITO is oriented along an axis parallel to the Z axis.

[0112] The contact portion 201 between the oxide semiconductor layer 70 and the metal oxide layer 32 does not come into contact with the seam 301 contained in the metal oxide layer 32.

[0113] When the metal oxide layer 132 is viewed along the vertical direction, the contact portion 201 is separated from the center of gravity 211cg. Preferably, when the metal oxide layer 132 is viewed along the vertical direction, the contact portion 201 and the seam 301 do not overlap.

[0114] Furthermore, the contact portion 201 is closer to the outer circumference of the metal oxide layer 132 than the center of gravity 211cg. More specifically, when viewing the metal oxide layer 132 along the vertical direction, the distance between the contact portion 201 and the outer circumference of the metal oxide layer 132 is shorter than the distance between the contact portion 201 and the center of gravity 211cg.

[0115] Figure 35 is a plan view of the metal oxide layer 50a viewed from below. As shown in Figures 32 and 35, when the metal oxide layer 50a is viewed along the vertical direction, the contact portion 202 (an example of the "second contact portion") between the oxide semiconductor layer 70 and the metal oxide layer 50a coincides with the centroid 212cg of the lower surface 212 of the metal oxide layer 50a.

[0116] Note that the contact portion 202 does not necessarily have to overlap with the center of gravity 212cg. In this case, preferably, the contact portion 202 is closer to the center of gravity 212cg than to the outer circumference of the metal oxide layer 50a. More specifically, when viewing the metal oxide layer 50a along the vertical direction, the distance between the contact portion 202 and the center of gravity 212cg is shorter than the distance between the contact portion 202 and the outer circumference of the metal oxide layer 50a.

[0117] (assignment) Figures 36 to 40 are cross-sectional views parallel to the ZX plane showing the manufacturing process of a comparative example semiconductor device.

[0118] First, as shown in Figure 36, a seam 301 is formed in the metal oxide layer 132. The seam 301 coincides with the centroid 211cg when the metal oxide layer 132 is viewed along the vertical direction.

[0119] Next, as shown in Figure 37, transistor holes TH are formed by reactive ion etching. However, when transistor holes TH are formed so that their bottoms overlap with the centroid 211cg, the presence of the seam 301 can cause the transistor holes TH to penetrate the metal oxide layer 132. In this case, the metal oxide layer 132 is exposed on the sidewalls of the transistor holes TH.

[0120] Next, as shown in Figure 38, a gate insulating film 43 is deposited so as to cover the inner surface of the transistor hole TH. However, the heat applied when the gate insulating film 43 is deposited can cause the temperature of the metal oxide layer 132 to rise, which may cause the metal oxide layer 132 to disappear.

[0121] Next, as shown in Figure 39, the gate insulating film 43 at the bottom of the transistor hole TH is etched by reactive ion etching. However, because the transistor hole TH has a tapered shape, the area at the bottom of the transistor hole TH is small, making it difficult to etch the gate insulating film 43.

[0122] Next, as shown in Figure 40, an oxide semiconductor layer 70 is formed in the transistor hole TH. However, because the transistor hole TH has a tapered shape, the contact area between the oxide semiconductor layer 70 and the conductive film 21 at the lower end 70b becomes small.

[0123] [Manufacturing method for semiconductor memory device 102] The following describes a method for manufacturing a semiconductor memory device 102 as an example of a method for manufacturing a semiconductor memory device according to the second embodiment.

[0124] First, as shown in Figure 41, a seam 301 is formed in the metal oxide layer 132. The seam 301 coincides with the centroid 211cg when the metal oxide layer 132 is viewed along the vertical direction.

[0125] Next, as shown in Figure 42, the transistor hole TH is formed by reactive ion etching such that the bottom of the transistor hole TH and the centroid 211cg are separated. This prevents the transistor hole TH from being continuous with the seam 301 located directly below the centroid 211cg, and thus prevents the transistor hole TH from penetrating the metal oxide layer 132.

[0126] Next, as shown in Figure 43, the gate insulating film 43 is deposited so as to cover the inner surface of the transistor hole TH. In this case, unlike the case shown in Figure 38, the exposure of the metal oxide layer 132 is suppressed to the bottom of the transistor hole TH, so even if the temperature of the metal oxide layer 132 rises due to the heat applied when the gate insulating film 43 is deposited, the disappearance of the metal oxide layer 132 can be suppressed.

[0127] Next, as shown in Figure 44, the gate insulating film 43 at the bottom of the transistor hole TH is etched by reactive ion etching. Unlike the case shown in Figure 39, the bottom of the transistor hole TH can be positioned higher, so a sufficient area at the bottom of the transistor hole TH can be secured, and the etching of the gate insulating film 43 can be performed well.

[0128] Next, as shown in Figure 45, an oxide semiconductor layer 70 is formed in the transistor hole TH. Unlike the case shown in Figure 40, the lower end 70b of the oxide semiconductor layer 70 can be positioned higher, so that a sufficient area of ​​the contact portion 201 can be secured.

[0129] (Variations in the shape of the seam) The shape of the seam 301 is not limited to a spindle shape (see Figure 32), but can take other shapes. For example, as shown in Figure 46, the seam 302 may have a vertically elongated columnar shape, with its upper and lower ends exposed from the metal oxide layer 132. In other words, the seam 302 penetrates the metal oxide layer 132.

[0130] Furthermore, as shown in Figure 47, the seam 303 is not limited to a configuration that penetrates the metal oxide layer 132 like the seam 302, but may also have a vertically elongated columnar shape and be embedded within the metal oxide layer 132. Alternatively, the upper or lower end of the seam 303 may be exposed from the metal oxide layer 132.

[0131] Furthermore, as shown in Figure 48, the seam 304 may have an upper end exposed from the metal oxide layer 132 and a tapered shape that narrows from top to bottom.

[0132] Furthermore, as shown in Figure 49, the seam 305 may have an upper and lower end that is exposed from the metal oxide layer 132 and a tapered shape that widens in diameter from top to bottom.

[0133] The shape of seams 301-305 is largely determined by the shape of the metal oxide layer 132, i.e., the shape of the recess 224a. The shapes of the metal oxide layer 132 in adjacent capacitors 120 are often almost the same. Therefore, seams of almost the same shape are often formed in adjacent metal oxide layers 132.

[0134] In the semiconductor memory device 101, the configuration described is one in which the central axis 70d of the oxide semiconductor layer 70 and the central axis 32d of the metal oxide layer 32 are aligned, but this is not the only configuration. The central axes 70d and 32d may be separated in a direction that intersects the vertical direction. Specifically, the semiconductor device 30B may be provided above the capacitor 20.

[0135] Furthermore, while the capacitor 120 has been described in which the recess 224a is formed by a barrier metal layer 224, it is not limited to this configuration. At least a portion of the recess 224a may be formed by other electrodes or insulating films.

[0136] Furthermore, although the semiconductor memory device 102 has been described in which one of the seams 301 to 305 of the metal oxide layer 132 is included, it is not limited to this configuration. The metal oxide layer 132 may also have a configuration that does not include the seams 301 to 305. Even when the metal oxide layer 132 includes one of the seams 301 to 305, the semiconductor memory device 102 exhibits good electrical characteristics, so it goes without saying that the semiconductor memory device 102 also exhibits good electrical characteristics when the metal oxide layer 132 does not include the seams 301 to 305.

[0137] (a) The semiconductor device is The insulating film or electrode further comprises at least a portion of the recess formed therein. The second electrode is embedded in the recess, When the second electrode is viewed along the vertical direction, the first contact portion and the seam do not overlap. Semiconductor equipment.

[0138] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of Symbols]

[0139] 10… Semiconductor substrates 11... Circuit 20, 20A, 120... Capacitors 21... Conductive film 22…Dielectric layer 22o…outer surface 22i…Inner peripheral surface 22a, 22b… insulating film 23... Conductor 24...Electrode 24o...outer surface 25...Electrode 25i…Inner peripheral surface 30, 30B… Semiconductor equipment 32…Metal oxide layer 32d…Central axis 32a...Opposing surface 33... Conductor 34…Insulating layer 35…Insulating layer 36…Hard mask layer 36a...Opening 37…Resistance layer 37a...Opening 40…Field-effect transistor 42...Conductive layer 43…Gate insulating film 45…Insulating layer 45a, 45b… Insulating film 50...electrode 50a... Metal oxide layer 50b... Barrier metal layer 50c…Metal film 63…Insulating layer 70…Oxide semiconductor layer 70a…Top end 70b…lower end 70d…Central axis 101, 102… Semiconductor memory devices 124...Electrode 132…Metal oxide layer 132L… Lateral orientation part 132V...Vertical orientation section 224... Barrier metal layer 224a…recess 201, 202... Contact area 211, 212…planes 211cg, 212cg...center of gravity 211c…Central part 211o…Outer periphery 301, 302, 303, 304, 305... Seam CH...Capacitor Hole TH... Transistor Hall

Claims

1. An oxide semiconductor stretched along the vertical direction, A first electrode comprising a first oxide conductive material and a first conductor connected to the upper end of the oxide semiconductor, A gate electrode facing the oxide semiconductor via a gate insulating film, A second electrode is provided below the oxide semiconductor and extends in the vertical direction, A dielectric layer provided on the outer surface of the second electrode, The dielectric layer comprises a third electrode provided on the outer circumferential surface of the dielectric layer, The second electrode includes a second oxide conductive material, is connected to the lower end of the oxide semiconductor, and includes a second conductor having a facing surface that faces the inner circumferential surface of the third electrode across the dielectric layer. Semiconductor memory device.

2. The second electrode is provided between the second conductor and the dielectric layer and further comprises a third conductor containing titanium and nitrogen. The semiconductor memory device according to claim 1.

3. The second oxide conductive material comprises at least one of indium, zinc, tin, iridium, ruthenium, titanium, and tungsten, and oxygen. The semiconductor memory device according to claim 1.

4. The second conductor is columnar in shape and has a first central axis extending along the vertical direction. The oxide semiconductor is columnar in shape, having a second central axis extending along the vertical direction. The first central axis and the second central axis are separated in a direction that intersects with the vertical direction. The semiconductor memory device according to claim 1.

5. An oxide semiconductor stretched along the vertical direction, A first electrode comprising a first oxide conductive material and a first conductor connected to the upper end of the oxide semiconductor, A gate electrode facing the oxide semiconductor via a gate insulating film, The device comprises a second electrode connected to the lower end of the oxide semiconductor and containing a second oxide conductive material, The first contact portion between the oxide semiconductor and the second electrode does not come into contact with the seam included in the second electrode. Semiconductor equipment.

6. The aforementioned semiconductor device is The insulating film or electrode further comprises at least a portion of the recess formed therein. The second electrode is embedded in the recess. The semiconductor device according to claim 5.

7. When the second electrode is viewed along the vertical direction, the center of gravity of the upper surface of the second electrode coincides with the seam. The semiconductor device according to claim 5.

8. The aforementioned semiconductor device is The insulating film or electrode further comprises at least a portion of the recess formed therein. The second electrode is embedded in the recess, When the second electrode is viewed along the vertical direction, the first contact portion is located away from the center of gravity of the upper surface of the second electrode. The semiconductor device according to claim 5.

9. The oxide semiconductor comprises at least one of indium, gallium, zinc, tin, aluminum, iridium, ruthenium, and titanium, and oxygen. The semiconductor device according to claim 5.

10. The second oxide conductive material comprises at least one of indium, zinc, tin, iridium, ruthenium, titanium, and tungsten, and oxygen. The semiconductor device according to claim 5.

11. The second contact portion between the oxide semiconductor and the first electrode coincides with the center of gravity of the lower surface of the first electrode. The semiconductor device according to claim 5.

12. The semiconductor device described in claim 5, A first capacitor electrode connected to the second electrode, A second capacitor electrode facing the first capacitor electrode, A dielectric film provided between the first capacitor electrode and the second capacitor electrode, Semiconductor memory device.

13. The semiconductor device described in claim 5, A second electrode is provided below the oxide semiconductor and extends in the vertical direction, A dielectric layer provided on the outer surface of the second electrode, The dielectric layer comprises a third electrode provided on the outer circumferential surface of the dielectric layer, The second electrode includes a second oxide conductive material, is connected to the lower end, and includes a second conductor having a facing surface that faces the inner circumferential surface of the third electrode across the dielectric layer. Semiconductor memory device.

14. An oxide semiconductor stretched along the vertical direction, A first electrode comprising a first oxide conductive material and a first conductor connected to the upper end of the oxide semiconductor, A gate electrode facing the oxide semiconductor via a gate insulating film, The device comprises a second electrode connected to the lower end of the oxide semiconductor and containing a second oxide conductive material, The first contact portion between the oxide semiconductor and the second electrode is located away from the center of gravity of the upper surface of the second electrode. Semiconductor equipment.

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