Semiconductor equipment

Abstract

To provide a semiconductor device with suppressed leakage current. [Solution] The first insulator is located in a first direction from the first substrate. The first conductor is located within the first insulator. The second substrate is located in a first direction from the first insulator. The first well region has a first conductivity type, is provided in the second substrate, and has a first impurity concentration. The first impurity region has a first conductivity type, is in contact with the first well region in a second direction from the first well region within the second substrate, and has a concentration of 1 × 10⁻⁶ times or more the first impurity concentration. 8 It has a second impurity concentration of less than twice the original concentration. The second well region has a second conductivity type and is in contact with the first impurity region in the second direction from the first impurity region within the second substrate.

Description

[Technical Field]

[0001] The embodiments generally relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices include memory devices. An example of a memory device includes one that contains memory cells arranged in three dimensions. Miniaturization of memory device components is progressing to improve the storage capacity of memory devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0005820 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor device with suppressed leakage current. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a first substrate, a first insulator, a first conductor, a second substrate, a first well region, a first impurity region, and a second well region. The first insulator is located in a first direction from the first substrate. The first conductor is located within the first insulator. The second substrate is located in the first direction from the first insulator. The first well region has a first conductivity type, is provided in the second substrate, and has a first impurity concentration. The first impurity region has the first conductivity type, is in contact with the first well region in a second direction from the first well region within the second substrate, and has a concentration of 1 × 10⁻¹⁶ times or more the first impurity concentration. 8 It has a second impurity concentration of less than or equal to twice the original concentration. The second well region has a second conductivity type and is in contact with the first impurity region in the second direction from the first impurity region within the second substrate. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the components of a semiconductor device according to the first embodiment and an example of the connections between the components. [Figure 2] Figure 2 shows the components and connections of one block of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 shows the external appearance of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 shows an example of the structure of a part of the surface of the semiconductor device of the first embodiment. [Figure 5] Figure 5 shows an example of the cross-sectional structure of a part of the semiconductor device of the first embodiment. [Figure 6] Figure 6 shows an example of the cross-sectional structure of a memory pillar of a semiconductor device according to the first embodiment, along the xy plane. [Figure 7] Figure 7 shows a partial structure of the semiconductor device of the first embodiment. [Figure 8] Figure 8 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 9] Figure 9 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 10] Figure 10 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 11] Figure 11 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 12] Figure 12 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 13] Figure 13 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 14] Figure 14 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to the first example. [Figure 15] Figure 15 shows an example of the state of a part of the semiconductor device of the first embodiment during manufacturing according to a second example. [Figure 16] FIG. 16 shows an example of the structure of a cross section of a part of a semiconductor device according to a modified example of the first embodiment. **Embodiments for Carrying Out the Invention**

[0007] Embodiments will be described below with reference to the drawings. In order to distinguish a plurality of components having substantially the same functions and configurations in a certain embodiment or different embodiments from each other, additional numbers or characters may be added to the end of the reference numerals.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. may be different from the actual ones. Also, there may be portions where the relationship of dimensions, arrangement, and / or ratio between the drawings are different from each other.

[0009] In this specification and the claims, when a first element is "connected to" a second element, it includes that the first element is connected to the second element directly or via an element that is always or selectively conductive.

[0010] Hereinafter, a three-dimensional orthogonal coordinate system is used to describe the embodiments. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, and up indicates the Z direction. The direction opposite to the Z direction is referred to as the -Z direction.

[0011] 1. First Embodiment 1.1. Configuration (Structure) The semiconductor device of the first embodiment is, as an example, a memory device. Hereinafter, the memory device 1 will be described as an example of the semiconductor device.

[0012] Figure 1 shows an example of the components and connections of a semiconductor device according to the first embodiment. The storage device 1 is a device that stores data using memory cells. The storage device 1 is controlled by an external memory controller. The storage device 1 operates based on commands CMD and address information ADD received, for example, from the memory controller. The storage device 1 receives data DAT to be written and outputs the data stored in the storage device 1.

[0013] The storage device 1 includes components such as a memory cell array 10, a row decoder 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17.

[0014] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (not shown). The region in which the memory cell array 10 is provided also includes wiring such as word lines WL (not shown) and bit lines BL (not shown).

[0015] The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transfers the voltage supplied from the driver 15 to one block BLK selected based on the block address received by the row decoder 11 from the register 12.

[0016] Register 12 is a circuit that holds the command CMD and address information ADD received by the storage device 1. The command CMD instructs the sequencer 13 to perform various operations, including data read, data write, and data erase. The address information ADD specifies the target of access in the memory cell array 10.

[0017] The sequencer 13 is a circuit that controls the operation of the entire storage device 1. Based on the command CMD received by the sequencer 13, the sequencer 13 controls the row decoder 11, the driver 15, and the sense amplifier 17 to perform various operations, including data reading, data writing, and data erasure.

[0018] The voltage generation circuit 14 is a circuit that generates multiple voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from outside the memory device 1 and generates multiple voltages from the power supply voltage. The voltage generation circuit 14 supplies the generated voltages to components such as the memory cell array 10, the driver 15, and the sense amplifier 17.

[0019] The driver 15 is a circuit that applies various voltages necessary for the operation of the memory device 1 to several components. The driver 15 receives multiple voltages from the voltage generation circuit 14 and supplies a selected voltage from among them to one or more row decoders 11.

[0020] The sense amplifier 17 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT and generates read data based on the sensed state. The sense amplifier 17 applies a voltage based on the write data to the bit line BL.

[0021] Figure 2 shows the components and connections of one block of the semiconductor device according to the first embodiment. Multiple blocks BLK, for example, all blocks BLK, include the components and connections shown in Figure 2.

[0022] A single block BLK contains multiple string units SU. Figure 2 shows an example of five string units SU_0 to SU_4.

[0023] As shown in Figure 2, m bit lines BL_0 to BL_m-1 are each connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK, where m is a positive integer.

[0024] Each NAND string NS contains one select gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4), where n is a positive integer. The memory cell transistor MT functions as a memory cell and is an element that stores data nonvolatilously. The memory cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings, and stores data nonvolatilously based on the charge in the charge storage film. Data is written to the memory cell transistor MT by injecting electrons into the charge storage film.

[0025] The selection gate transistor ST, memory cell transistors MT_0 to MT_n-1, and selection gate transistor DT are connected in this order in series between the source line SL and one bit line BL.

[0026] Multiple NAND strings NS, each connected to a different bit line BL, constitute a single string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of memory cell transistors MT sharing a word line WL within a single string unit SU is referred to as a cell unit CU.

[0027] The selection gate transistors DT_0 to DT_4 belong to string units SU_0 to SU_4, respectively. In Figure 2, the selection gate transistors DT_2, DT_3, and DT_4 are omitted from the illustration. The gates of each selection gate transistor DT0 of the multiple NAND strings NS of string unit SU_0 are connected to the selection gate line SGDL_0. Similarly, the gates of each selection gate transistor DT_1, DT_2, DT_3, and DT_4 of the multiple NAND strings NS of string units SU_1, SU_2, SU_3, and SU_4 are connected to the selection gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4.

[0028] The gate of the selection gate transistor ST is connected to the selection gate line SGSL.

[0029] Figure 3 shows the external appearance of a semiconductor device according to the first embodiment. As shown in Figure 3, the memory device 1 includes a first structure 100, a second structure 200, and a third structure 300. The first structure 100, the second structure 200, and the third structure 300 are spread along the xy plane and aligned in the Z direction. The second structure 200 is located on the Z-side surface (top surface) of the first structure 100. The third structure 300 is located on the top surface of the second structure 200.

[0030] The first structure 100, the second structure 200, and the third structure 300 each include a plurality of semiconductors, a plurality of various conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100, the second structure 200, and the third structure 300 each include a plurality of elements and wiring realized by semiconductors, conductors, and insulators. The first structure 100, the second structure 200, and the third structure 300 each include an electrical circuit including elements and wiring. The elements and wiring in the first structure 100, the elements and wiring in the second structure 200, and the elements and wiring in the third structure 300 are electrically connected to each other.

[0031] The set of the first structure 100 and the second structure 200 includes a row decoder 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17. The first structure 100 may include any of the row decoder 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. The second structure 200 may include any of the row decoder 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17.

[0032] The third structure 300 includes a memory cell array 10 and a plurality of external connection terminals PD. The external connection terminals PD are exposed on the upper surface of the third structure 300.

[0033] Figure 4 shows an example of the structure of some faces of the semiconductor device of the first embodiment. Figure 4 shows an exploded view of the structure in Figure 3.

[0034] As shown in Figure 4, the first structure 100 includes a plurality of conductive junction terminals BP1. The junction terminals BP1 are exposed on the upper surface of the first structure 100. The junction terminals BP1 are connected to elements in the first structure 100.

[0035] The second structure 200 includes a plurality of conductive junction terminals BP2L and a plurality of conductive junction terminals BP2U. The junction terminals BP2L are exposed on the -Z-direction side (bottom surface) of the second structure 200. The junction terminals BP2L are connected to elements in the second structure 200. The junction terminals BP2L have the same layout as the junction terminals BP1 of the first structure 100. The junction terminals BP2L are arranged such that when the first structure 100 and the second structure 200 are joined, each junction terminal BP2L is in contact with one of the junction terminals BP1 of the first structure 100 that corresponds to that junction terminal BP2L. A particular junction terminal BP2L and one of the junction terminals BP1 of the first structure 100 that corresponds to that particular junction terminal BP2L are elements that function as the same node in the circuit.

[0036] The junction terminal BP2U is exposed on the upper surface of the second structure 200. The junction terminal BP2U is connected to an element in the second structure 200.

[0037] The third structure 300 includes a plurality of conductive junction terminals BP3. The junction terminals BP3 are exposed on the underside of the third structure 300. The junction terminals BP3 are connected to elements in the third structure 300. The junction terminals BP3 have the same layout as the junction terminals BP2U of the second structure 200. The junction terminals BP3 are arranged such that when the second structure 200 and the third structure 300 are joined, each junction terminal BP3 is in contact with one of the junction terminals BP2U of the second structure 200 that corresponds to that junction terminal BP3. A particular junction terminal BP3 and one of the junction terminals BP2U of the second structure 200 that corresponds to that particular junction terminal BP3 are elements that function as the same node in the circuit.

[0038] Figure 5 shows an example of the structure of a cross-section of a part of the semiconductor device of the first embodiment. As shown in Figure 5, the first structure 100 further includes a substrate W1, a transistor Tr1, contacts CS1, C0, C1, C2, and C3, conductors L0, L1, and L2, and insulators 21 and 22. In the following description, conductors also include semiconductors that are conductive due to the presence of impurities. In one example, the substrate W1 contains silicon. In one example, the contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 contain copper or tungsten. In one example, the insulators 21 and 22 contain silicon oxide.

[0039] Transistor Tr1 is located in the region above and near the top surface of substrate W1. Transistor Tr1 includes a gate insulator on the top surface of substrate W1, a gate electrode on the top surface of the gate insulator, and a pair of source / drain regions flanking the region below the gate electrode.

[0040] Each contact C0 is in contact with the upper surface of the gate electrode of one transistor Tr1 on its lower surface. Each contact CS1 is in contact with one source / drain region on its lower surface.

[0041] Each conductor L0 is in contact with one contact C0 or CS1 on its lower surface. Each contact C1 is in contact with the upper surface of one conductor L0 on its lower surface.

[0042] Each conductor L1 is in contact with the upper surface of one contact C1 on its lower surface. Each contact C2 is in contact with the upper surface of one conductor L1 on its lower surface.

[0043] Each conductor L2 is in contact with the upper surface of one contact C2 on its lower surface. Each contact C3 is in contact with the upper surface of one conductor L2 on its lower surface.

[0044] The set of transistors Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 realizes the circuit included in the first structure 100. Thus, the first structure 100 has transistors Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 in any shape and arrangement that realize the circuit included in the first structure 100.

[0045] The insulator 21 extends from the height of the top surface of the substrate W1 to the height of the top surface of the contact C3. The insulator 21 fills in the areas of the first structure 100 where no components are provided, namely the areas where the transistor Tr1, contacts CS1, C0, C1, C2, and C3, and conductors L0, L1, and L2 are not provided.

[0046] Each junction terminal BP1 is in contact with the upper surface of one contact C3 on its lower surface. The insulator 22 fills the region of the layer where the junction terminals BP1 are located, in the area where the junction terminals BP1 are not provided.

[0047] The second structure 200 further comprises a substrate W2, a transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, conductors L3, L4, L5, and L6, and insulators 24, 25, 26, and 27. In one example, the substrate W2 contains silicon. In one example, the contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and the conductors L3, L4, L5, and L6 contain copper or tungsten. In one example, the insulators 24, 25, 26, and 27 contain silicon oxide.

[0048] Each junction terminal BP2L is located in the bottom layer of the second structure 200. The insulator 24 fills the region of the layer where the junction terminals BP2L are located, but where the junction terminals BP2L are not provided.

[0049] Each contact C4 is in contact with the upper surface of one bonding terminal BP2L on its lower surface.

[0050] Each conductor L3 is in contact with the upper surface of one contact C4 at its lower surface. In one example, the conductor L3 includes copper (Cu), aluminum (Al), and / or tungsten (W). Each contact C5 is in contact with the upper surface of one conductor L3 at its lower surface. The conductors L3 are electrically connected to the voltage generation circuit 14 and receive a high positive voltage.

[0051] The insulator 25 extends from the height of the upper surface of the junction terminal BP2L and the upper surface of the insulator 24 to the height of the upper surface of the contact C5. The insulator 25 fills the area above the junction terminal BP2L and the insulator 24 where contacts C4 and C5 and the conductor L3 are not provided.

[0052] The substrate W2 is located on the upper surface of the insulator 25. Vias TS penetrate the substrate W2 across its upper and lower surfaces. Each via TS contacts the upper surface of one contact C5 on its lower surface. Insulator SP penetrates the substrate W2 across its upper and lower surfaces. Each insulator SP covers the side of one via TS.

[0053] Transistor Tr2 is located in the region above and near the top surface of substrate W2. Transistor Tr2 includes a gate insulator on the top surface of substrate W2, a gate electrode on the top surface of the gate insulator, and a pair of source / drain regions flanking the region below the gate electrode.

[0054] Each contact C7 is in contact with the upper surface of the gate electrode of one transistor Tr2 on its lower surface. Each contact CS2 is in contact with one source / drain region on its lower surface. Each contact CS5 is in contact with the upper surface of one via TS on its lower surface.

[0055] Each conductor L4 is in contact with the upper surface of one contact C7, CS2, or CS5 on its lower surface. Each contact C8 is in contact with the upper surface of one conductor L4 on its lower surface.

[0056] Each conductor L5 is in contact with the upper surface of one contact C8 on its lower surface. Each contact C9 is in contact with the upper surface of one conductor L5 on its lower surface.

[0057] Each conductor L6 is in contact with the upper surface of one contact C9 on its lower surface. Each contact C10 is in contact with the upper surface of one conductor L6 on its lower surface.

[0058] The set of transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and conductors L3, L4, L5, and L6 realizes the circuit included in the second structure 200. Thus, the second structure 200 has transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9, and C10, and conductors L3, L4, L5, and L6 in any shape and arrangement that realizes the circuit included in the second structure 200.

[0059] The insulator 26 extends from the height of the top surface of the substrate W2 to the height of the top surface of the contact C10. The insulator 26 fills the region from the height of the top surface of the substrate W2 to the height of the top surface of the contact C10 where no components are provided, i.e., the region where transistors Tr2, Tr2, contacts CS2, CS5, C7, C8, C9, and C10, and conductors L4, L5, and L6 are not provided.

[0060] Each junction terminal BP2U contacts the upper surface of one contact C10 on its lower surface. The insulator 27 fills the region of the layer where the junction terminals BP2U are located, in the region where the junction terminals BP2U are not provided.

[0061] The third structure 300 further includes contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, 38, insulators 29, 34, 35, 37, 40, 41, and memory pillar MP.

[0062] Each junction terminal BP3 is located in the bottom layer of the third structure 300. The insulator 29 fills in the areas of the layer where the junction terminals BP3 are located but where the junction terminals BP3 are not provided.

[0063] Each contact C11 is in contact with the upper surface of one of the junction terminals BP3 on its lower surface.

[0064] Each conductor L7 is in contact with the upper surface of one contact C11 on its lower surface. Each contact C12 is in contact with the upper surface of one conductor L7 on its lower surface.

[0065] Each conductor L8 is in contact with the upper surface of one contact C12 on its lower surface.

[0066] The conductor 31 is located above the conductor L8. The conductor 31 has a plate-like shape along the xy plane. The conductor 31 functions as at least part of the selected gate line SGDL. The lower surface of the conductor 31 is exposed at the ends and has terraces.

[0067] The insulator 32 is located on the upper surface of the conductor 31. The insulator 32 has a plate-like shape along the xy plane.

[0068] The conductors 33 and insulators 34 are stacked alternately one by one on the upper surface of the insulator 32. The conductors 33 and insulators 34 have a plate-like shape along the xy plane. Each conductor 33 functions as at least part of the word line WL. Figure 5 shows an example where n, i.e., the number of memory cell transistors MT, is 8. The conductors 33, from bottom to top, function as at least part of the word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. The lower surface of each conductor 33 is exposed at the edge and has a terrace.

[0069] The insulator 35 is located on the upper surface of the top conductor 33.

[0070] The conductor 36 is located on the upper surface of the insulator 35. The conductor 36 functions as at least part of the selected gate line SGSL.

[0071] The insulator 37 is located on the upper surface of the conductor 36. The conductor 38 is located on the upper surface of the insulator 37. The lower surface of the conductor 38 is exposed at its edges and has terraces.

[0072] The memory pillar MP extends along the z-axis and penetrates the conductors 31, 33, and 36, and the set of insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, a semiconductor SM, and a laminate SS. The semiconductor SM covers the sides of the insulator CI. The laminate SS covers the sides of the semiconductor SM. The laminate SS has an opening at the top end of the memory pillar MP. A portion of the semiconductor SM is located in the opening and, on its upper surface, is in contact with the conductor 38.

[0073] The upper part of the memory pillar MP is located within the conductor 38, and the laminate SS has an opening where it faces the conductor 38, and a part of the semiconductor SM may be located within the opening.

[0074] The portion of each memory pillar MP facing the conductor 31 functions as one selection gate transistor DT. The portion of the memory pillar MP facing the conductor 33 functions as one memory cell transistor MT. The portion of the memory pillar MP facing the conductor 36 functions as one selection gate transistor ST. The lower surface of the semiconductor SM is exposed on the lower surface of each memory pillar MP. The lower surface of the semiconductor SM is exposed on the upper surface of each memory pillar MP.

[0075] Each contact C13 is in contact with the upper surface of one conductor L8 on its lower surface. Each of several contacts C13 is in contact with the lower surface of the semiconductor SM of one memory pillar MP on its upper surface. Each of several contacts C13 is in contact with the lower surface of one terrace portion of conductors 31, 33, and 36 on its upper surface.

[0076] The insulator 40 extends from the height of the upper surface of the insulator 29 to the height of the upper surface of the conductor 38. The insulator 40 fills the areas of the third structure 300 where no components are provided, namely, the areas where contacts C11, C12, and C13, conductors L7, L8, 31, 33, 36, 38, insulators 40, 32, 34, 35, 37, and memory pillar MP are not provided.

[0077] The insulator 41 is located on the upper surfaces of the conductor 38 and the insulator 40, respectively.

[0078] Figure 6 shows an example of the cross-sectional structure of a memory pillar of a semiconductor device according to the first embodiment, along the xy plane. As shown in Figure 6, in one example, the laminate SS includes a tunnel insulator TI, a charge storage film CA, and a block insulator BI.

[0079] The tunnel insulator TI surrounds the side surface of the semiconductor SM. The charge storage film CA surrounds the side surface of the tunnel insulator TI. The block insulator BI surrounds the side surface of the charge storage film CA. The conductors 31, 33, or 36 surround the side surface of the block insulator BI.

[0080] The semiconductor SM functions as a channel (current path) for the memory cell transistor MT and the selection gate transistors DT and ST. In one example, the tunnel insulator TI and the block insulator BI each contain silicon oxide. The charge storage film CA stores charge. In one example, the charge storage film CA contains silicon nitride.

[0081] Figure 7 shows a partial structure of the semiconductor device of the first embodiment. Figure 7 shows details of the substrate W2 and its surrounding structure.

[0082] As shown in Figure 7, the second structure 200 further includes structure STI, an n-well region nw, a p-well region pw, and an impurity region DA. Although Figure 7 shows only one p-well region pw, two or more p-well regions pw are provided.

[0083] Substrate W2 contains p-type impurities. An example of a p-type impurity is boron (B).

[0084] The structural STI isolates the elements, contains an insulator, and has a structure based on STI (Shallow Trench Isolation). The structural STI is located in a region including the upper surface of the substrate W2. The structural STI extends downward from the upper surface of the substrate W2. In one example, the structural STI contains silicon oxide.

[0085] The n-well region nw is located between two adjacent structures STI. The n-well region nw extends from the top to the bottom surface of the substrate W2. The n-well region nw contains n-type impurities. Examples of n-type impurities include phosphorus (P) and arsenic (As).

[0086] The p-well region pw is located between two adjacent structures STI. The p-well region pw extends from the top to the bottom surface of the substrate W2. The p-well region pw contains p-type impurities. In one example, the p-well region pw contains 1 × 10⁻¹⁶ particles in the region including the boundary with the insulator 25. 14 [atoms / cm 3 ] More than 2 x 10 16[atoms / cm 3 It contains p-type impurities at concentrations below the specified range. In one example, the impurity concentration is the average concentration.

[0087] Transistor Tr2 includes p-type transistor Tr2_p and n-type transistor Tr2_n.

[0088] Transistor Tr2_p is located between two adjacent structures STI. Transistor Tr2_p is located in and above the n-well region nw. Transistor Tr2_p includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_p. The gate insulator GO is located on the upper surface of the substrate W2. In one example, the gate insulator GO contains silicon oxide. The gate electrode GC is located on the upper surface of the gate insulator GO. In one example, the gate electrode GC contains polysilicon which is conductive due to the introduction of impurities. The source / drain region SD_p encloses the portion below the gate electrode GC in a region that includes the upper surface of the substrate W2. The source / drain region SD_p contains p-type impurities.

[0089] Transistor Tr2_n is located between two adjacent structures STI. Transistor Tr2_n is located in and above the p-well region pw. Transistor Tr2_n includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_n. The source / drain region SD_n encloses the portion below the gate electrode GC in the region including the upper surface of the substrate W2. The source / drain region SD_n contains n-type impurities.

[0090] Each impurity region DA is located below one of the STIs in the substrate W2. The impurity region DA contacts the lower surface of the STI and reaches the lower surface of the substrate W2. The impurity region DA contacts two adjacent ones of the n-well region nw and the p-well region pw and electrically separates these two adjacent ones. The impurity region DA contains p-type impurities. An example of the p-type impurities includes boron. The impurity region DA is formed separately from the p-well region pw by ion implantation or the like. Thus, the impurity region DA has an impurity concentration higher than that of the p-well region pw, and has a p-type impurity concentration higher than the p-type impurity concentration that the region of the position of the impurity region DA would have if the p-type impurities in the p-well region pw diffused without forming the impurity region DA. In one example, the impurity region DA contains p-type impurities at a concentration of 1×10 16 [atoms / cm 3 or more and 3×10 18 [atoms / cm 3 or less. In one example, the impurity region DA contains p-type impurities at a concentration of 8×10 16 [atoms / cm 3 or more and 1×10 22 [atoms / cm 3 or less in a region including the boundary with the insulator 25. In one example, the p-type impurity concentration of the impurity region DA is 4 times or more and 1×10 8 times or less the p-type impurity concentration of the p-well region pw.

[0091] The contacts CS2, CS5, and C7, and the structure STI have a tapered shape. A component having a tapered shape has an area larger than the area of the lower end at the upper end and, in one example, has an area (area along the xy plane) that decreases from the upper end toward the lower end. That is, the contacts CS2, CS5, and C7, and the structure STI have an area larger than the area of the -Z-direction side end at the Z-direction side end.

[0092] The via TS, insulator SP, and contact C5 have a reverse taper shape. Components with a reverse taper shape have an area at the upper end that is smaller than the area at the lower end, and in one example, an area that increases from the upper end to the lower end. That is, the via TS, insulator SP, and contact C5 have an area at the end on the Z-direction side that is smaller than the area at the end on the -Z-direction side.

[0093] The p-well region pw, along with further p-well regions pw not shown in the diagram, encloses one n-well region nw.

[0094] 1.2. Manufacturing method The manufacturing process for the memory device 1 includes the steps of manufacturing the first structure 100, the second structure 200, and the third structure 300 in separate processes, and the step of bonding the manufactured first structure 100, the second structure 200, and the third structure 300 together. The manufacturing method for the second structure 200 is described below.

[0095] 1.2.1. First example of a manufacturing method for the second structure Figures 8 to 14 show examples of the state during manufacturing according to the first example of the second structure of the semiconductor device of the first embodiment.

[0096] As shown in Figure 8, n-well regions nwA and p-well regions pwA are formed in substrate W2A. Substrate W2A is the element that will become substrate W2 in a later process. The n-well region nwA encompasses the n-well region nw and is also located in the region where the impurity region DA is to be formed. The p-well region pwA encompasses the p-well region pw and is also located in the region where the impurity region DA is to be formed.

[0097] Either the n-well region (nwA) or the p-well region (pwA) may be formed first. An example of a method for forming the n-well region (nwA) and the p-well region (pwA) involves ion implantation using a mask.

[0098] As shown in Figure 9, source / drain regions SDA_n and SDA_p are formed in the substrate W2A. Source / drain region SDA_n encompasses source / drain region SD_n and is also located in the region where impurity region DA is to be formed. Source / drain region SDA_p encompasses source / drain region SD_p and is also located in the region where impurity region DA is to be formed.

[0099] Either the source / drain region SDA_n or SDA_p may be formed first. An example of a method for forming the source / drain regions SDA_n and SDA_p includes ion implantation using a mask.

[0100] As shown in Figure 10, a trench 51 is formed. The trench 51 occupies the region where the structural STI is to be formed. An example of the formation method includes a combination of a photolithography process and anisotropic etching, and an example of anisotropic etching includes RIE (Reactive Ion Etching). That is, a mask 52 is formed on the upper surface of the substrate W2A. The mask 52 has an opening above the region where the structural STI is to be formed, exposing the upper surface of the substrate W2A at the opening. Then, anisotropic etching of the mask 52 forms a trench 51 below the opening in the mask 52. With the formation of the trench 51, the n-well region nwA becomes the n-well region nw, and the p-well region pwA becomes the p-well region pw. Also, with the formation of the trench 51, the source / drain region SDA_n becomes the source / drain region SD_n, and the source / drain region SDA_p becomes the source / drain region SD_p.

[0101] As shown in Figure 11, an impurity region DA is formed. That is, ion implantation into the mask 52 forms an impurity region DA below the trench 51 in the substrate W2A. The implanted ions include the elements of the impurities contained in the impurity region DA.

[0102] As shown in Figure 12, the structural STI, gate insulator GO, gate electrode GC, sidewall insulator SW, insulator 26, and contacts CS2, CS5, and C7 are formed. That is, first, the material for the structural STI is deposited in the trench 51. An example of a deposition method is CVD (Chemical Vapor Deposition).

[0103] A gate insulator GO, a gate electrode GC, and a sidewall insulator SW are formed. An example of a method for forming the gate insulator GO includes thermal oxidation. An example of a method for forming the gate electrode GC includes CVD, as well as a combination of photolithography and anisotropic etching. An example of a method for forming the sidewall insulator SW includes CVD, as well as a combination of photolithography and anisotropic etching.

[0104] An insulator 26 is formed on the upper surface of the structure obtained through the steps up to this point. An example of a formation method includes CVD.

[0105] Contacts CS2, CS5, and CS7 are formed. Examples of formation methods include a combination of photolithography and anisotropic etching, as well as CVD.

[0106] Next, contacts C8, C9, and C10, conductors L4, L5, and L6, insulator 27, and junction terminal BP2U (not shown) are formed as shown in Figure 5.

[0107] As shown in Figure 13, the structure obtained through the steps up to this point is inverted with respect to the xy-plane. In the descriptions of Figures 13 and 14, "top surface" refers to the surface on the -Z side.

[0108] The top surface of substrate W2A is removed by CMP (Chemical Mechanical Polishing). This thins substrate W2A, leaving substrate W2. CMP is continued until the impurity region DA is exposed.

[0109] A portion of the insulator 25 is formed on the upper surface of the substrate W2. An example of the formation method includes CVD.

[0110] Vias TS and insulators SP are formed. Examples of formation methods include a combination of photolithography and anisotropic etching, as well as CVD.

[0111] As shown in Figure 14, the remaining portion of the insulator 25, contact C5, and conductor L3 are formed. Examples of formation methods include a combination of photolithography and anisotropic etching, as well as CVD.

[0112] Next, the contact C4, insulator 24, and junction terminal BP1 shown in Figure 5 are formed.

[0113] 1.2.2. Second example of a manufacturing method for the second structure Figure 15 shows an example of the state during manufacturing according to a second example of the second structure of the semiconductor device of the first embodiment. The steps described with reference to Figure 15 follow the steps described above with reference to Figure 9.

[0114] As shown in Figure 15, a mask 54 is formed on the upper surface of the structure obtained by the process described above with reference to Figure 9. The mask 54 has an opening above the region where the impurity region DA is to be formed.

[0115] Ion implantation into the mask 54 forms an impurity region DAA below the opening of the mask 54 in the substrate W2A. The impurity region DAA extends from the upper surface of the substrate W2A to the lower end of the region where the impurity region DA is to be formed.

[0116] As shown in Figure 11, a trench 51 is formed. That is, mask 54 is removed and mask 52 is formed, and a trench 51 is formed below the opening of mask 52, as in the steps described above with reference to Figure 10. Mask 52 may be the same as mask 54. The subsequent steps are the same as in the first example.

[0117] 1.3. Advantages (Effects) According to the first embodiment, a memory device with suppressed leakage current is provided, as described below.

[0118] For comparative purposes, a structure without the impurity region DA of the first embodiment can be considered. This structure includes a p-well region pwA and an n-well region nwA, as shown in Figure 10, instead of the p-well region pw and n-well region nw of the first embodiment, respectively. Two adjacent n-well regions nwA, p-well region pwA, and n-well region nwA are adjacent to each other. In the reference structure, when a positive high voltage is applied to the conductor L3, an inversion layer is formed in the p-well region pwA. That is, due to the electric field caused by the positive high voltage, electrons gather in the portion of the p-well region pwA facing the conductor L3, and an n-type region is formed by the electrons. The n-type region electrically conducts the n-well regions nw on both sides. As a result, a leakage current flows between the n-well regions nwA through the n-type region.

[0119] Electrons tend to accumulate more easily when the distance between the conductor L3 and the p-well region pwA is small. The distance between the conductor L3 and the p-well region pwA depends on the thickness of the substrate W2 (especially the distance between the lower edge of the p-well region pwA and the lower edge of the substrate W2) and the thickness of the insulator 25. To arrange vias TS at high density, a small aspect ratio of the vias TS is desirable, and for this purpose, it is desirable that the substrate W2 and the insulator 25 be thin. As a result of thinning the substrate W2, the lower edge of the p-well region pw coincides with the lower edge of the substrate W2, and consequently, the distance between the conductor L3 and the p-well region pw is small.

[0120] The memory device 1 of the first embodiment includes an adjacent n-well region nw and a p-well region pw, and a p-type impurity region DA between the n-well region nw and the p-well region pw. The impurity region DA has a higher impurity concentration than the p-well region pw. Therefore, even if a positive high voltage is applied to the conductor L3, n-type regions are less likely to form in the region of the impurity region DA facing the conductor L3 than to the extent that n-type regions are formed in the region of the p-well region pw facing the conductor L3. Therefore, even if n-type regions are formed in the p-well region pw by the application of a positive high voltage to the conductor L3, the impurity region DA suppresses the electrical connection between the two n-well regions nw by the n-type regions in the p-well region pw. Therefore, leakage current between the n-well regions nw is suppressed.

[0121] 1.4. Variations The description so far concerns an example in which the impurity region DA contains p-type impurities at a higher concentration than the p-type impurities in the p-well region pw. The impurity region DA may also contain n-type impurities at a higher concentration than the n-type impurities in the n-well region nw. By a similar mechanism to how leakage current is generated when an n-type region is formed in the p-well region pw, leakage current can be generated when a p-type region is formed in the n-well region nw. That is, when a negative high voltage is applied to the conductor L3, a p-type region is formed in the n-well region nw, and the p-type region electrically conducts the p-well regions pw on both sides.

[0122] Even in this case, leakage current is suppressed by the first embodiment. That is, because the impurity region DA contains n-type impurities at a higher concentration than the n-type impurities in the n-well region nw, even if a negative high voltage is applied to the conductor L3, it is difficult for a p-type region to form in the region of the impurity region DA that faces the conductor L3. Therefore, even if a p-type region is formed in the n-well region nw due to the application of a negative high voltage to the conductor L3, the impurity region DA suppresses the electrical connection between the two p-well regions pw by the p-type region in the n-well region nw.

[0123] A conductor L3 facing the p-well region pw and capable of generating an n-type region in the p-well region pw by the application of a positive high voltage may be located in the first structure 100. Figure 16 shows such an example, illustrating the structure of a cross-section of a part of the memory device of a modification of the first embodiment. Figure 16 shows the same region as shown in Figure 5.

[0124] As shown in Figure 16, the second structure 200 does not include the conductor L3 and contact C4. On the other hand, the third structure 300 further includes the conductor L10 and contact C15.

[0125] Contact C5 is in contact with the upper surface of junction terminal BP2L on its lower surface. Each contact C3 is in contact with the lower surface of one conductor L10 on its upper surface. Each contact C15 is in contact with the upper surface of one conductor L10 on its lower surface. Each contact C15 is in contact with the lower surface of one junction terminal BP1 on its upper surface. Conductor L10, like conductor L3, can receive a high positive voltage or a high negative voltage.

[0126] Depending on the modified structure, if the thickness of the insulator 25 and the thickness of the portion of the insulator 21 above the upper surface of the conductor L10 are thin, an n-type region may be formed in the p-well region pw, and a p-type region may be formed in the n-well region nw. By providing the impurity region DA, leakage current due to the formed n-type or p-type region is suppressed.

[0127] The description so far is based on an example where the semiconductor device of the first embodiment is a memory device. The first embodiment can be applied to structures such as the first structure 100 and the second structure 200, which are bonded together and include a transistor Tr2 and a conductor L3 (or L10). Other examples of such semiconductor devices include image sensors and integrated circuits (ICs). In this case, the third structure 300 is not provided.

[0128] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0129] 100...first structure, 200...Second structure, 300...Third structure, BP1, BP2L, BP2U...connecting terminals, W1, W2, W3... circuit boards, Tr1, Tr2...transistors, CS1, CS2, CS5, C0, C1, C2, C3, C4, C5, C7, C8, C9, C10, C11, C12, C13… Contact lenses, L0, L1, L2, L3, L4, L5, L6, L7, L8, 31, 33, 36, 38...Conductor, 21, 22, 24, 25, 26, 27, 29, 32, 34, 35, 37, 40, 41... insulator, nw...n-well region, pw...p-well region, DA...Impurity Region

Claims

1. First substrate and A first insulator located in a first direction from the first substrate, The first conductor in the first insulator, A second substrate located in the first direction relative to the first insulator, A first well region having a first conductivity type, provided in the second substrate, and having a first impurity concentration, Having the first conductivity type, in contact with the first well region in the second substrate from the first well region in a second direction, and having a first impurity concentration of 4 times or more (1 × 10⁻¹⁶). ８ A first impurity region having a second impurity concentration of less than twice the original concentration, A second well region having a second conductivity type, which is in contact with the first impurity region in the second direction from the first impurity region within the second substrate, A semiconductor device equipped with the following features.

2. The first well region, the second well region, and the first impurity region are in contact with the first insulator. The semiconductor device according to claim 1.

3. The first conductor and the first well region are aligned in the first direction. The semiconductor device according to claim 1.

4. The first transistor further comprises a source / drain region in the first well region and a gate electrode located in the first direction from the first well region. The semiconductor device according to claim 1.

5. The second substrate further comprises a second conductor that penetrates in the first direction. The semiconductor device according to claim 1.

6. The second conductor is located in the second direction from the second well region and is electrically connected to the first conductor. The semiconductor device according to claim 5.

7. The first well region has the first impurity concentration at the end on the first direction side, The first impurity region has the second impurity concentration at the end on the first direction side. The semiconductor device according to claim 1.

8. The first conductivity type is p-type, The first well region and the first impurity region contain boron (B), The second conductivity type is n-type, The second well region contains phosphorus (P) or arsenic (As), The semiconductor device according to claim 1.

9. The first conductivity type is n-type, The first well region and the first impurity region contain phosphorus (P) or arsenic (As), The second conductivity type is p-type, The second well region contains boron (B), The semiconductor device according to claim 1.

10. A second impurity region having the first conductivity type, in contact with the first well region in the second substrate in a third direction opposite to the second direction from the first well region, and having the second impurity concentration, A third well region having a second conductivity type and in the second substrate, in contact with the second impurity region in the third direction from the second impurity region and The semiconductor device according to claim 1, further comprising:

11. The first well region, the second well region, the third well region, and the first impurity region are in contact with the first insulator. The semiconductor device according to claim 10.

12. The first conductor and the first well region are aligned in the first direction. The semiconductor device according to claim 10.

13. The first transistor further comprises a source / drain region in the first well region and a gate electrode located in the first direction from the first well region. The semiconductor device according to claim 10.

14. The second substrate further comprises a second conductor that penetrates in the first direction. The semiconductor device according to claim 10.

15. The second conductor is located in the second direction from the second well region and is electrically connected to the first conductor. The semiconductor device according to claim 14.

16. The first well region has the first impurity concentration at the end on the first direction side, Each of the first impurity region and the second impurity region has the second impurity concentration at the end on the first direction side. The semiconductor device according to claim 10.

17. The first conductivity type is p-type, The first well region and the first impurity region contain boron (B), The second conductivity type is n-type, The second well region and the third well region contain phosphorus (P) or arsenic (As). The semiconductor device according to claim 10.

18. The first conductivity type is n-type, The first well region and the first impurity region contain phosphorus (P) or arsenic (As), The second conductivity type is p-type, The second well region and the third well region contain boron (B), The semiconductor device according to claim 10.

19. The first insulator includes a second insulator and a third insulator. The semiconductor device further comprises a third conductor in the second insulator and a fourth conductor in the third insulator. The third conductor is in contact with the fourth conductor, The first conductor is located in the third insulator. The semiconductor device according to claim 1.

20. The first insulator includes a second insulator and a third insulator. The semiconductor device further comprises a third conductor in the second insulator and a fourth conductor in the third insulator. The third conductor is in contact with the fourth conductor, The first conductor is located in the second insulator. The semiconductor device according to claim 1.

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