Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

One embodiment provides a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve electrical characteristics. [Solution] A semiconductor memory device according to one embodiment includes a first stack, a second stack, a source line, a first columnar portion, a second columnar portion, a first bit line, and a second bit line. The source line is positioned between the first stack and the second stack in the first direction. The first columnar portion extends within the first stack in the first direction. The second columnar portion extends within the second stack in the first direction. The first bit line is positioned on the opposite side of the first stack from the source line. The second bit line is positioned on the opposite side of the second stack from the source line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device.

Background Art

[0002] A NAND type flash memory in which memory cells are three-dimensionally arranged is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a semiconductor memory device and a method of manufacturing the semiconductor memory device capable of improving electrical characteristics.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment includes a first stack, a second stack, a source line, a first columnar portion, a second columnar portion, a first bit line, and a second bit line. The first stack includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately one layer at a time in a first direction. The second stack is located on the first side of the first stack in the first direction. The second stack includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately one layer at a time in the first direction. The source line is located between the first stack and the second stack in the first direction. The source line extends in a second direction intersecting the first direction. The first columnar portion extends within the first stack in the first direction. The first columnar portion includes a first memory film including a charge storage portion and a first semiconductor film. The second columnar portion extends in the first direction within the second laminate. The second columnar portion includes a second memory film containing a charge storage portion and a second semiconductor film. The first bit line is positioned on the opposite side of the first laminate from the source line. The first bit line is electrically connected to the first columnar portion. The second bit line is positioned on the opposite side of the second laminate from the source line. The second bit line is electrically connected to the second columnar portion. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing a part of the semiconductor memory device of the first embodiment. [Figure 2] A diagram showing an equivalent circuit of a portion of the memory cell array of the first embodiment. [Figure 3] A diagram illustrating a semiconductor memory device according to the first embodiment. [Figure 4] A diagram illustrating the regional divisions of the memory cell array in the first embodiment. [Figure 5] A cross-sectional view of the semiconductor memory device shown in Figure 4, along the F5-F5 line. [Figure 6] A cross-sectional view of the semiconductor memory device shown in Figure 4, along the F6-F6 line. [Figure 7] This figure shows a magnified view of the region enclosed by line F7 in the structure shown in Figure 4. [Figure 8] This figure shows a magnified view of the region enclosed by line F8 in the structure shown in Figure 7. [Figure 9] A cross-sectional view illustrating the memory pillar of the first embodiment. [Figure 10] A cross-sectional view of the structure shown in Figure 9, along the line F10-F10. [Figure 11] A schematic cross-sectional view showing the structure of the semiconductor memory device of the first embodiment. [Figure 12] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 13] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 14] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 15] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 16] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 17] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 18] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 19] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 20] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 21] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 22] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 23] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 24]Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 25] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 26] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 27] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 28] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 29] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 30] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 31] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 32] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 33] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 34] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 35] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 36] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 37] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 38] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 39] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 40] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 41] Cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 42] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 43] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 44] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 45] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 46] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 47] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 48] A cross-sectional view showing a part of the semiconductor memory device of the second embodiment. [Figure 49] A cross-sectional view illustrating the memory pillar of the second embodiment. [Figure 50] A cross-sectional view of the structure shown in Figure 48, along the F50-F50 line. [Figure 51] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 52] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 53] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 54] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 55] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 56] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to the second embodiment. [Modes for carrying out the invention]

[0007] The semiconductor memory device and the method for manufacturing the semiconductor memory device according to the embodiments will be described below with reference to the drawings. In the following description, components having the same or similar functions will be denoted by the same reference numeral. Duplication of descriptions of these components may be omitted. In the following description, reference numerals or letters at the end of reference numerals may be omitted if they do not need to be distinguished from each other. In the drawings described below, illustrations of components not relevant to the description may be omitted.

[0008] In this application, terms are defined as follows: “Parallel,” “Orthogonal,” or “Same” may include “Approximately parallel,” “Approximately orthogonal,” or “Approximately the same,” respectively. “Connection” may include electrical connections, not just mechanical ones. That is, “Connection” may include cases where multiple elements are connected with another element in between, not just cases where multiple elements are directly connected. “Adjacent” may include cases where multiple elements are adjacent with another element in between, not just cases where multiple elements are touching each other.

[0009] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the word line WL described later extends (see FIG. 5). The -X direction is the opposite direction of the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the "X direction". The +Y direction is a direction that intersects (e.g., is orthogonal to) the X direction. The +Y direction is the direction in which the bit line BL extends (see FIG. 7). The -Y direction is the opposite direction of the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the "Y direction". The +Z direction is a direction that intersects (e.g., is orthogonal to) the X direction and the Y direction. The +Z direction is the direction from the first laminate 40A to the second laminate 40B described later (see FIG. 5). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the "Z direction". In the present application, the +Z direction side may be referred to as "up", and the -Z direction side may be referred to as "down". Also, in the present application, the position in the Z direction may be referred to as "height". However, these expressions are for convenience of explanation and do not define the direction of gravity. The Z direction is an example of the "first direction". The +Z direction side is an example of the "first side". The -Z direction side is an example of the "second side". The X direction is an example of the "second direction".

[0010] (First Embodiment) <A1. Configuration of Semiconductor Memory Device> FIG. 1 is a block diagram showing a part of the semiconductor memory device 1 of the first embodiment. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k - 1) (k is an integer of 1 or more). A block BLK is a set of memory cell transistors. A block BLK is used as a data erasure unit. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0012] The command register 12 holds a command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used for selecting a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0013] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. The sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line in a read operation, and transfers the determination result to the host device as read data DAT. The sense amplifier module 17 is an example of a "circuit".

[0014] <A2. Electrical Configuration of Memory Cell Array> <A2.1 Configuration Related to One Block BLK> FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. FIG. 2 shows one block BLK included in the memory cell array 11. A block BLK includes a plurality of strings STR (for example, four strings STR0 to STR3).

[0015] Each string STR contains multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), one or more drain-side selection transistors STD, and one or more source-side selection transistors STS.

[0016] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is stored in the charge storage unit in accordance with the voltage applied to the control gate via the word line WL, and data is held non-volatile.

[0017] The drain of the drain-side selection transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side selection transistor STD is connected to one of the drain-side selection gate lines SGD0 to SGD3. The drain-side selection transistor STD is electrically connected to the row decoder module 16 via the drain-side selection gate line SGD. The drain-side selection transistor STD connects the NAND string NS and the bit line BL when a predetermined voltage is applied to the corresponding drain-side selection gate line SGD.

[0018] The drain of the source-side selection transistor STS is connected to the other ends of the memory cell transistors MT0 to MTn connected in series. The source of the source-side selection transistor STS is connected to the source line SL. The control gate of the source-side selection transistor STS is connected to the source-side selection gate line SGS. When a predetermined voltage is applied to the source-side selection gate line SGS, the source-side selection transistor STS connects the NAND string NS and the source line SL.

[0019] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn, respectively. In the same string STR, the control gate of the drain-side selection transistor STD is commonly connected to the corresponding drain-side selection gate line SGD. The control gate of the source-side selection transistor STS is commonly connected to the source-side selection gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in a plurality of strings STR.

[0020] <A2.2 Configuration related to a plurality of blocks BLK> FIG. 3 is a diagram for explaining the semiconductor memory device 1. FIG. 3 shows a plurality of blocks BLK included in the memory cell array 11. The memory cell array 11 includes, as a plurality of blocks BLK, a plurality of blocks BLKA (a plurality of blocks BLKA0 to BLKAj (j is an integer of 1 or more)) and a plurality of BLKB (a plurality of blocks BLKB0 to BLKBj (j is an integer of 1 or more)). The block BLKA is a block BLK included in the first stacked body 40A (see FIG. 5) described later. The block BLKB is a block BLK included in the second stacked body 40B (see FIG. 5) described later.

[0021] In the present embodiment, the memory cell array 11 includes, as a plurality of bit lines BL, a plurality of bit lines BLA (bit lines BLA0 to BLAm (m is an integer of 1 or more)) and a plurality of bit lines BLB (bit lines BLB0 to BLBm (m is an integer of 1 or more)).

[0022] Multiple bit lines BLA are provided to correspond to multiple block BLKAs. For example, multiple bit lines BLA are provided in common for multiple block BLKAs. For convenience of explanation below, bit lines BLA may be referred to as "lower bit lines BLA". Lower bit lines BLA are an example of "first bit lines".

[0023] Multiple bitline BLBs are provided to correspond to multiple block BLKBs. For example, multiple bitline BLBs are provided in common for multiple block BLKBs. For convenience of explanation below, bitline BLBs may be referred to as "upper bitline BLBs." Upper bitline BLBs are an example of "second bitlines."

[0024] The sense amplifier module 17 has a plurality of sense amplifier units 17a. The plurality of sense amplifier units 17a are provided corresponding to a plurality of bit lines BL. Each sense amplifier unit 17a is a circuit controlled, for example, by a signal from the control circuit 14. For example, the sense amplifier unit 17a has a latch circuit that is electrically connected to the corresponding bit line BL and applies a voltage to the corresponding bit line BL based on the signal from the control circuit 14. Each sense amplifier unit 17a has a terminal 17t to which an electrical connection line 18, described later, is connected. Terminal 17t is an example of a "first terminal".

[0025] In this embodiment, the memory cell array 11 has, in addition to the configuration described above, a plurality of electrical connection lines 18 and a switching circuit 19.

[0026] Multiple electrical connection lines 18 are provided between multiple sense amplifier units 17a and multiple bit lines BL. Multiple electrical connection lines 18 are connection lines that electrically connect multiple sense amplifier units 17a and multiple bit lines BL. Multiple electrical connection lines 18 are provided in a one-to-one relationship with multiple sense amplifier units 17a. For example, multiple electrical connection lines 18 are electrically connected in a one-to-one relationship to terminals 17t of multiple sense amplifier units 17a.

[0027] The switching circuit 19 is a circuit that can switch between a first state in which terminals 17t of multiple sense amplifier units 17a are electrically connected one-to-one with multiple lower bit lines BLA, and a second state in which terminals 17t of multiple sense amplifier units 17a are electrically connected one-to-one with multiple upper bit lines BLB. The switching circuit 19 includes, for example, a switching circuit 19A and a switching circuit 19B.

[0028] The switching circuit 19A is provided between a plurality of electrical connection lines 18 and a plurality of lower bit lines BLA. The switching circuit 19A includes a plurality of switching elements 19Aa that electrically connect the plurality of electrical connection lines 18 and the plurality of lower bit lines BLA in a one-to-one relationship. The plurality of switching elements 19Aa are controlled, for example, by a common signal from the control circuit 14 to the plurality of switching elements 19Aa. The switching circuit 19A is switchable between a first state in which the plurality of electrical connection lines 18 and the plurality of lower bit lines BLA are electrically connected and a second state in which the plurality of electrical connection lines 18 and the plurality of lower bit lines BLA are electrically disconnected.

[0029] The switching circuit 19B is provided between the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB. The switching circuit 19B includes a plurality of switching elements 19Ba that electrically connect the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB in a one-to-one relationship. The plurality of switching elements 19Ba are controlled, for example, by a common signal from the control circuit 14 for the plurality of switching elements 19Ba. The switching circuit 19B can be switched between a first state in which the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB are electrically connected and a second state in which the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB are electrically disconnected.

[0030] <A3. Structure of the semiconductor memory device> Next, the structure of the semiconductor memory device 1 will be described.

[0031] <A3.1 Region division of the memory cell array> Here, the region division of the memory cell array 11 will be described first. FIG. 4 is a diagram for explaining the region division of the memory cell array 11. The memory cell array 11 includes, for example, a plurality of array regions AR, a plurality of hookup regions FR, and a plurality of bit line tap regions BR.

[0032] The array region AR is a region where a plurality of memory pillars MH, which will be described later, are provided and where data can be stored. The hookup region FR is a region where a plurality of contacts CC, which will be described later, are provided and where a plurality of gate electrode layers 41 and a wiring portion 60, which will be described later, are electrically connected. In the example shown in FIG. 4, the hookup region FR is provided on one side in the X direction of the array region AR. However, the hookup region FR may be provided on both sides in the X direction of the array region AR.

[0033] The bit line tap region BR is an area where a plurality of contacts CS described later are provided, and where the switching circuit 19 (or the sense amplifier module 17) and the plurality of upper bit lines BLB are electrically connected. The bit line tap region BR may be referred to as a "bit line connection region". The bit line tap region BR is arranged between two adjacent array regions AR in the Y direction. The bit line tap region BR extends along the X direction.

[0034] <A3.2 Bonding Structure> Next, the bonding structure of the semiconductor memory device 1 will be described. FIG. 5 is a cross-sectional view taken along the F5-F5 line of the semiconductor memory device 1 shown in FIG. 4. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0035] (First Chip) The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0036] The semiconductor substrate 21 is, for example, a substrate serving as the base of the first chip 2. At least a part of the semiconductor substrate 21 is plate-shaped along the X and Y directions. The semiconductor substrate 21 is formed of a semiconductor material such as silicon, for example.

[0037] The peripheral circuit 22 is a circuit for operating the memory cell array 11 described above. The peripheral circuit 22 includes a plurality of transistors 22a and a plurality of electrical connection lines 22b. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, sense amplifier module 17, plurality of electrical connection lines 18, and switching circuit 19 described above. For example, each of the switching elements 19Aa and 19Ba of the switching circuit 19 is formed by a transistor 22a provided on the semiconductor substrate 21. The insulating portion 23 covers the peripheral circuit 22. The plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0038] (Second chip) The second chip 3 is an array chip including the memory cell array 11. The second chip 3 has, for example, a memory cell array 11, an insulating portion 31, and a plurality of pads 32. Here, the insulating portion 31 and the plurality of pads 32 will be described, and the memory cell array 11 will be described later.

[0039] The insulating portion 31 covers the memory cell array 11 from the -Z direction side. The plurality of pads 32 are provided on the surface of the insulating portion 31. Each pad 32 is electrically connected to an electrical connection line (for example, electrical connection lines 61, 62, 63, 64) included in the wiring portion 60 of the memory cell array 11 described later. In the present embodiment, the first chip 2 and the second chip 3 are integrated by facing and bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3.

[0040] <A4. Structure of array region and hookup region> Next, the structures of the array region AR and the hookup region FR will be described. As shown in FIG. 5, the memory cell array 11 includes, for example, a laminate 40, an insulating portion 45, a plurality of memory pillars MH, a plurality of lower bit lines BLA, a plurality of upper bit lines BLB, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the gate electrode layer, a plurality of dividing portions 50 (see FIG. 6), and a wiring portion 60. The laminate 40 includes a first laminate 40A, a second laminate 40B, and a source line SL. Note that the memory pillar MH will be described later.

[0041] <A4.1 First laminate> The first laminate 40A is a laminate that forms the plurality of blocks BLKA described above. The first laminate 40A includes, for example, a plurality of gate electrode layers 41A, a plurality of insulating layers 42A, and an insulating layer 43. The plurality of gate electrode layers 41A and the plurality of insulating layers 42A are alternately stacked one layer at a time in the Z direction.

[0042] The gate electrode layer 41A is a conductive layer along the X direction and the Y direction. Each gate electrode layer 41A includes a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities). The gate electrode layer 41A is an example of a "first gate electrode layer".

[0043] One or more (for example, a plurality) of the gate electrode layers 41A located above among the plurality of gate electrode layers 41A function as a source side selection gate line SGS (source side selection gate line SGSA) for the block BLKA. The source side selection gate line SGSA is provided in common to the lower columnar portions 91 (described later) of the plurality of memory pillars MH arranged in the X direction or the Y direction. The intersection portion between the source side selection gate line SGSA and the channel layer 72 (described later) of each memory pillar MH functions as the source side selection transistor STS described above.

[0044] One or more (e.g., multiple) of the lower gate electrode layers 41A function as drain-side select gate lines SGD (drain-side select gate lines SGDA) for block BLKA. The drain-side select gate lines SGDA are provided in common for the lower columnar portions 91 (described later) of multiple memory pillars MH aligned in the X or Y direction. The intersection of the drain-side select gate lines SGDA and the channel layer 72 (described later) of each memory pillar MH functions as the drain-side select transistor STD described above.

[0045] Of the multiple gate electrode layers 41A, at least a portion of the remaining gate electrode layers 41A provided between the gate electrode layers 41A that function as the source-side selected gate line SGSA and the drain-side selected gate line SGDA functions as a word line WL (WLA) for block BLKA. The word line WL is provided in common for the lower columnar portions 91 (described later) of multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersection portion of the word line WL and the channel layer 72 (described later) of each memory pillar MH functions as the memory cell transistor MT described above.

[0046] The multiple gate electrode layers 41A have different lengths in the X direction within the hookup region FR. For example, the length of the gate electrode layers 41A in the X direction is greater for gate electrode layers 41A located on the +Z direction side. As a result, the ends of the multiple gate electrode layers 41A are arranged in a stepped manner within the hookup region FR.

[0047] The insulating layer 42A is an interlayer insulating film provided between two adjacent gate electrode layers 41A in the Z direction, and insulates the two gate electrode layers 41A. The insulating layer 42A is oriented along the X and Y directions. The insulating layer 42A is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42A is an example of a "first insulating layer".

[0048] The insulating layer 43 is an insulating layer provided above the gate electrode layer 41A disposed at the uppermost position. The insulating layer 43A is disposed between the gate electrode layer 41A disposed at the uppermost position and the source line SL. The insulating layer 43A extends along the X direction and the Y direction. The insulating layer 43 is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is larger than the thickness of the insulating layer 42A in the Z direction.

[0049] <A4.2 Second Stacked Body> The second stacked body 40B is a stacked body forming the plurality of blocks BLKB described above. The second stacked body 40B is disposed above the first stacked body 40A (on the +Z direction side). The second stacked body 40B includes, for example, a plurality of gate electrode layers 41B, a plurality of insulating layers 42B, and an insulating layer 44. The plurality of gate electrode layers 41B and the plurality of insulating layers 42B are alternately stacked one layer at a time in the Z direction.

[0050] The gate electrode layer 41B is a conductive layer extending along the X direction and the Y direction. Each gate electrode layer 41B contains a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities). The gate electrode layer 41B is an example of a "second gate electrode layer".

[0051] One or more (e.g., a plurality) of the gate electrode layers 41B located below among the plurality of gate electrode layers 41B function as source-side selection gate lines SGS (source-side selection gate lines SGSB) for the block BLKB. The source-side selection gate line SGSB is commonly provided for the upper columnar portions 92 (described later) of a plurality of memory pillars MH arranged in the X direction or the Y direction. The intersection portion between the source-side selection gate line SGSB and the channel layer 72 (described later) of each memory pillar MH functions as the source-side selection transistor STS described above.

[0052] One or more gate electrode layers 41B located in the upper part of the multiple gate electrode layers 41B function as drain-side selection gate lines SGD (drain-side selection gate lines SGDB) for block BLKB. The drain-side selection gate lines SGDB are provided in common for the upper columnar portions 92 (described later) of multiple memory pillars MH aligned in the X or Y direction. The intersection of the drain-side selection gate lines SGDB and the channel layer 72 (described later) of each memory pillar MH functions as the drain-side selection transistor STD described above.

[0053] Of the multiple gate electrode layers 41B, at least a portion of the remaining gate electrode layers 41B provided between the gate electrode layers 41B that function as the source-side selection gate line SGSB and the drain-side selection gate line SGDB functions as a word line WL (WLB) for block BLKB. The word line WL is provided in common for the upper columnar portions 92 (described later) of multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersection portion of the word line WL and the channel layer 72 (described later) of each memory pillar MH functions as the memory cell transistor MT described above.

[0054] The multiple gate electrode layers 41B have different lengths in the X direction within the hookup region FR. For example, the length of the gate electrode layers 41B in the X direction is greater for gate electrode layers 41B located on the +Z direction side. As a result, the ends of the multiple gate electrode layers 41B are arranged in a stepped manner within the hookup region FR.

[0055] The insulating layer 42B is an interlayer insulating film provided between two adjacent gate electrode layers 41B in the Z direction, and insulates the two gate electrode layers 41B. The insulating layer 42B is oriented along the X and Y directions. The insulating layer 42B is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42B is an example of a "second insulating layer".

[0056] The insulating layer 44 is an insulating layer provided below the gate electrode layer 41B disposed at the lowermost position. The insulating layer 44 is disposed between the gate electrode layer 41B disposed at the lowermost position and the source line SL. The insulating layer 44 extends along the X direction and the Y direction. The insulating layer 44 is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film). For example, the thickness of the insulating layer 44 in the Z direction is larger than the thickness of the insulating layer 42B in the Z direction.

[0057] In an example of the semiconductor memory device 1, the number of the plurality of gate electrode layers 41A included in the first stacked body 40A is different from the number of the plurality of gate electrode layers 41B included in the second stacked body 40B. In this case, the size of the block BLKA included in the first stacked body 40A is different from the size of the block BLKB included in the second stacked body 40B. This will be described in detail later. Note that the number of the plurality of gate electrode layers 41A included in the first stacked body 40A and the number of the plurality of gate electrode layers 41B included in the second stacked body 40B may be the same.

[0058] Hereinafter, when the first gate electrode layer 41A and the second gate electrode layer 41B are not distinguished, they may be simply referred to as "gate electrode layer 41". When the first insulating layer 42A and the second insulating layer 42B are not distinguished, they may be simply referred to as "insulating layer 42".

[0059] <A4.3 Source Line> The source line SL is disposed between the first stacked body 40A and the second stacked body 40B in the Z direction. The source line SL extends in the X direction and the Y direction. The source line SL is a conductive layer or a semiconductor layer extending along the X direction and the Y direction. The source line SL is formed of, for example, a semiconductor material containing silicon. The source line SL is formed of, for example, polysilicon doped with impurities. However, the material of the source line SL is not limited to the above example. The source line SL may be formed of a metal material such as tungsten or molybdenum. The thickness of the source line SL in the Z direction is larger than, for example, the total of the thickness of the gate electrode layer 41 in the Z direction and the thickness of the insulating layer 42 in the Z direction.

[0060] In this embodiment, the source line SL extends across the array region AR and the hookup region FR. The source line SL includes a first portion SLa disposed in the array region AR and a second portion SLb disposed in the hookup region FR. In this embodiment, the first portion SLa and the second portion SLb have different thicknesses in the Z direction. The thickness T1 of the first portion SLa in the Z direction is greater than the thickness T2 of the second portion SLb in the Z direction. For example, the thickness T1 of the first portion SLa in the Z direction is at least twice the thickness T2 of the second portion SLb in the Z direction. There is a step between the first portion SLa and the second portion SLb.

[0061] <A4.4 Insulating portion of the hookup region> The insulating portion 45 is an insulating portion provided in the hookup region FR. The insulating portion 45 is formed, for example, using TEOS (tetraethyl orthosilicate (Si(OC2H5)4)). A part of the insulating portion 45 covers the ends of the plurality of gate electrode layers 41A arranged in a stepped manner from the -Z direction side. A part of the insulating portion 45 covers the ends of the plurality of gate electrode layers 41B arranged in a stepped manner from the -Z direction side. A part of the insulating portion 45 is disposed between the second portion SLb of the source line SL and the first laminate 40A and covers the second portion SLb of the source line SL from the -Z direction side.

[0062] <A4.5 Lower bit line> The lower bit line BLA is an electrical connection line for selecting one of the plurality of lower columnar portions 91 described later. The plurality of lower bit lines BLA are disposed below (-Z direction side) the first laminate 40A. The plurality of lower bit lines BLA are disposed on the opposite side of the source line SL with respect to the first laminate 40A. The plurality of lower bit lines BLA are spaced apart in the X direction and arranged in the X direction. The lower bit line BLA extends in the Y direction (see FIG. 6). The lower bit line BLA extends so as to pass below the corresponding plurality of lower columnar portions 91.

[0063] The lower bit line BLA is electrically connected to the channel layer 72 of the lower columnar portion 91, which will be described later, via the contact VY and the contact CH. Thereby, by the combination of the word line WLA and the lower bit line BLA, any memory cell transistor MT can be selected from the plurality of memory cell transistors MT three-dimensionally arranged in the first stacked body 40A.

[0064] <A4.6 Upper bit line> The upper bit line BLB is an electrical connection line for selecting one upper columnar portion 92 from a plurality of upper columnar portions 92, which will be described later. The plurality of upper bit lines BLB are arranged on the upper side (+Z direction side) with respect to the second stacked body 40B. The plurality of upper bit lines BLB are arranged on the opposite side of the source line SL with respect to the second stacked body 40B. The plurality of upper bit lines BLB are spaced apart in the X direction and arranged side by side in the X direction. The upper bit line BLB extends in the Y direction (see FIG. 6). The upper bit line BLB extends so as to pass above the corresponding plurality of upper columnar portions 92.

[0065] The upper bit line BLB is electrically connected to the channel layer 72 of the upper columnar portion 92, which will be described later, via the contact VY and the contact CH. Thereby, by the combination of the word line WLB and the upper bit line BLB, any memory cell transistor MT can be selected from the plurality of memory cell transistors MT three-dimensionally arranged in the second stacked body 40B.

[0066] <A4.7 Contact for gate electrode layer> The contact CC is an electrical connection portion that electrically connects the gate electrode layer 41 and an electrical connection line 63 (to be described later) included in the wiring portion 60. The plurality of contacts CC are provided, for example, in the hook-up region FR of the memory cell array 11. The plurality of contacts CC extend in the Z direction within the stacked body 40. The plurality of contacts CC have different lengths in the Z direction and are connected to different gate electrode layers 41. The contact CC has conductivity. The contact CC is formed of a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0067] In this embodiment, the contact CC is connected to the plurality of gate electrode layers 41A included in the first laminate 40A from the -Z direction side. Similarly, the contact CC is connected to the plurality of gate electrode layers 41B included in the second laminate 40B from the -Z direction side.

[0068] <A4.8 Disconnection portion> Next, the disconnection portion 50 will be described. FIG. 6 is a cross-sectional view taken along the F6-F6 line of the semiconductor memory device shown in FIG. 4. The plurality of disconnection portions 50 are provided in the laminate 40. The plurality of disconnection portions 50 are arranged separately in the Y direction. The plurality of disconnection portions 50 extend in the Z direction within the laminate 40 and disconnect one or more gate electrode layers 41 including the lowermost layer or the uppermost layer among the plurality of gate electrode layers 41 in the Y direction. The plurality of disconnection portions 50 include, for example, a plurality of disconnection portions ST (only one is shown in FIG. 6) and a plurality of disconnection portions SHE.

[0069] (Disconnection portion ST) The disconnection portion ST is a wall portion that disconnects the laminate 40 in the Y direction. The plurality of disconnection portions ST are arranged separately in the Y direction. The disconnection portion ST extends in the Z direction and penetrates the laminate 40. For example, the disconnection portion ST penetrates the first laminate 40A, the source line SL, and the second laminate 40B in the Z direction.

[0070] The disconnection portion ST extends in the X direction (see FIG. 7). For example, the disconnection portion ST extends in the X direction so as to span the array region AR and the hook-up region FR. The disconnection portion ST is a wall portion along the X direction and the Z direction. The disconnection portion ST disconnects each of all the gate electrode layers 41 (all the gate electrode layers 41A and all the gate electrode layers 41B) included in the laminate 40 in the Y direction. In this embodiment, in the first laminate 40A, the region sandwiched between two adjacent disconnection portions ST in the Y direction corresponds to one block BLKA. Similarly, in the second laminate 40B, the region sandwiched between two adjacent disconnection portions ST in the Y direction corresponds to one block BLKB.

[0071] In this embodiment, the divided portion ST has an insulating film 51 and a conductive layer (conductive portion) 52. The insulating film 51 extends in the Z direction and penetrates the laminate 40. The insulating film 51 is provided along the entire length of the divided portion ST in the X direction. The insulating film 51 covers the conductive layer 52. The insulating film 51 has an insulating film 51s1 that forms the surface of the divided portion ST on the +Y direction side and an insulating film 51s2 that forms the surface of the divided portion ST on the -Y direction side. The insulating film 51 is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film).

[0072] The conductive layer 52 is located inside the insulating film 51. For example, the conductive layer 52 is located between the insulating film 51s1 and the insulating film 51s2 in the Y direction. The conductive layer 52 extends in the Z direction and penetrates the laminate 40. The conductive layer 52 is formed of a conductive material such as tungsten, molybdenum, or silicon doped with impurities. The upper end of the conductive layer 52 is electrically connected to the electrical connection lines 64 in the memory cell array 11 via contacts 55 and 56.

[0073] In this embodiment, the divided portion ST has a first portion STa and a second portion STb. The insulating film 51 and conductive layer 52 described above are provided across the first portion STa and the second portion STb.

[0074] The first portion STa penetrates the first laminate 40A in the Z direction. The first portion STa divides each of the multiple gate electrode layers 41A in the Y direction. The first portion STa extends from the bottom to the top of the first laminate 40A. The upper end of the first portion STa is located inside the source line SL.

[0075] The second portion STb is located above (towards the +Z direction) the first portion STa. The second portion STb penetrates the second laminate 40B in the Z direction. The second portion STb divides each of the multiple gate electrode layers 41B in the Y direction. The second portion STb extends from the bottom to the top of the second laminate 40B. The lower end of the second portion STb is located inside the source line SL. The lower end of the second portion STb is connected to the upper end of the first portion STa inside the source line SL. The boundary between the first portion STa and the second portion STb is located inside the source line SL.

[0076] The width W1 in the Y direction of the first portion STa is greater than the width W2 in the Y direction of the second portion STb. For example, the width W1 in the Y direction of the first portion STa is more than twice the thickness of the insulating film 51s1 in the Y direction compared to the width W2 in the Y direction of the second portion STb. A step Ts is formed at the boundary between the first portion STa and the second portion STb, based on the difference between the width W1 in the Y direction of the first portion STa and the width W2 in the Y direction of the second portion STb. The step Ts is a step in the Y direction. The step Ts is located inside the source line SL.

[0077] In this embodiment, the insulating film 51 is not provided at the step Ts of the divided portion ST. The insulating film 51 is divided in the Y direction at the boundary (step Ts) between the first portion STa and the second portion STb of the divided portion ST. For example, the insulating film 51 includes a first insulating film 51a located at the first portion STa of the divided portion ST and a second insulating film 51b located at the second portion STb of the divided portion ST. The first insulating film 51a extends in the Z direction in the first portion STa and is located between the conductive layer 52 and the plurality of gate electrode layers 41A. The second insulating film 51b extends in the Z direction in the second portion STb and is located between the conductive layer 52 and the plurality of gate electrode layers 41B. In this embodiment, at the step Ts, the first insulating film 51a and the second insulating film 51b are separated in the Y direction.

[0078] On the other hand, the conductive layer 52 is provided in the first portion STa and the second portion STb. For example, the conductive layer 52 is continuous across the first portion STa and the second portion STb. Therefore, in the region where the insulating film 51 is divided (step Ts), the conductive layer 52 is exposed to the outside of the divided portion 50 (outside the insulating film 51) and connected to the source wire SL. As a result, the conductive layer 52 and the source wire SL are electrically connected. A voltage is applied to the source wire SL via the electrical connection line 64, contacts 55 and 56, and the conductive layer 52 of the divided portion ST, which will be described later.

[0079] (Divided section SHE) The dividing section SHE is a dividing section that has a shorter length in the Z direction compared to the dividing section ST, and is a wall section that divides the lower or upper end of the laminate 40 in the Y direction. Multiple dividing sections SHE include, for example, multiple dividing sections SHEA and multiple dividing sections SHEB.

[0080] The dividing section SHEA is a wall section that divides the lower end of the first laminate 40A in the Y direction. Multiple dividing sections SHEA are arranged separately in the Y direction. In this embodiment, there are multiple (for example, three) dividing sections SHEA between two adjacent dividing sections ST in the Y direction. The dividing section SHEA extends partway down the first laminate 40A in the Z direction and also extends in the X direction. The dividing section SHEA is a wall section that runs along the X and Z directions.

[0081] The partition SHEA penetrates some of the gate electrode layers 41A, including the bottom layer, among the multiple gate electrode layers 41A, and partitions those gate electrode layers 41A in the Y direction. For example, the partition SHEA penetrates each of all the gate electrode layers 41A that function as drain-side selected gate lines SGDA. On the other hand, the partition SHEA does not reach the gate electrode layers 41A that function as word lines WLA. The partition SHEA partitions only the gate electrode layers 41A that function as drain-side selected gate lines SGDA in the Y direction. The partition SHEA is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). In this embodiment, the region sandwiched between two adjacent partition SHEAs in the Y direction corresponds to one string STR.

[0082] The dividing portion SHEB is a wall portion that divides the upper end portion of the second laminate 40B in the Y direction. The plurality of dividing portions SHEB are arranged separately in the Y direction. In the present embodiment, a plurality (for example, three) of dividing portions SHEB exist between two adjacent dividing portions ST in the Y direction. The dividing portion SHEB extends in the Z direction up to the middle of the second laminate 40B and extends in the X direction. The dividing portion SHEB is a wall portion along the X direction and the Z direction.

[0083] The dividing portion SHEB penetrates a part of the gate electrode layers 41B including the uppermost layer among the plurality of gate electrode layers 41B, and divides the part of the gate electrode layers 41B in the Y direction. For example, the dividing portion SHEB penetrates each of all the gate electrode layers 41B that function as the drain side selection gate lines SGDB. On the other hand, the dividing portion SHEB does not reach the gate electrode layers 41B that function as word lines WLB. The dividing portion SHEB divides only the gate electrode layers 41B that function as the drain side selection gate lines SGDB in the Y direction. The dividing portion SHEB is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film). In the present embodiment, the region sandwiched between two adjacent dividing portions SHEB in the Y direction corresponds to one string STR.

[0084] <A4.9 Wiring portion> The wiring portion 60 is an electrical connection portion that electrically connects the plurality of pads 32 and each component included in the memory cell array 11. The wiring portion 60 includes, for example, a wiring portion 60A and a wiring portion 60B.

[0085] The wiring portion 60A is a wiring portion disposed between the first laminate 40A and the semiconductor substrate 21. The wiring portion 60A includes, for example, a plurality of electrical connection lines 61, a plurality of electrical connection lines 62, and a plurality of electrical connection lines 63 (see FIG. 5).

[0086] Multiple electrical connection lines 61 are arranged, for example, on the lower side (-Z direction side) relative to multiple lower bit lines BLA. Each electrical connection line 61 extends, for example, in the X direction or the Y direction. Vias VA are provided between the electrical connection lines 61 and the lower bit lines BLA to electrically connect the electrical connection lines 61 and the lower bit lines BLA.

[0087] The electrical connection line 61 electrically connects the peripheral circuit (e.g., sense amplifier unit 17a) to the lower bit line BLA. For example, the electrical connection line 61 electrically connects the switching circuit 19 (e.g., switching circuit 19A) to the lower bit line BLA. For example, the electrical connection line 61 electrically connects the switching element 19Aa of the switching circuit 19A to the lower bit line BLA. In this embodiment, the electrical connection line 61 is electrically connected to the bonding pad 32. The electrical connection line 61 is electrically connected to the switching circuit 19A via pads 24 and 32.

[0088] Multiple electrical connection lines 62 are positioned, for example, below (-Z direction) multiple contacts CS (only one is shown in Figure 6) provided in the bit line tap region BR. Each electrical connection line 62 extends, for example, in the X direction or the Y direction. A contact VB is provided between the electrical connection line 62 and the contact CS to electrically connect the electrical connection line 62 and the contact CS.

[0089] The electrical connection line 62 electrically connects the peripheral circuit (e.g., sense amplifier unit 17a) to the contact CS. For example, the electrical connection line 62 electrically connects the switching circuit 19 (e.g., switching circuit 19B) to the contact CS. For example, the electrical connection line 62 electrically connects the switching element 19Ba of the switching circuit 19B to the contact CS. In this embodiment, the electrical connection line 62 is electrically connected to the bonding pad 32. The electrical connection line 62 is electrically connected to the switching circuit 19B via pads 24 and 32.

[0090] The electrical connection line 63 electrically connects the peripheral circuit and the contact CC (see FIG. 5). In the present embodiment, the electrical connection line 63 is electrically connected to the bonding pad 32. A voltage for selecting the gate electrode layer 41 (word line WL, drain side selection gate line SGD, or source side selection gate line SGS) is applied to the electrical connection line 63.

[0091] <A5. Structure of Bit Line Tap Region> Next, the structure of the bit line tap region BR will be described. As shown in FIG. 6, the bit line tap region BR includes a third laminate 40C, a fourth laminate 40D, an insulating portion 47, and a plurality of contacts CS (only one is shown in FIG. 6).

[0092] <A5.1 Third Laminate> The third laminate 40C is a laminate located around a part of the contact CS. The third laminate 40C includes, for example, a plurality of insulating layers 46A and a plurality of insulating layers 42A. The plurality of insulating layers 46A and the plurality of insulating layers 42A are alternately laminated one layer at a time in the Z direction.

[0093] The insulating layer 46A is located at the same height as the gate electrode layer 41A. The insulating layer 46A extends along the X direction and the Y direction. The insulating layer 46A is connected to the gate electrode layer 41A in the Y direction. The insulating layer 46A is formed, for example, by a part of a sacrificial layer (sacrificial layer 111A described later) that is not replaced and remains when the gate electrode layer 41A is replaced during the manufacturing process. The insulating layer 46A is formed of a material different from that of the insulating layer 42A. The insulating layer 46A is formed, for example, by a film containing silicon and nitrogen (e.g., a silicon nitride film).

[0094] The insulating layer 42A is provided between two adjacent insulating layers 46A in the Z direction. The insulating layer 42A extends along the X and Y directions. The insulating layer 42A is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42A included in the bit line tap region BR is located at the same height as the insulating layer 42A included in the array region AR. The insulating layer 42A included in the bit line tap region BR is continuous with the insulating layer 42A included in the array region AR.

[0095] <A5.2 Fourth laminate> The fourth laminate 40D is a laminate located around another part of the contact CS. The fourth laminate 40D is disposed above (on the +Z direction side) with respect to the third laminate 40C. The fourth laminate 40D includes, for example, a plurality of insulating layers 46B and a plurality of insulating layers 42B. The plurality of insulating layers 46B and the plurality of insulating layers 42B are alternately laminated one layer at a time in the Z direction.

[0096] The insulating layer 46B is located at the same height as the gate electrode layer 41B. The insulating layer 46B extends along the X and Y directions. The insulating layer 46B is connected to the gate electrode layer 41B in the Y direction. The insulating layer 46B is formed, for example, by a part of a sacrificial layer (sacrificial layer 111B described later) that is not replaced and remains in the gate electrode layer 41B during the manufacturing process. The insulating layer 46B is formed of a material different from that of the insulating layer 42B. The insulating layer 46B is formed of, for example, a film containing silicon and nitrogen (e.g., a silicon nitride film).

[0097] The insulating layer 42B is provided between two adjacent insulating layers 46B in the Z direction. The insulating layer 42B extends along the X and Y directions. The insulating layer 42B is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42B included in the bit line tap region BR is located at the same height as the insulating layer 42B included in the array region AR. The insulating layer 42B included in the bit line tap region BR is continuous with the insulating layer 42B included in the array region AR.

[0098] <A5.3 Insulating portion> The insulating portion 47 is located between the third laminate 40C and the fourth laminate 40D in the Z direction. The insulating portion 47 fills the space between the third laminate 40C and the fourth laminate 40D. The insulating portion 47 is adjacent to the source wire SL in the Y direction.

[0099] <A5.4 コンタクト> Contact CS is an electrical connection that electrically connects a peripheral circuit (e.g., sense amplifier unit 17a) to the upper bit line BLB. In this embodiment, contact CS electrically connects the switching circuit 19 to the upper bit line BLB. For example, contact CS electrically connects the switching element 19Ba of the switching circuit 19B to the upper bit line BLB.

[0100] In this embodiment, the contact CS is a columnar body extending in the Z direction. The contact CS penetrates the third laminate 40C, the fourth laminate 40D, and the insulating portion 47 in the Z direction. The contact CS extends across the lower side of the third laminate 40C and the upper side of the fourth laminate 40D.

[0101] The upper end of contact VB is electrically connected to the upper bit line BLB, for example, via contact VC. The lower end of contact CS is electrically connected to the switching circuit 19, for example, via contact VB. In another example of the semiconductor memory device 1, the switching circuit 19 may not be present. In a structure without the switching circuit 19, the lower end of contact CS is electrically connected to the sense amplifier unit 17a, for example, via contact VB.

[0102] Figure 7 is a magnified view of the region enclosed by the F7 line in the structure shown in Figure 4. As shown in Figure 7, the upper bit line BLB extends in the Y direction so as to overlap with the contact CS and multiple block BLK when viewed from the Z direction.

[0103] FIG. 8 is a diagram showing an enlarged view of a region surrounded by the F8 line of the structure shown in FIG. 7. As shown in FIG. 7, in the bit line tap region BR, a plurality of contacts CS are arranged apart from each other. For example, the plurality of contacts CS are arranged shifted in the X direction and the Y direction. The plurality of upper bit lines BLB are electrically connected in a one-to-one relationship to the corresponding contacts CS via the above-described contacts VC in the bit line tap region BR.

[0104] <A6. Memory pillar> <A6.1 Internal structure of memory pillar> Next, the memory pillar MH will be described. The plurality of memory pillars MH are arranged in the X direction and the Y direction (see FIG. 7). Each memory pillar MH extends in the Z direction within the laminate 40 and penetrates the laminate 40. The memory pillar MH is an example of a "columnar body".

[0105] FIG. 9 is a cross-sectional view for explaining the memory pillar MH. The memory pillar MH has, for example, a memory film (multilayer film) 71, a channel layer 72, an insulating portion 73, and a cap portion 74.

[0106] The memory film 71 is arranged on the outer peripheral portion of the memory pillar MH. The memory film 71 extends in the Z direction. The memory film 71 extends over the entire Z-direction length of the memory pillar MH except for the upper end portion and the intermediate portion of the memory pillar MH. The memory film 71 is located between the plurality of gate electrode layers 41 and the channel layer 72.

[0107] FIG. 10 is a cross-sectional view taken along the F10-F10 line of the structure shown in FIG. 9. The memory film 71 includes, for example, a block insulating film 81, a charge trap film 82, and a tunnel insulating film 83.

[0108] The block insulating film 81 is located on the outermost periphery of the memory pillar MH. The block insulating film 81 is provided between the multiple gate electrode layers 41 and the charge trap film 82. The block insulating film 81 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charge returns from the word line WL to the charge trap film 82. The block insulating film 81 is formed in an annular shape and extends in the Z direction. The block insulating film 81 extends along the entire length of the memory pillar MH in the Z direction, except for, for example, the upper end and middle portion of the memory pillar MH. The block insulating film 81 is a laminated structure film in which multiple insulating films are stacked, such as a film containing silicon and oxygen or a film containing metal and oxygen. An example of a film containing metal and oxygen is an aluminum oxide film. The block insulating film 81 may also contain a high-dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0109] The charge trap film 82 is provided on the inner circumference side of the block insulating film 81 in the X and Y directions. The charge trap film 82 is located between the block insulating film 81 and the tunnel insulating film 83. The charge trap film 82 is formed in an annular shape and extends in the Z direction. The charge trap film 82 extends along the entire length of the memory pillar MH in the Z direction, except for the upper end and middle portion of the memory pillar MH. The charge trap film 82 is a functional film having numerous crystal defects (trap levels) and capable of trapping charges in the crystal defects. The charge trap film 82 is formed from a film containing silicon and nitrogen, for example. The portion of the charge trap film 82 adjacent to each word line WL forms an example of a "charge storage portion 82a" capable of storing information by accumulating charge.

[0110] The tunnel insulating film 83 is provided on the inner circumference side of the charge trap film 82 in the X and Y directions. The tunnel insulating film 83 is provided between the charge trap film 82 and the channel layer 72. The tunnel insulating film 83 is, for example, annular along the outer circumferential surface of the channel layer 72 and extends in the Z direction along the channel layer 72. The tunnel insulating film 83 extends along the entire length of the memory pillar MH in the Z direction, for example, except for the upper end and middle portion of the memory pillar MH. The tunnel insulating film 83 is a potential barrier between the charge trap film 82 and the channel layer 72. The tunnel insulating film 83 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0111] The channel layer 72 is provided on the inner circumference side of the memory film 71 in the X and Y directions. The channel layer 72 is formed in an annular shape. The channel layer 72 extends in the Z direction. The channel layer 72 extends, for example, along the entire length of the memory pillar MH in the Z direction. The channel layer 72 is made of a semiconductor material such as polysilicon. The channel layer 72 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 72 forms a channel to electrically connect the bit line BL and the source line SL. The channel layer 72 is an example of a "semiconductor film".

[0112] With the above configuration, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed at the same height as each word line WL by the edges of the word lines WL adjacent to the memory pillar MH, the block insulating film 81, the charge trap film 82, the tunnel insulating film 83, and the channel layer 72. The memory film 71 may have a floating gate type charge storage unit (floating gate electrode) instead of the charge trap film 82 as a charge storage unit. The floating gate type charge storage unit is formed, for example, from polysilicon containing impurities.

[0113] Returning to Figure 9, the remaining components of the memory pillar MH will be described. The insulating portion 73 is provided on the inner peripheral side of the channel layer 72 in the X direction and the Y direction. The insulating portion 73 fills at least a part of the inside of the channel layer 72. The insulating portion 73 is formed of a film containing silicon and oxygen (for example, a silicon oxide film). The insulating portion 73 extends in the Z direction. The insulating portion 73 extends over the entire length of the memory pillar MH in the Z direction, for example, excluding the lower end portion of the memory pillar MH.

[0114] The cap portion 74 is provided below the insulating portion 73. The cap portion 74 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 74 may be doped with impurities, for example. The cap portion 74 is disposed on the inner peripheral side of the lower end portion of the memory film 71 and is formed integrally with the channel layer 72. The cap portion 74 forms the lower end portion of the memory pillar MH together with the lower end portion of the channel layer 72.

[0115] <A6.2 Multistage Structure of Memory Pillar> In the present embodiment, the memory pillar MH is formed by a plurality of stages (for example, three stages) of columnar bodies. For example, the memory pillar MH includes a columnar body Ma, a columnar body Mb, and a columnar body Mc. Each of the columnar bodies Ma, Mb, and Mc has the above-described memory film (multilayer film) 71, channel layer 72, and insulating portion 73.

[0116] The lower columnar body Ma is provided in the first laminate 40A. The columnar body Ma extends in the Z direction inside the first laminate 40A. The lower end of the columnar body Ma is electrically connected to the lower bit line BLA via the contact CH and the contact VY. The upper end of the columnar body Ma is located inside the first laminate 40A. As the columnar body Ma proceeds from the upper side to the lower side, the perimeter (diameter) of the columnar body Ma in the cross section along the X direction and the Y direction gradually increases.

[0117] The middle columnar body Mb is provided above the columnar body Ma (on the +Z direction side). The columnar body Mb is provided so as to span the first stacked body 40A and the second stacked body 40B. The columnar body Mb penetrates the source line SL in the Z direction and extends in the Z direction inside the first stacked body 40A and inside the second stacked body 40B. The lower end of the columnar body Mb is connected to the upper end of the columnar body Ma inside the first stacked body 40A. The upper end of the columnar body Mb is connected to the lower end of the columnar body Mc inside the second stacked body 40B. As it progresses from the upper side to the lower side, the perimeter (diameter) of the columnar body Mb in the cross section along the X direction and the Y direction gradually increases.

[0118] The upper columnar body Mc is provided above the columnar body Mb (on the +Z direction side). The columnar body Mc is provided in the second stacked body 40B. The columnar body Mc extends in the Z direction inside the second stacked body 40B. The upper end of the columnar body Mc is electrically connected to the upper bit line BLB via the contact CH and the contact VY. As it progresses from the upper side to the lower side, the perimeter (diameter) of the columnar body Mc in the cross section along the X direction and the Y direction gradually increases.

[0119] Note that the configuration of the memory pillar MH is not limited to the above example. For example, instead of being formed by three-stage columnar bodies, the memory pillar MH may be formed by one-stage or two-stage columnar bodies, or may be formed by four-stage or more columnar bodies.

[0120] <A6.3 Lower columnar part and upper columnar part> As shown in FIG. 9, the memory pillar MH includes a lower columnar part 91, an upper columnar part 92, and an intermediate part 93.

[0121] (Lower columnar part) The lower columnar portion 91 is a part of the memory pillar MH that corresponds to the first laminate 40A. The lower columnar portion 91 extends in the Z direction within the first laminate 40A and penetrates the first laminate 40A in the Z direction. In this embodiment, the lower columnar portion 91 is formed by the entirety of the columnar body Ma and the lower part of the columnar body Mb. In this embodiment, for more than half of the lower columnar portion 91 in the Z direction, the circumference (diameter) of the lower columnar portion 91 in the cross-section along the X and Y directions gradually increases as you proceed from the top to the bottom.

[0122] The lower columnar portion 91 includes parts of the memory film 71, the channel layer 72, and the insulating portion 73, as well as the cap portion 74. For the sake of explanation, the portion of the memory film 71 included in the lower columnar portion 91 may be referred to as the "lower memory film 71A." The lower memory film 71A is an example of the "first memory film." Also for the sake of explanation, the portion of the channel layer 72 included in the lower columnar portion 91 may be referred to as the "lower semiconductor film 72A." The lower semiconductor film 72A is an example of the "first semiconductor film."

[0123] Contact CH is in contact with the lower end of the lower columnar portion 91 from the -Z direction side. The lower end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the lower bit line BLA via contact CH and contact VY. The upper end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the source line SL via the intermediate portion 93, which will be described later.

[0124] (upper columnar part) The upper columnar portion 92 is positioned above (towards the +Z direction) the lower columnar portion 91. The upper columnar portion 92 is a part of the memory pillar MH that corresponds to the second laminate 40B. The upper columnar portion 92 extends in the Z direction within the second laminate 40B and penetrates the second laminate 40B in the Z direction. In this embodiment, the upper columnar portion 92 is formed by the entirety of the columnar body Mc and the upper part of the columnar body Mb. In this embodiment, when viewed from the Z direction, the lower columnar portion 91 and the upper columnar portion 92 overlap. In this embodiment, for more than half of the upper columnar portion 92 in the Z direction, the circumference (diameter) of the upper columnar portion 92 in the cross-section along the X and Y directions gradually increases as you proceed from the top to the bottom.

[0125] The upper columnar portion 92 includes parts of the memory film 71, the channel layer 72, and the insulating portion 73. For the sake of explanation, the portion of the memory film 71 included in the upper columnar portion 92 may be referred to as the "upper memory film 71B." The upper memory film 71B is an example of the "second memory film." Also for the sake of explanation, the portion of the channel layer 72 included in the upper columnar portion 92 may be referred to as the "upper semiconductor film 72B." The upper semiconductor film 72B is an example of the "second semiconductor film."

[0126] Contact CH is in contact with the upper end of the upper columnar portion 92 from the +Z direction side. The upper end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the upper bit line BLB via contact CH and contact VY. The lower end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the source line SL via the intermediate portion 93, which will be described later.

[0127] (Middle section) The intermediate portion (intermediate columnar portion) 93 is provided between the lower columnar portion 91 and the upper columnar portion 92 in the Z direction. The intermediate portion 93 penetrates the source wire SL in the Z direction. In this embodiment, the intermediate portion 93 is formed from a part of the columnar body Mb. The intermediate portion 93 includes a part of the memory film 71, the channel layer 72, and the insulating portion 73, respectively.

[0128] On the other hand, in at least a part of the intermediate portion 93, the memory film 71 does not exist. In the present embodiment, the memory film 71 (lower memory film 71A) of the lower columnar portion 91 and the memory film 71 (upper memory film 71B) of the upper columnar portion 92 are separated in the Z direction. Therefore, in the intermediate portion 93, in a region where the memory film 71 does not exist (the region between the lower memory film 71A and the upper memory film 71B), the channel layer 72 is exposed outside the memory pillar MH and is connected to the source line SL. As a result, the channel layer 72 and the source line SL are electrically connected.

[0129] <A7. Arrangement Examples of Disconnection Portions and Bit Line Tap Regions> <A7.1 Arrangement Example of Disconnection Portion> As shown in FIG. 6, the disconnection portion ST is arranged between a plurality of memory pillars MH (memory pillar MHA and memory pillar MHB) arranged in the Y direction.

[0130] The lower columnar portion 91 included in the memory pillar MHA is an example of the "first columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory pillar MHA is an example of the "first memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory pillar MHA is an example of the "first semiconductor film".

[0131] The upper columnar portion 92 included in the memory pillar MHA is an example of the "second columnar portion". The upper memory film 71B of the upper columnar portion 92 included in the memory pillar MHA is an example of the "second memory film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory pillar MHA is an example of the "second semiconductor film".

[0132] From one perspective, the lower columnar portion 91 included in the memory pillar MHB is an example of the "third columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory pillar MHB is an example of the "third memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory pillar MHB is an example of the "third semiconductor film".

[0133] In one aspect, the upper columnar portion 92 included in the memory pillar MHB is an example of a "fourth columnar portion". The upper memory film 71B of the upper columnar portion 92 included in the memory pillar MHA is an example of a "fourth memory film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory pillar MHB is an example of a "fourth semiconductor film".

[0134] In the present embodiment, the conductive layer 52 of the dividing portion ST is provided in at least one of the regions between the lower columnar portion 91 (first columnar portion) of the memory pillar MHA and the lower columnar portion 91 (third columnar portion) of the memory pillar MHB, and between the upper columnar portion 92 (second columnar portion) of the memory pillar MHA and the upper columnar portion 92 (fourth columnar portion) of the memory pillar MHB. And the conductive layer 52 of the dividing portion ST extends in the Z direction in the above region and is connected to the source line SL.

[0135] <A7.2 Arrangement Example of Bit Line Tap Region> As shown in FIG. 6, the bit line tap region BR is arranged between a plurality of memory pillars MH (memory pillar MHA and memory pillar MHC) arranged in the Y direction.

[0136] In one aspect, the lower columnar portion 91 included in the memory pillar MHC is an example of a "fifth columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory pillar MHC is an example of a "fifth memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory pillar MHC is an example of a "fifth semiconductor film".

[0137] In one aspect, the upper columnar portion 92 included in the memory pillar MHC is an example of a "sixth columnar portion". The upper memory film 71B of the upper columnar portion 92 included in the memory pillar MHC is an example of a "sixth memory film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory pillar MHC is an example of a "sixth semiconductor film".

[0138] In this embodiment, the peripheral circuit (for example, the sense amplifier module 17 or the switching circuit 19) is disposed on the opposite side (-Z direction side) of the second laminate 40B with respect to the first laminate 40A. The contact CS of the bit line tap region BS is provided in the region between the lower columnar portion 91 (first columnar portion) of the memory pillar MHA and the lower columnar portion 91 (fifth columnar portion) of the memory pillar MHC, and between the upper columnar portion 92 (second columnar portion) of the memory pillar MHA and the upper columnar portion 92 (sixth columnar portion) of the memory pillar MHC. The contact CS of the bit line tap region BS extends in the Z direction in the above region and electrically connects the peripheral circuit and the upper bit line BLB.

[0139] <A8. Manufacturing method> Next, a method for manufacturing the semiconductor memory device 1 will be described. Here, FIG. 11 is a cross-sectional view schematically showing the structure of the semiconductor memory device 1. For convenience of explanation in FIG. 11, the hook-up region FR, the bit line tap region BR, and the array region AR are shown side by side. FIG. 11 schematically shows the structure related to the X direction and the structure related to the Y direction in an aggregated manner. Hereinafter, the manufacturing method will be described by taking the structure shown in FIG. 11 as an example.

[0140] FIGS. 12 to 47 are cross-sectional views for explaining the manufacturing method of the semiconductor memory device 1. Note that FIGS. 12 to 47 show the structure during manufacturing in a posture that is upside down with respect to FIG. 11.

[0141] First, as shown in FIG. 12, an insulating layer 101 is formed on the semiconductor substrate 100. The insulating layer 101 is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film). Next, as shown in FIG. 13, the sacrificial layer 111B and the insulating layer 42B are alternately laminated one layer at a time in the Z direction. Thereby, a structure 40MA including the insulating layer 101, a plurality of sacrificial layers 111B, and a plurality of insulating layers 42B is formed. The sacrificial layer 111B is formed of, for example, a film containing silicon and nitrogen (for example, a silicon nitride film).

[0142] Next, as shown in Figure 14, a hole H1 corresponding to the columnar body Mc is formed in the structure 40MA. The hole H1 is filled with sacrificial material 112. Next, as shown in Figure 15, sacrificial layers 111B and insulating layers 42B are stacked alternately one layer at a time in the Z direction. In addition, an insulating layer 44 is formed on top of the uppermost sacrificial layer 111B. This forms a structure 40MB in which multiple sacrificial layers 111B, multiple insulating layers 42B, and insulating layer 44 are added to the structure 40MA. Structure 40MB is an example of a "first-stage laminate". Sacrificial layer 111B is an example of a "first layer". Insulating layer 42B is an example of a "second layer".

[0143] Next, as shown in Figure 16, a conductive layer 121, a sacrificial layer 122, a sacrificial layer 123, a sacrificial layer 124, a conductive layer 125, and a stopper layer 126 are sequentially laminated on the 40 MB structure. Each of the conductive layer 121, sacrificial layer 122, sacrificial layer 123, sacrificial layer 124, conductive layer 125, and stopper layer 126 extends in the X and Y directions. The conductive layers 121 and 125 are formed, for example, from polysilicon doped with impurities. The sacrificial layers 122 and 124 are formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). The sacrificial layer 123 and stopper layer 126 are formed, for example, from a film containing silicon and nitrogen (e.g., a silicon nitride film). Sacrificial layer 123 is an example of a "third layer". Next, as shown in Figure 17, portions of the sacrificial layers 122, 123, 124, the conductive layer 125, and the stopper layer 126 that are included in the bit line tap region BR and the hookup region FR are removed.

[0144] Next, as shown in Figure 18, the portion of the conductive layer 121 that is included in the bit line tap region BR and the unnecessary portion included in the hookup region FR are removed. Next, as shown in Figure 19, the stopper layer 126 is removed. Then, TEOS is supplied to the array region AR, the bit line tap region BR, and the hookup region FR, forming the insulating layer 43, the insulating layer 44, and a part of the insulating portion 45. This forms the structure 40MC.

[0145] Next, as shown in Figure 20, sacrificial layers 111A and insulating layers 42A are alternately stacked one layer at a time in the Z direction on top of the structure 40MC. This forms a structure 40MD containing multiple sacrificial layers 111A and multiple insulating layers 42A. Next, as shown in Figure 21, holes H2 corresponding to columnar bodies Mb are formed. The holes H2 are filled with sacrificial material 112.

[0146] Next, as shown in Figure 22, sacrificial layers 111A and insulating layers 42A are alternately stacked one layer at a time in the Z direction on top of the structure 40MD. This forms a structure 40ME in which multiple sacrificial layers 111A and multiple insulating layers 42A are added to the structure 40MD. Structure 40ME is an example of a "second-stage laminate". Sacrificial layer 111A is an example of a "fourth layer". Insulating layer 42A is an example of a "fifth layer". Next, holes H3 corresponding to columnar bodies Ma are formed. Then, the sacrificial material 112 that filled holes H1 and H2 is removed by etching through holes H3.

[0147] Next, as shown in Figure 23, the memory film 71, channel layer 72, and insulating portion 73 are sequentially laminated on the inner circumferential surfaces of holes H1, H2, and H3. Then, the cap portion 74 is formed. This completes the basic structure of the memory pillar MH. The upper columnar portion 92 of the memory pillar MH is an example of the "first stage columnar portion". The lower columnar portion 91 of the memory pillar MH is an example of the "second stage columnar portion".

[0148] Next, an insulating layer 131 is formed on the structure 40ME. The insulating layer 131 is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). This forms the structure 40MF.

[0149] Next, as shown in Figure 24, a groove G1 is formed in the structure 40MF at a position corresponding to the division ST. The groove G1 is a groove that extends in the Z direction and the X direction. The groove G1 is formed using, for example, a conductive layer 121 or a conductive layer 125 as a stopper. Next, as shown in Figure 25, the conductive layers 121 and 125 are removed at the bottom of the groove G1 by etching. As a result, in the array region AR, the sacrificial layer 124 is exposed at the bottom of the groove G1.

[0150] Next, as shown in Figure 26, a semiconductor film 132 is formed on the inner surface of the groove G1. The semiconductor film 132 is formed from, for example, amorphous silicon. Then, as shown in Figure 27, the bottom of the semiconductor film 132 and a portion of the sacrificial layer 124 are removed while using the semiconductor film 132 as a protective film to protect the second sacrificial layer 112B and the second insulating layer 42B. This forms an opening K1 that reaches the sacrificial layer 123.

[0151] Next, as shown in Figure 28, an etching agent capable of removing the silicon nitride film (e.g., hot phosphoric acid) is supplied to the opening K1 to remove the sacrificial layer 123. Then, as shown in Figure 29, an etching agent capable of removing the silicon oxide film is supplied to the opening K1 to remove the sacrificial layers 122 and 124, and also remove the memory film 71 exposed in the space S1 between the conductive layers 121 and 125. This exposes the channel layer 72 in the space S1 between the conductive layers 121 and 125. This completes the memory pillar MH.

[0152] Next, as shown in Figure 30, the insulating layer 131 is removed. Then, a conductive layer 141 is formed in the space S1 between the conductive layers 121 and 125 through the groove G1. The conductive layer 141 is formed of impurity-doped polysilicon. The conductive layer 141 is connected to the channel layer 72 of the memory pillar MH and integrated with the conductive layers 121 and 125. Thus, the conductive layers 121, 125, and 141 form the source wire SL.

[0153] Next, as shown in Figure 31, an insulating film 146 is formed on the inner surface of the groove G1 as a protective film. The insulating film 146 is formed, for example, by a film containing silicon and oxygen (e.g., a silicon oxide film). Next, as shown in Figure 32, a mask 147 is formed on the inner surface of the insulating film 146. The mask 147 is formed, for example, by a metallic material such as titanium nitride or tungsten.

[0154] Next, as shown in Figure 33, a groove G2 is formed at the bottom of groove G1, penetrating the mask 147 and the insulating film 146, and also penetrating the structure 40MF in the Z direction. Here, since the mask 147 and the insulating film 146 are provided on the inner surface of groove G1, the width of groove G2 in the Y direction is smaller than the width of groove G1 in the Y direction by the thickness corresponding to the mask 147 and the insulating film 146. Next, as shown in Figure 34, the insulating film 146 and the mask 147 are removed. As a result, grooves G1 and G2 form a groove G3 with a step Ts in the middle of the source line SL in the Z direction.

[0155] Next, as shown in Figure 35, an insulating film 151 is formed on the inner surface of the groove G3 in the portion corresponding to the source wire SL. The insulating film 151 is formed, for example, by a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating film 151 is formed, for example, by oxidizing the surface of the source wire SL. The insulating film 151 is a protective film that protects the source wire SL in the replacement process described later.

[0156] Next, as shown in Figure 36, an etching agent capable of removing the silicon nitride film (e.g., hot phosphoric acid) is supplied to the groove G3 to remove multiple first sacrificial layers 111A and multiple second sacrificial layers 111B. At this time, the bit line tap region BR is located far from the groove G3, making it difficult for the etching agent to reach it. Therefore, in the bit line tap region BR, multiple first sacrificial layers 111A and multiple second sacrificial layers 111B remain as multiple insulating layers 46A and multiple insulating layers 46B.

[0157] Next, as shown in Figure 37, conductive material is supplied through the groove G3 to the space where the multiple first sacrificial layers 111A and multiple second sacrificial layers 111B have been removed. This forms multiple first gate electrode layers 41A and multiple second gate electrode layers 41B. Next, an insulating film 152 is formed on the inner surface of the groove G3. The insulating film 152 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film).

[0158] Next, as shown in Figure 38, the insulating film 151 (the portion of the insulating film 151 along the X and Y directions) present in the step Ts of the groove G3 is removed by reactive ion etching (RIE). This exposes the source wire SL at the step Ts of the groove G3. In this embodiment, the insulating film 51 of the divided portion ST is formed by the insulating film 151 and the insulating film 152. Next, as shown in Figure 39, a conductive material is supplied into the interior of the groove G3 to form a conductive layer 52. This forms the divided portion ST.

[0159] Next, as shown in Figure 40, the divided portion SHEA and the contact CH that contacts the lower columnar portion 91 of the memory pillar MH are formed. Next, as shown in Figure 41, the contact CS is formed in the bit line tap region BR and the contact CC is formed in the hook-up region FR. Next, as shown in Figure 42, the contact VY, bit line BLA, and wiring portion 60A are formed. This completes the formation of the structure 40MG, which is the basic structure of the second chip 3.

[0160] Next, as shown in Figure 43, the structure 40MG is inverted and bonded to the separately prepared first chip 2. Then, the semiconductor substrate 100 is removed. Next, the memory film 71 is removed from the upper end of the memory pillar MH to expose the channel layer 72. At this stage, an additional step may be performed to thicken the upper end of the channel layer 72.

[0161] Next, as shown in FIG. 44, an insulating portion 161 is formed on the structure 40MG. Next, a dividing portion SHEB is formed. Next, as shown in FIG. 45, a contact CH that contacts the upper columnar portion 92 of the memory pillar MH and a contact 55 that contacts the dividing portion ST are formed.

[0162] Next, as shown in FIG. 46, an upper bit line BLB is formed. Next, as shown in FIG. 47, an insulating portion 162 that covers the upper bit line BLB is formed. Next, on the insulating portion 162, an electrical connection line 84 that is electrically connected to the source line SL via the dividing portion ST is formed. Next, an insulating portion that covers the electrical connection line 84 is formed. Thus, the semiconductor memory device 1 is completed.

[0163] <A9. Advantages> In recent years, with the increase in the capacity of semiconductor memory devices, the number of stacked gate electrode layers has tended to increase. When the number of stacked gate electrode layers increases, the resistance of the string STR increases, and it becomes difficult to secure the current flowing through the channel layer of the memory pillar.

[0164] On the other hand, in the present embodiment, the semiconductor memory device 1 includes a first stacked body 40A, a second stacked body 40B, a source line SL, a lower columnar portion 91, an upper columnar portion 92, a lower bit line BLA, and an upper bit line BLB. The source line SL is disposed between the first stacked body 40A and the second stacked body 40B in the Z direction. The lower columnar portion 91 extends in the Z direction within the first stacked body 40A. The lower columnar portion 91 includes a memory film 71A including a charge storage portion 82a and a channel layer 72A. The upper columnar portion 92 extends in the Z direction within the second stacked body 40B. The upper columnar portion 92 includes a memory film 71B including a charge storage portion 82a and a channel layer 72B. The lower bit line BLA is disposed on the opposite side of the source line SL with respect to the first stacked body 40A. The lower first bit line BLA is electrically connected to the lower columnar portion 91. The upper bit line BLB is disposed on the opposite side of the source line SL with respect to the second stacked body 40B. The upper bit line BLB is electrically connected to the upper columnar portion 92.

[0165] With this configuration, for example, compared to the case where the source line SL is on the +Z direction side with respect to the first stack 40A and the second stack 40B, the resistance of the string STR becomes smaller, making it easier to secure the current flowing through the channel layer 72. Easier securing of the current flowing through the channel layer 72 improves the reliability of the writing operation of the semiconductor memory device 1. This makes it possible to provide a semiconductor memory device 1 with improved electrical characteristics.

[0166] In this embodiment, the lower columnar portion 91 and the upper columnar portion 92 overlap when viewed from the Z direction. With this configuration, the lower columnar portion 91 and the upper columnar portion 92 can be arranged at a higher density in the semiconductor memory device 1. This makes it easier to further increase the capacity of the semiconductor memory device 1.

[0167] In this embodiment, the semiconductor memory device 1 includes a memory pillar MH. The memory pillar MH includes a lower columnar portion 91 and an upper columnar portion 92, and penetrates the first stacked body 40A, the second stacked body 40B, and the source line SL in the Z direction. With this configuration, the lower columnar portion 91 and the upper columnar portion 92 can be formed by a single memory pillar MH. This improves the manufacturability of the semiconductor memory device 1 compared to the case where the lower columnar portion 91 and the upper columnar portion 92 are formed by separate memory pillars MH.

[0168] In this embodiment, the memory film 71 of the lower columnar portion 91 and the memory film 71 of the upper columnar portion 92 are separated in the Z direction. The memory pillar MH has the memory film 71 of the lower columnar portion 91, the memory film 71 of the upper columnar portion 92, and a channel layer 72. The channel layer 72 is connected to the source line SL in the region between the memory film 71 of the lower columnar portion 91 and the memory film 71 of the upper columnar portion 92. With this configuration, electrical connection between the memory pillar MH and the source line SL can be ensured at a point along the Z direction of the memory pillar MH.

[0169] In this embodiment, the number of gate electrode layers 41A included in the first laminate 40A is different from the number of gate electrode layers 41B included in the second laminate 40B. With this configuration, the capacity of block BLKA included in the first laminate 40A and the capacity of block BLKB included in the second laminate 40B can be made different. Making the capacity of block BLKA included in the first laminate 40A and the capacity of block BLKB included in the second laminate 40B different allows for more appropriate writing operations. For example, by making the capacity of block BLKA smaller than that of block BLKB, and prioritizing the writing of data with a smaller data size to block BLKA compared to block BLKB, the writing operation can be made faster.

[0170] In this embodiment, the semiconductor memory device 1 comprises a sense amplifier module 17 having a terminal 17t and a switching circuit 19. The switching circuit 19 can switch between a first state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the lower bit line BLA, and a second state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the upper bit line BLB. With this configuration, for example, compared to the case in which the write target is switched between the first stack 40A and the second stack 40B using drain-side selection gate lines SGDA and SGDB, power consumption related to switching the write target can be reduced.

[0171] In this embodiment, the semiconductor memory device 1 is provided between the memory pillar MHA and the memory pillar MHC, extends in the Z direction, and includes a switching circuit 19 (or sense amplifier module 17). It has a contact CS that electrically connects to the upper bit line BLB. With this configuration, the electrical connection path between the switching circuit 19 (or sense amplifier module 17) and the upper bit line BLB can be shortened. This makes it possible to improve the processing speed of the semiconductor memory device 1 or reduce its power consumption.

[0172] In this embodiment, the semiconductor memory device 1 has a dividing portion ST. The dividing portion ST includes a first portion STa that divides each of the plurality of gate electrode layers 41A in the Y direction, and a second portion STb that divides each of the plurality of gate electrode layers 41B in the Y direction. The dividing portion ST has a conductive layer 52 and an insulating film 51 that covers the conductive layer 52. The conductive layer 52 and the insulating film 51 are provided across the first portion STa and the second portion STb. The width W1 in the Y direction of the first portion STa is larger than the width W2 in the Y direction of the second portion STb. The boundary between the first portion STa and the second portion STb is located inside the source line SL and has a step Ts in the Y direction. At the step Ts, the insulating film 51 is divided in the Y direction, and the conductive layer 52 is exposed outside the insulating film 51 and connected to the source line SL.

[0173] According to such a configuration, an electrical connection path connected to the source line SL can be provided inside the array region AR. According to this configuration, compared with the case where the above electrical connection path is provided in the hookup region FR, it becomes easier to improve the electrical characteristics of the semiconductor memory device 1. For example, according to the above configuration, compared with the case where the above electrical connection path is provided in the hookup region FR, the number of the above electrical connection paths can be increased, the resistance of the electrical connection path to the source line SL can be reduced, and / or the path length between the above electrical connection path and each memory pillar MH can be shortened.

[0174] <A9. Modification Example> Hereinafter, some modification examples of the first embodiment will be described. Note that these modification examples may also be applied to the second embodiment described later.

[0175] In the semiconductor memory device 1 of the first embodiment described above, a switching circuit 19 is provided, and the lower bit line BLA and the upper bit line BLB are switched by the switching circuit 19. Instead of this, the switching circuit 19 may not be provided. In this case, the switching between the lower bit line BLA and the upper bit line BLB may be performed using, for example, the drain side selection gate line SGDA of the first laminate 40A and the drain side selection gate line SGDB of the second laminate 40B.

[0176] In the semiconductor memory device 1 of the first embodiment described above, the electrical connection between the source line SL and the electrical connection line 64 is ensured by the conductive layer 52 of the separation portion ST. Alternatively, the conductive layer 52 of the separation portion ST may be omitted. In this case, a contact CC for electrically connecting the source line SL and the electrical connection line 64 may be provided in the hookup region FR.

[0177] (Second Embodiment) Next, the semiconductor memory device 1A of the second embodiment will be described. The second embodiment differs from the first embodiment in that the lower columnar portion 91 and the upper columnar portion 92 are formed by separate memory pillars. Other than what is described below, the configuration is the same as that of the first embodiment.

[0178] <B1.メモリピラー> Figure 48 is a cross-sectional view showing a part of the semiconductor memory device 1A of the second embodiment. In this embodiment, the semiconductor memory device 1A has a plurality of first memory pillars MH1 and a plurality of second memory pillars MH2 instead of the plurality of memory pillars MH of the first embodiment.

[0179] (First memory pillar) Multiple first memory pillars MH1 are arranged in the X and Y directions. The first memory pillars MH1 extend in the Z direction within the first laminate 40A and penetrate the first laminate 40A in the Z direction. In this embodiment, the total length in the Z direction of the lower columnar portion 91 is formed by the total length in the Z direction of the first memory pillar MH1. The lower columnar portion 91 is an example of the "first columnar portion". Note that the first memory pillar MH1 is not limited to a single-stage memory pillar in the Z direction, but may be a two-stage or more memory pillar in which multiple columnar bodies are stacked in the Z direction.

[0180] (Second memory pillar) Multiple second memory pillars MH2 are arranged in the X and Y directions. The second memory pillars MH2 extend in the Z direction within the second laminate 40B and penetrate the second laminate 40B in the Z direction. In this embodiment, the total length in the Z direction of the upper columnar portion 92 is formed by the total length in the Z direction of the second memory pillars MH2. The second memory pillars MH2 are an example of the "second columnar portion". Note that the second memory pillars MH2 are not limited to a single-stage memory pillar in the Z direction, but may be a two-stage or more memory pillar with multiple columnar bodies stacked in the Z direction.

[0181] Figure 49 is a cross-sectional view illustrating the memory pillars MH1 and MH2 of the second embodiment. The first memory pillar MH1 (lower columnar portion 91) includes a memory film 71 (lower memory film 71A), a channel layer 72 (lower semiconductor film 72A), an insulating portion 73, and a cap portion 74. The memory film 71 included in the first memory pillar MH1 is an example of the "first memory film". The channel layer 72 included in the first memory pillar MH1 is an example of the "first semiconductor film".

[0182] The first memory pillar MH1 does not penetrate the source line SL. The upper end of the first memory pillar MH1 is physically and electrically connected to the source line SL. Contact CH is in contact with the lower end of the first memory pillar MH1 from the -Z direction side. The channel layer 72 of the first memory pillar MH1 is electrically connected to the lower bit line BLA via contact CH and contact VY. In this embodiment, the circumference (diameter) of the first memory pillar MH1 (lower columnar portion 91) gradually increases in the cross-section along the X and Y directions as you proceed from the top to the bottom.

[0183] The first memory pillar MH1 has a first end MHe1 (the end on the +Z direction side) that is in contact with the source line SL, and a second end MHe2 (the end on the -Z direction side) located on the opposite side from the first end MHe1. The second end MHe2 is in contact with contact CH and is electrically connected to the bit line BLA via contact CH. In this embodiment, the circumference (diameter) of the first memory pillar MH1 at the second end MHe2 is greater than the circumference (diameter) of the first memory pillar MH1 at the first end MHe1.

[0184] The second memory pillar MH2 (upper columnar portion 92) includes a memory film 71 (upper memory film 71B), a channel layer 72 (upper semiconductor film 72B), an insulating portion 73, and a cap portion 74. The memory film 71 included in the second memory pillar MH2 is an example of the "second memory film". The channel layer 72 included in the second memory pillar MH2 is an example of the "second semiconductor film".

[0185] The second memory pillar MH2 does not penetrate the source line SL. The lower end of the second memory pillar MH2 is physically and electrically connected to the source line SL. Contact CH is in contact with the upper end of the second memory pillar MH2 from the +Z direction side. The channel layer 72 of the second memory pillar MH2 is electrically connected to the upper bit line BLB via contact CH and contact VY. In this embodiment, the circumference (diameter) of the second memory pillar MHB in the cross section along the X and Y directions gradually increases as you proceed from the top to the bottom of the second memory pillar MH2 (upper columnar portion 92).

[0186] The second memory pillar MH2 has a third end MHe3 (the end on the -Z direction side) that is in contact with the source line SL, and a fourth end MHe4 (the end on the +Z direction side) located on the opposite side from the third end MHe3. The fourth end MHe4 is in contact with contact CH and is electrically connected to the bit line BLB via contact CH. In this embodiment, the circumference (diameter) of the second memory pillar MH2 at the fourth end MHe4 is smaller than the circumference (diameter) of the second memory pillar MH2 at the third end MHe3.

[0187] In this embodiment, the second memory pillar MH2 is separated from the first memory pillar MH1 in the Z direction. The first memory pillar MH1 and the second memory pillar MH2 are separated from each other. For example, the channel layer 72 (lower semiconductor film 72A) included in the first memory pillar MH1 and the channel layer 72 (upper semiconductor film 72B) included in the second memory pillar MH2 are separated in the Z direction. The channel layer 72 (lower semiconductor film 72A) included in the first memory pillar MH1 and the channel layer 72 (upper semiconductor film 72B) included in the second memory pillar MH2 are each electrically connected to the source line SL and are electrically connected to each other via the source line SL.

[0188] <B2. Division section> FIG. 50 is a cross-sectional view taken along the line F50-F50 of the semiconductor memory device 1A shown in FIG. 48. In this embodiment, the semiconductor memory device 1A includes a first division section ST1 and a second division section ST2 instead of the division section ST of the first embodiment.

[0189] (First division section) The first division section ST1 is a wall section along the Z direction and the Y direction. The first division section ST1 extends in the Z direction within the first laminate 40A and penetrates the first laminate 40A in the Z direction. The first division section ST1 divides all the gate electrode layers 41 included in the first laminate 40A in the Y direction. The first division section ST1 does not penetrate the source line SL. In the example shown in FIG. 50, the first division section ST1 is formed only by the insulating film 51 without having the conductive layer 52. Instead of the above example, the first division section ST1 may have the insulating film 51 and the conductive layer 52.

[0190] (Second division section) The second dividing portion ST2 is a wall portion along the Z direction and the Y direction. The second dividing portion ST2 extends in the Z direction within the second stacked body 40B and penetrates the second stacked body 40B in the Z direction. The second dividing portion ST2 divides all the gate electrode layers 41 included in the second stacked body 40B in the Y direction. In the present embodiment, the second dividing portion ST2 does not penetrate the source line SL. In the present embodiment, the second dividing portion ST2 is separated from the first dividing portion ST1 in the Z direction. In the example shown in FIG. 50, the second dividing portion ST2 has an insulating film 51 and a conductive layer 52. Instead of this, when the first dividing portion ST1 has the conductive layer 52, the second dividing portion ST2 may be formed only by the insulating film 51 without having the conductive layer 52.

[0191] <B3. Manufacturing method> Next, a method for manufacturing the semiconductor memory device 1A will be described. FIGS. 51 to 56 are diagrams for explaining a method for manufacturing the semiconductor memory device 1A. First, as shown in FIG. 51, an insulating layer 101 is formed on the semiconductor substrate 100. Next, the sacrificial layer 111B and the insulating layer 42B are alternately stacked in the Z direction. Next, the ends of the plurality of sacrificial layers 111B are formed in a stepped shape. Also, the second memory pillar MH2 and the second dividing portion ST2 are formed. Next, by a replacement process, the plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B. Thereby, the structure 40NA is formed.

[0192] Next, as shown in FIG. 52, a source line SL is provided on the structure 40NA. Thereby, the structure 40NB is formed. The source line SL is an example of the "third layer".

[0193] Next, as shown in FIG. 53, the sacrificial layer 111A and the insulating layer 42A are alternately stacked in the Z direction on the structure 40NA. Next, the ends of the plurality of sacrificial layers 111A are formed in a stepped shape. Also, the first memory pillar MH1 and the first dividing portion ST1 are provided. Next, by a replacement process, the plurality of sacrificial layers 111A are replaced with a plurality of gate electrode layers 41A. Thereby, the structure 40NC is formed.

[0194] Next, as shown in FIG. 54, a dividing portion SHEA, a contact CH, a contact VY, a lower bit line BLA, a pad 32, and a wiring portion 60A are formed. Thereby, a structure 40ND is formed. The structure 40ND includes a basic portion of the second chip 3.

[0195] Next, as shown in FIG. 55, the structure 40ND is turned upside down, and the separately prepared first chip 2 and the structure 40ND are bonded together. Next, the semiconductor substrate 100 is removed. Next, as shown in FIG. 56, an upper bit line BLB is formed. Next, a wiring portion 60B, an insulating portion, and the like are provided. Thereby, the semiconductor memory device 1A is completed.

[0196] <B4. Advantages> According to such a configuration, similar to the first embodiment, the electrical characteristics of the semiconductor memory device 1A can be improved.

[0197] <B5. Modification of the manufacturing method> In the second embodiment described above, before the source line SL is formed, a replace process in which a plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B is performed. Instead, the replace process in which a plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B may be performed after the source line SL is formed. For example, the replace process in which a plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B may be performed simultaneously with the replace process in which a plurality of sacrificial layers 111A are replaced with a plurality of gate electrode layers 41A.

[0198] The above describes several embodiments and modifications. However, the embodiments and modifications are not limited to the above examples. For example, the above-described embodiments and modifications may be realized by being appropriately combined. Also, the source line SL may be provided by being divided for each string STR. Also, the lower bit line BLB and the upper bit line BLB may be directly electrically connected to the sense amplifier module 17 without passing through the switching circuit 19.

[0199] According to at least one embodiment described above, the semiconductor memory device includes a first stack, a second stack, a source line, a first columnar portion, a second columnar portion, a first bit line, and a second bit line. The first stack includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately one layer at a time in a first direction. The second stack is located on the first side of the first stack in the first direction. The second stack includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately one layer at a time in the first direction. The source line is located between the first stack and the second stack in the first direction. The source line extends in a second direction different from the first direction. The first columnar portion extends within the first stack in the first direction. The first columnar portion includes a first memory film including a charge storage portion and a first semiconductor film. The second columnar portion extends in the first direction within the second stacked body. The second columnar portion includes a second memory film containing a charge storage portion and a second semiconductor film. The first bit line is located on the second side of the first stacked body, opposite to the first side in the first direction. The first bit line is electrically connected to the first columnar portion. The second bit line is located on the first side of the second stacked body, in the first direction. The second bit line is electrically connected to the second columnar portion. With this configuration, the electrical characteristics of the semiconductor memory device can be improved.

[0200] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0201] 1,1A…Semiconductor memory 17…Sense amplifier module (circuit) 17a...Sense Amplifier Unit 17t... Terminal (Terminal 1) 19…Switching circuit (circuit) 40A…First layer 40B…Second layer 41A...Gate electrode layer (first gate electrode layer) 41B...Gate electrode layer (second gate electrode layer) 42A...Insulating layer (first insulating layer) 42B...Insulating layer (second insulating layer) 71...Memory film 72... Channel Layer 91...Lower columnar part (first columnar part) 92...Upper columnar part (second columnar part) MH...Memory Pillar (Columnar Body) MH1...First memory pillar MH2...Second memory pillar SL…Source Line BLA... Lower bit line (1st bit line) BLB... Upper bit line (2nd bit line)

Claims

1. A first laminate comprising a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked one layer at a time in a first direction, A second laminate is positioned on the first side in the first direction relative to the first laminate, and includes a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked one layer at a time in the first direction, A source line is positioned between the first laminate and the second laminate in the first direction and extends in a second direction intersecting the first direction, The first columnar portion includes a first memory film that extends in the first direction within the first laminate and includes a charge storage portion, and a first semiconductor film, The second columnar portion includes a second memory film that extends in the first direction within the second laminate and includes a charge storage portion, and a second semiconductor film, A first bit line is positioned on the opposite side of the first laminate from the source line and is electrically connected to the first columnar portion, A second bit line is positioned on the opposite side of the second laminate from the source line and is electrically connected to the second columnar portion, A semiconductor memory device equipped with [specific features / features].

2. When viewed from the first direction, the first columnar portion and the second columnar portion overlap. The semiconductor memory device according to claim 1.

3. The first columnar portion and the second columnar portion are included, and the first laminate, the second laminate, and the columnar portion through which the source line penetrates in the first direction are provided. A semiconductor memory device according to claim 1 or claim 2.

4. The first memory film and the second memory film are separated in the first direction. The columnar body has a semiconductor film comprising the first semiconductor film and the second semiconductor film, The semiconductor film is connected to the source line in the region between the first memory film and the second memory film. The semiconductor memory device according to claim 3.

5. The first semiconductor film and the second semiconductor film are separated from each other in the first direction and are electrically connected to the source line. A semiconductor memory device according to claim 1 or claim 2.

6. For more than half of the first columnar portion in the first direction, as it extends from the first side toward the second side opposite to the first side, the circumference of the first columnar portion in the cross-section intersecting the first direction increases. For more than half of the second columnar portion in the first direction, the circumference of the second columnar portion in the cross-section intersecting the first direction increases as it progresses from the first side toward the second side. A semiconductor memory device according to claim 1 or claim 2.

7. The first columnar portion has a first end that is in contact with the source line and a second end located on the opposite side of the first end, and the circumference of the first columnar portion at the second end is greater than the circumference of the first columnar portion at the first end. The second columnar portion has a third end in contact with the source line and a fourth end located on the opposite side of the third end, and the circumference of the second columnar portion at the fourth end is smaller than the circumference of the second columnar portion at the third end. A semiconductor memory device according to claim 1 or claim 2.

8. The first laminate extends in the first direction and includes a third memory film containing a charge storage portion and a third semiconductor film, and a third columnar portion, The second laminate extends in the first direction and includes a fourth memory film containing a charge storage portion and a fourth semiconductor film, and a fourth columnar portion, A conductive layer is provided between the first columnar portion and the third columnar portion, and between the second columnar portion and the fourth columnar portion, extending in the first direction and connected to the source wire, Furthermore, A semiconductor memory device according to claim 1 or claim 2.

9. The number of the plurality of first gate electrode layers included in the first laminate and the number of the plurality of second gate electrode layers included in the second laminate are different. A semiconductor memory device according to claim 1 or claim 2.

10. The number of the plurality of first gate electrode layers included in the first laminate is the same as the number of the plurality of second gate electrode layers included in the second laminate. A semiconductor memory device according to claim 1 or claim 2.

11. A sense amplifier module having a first terminal, A switching circuit capable of switching between a first state in which the first terminal and the first bit line are electrically connected, and a second state in which the first terminal and the second bit line are electrically connected. Furthermore, A semiconductor memory device according to claim 1 or claim 2.

12. The first columnar portion extends in the first direction within the first laminate and includes a fifth memory film containing a charge storage portion and a fifth semiconductor film, The second laminate extends in the first direction and includes a sixth memory film containing a charge storage portion and a sixth semiconductor film, and a sixth columnar portion, A circuit arranged on the opposite side of the first laminate from the second laminate, A contact is provided between the first columnar portion and the fifth columnar portion, and between the second columnar portion and the sixth columnar portion, extending in the first direction, and electrically connecting the circuit and the second bit line, Furthermore, A semiconductor memory device according to claim 1 or claim 2.

13. The device further comprises a dividing portion including a first portion that divides each of the plurality of first gate electrode layers in the second direction, and a second portion that divides each of the plurality of second gate electrode layers in the second direction. The divided portion has a conductive layer and an insulating film covering the conductive layer, and the conductive layer and the insulating film are provided across the first portion and the second portion. The width of the first portion in the second direction is greater than the width of the second portion in the second direction. The boundary between the first part and the second part is located inside the source line and has a step in the second direction. In the step, the insulating film is divided in the second direction, and the conductive layer is exposed to the outside of the insulating film and connected to the source wire. A semiconductor memory device according to claim 1 or claim 2.

14. A first-stage laminate is formed by including a plurality of first layers and a plurality of second layers, wherein the plurality of first layers and the plurality of second layers are stacked alternately one layer at a time in a first direction. A third layer is formed above the first layer of laminate, extending in a direction intersecting the first direction. Above the third layer, a second-stage laminate is formed, which includes a plurality of fourth layers and a plurality of fifth layers, and in which the plurality of fourth layers and the plurality of fifth layers are stacked alternately one layer at a time in the first direction. A first-stage columnar portion is formed within the first-stage laminate, extending in the first direction and including a memory film containing a charge storage portion and a semiconductor film. A second columnar portion is formed within the second-stage laminate, extending in the first direction and including a memory film containing a charge storage portion and a semiconductor film. A bit wire is formed that is located on the opposite side of the third layer from the second columnar portion and is electrically connected to the second columnar portion. A bit wire is formed which is located on the opposite side of the third layer from the first columnar portion and is electrically connected to the first columnar portion. A method for manufacturing a semiconductor memory device, including the following.

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