Memory device

Abstract

To reduce the size of storage devices. [Solution] The memory device has a memory cell array and a peripheral circuit, the first circuit of the peripheral circuit includes a first transistor, a second transistor, a trench, a first insulating layer and a second insulating layer, the first transistor is connected to the first word line via the first connecting electrode and the fourth connecting electrode, the second transistor is connected to the second word line via the second connecting electrode and the fifth connecting electrode, the trench is provided in the first semiconductor layer between the first transistor and the second transistor, the first insulating layer is formed in the trench, the second circuit is connected to the bit line via the third connecting electrode and the sixth connecting electrode, and the second insulating layer is in contact with the first insulating layer at the end of the first insulating layer furthest from the memory cell array.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory device.

Background Art

[0002] A memory device composed of a plurality of transistors formed on a semiconductor substrate is known. The memory device is composed of a memory cell array and peripheral circuits. In the memory cell array, with an increase in the number of layers in the multilayer wiring structure used as word lines and an increase in the number of bits per memory cell to make the memory cell multi-valued, miniaturization and high density of the memory device's layout area are required. On the other hand, with the speeding up of the input / output circuits, high performance of the peripheral circuits is required. Therefore, there is a problem that it is difficult to miniaturize the peripheral circuits.

[0003] In order to solve such problems, in recent years, a CBA (CMOS directly Bonded to Array) process for forming a memory chip has been developed, in which a memory wafer on which a memory cell array is formed and a CMOS wafer on which peripheral circuits are formed are separately formed, and wirings provided on these wafers are bonded together.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to miniaturize the memory device. Or, one of the aims is to speed up and reduce power consumption of the input / output circuits used in the memory device. [Means for solving the problem]

[0006] A memory device according to one embodiment includes a memory cell array comprising a first memory cell, a second memory cell, a first word line connected to the first memory cell, a second word line connected to the second memory cell, bit lines connected to the first and second memory cells, a first connection electrode, a second connection electrode, and a third connection electrode; and a peripheral circuit comprising a first circuit, a second circuit, a third circuit connected to the first and second circuits for transmitting and receiving signals with an external device, a fourth connection electrode attached to the first connection electrode, a fifth connection electrode attached to the second connection electrode, and a sixth connection electrode attached to the third connection electrode, wherein the first circuit comprises a first semiconductor layer The device includes a first transistor and a second transistor, a trench, a first insulating layer, and a second insulating layer, wherein the first transistor is connected to the first word line via the first connecting electrode and the fourth connecting electrode, the second transistor is connected to the second word line via the second connecting electrode and the fifth connecting electrode, the trench is provided in the first semiconductor layer between the first transistor and the second transistor, the first insulating layer is formed in the trench, the second circuit is connected to the bit line via the third connecting electrode and the sixth connecting electrode, and the second insulating layer is in contact with the first insulating layer at the end of the first insulating layer furthest from the memory cell array. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram illustrating the configuration of a storage device according to one embodiment. [Figure 2] This diagram illustrates an equivalent circuit showing the configuration of a memory cell array in a storage device according to one embodiment. [Figure 3] This figure illustrates the circuit configuration of a sense amplifier module of a storage device according to one embodiment. [Figure 4] This is a diagram illustrating the circuit configuration of a low decoder in a storage device according to one embodiment. [Figure 5] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 6] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 7] This is a cross-sectional view showing an overview of a storage device related to a comparative example. [Figure 8] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 9] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 10] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 11] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 12] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 13] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 14] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 15] This is a cross-sectional view showing an overview of a storage device according to one embodiment. [Figure 16] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 17] A cross-section illustrating a method for manufacturing a storage device according to one embodiment. [Figure 18] This figure illustrates the circuit configuration of a sense amplifier module of a storage device according to one embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, the memory device according to this embodiment will be specifically described with reference to the drawings. In the following description, elements having substantially the same functions and configurations are denoted by the same reference numerals, and redundant descriptions will be given only when necessary. Each of the embodiments shown below exemplifies an apparatus and a method for embodying the technical idea of this embodiment. The technical idea of the embodiment is not limited to the following in terms of the material, shape, structure, arrangement, etc. of the components. The technical idea of the embodiment may be variously modified with respect to the claims.

[0009] [1. First Embodiment] The memory device according to the first embodiment will be described with reference to FIGS. 1 to 7.

[0010] [1-1. Overall Configuration of Memory Device] FIG. 1 is a block diagram of a memory device 10 according to an embodiment. As shown in FIG. 1, the memory device 10 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0011] The input / output circuit 310 controls the input / output of a signal DQ to an external device (not shown) such as a memory controller that controls the memory device 10. The signal DQ is, for example, an 8-bit signal of DQ0 to DQ7. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0012] The input circuit transmits data DAT such as write data WDT received from an external device to the data register 540, transmits an address ADD to the address register 340, and transmits a command CMD to the command register 350.

[0013] The output circuit transmits status information STT received from status register 330, data DAT such as read data RDT received from data register 540, and address ADD received from address register 340 to an external device.

[0014] The logic control circuit 320 receives signals from an external device, such as a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The logic control circuit 320 controls the input / output circuit 310 and the sequencer 360 according to the received signals.

[0015] The status register 330 temporarily holds status information STT during data write, read, and erase operations, and notifies an external device via the input / output circuit 310 whether the operation has been completed successfully.

[0016] The address register 340 temporarily holds the address ADD received from an external device via the input / output circuit 310. The address register 340 transfers the row address RA to the row decoder 520 and the column address CA to the column decoder 550.

[0017] The command register 350 temporarily stores the command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360.

[0018] The sequencer 360 controls the operation of the entire storage device 10. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550, etc., in response to the command CMD transferred from the command register 350, and performs write operations, read operations, erase operations, etc.

[0019] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360.

[0020] The voltage generation circuit 380 generates the voltages necessary for write, read, and erase operations in response to the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0021] The memory cell array 510 includes multiple blocks BLK (BLK0-BLKn), where n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines. For example, a block BLK is a data erasure unit. The memory cells are, for example, charge-holding transistors that store data non-volatilely by the charge they hold. By providing such memory cells, the storage device 10 functions as, for example, a NAND-type non-volatile memory.

[0022] The row decoder 520 decodes the row address RA. Based on the result of the decoding, the row decoder 520 selects one of several blocks BLK. The row decoder 520 applies the voltages required for the write, read, and erase operations to the block BLK.

[0023] During a read operation, the sense amplifier module 530 senses (detects) the data read from the memory cell array 510. During a read operation, the sense amplifier module 530 sends the read data RDT to the data register 540. During a write operation, the sense amplifier module 530 sends the write data WDT to the memory cell array 510.

[0024] As will be explained in more detail later, the data register 540 includes multiple latch circuits. The latch circuits hold the write data WDT and the read data RDT. For example, during a write operation, the data register 540 temporarily holds the write data WDT received from the input / output circuit 310 and transmits it to the sense amplifier module 530. During a read operation, the data register 540 temporarily holds the read data RDT received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0025] The column decoder 550 decodes the column address CA during write, read, and erase operations, and selects a latch circuit in the data register 540 according to the result of the decoding.

[0026] The group of circuits arranged around the memory cell array 510 is sometimes referred to as the peripheral circuit 590 (see Figure 5). The peripheral circuit 590 includes at least the input / output circuit 310, the row decoder 520, and the sense amplifier module 530. The status register 330, the address register 340, the command register 350, and the sequencer 360 may also be included in the peripheral circuit 590. Furthermore, the logic control circuit 320, the ready / busy circuit 370, and the voltage generation circuit 380 may also be included in the peripheral circuit 590.

[0027] Thus, the storage device 10 comprises a memory cell array 510 containing multiple memory cells and peripheral circuits 590 that drive the multiple memory cells.

[0028] [1-2. Memory cell array configuration] The circuit configuration of the memory cell array 510 will be explained using Figure 2. Figure 2 is a diagram illustrating an equivalent circuit showing the configuration of a memory cell array in a storage device according to one embodiment.

[0029] The memory cell array 510 comprises multiple block BLKs as described above. Each of the multiple block BLKs comprises multiple string units SUs. Each of the multiple string units SUs comprises multiple memory strings MSs. One end of each of the multiple memory strings MSs is connected to a peripheral circuit 590 such as a sense amplifier module 530 via a bit line BL. The other end of each of the multiple memory strings MSs is connected to the peripheral circuit 590 via a common source line SL.

[0030] The memory string MS is located between the bit line BL and the source line SL. The memory string MS comprises a drain selection transistor STD, multiple memory cells MC, and a source selection transistor STS, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain selection transistor STD and the source selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0031] A memory cell MC is, for example, a field-effect transistor (FET) that includes a charge storage layer in its gate isolation layer. The threshold voltage of the memory cell MC changes depending on the amount of charge held in the charge storage layer. By providing one or more threshold voltages, the memory cell MC can store one or more bits of data. Word lines WL are connected to the gate terminals of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are each connected in common to multiple (or all) memory string MS in a single block BLK.

[0032] The selection transistors (STD, STS) are, for example, field-effect transistors. Selection gate lines (SGD, SGS) are connected to the gate terminals of the selection transistors (STD, STS), respectively. The selection gate line SGD, connected to the drain selection transistor STD, is provided corresponding to the string unit SU and is commonly connected to multiple (or all) memory strings MS within a single string unit SU. The selection gate line SGS, connected to the source selection transistor STS, is commonly connected to multiple (or all) memory strings MS within a single block BLK.

[0033] One end of the word line WL and the selection gate lines (SGD, SGS) are each connected to a peripheral circuit 590 such as a low decoder 520.

[0034] [1-3. Sense Amp Module Configuration] The circuit configuration of the sense amplifier module 530 will be explained using Figure 3. Figure 3 is a diagram illustrating the circuit configuration of a sense amplifier module of a storage device according to one embodiment. As shown in Figure 3, the sense amplifier module 530 includes a sense amplifier circuit SA, a plurality of latch circuits DL, and a latch circuit XDL.

[0035] A sense amplifier circuit SA is provided for each bit line BL, which is one or more bit lines. For example, in a read operation, the sense amplifier circuit SA senses the data stored in the memory cell to be read, which has been read on the bit line BL corresponding to that memory cell, and determines whether the read data is "0" or "1".

[0036] Multiple latch circuits DL and latch circuits XDL are provided, each corresponding to multiple sense amplifier circuits SA. In other words, multiple latch circuits DL and latch circuits XDL are provided for each bit line BL, and multiple latch circuits DL are provided for one sense amplifier circuit SA. The number of latch circuits DL is designed, for example, based on the bit line BL of data that one memory cell MC can hold. Multiple latch circuits DL and latch circuits XDL temporarily hold the results determined by the sense amplifier circuit SA for the corresponding bit line BL.

[0037] Figure 3 shows a sense amplifier circuit SA within the sense amplifier module 530, and a plurality of latch circuits DL and latch circuits XDL provided in conjunction with the sense amplifier circuit SA. Multiple control signals supplied to the sense amplifier circuit SA, etc., are controlled by the sequencer 360. Although Figure 3 shows a typical configuration of latch circuit DL, it is possible to simplify the configuration of latch circuit DL by utilizing the characteristics resulting from the transistor structure of this embodiment (details will be described later).

[0038] As shown in Figure 3, the sense amplifier circuit SA includes transistors Tr31 to Tr38 and capacitor CAP. Transistor Tr31 is a P-channel MOS (Metal Oxide Semiconductor) transistor. Transistors Tr32 to Tr38 are N-channel MOS transistors.

[0039] The CMOS transistors, including the P-channel MOS transistors and N-channel MOS transistors described above, are transistors to which relatively low voltages are applied, and are sometimes called low-voltage (LV: Low Voltage, VLV: Very Low Voltage) MOS transistors. On the other hand, the high-voltage CMOS transistors, including the high-voltage P-channel MOS transistors and high-voltage N-channel MOS transistors described later, are transistors to which relatively high voltages are applied, and are sometimes called high-voltage (HV: High Voltage) MOS transistors.

[0040] The first terminal of transistor Tr31 is connected to a power line supplied with the power supply voltage Vdd, and the gate terminal of transistor Tr31 is connected to node INV. The first terminal of transistor Tr32 is connected to the second terminal of transistor Tr31, and the second terminal of transistor Tr32 is connected to node COM. The control signal BLX is input to the gate terminal of transistor Tr32. The first terminal of transistor Tr33 is connected to node COM, and the second terminal of transistor Tr33 is connected to the corresponding bit line BL via a high-voltage N-channel MOS transistor (not shown). The control signal BLC is input to the gate terminal of transistor Tr33.

[0041] The first terminal of transistor Tr34 is connected to node COM, the second terminal of transistor Tr34 is connected to node SRC, and the gate terminal of transistor Tr34 is connected to node INV.

[0042] The first terminal of transistor Tr35 is connected to the second terminal of transistor Tr31, and the second terminal of transistor Tr35 is connected to node SEN. The control signal HLL is input to the gate terminal of transistor Tr35. The first terminal of transistor Tr36 is connected to node SEN, and the second terminal of transistor Tr36 is connected to node COM. The control signal XXL is input to the gate terminal of transistor Tr36.

[0043] The first terminal of transistor Tr37 is supplied with the ground voltage VSS. The gate terminal of transistor Tr37 is connected to node SEN. The first terminal of transistor Tr38 is connected to the second terminal of transistor Tr37, and the second terminal of transistor Tr38 is connected to the bus LBUS. The gate terminal of transistor Tr38 is input with the control signal STB. The first terminal of capacitor CAP is connected to node SEN. The second terminal of capacitor CAP is input with the clock signal CLK.

[0044] The latch circuit DL comprises inverters IVa and IVb and transistors Tr41 and Tr42. As described above, the latch circuit DL is located in the data register 540. Transistors Tr41 and Tr42 are N-channel MOS transistors. Hereafter, transistors Tr41 and Tr42 included in the latch circuit DL may be simply referred to as transistor Tr.

[0045] Inverter IVa has an input terminal connected to node LAT and an output terminal connected to node INV. Inverter IVb has an input terminal connected to node INV and an output terminal connected to node LAT.

[0046] Transistor Tr41 has a configuration in which its first terminal is connected to node INV, its second terminal is connected to bus LBUS, and the control signal STI is input to its gate terminal. Transistor Tr42 has a configuration in which its first terminal is connected to node LAT, its second terminal is connected to bus LBUS, and the control signal STL is input to its gate terminal.

[0047] The latch circuit XDL has a configuration substantially similar to that of the latch circuit DL, for example, and is connected to the bus LBUS so that it can transmit and receive data with the sense amplifier circuit SA and the latch circuit DL. The latch circuit XDL is connected to the input / output circuit 310 described above and is used for data input and output between the sense amplifier circuit SA and the input / output circuit 310.

[0048] The latch circuit XDL is also used for the cache operation of the storage device 10. In other words, even if all the latch circuits DL corresponding to the sense amplifier circuits SA are in use, the storage device 10 can still receive data from the outside as long as there are available latch circuits XDL.

[0049] Next, the operation of the sense amplifier circuit SA with the above configuration will be briefly explained. When data is written to the memory cell MC, charge is injected into the memory cell MC to raise the threshold. In this case, node INV of the latch circuit DL is controlled to the "H" level (for example, "1" data is stored). As a result, transistor Tr34, whose gate terminal is connected to node INV, turns on, and the voltage supplied to node SRC (for example, 0V) is supplied to bit line BL. On the other hand, when charge is not injected into the memory cell MC and the threshold is not changed, node INV of the latch circuit DL is controlled to the "L" level (for example, "0" data is stored). As a result, transistor Tr31, whose gate terminal is connected to node INV, turns on, and a predetermined positive voltage (the voltage supplied to the power supply voltage Vdd) is supplied to bit line BL.

[0050] When a read operation is performed, node INV is controlled to the "L" level, and transistor Tr31 turns on. Furthermore, the bit line BL is precharged by transistor Tr31 via transistors Tr32 and Tr33. Transistor Tr35 also turns on, and node SEN is charged to a predetermined potential.

[0051] Subsequently, transistor Tr35 turns off, and the control signal XXL is controlled to the "H" level, causing transistor Tr36 to turn on. As a result, if the corresponding memory cell MC is on, the potential of node SEN decreases, and transistor Tr37 turns off. On the other hand, if the corresponding memory cell MC is off, the potential of node SEN is maintained at the "H" level, and transistor Tr37 turns on.

[0052] Next, the control signal STB turns on transistor Tr38, and the potential corresponding to the on / off state of transistor Tr37 is read to the bus LBUS and held in the latch circuit DL.

[0053] The circuit configuration of the sense amplifier circuit SA, the multiple latch circuits DL, and the latch circuit XDL shown in Figure 3 is just one example, and other configurations are also possible. In other words, the number and type of transistors Tr included in the sense amplifier circuit SA and the latch circuits DL and XDL may differ from the above configuration. For example, the sense amplifier circuit SA and the latch circuits DL and XDL may include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors, etc.

[0054] [1-4. Circuit configuration of the low decoder] The circuit configuration of the row decoder 520 will be explained with reference to Figure 4. Figure 4 is a diagram illustrating the circuit configuration of a row decoder in a storage device according to one embodiment. As shown in Figure 4, the row decoder 520 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23.

[0055] The address decoder 21 includes multiple block selection lines BLKSEL and multiple voltage selection lines VOLSEL. The address decoder 21 refers to the address data of the address register 340 included in the peripheral circuit 590 described above, for example, according to a control signal from the sequencer 360.

[0056] The address decoder 21 decodes the referenced address data and controls transistors Tr22 and Tr23 corresponding to the address data to be turned ON, while controlling the other transistors Tr22 and Tr23 to be turned OFF. Transistors Tr22 and Tr23 are transistors included in the block selection circuit 22 and voltage selection circuit 23, respectively, which will be described later.

[0057] The address decoder 21 controls, for example, the block selection line BLKSEL and voltage selection line VOLSEL corresponding to the address data to the "H" level, and the other block selection lines BLKSEL and voltage selection lines VOLSEL to the "L" level. Note that the above example is an example in which N-type transistors are used in the block selection circuit 22 and voltage selection circuit 23. If P-type transistors are used in the block selection circuit 22 and voltage selection circuit 23, the voltages applied to each wire will be reversed.

[0058] In the example shown in Figure 4, the address decoder 21 is provided with one block selection line BLKSEL for each block BLK included in the memory cell array 510. However, this configuration can be modified as appropriate. For example, one block selection line BLKSEL may be provided for two or more block BLKs.

[0059] The block selection circuit 22 comprises a plurality of block selection units 220. Each of the plurality of block selection units 220 corresponds to a block BLK of the memory cell array 510. Each of these plurality of block selection units 220 comprises a plurality of transistors Tr22 corresponding to a word line WL and a selection gate line (SGD, SGS). The transistors Tr22 are transistors that select the word line WL corresponding to the target memory cell MC.

[0060] Transistor Tr22 is a high-voltage N-channel MOS transistor and functions as a block drive transistor. The drain terminal of transistor Tr22 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS), respectively. The source terminal of transistor Tr22 is electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23, respectively. The voltage output terminal OTM is electrically connected to the voltage generation circuit 380. The gate terminal of transistor Tr22 is commonly connected to the corresponding block selection line BLKSEL.

[0061] Although not shown in the diagram, the block selection circuit 22 includes a plurality of transistors connected between the selection gate lines (SGD, SGS) and the ground voltage supply terminal. These plurality of transistors are high-voltage CMOS transistors. These plurality of transistors connect the selection gate lines (SGD, SGS) included in the unselected block BLK in the memory cell array 510 to the ground voltage supply terminal. The plurality of word lines WL included in the unselected block BLK are in a floating state.

[0062] The voltage selection circuit 23 includes a plurality of voltage selection units 230 corresponding to the word line WL and the selection gate lines (SGD, SGS). Each of these plurality of voltage selection units 230 includes a plurality of transistors Tr23.

[0063] Transistor Tr23 is a high-voltage N-channel MOS transistor that functions as a voltage selector transistor. The drain terminal of transistor Tr23 is electrically connected to the corresponding word line WL or selector gate line (SGD, SGS) via wiring WR and block selector circuit 22, respectively. The source terminal of transistor Tr23 is electrically connected to the corresponding voltage output terminal OTM. The gate terminal of transistor Tr23 is connected to the corresponding voltage selector line VOLSEL.

[0064] Thus, the raw decoder 520 belonging to the peripheral circuit 590 includes multiple transistors Tr22, Tr23, etc. However, the circuit configuration of the raw decoder 520 shown in Figure 4 is just one example, and the number and types of transistors Tr22, Tr23, etc. included in the raw decoder 520 are not limited to the above example.

[0065] [1-5. Cross-sectional structure of the storage device 10] The cross-sectional structure of the memory device 10 will be explained using Figure 5. Figure 5 is a cross-sectional view showing an overview of a memory device according to one embodiment. As shown in Figure 5, the main surface of the semiconductor layer 591 of the peripheral circuit 590 extends in the X and Y directions. The direction perpendicular to each of the X and Y directions is the Z direction. In the following explanation, the Z direction may be referred to as up or upward, and the opposite may be referred to as down or downward.

[0066] As shown in Figure 5, the memory cell array 510 and the peripheral circuit 590 are bonded to each other at bonding surface B. A connecting electrode P1 is provided on the bonding surface B side of the memory cell array 510. A connecting electrode P2 is provided on the bonding surface B side of the peripheral circuit 590. The circuit provided on the memory cell array 510 is electrically connected to the circuit provided on the peripheral circuit 590 via connecting electrodes P1 and P2.

[0067] In the following explanation, when referring to the connecting electrode P1 individually, they will be called connecting electrode P1-1, P1-2, and P1-3, respectively. When there is no need to distinguish between them, they will be referred to as connecting electrode P1, as above. Similarly, when referring to the connecting electrode P2 individually, they will be called connecting electrode P2-4, P2-5, and P2-6, respectively. When there is no need to distinguish between them, they will be referred to as connecting electrode P2, as above.

[0068] The connecting electrode P1-1 is sometimes called the "first connecting electrode." The connecting electrode P1-2 is sometimes called the "second connecting electrode." The connecting electrode P1-3 is sometimes called the "third connecting electrode." The connecting electrode P2-4 is sometimes called the "fourth connecting electrode." The connecting electrode P2-5 is sometimes called the "fifth connecting electrode." The connecting electrode P2-6 is sometimes called the "sixth connecting electrode." The connecting electrode P1-1 (first connecting electrode) is attached to the connecting electrode P2-4 (fourth connecting electrode). The connecting electrode P1-2 (second connecting electrode) is attached to the connecting electrode P2-5 (fifth connecting electrode). The connecting electrode P1-3 (third connecting electrode) is attached to the connecting electrode P2-6 (sixth connecting electrode).

[0069] The peripheral circuit 590 includes a semiconductor layer 591, a processing circuit 592, a via 593, wiring 594, an insulating layer 595, a contact 596, an insulating layer 597, and a connecting electrode P2.

[0070] For example, a silicon layer is used as the semiconductor layer 591. The semiconductor layer 591 is generally thinner than the silicon wafer used as a substrate. The thickness of the semiconductor layer 591 is 10 nm or more and 1 μm or less. The thickness of the semiconductor layer 591 may also be 50 nm or more and 1 μm or less, 100 nm or more and 500 nm or less, or 100 nm or more and 300 nm or less. For example, the thickness of the semiconductor layer 591 may be the same as the thickness of the active layer in a commonly used SOI (Silicon On Insulator) substrate.

[0071] A trench 598 is provided in the semiconductor layer 591. An insulating layer 599 is provided inside the trench 598. The lower surface of the semiconductor layer 591 is covered by the insulating layer 597. Since the trench 598 reaches the insulating layer 597, the lower surface of the insulating layer 599 is in contact with the insulating layer 597. For example, silicon oxide or silicon nitride can be used as the insulating layers 597 and 599. In this embodiment, since the trench 598 is formed from above, the side walls of the trench 598 have a tapered shape with the slope facing upward. In other words, the shape of the trench 598 in cross-section is such that the width of the trench 598 in the direction parallel to the bonding surface B increases as it approaches the memory cell array 510. In other words, the distance between opposing side walls in the trench 598 gradually increases from bottom to top.

[0072] The insulating layer 599 is sometimes referred to as the "first insulating layer." The insulating layer 597 is sometimes referred to as the "second insulating layer." The insulating layer 597 (second insulating layer) is in contact with the insulating layer 599 (first insulating layer) at its lower end (the end furthest from the memory cell array 510). Similarly, the insulating layer 597 (second insulating layer) is in contact with the semiconductor layer 591 (first semiconductor layer) at its lower surface (the surface furthest from the memory cell array 510).

[0073] The processing circuit 592 includes a transistor Tr that forms a channel with the semiconductor layer 591. For example, the processing circuit 592 includes an input / output circuit 310, a row decoder 520, and a sense amplifier module 530. The transistors Tr included in the row decoder 520 are sometimes referred to as the first transistor Tr1 and the second transistor Tr2. The transistor Tr included in the sense amplifier module 530 is sometimes referred to as the third transistor Tr3. The transistor Tr included in the input / output circuit 310 is sometimes referred to as the fourth transistor Tr4. When there is no need to distinguish between these transistors, they are simply referred to as transistors Tr. In addition to transistors, the processing circuit 592 also includes capacitive elements and resistive elements.

[0074] The semiconductor layer 591 corresponding to the first transistor Tr1 and the second transistor Tr2 is sometimes referred to as the "first semiconductor layer." The semiconductor layer 591 corresponding to the third transistor Tr3 is sometimes referred to as the "second semiconductor layer." The semiconductor layer 591 corresponding to the fourth transistor Tr4 is sometimes referred to as the "third semiconductor layer." The lower surfaces of the second and third semiconductor layers (the surfaces furthest from the memory cell array 510) are covered by an insulating layer 597 (second insulating layer). In this embodiment, the thickness of the first semiconductor layer, the thickness of the second semiconductor layer, and the thickness of the third semiconductor layer are the same.

[0075] The raw decoder 520 is sometimes referred to as the "first circuit." The sense amplifier module 530 is sometimes referred to as the "second circuit." The input / output circuit 310 is sometimes referred to as the "third circuit." In this case, the raw decoder 520 (first circuit) can be said to include the first transistor Tr1 and the second transistor Tr2. The sense amplifier module 530 (second circuit) can be said to include the third transistor Tr3. The sense amplifier module 530 (second circuit) can be said to include the fourth transistor Tr4.

[0076] The raw decoder 520 (first circuit), sense amplifier module 530 (second circuit), and input / output circuit 310 (third circuit) are controlled by the logic control circuit 320 and the sequencer 360. The logic control circuit 320 and the sequencer 360 are sometimes collectively referred to as the "control circuit."

[0077] The raw decoder 520 (first circuit), sense amplifier module 530 (second circuit), and input / output circuit 310 (third circuit) include an insulating layer 597, a trench 598, and an insulating layer 599. The trench 598 is provided between adjacent transistors. Specifically, the trench 598 is provided between the first transistor Tr1 and the second transistor Tr2. As described above, the input / output circuit 310 (third circuit) is connected to the raw decoder 520 (first circuit) and the sense amplifier module 530 (second circuit) and transmits and receives signals with external devices.

[0078] Contact 596 is an electrode extending in the Z direction, provided at an opening in the insulating layer 595. Contact 596 is in contact with the semiconductor layer 591 and is electrically connected to the source and drain terminals of the transistor Tr.

[0079] Via 593 is a wiring extending in the Z direction, provided in an opening in the insulating layer 595. Via 593 electrically connects contact 596 and wiring 594. In Figure 5, only one layer of wiring 594 is shown, but multiple layers of wiring 594 are provided in the Z direction via the insulating layer 595, and adjacent wiring 594 in the Z direction are connected by via 593. Similarly, adjacent wiring 594 and connecting electrode P2 in the Z direction are also connected by via 593.

[0080] At the end of peripheral circuit 590, there is an N sandwiched on both sides by P wells PW. + A diffusion region DF is provided. + The diffusion region DF is connected to the connection electrode P1 of the memory cell array 510 via vias 593, wiring 594, contacts 596, and connection electrode P2 provided in the semiconductor layer 591.

[0081] The memory cell array 510 comprises a memory string MS, a slit ST, a source layer SLL, insulating layers 511, 513, 515, 518, a contact C1, vias C2, C3, 512, 516, and wiring 514, 519.

[0082] A memory string MS comprises a pillar PL, multiple wirings 517, and multiple insulating layers 518. The pillar PL extends in the Z direction. Multiple pillar PLs are provided in the Z direction. In the example in Figure 5, two pillar PLs are stacked in the Z direction. The configuration including the stacked pillar PLs and multiple memory strings MS is called a string unit SU.

[0083] The pillar PL includes a core layer, a semiconductor layer, an insulating layer, and a charge storage layer. The core layer is the core of the pillar PL and is an insulator. A semiconductor layer is provided around the core layer, an insulating layer is provided around the semiconductor layer, a charge storage layer is provided around the insulating layer, an insulating layer is provided around the charge storage layer, and wiring 517 is provided around the insulating layer. The wiring 517 and insulating layer 518 are stacked alternately along the Z direction. Multiple wirings 517 are provided so as described above, each surrounding the insulating layer on the outside of the pillar PL. The portion where one of the multiple wirings 517 faces the pillar PL is a memory cell MC. In other words, the wiring 517 functions as the gate electrode of the memory cell MC.

[0084] Multiple wires 517 extend in the Y direction. Multiple wires 517 function as word lines WL and selection gate lines. Stepped sections STP are provided at the Y-direction ends of multiple wires 517. Due to the step shape of the stepped sections STP, each of the multiple wires 517 is sequentially exposed from the wire 517 below it and connected to wire 519 via via C0.

[0085] The semiconductor layer of the pillar PL is connected to via 516 and the source layer SLL. Via 516 is connected to wiring 519, which functions as a bit line BL. Bit line BL extends in the X direction. Bit line BL is connected to connecting electrode P1 via via 516.

[0086] Above the source layer SLL, vias 512, insulating layer 513, wiring 514, and insulating layer 515 are provided. N of the peripheral circuit 590 + Wiring 514, located at a position corresponding to the diffusion region DF, is connected to the connection electrode P2 of the peripheral circuit 590 via via C3, wiring 519, via 516, and connection electrode P1. The semiconductor layer 591 and the source layer SLL are electrically connected via via C1, wiring 519, via 516, and connection electrode P1.

[0087] Of the multiple wirings 517, the wiring 517 connected to the connecting electrode P1-1 via via C0 in the stepped portion STP is sometimes called the "first word wire W1". Similarly, the wiring 517 connected to the connecting electrode P1-2 via via C0 is sometimes called the "second word wire W2". A memory cell MC with the first word wire W1 as the gate electrode is sometimes called the "first memory cell MC1". A memory cell MC with the second word wire W2 as the gate electrode is sometimes called the "second memory cell MC2".

[0088] In this case, both the first and second memory cells are connected to a common bit line BL. The first transistor Tr1 is connected to the first word line W1 via connecting electrodes P1-1 (first connecting electrode) and P2-4 (fourth connecting electrode). The second transistor Tr2 is connected to the second word line W2 via connecting electrodes P1-2 (second connecting electrode) and P2-5 (fifth connecting electrode). The third transistor Tr3 is connected to the bit line BL via connecting electrodes P1-3 (third connecting electrode) and P2-6 (sixth connecting electrode).

[0089] Since the third transistor Tr3 is a transistor included in the sense amplifier module 530 (second circuit), it can also be said that the second circuit is connected to the bit line BL. For example, the third transistor Tr3 may be a transistor used in one of the multiple latch circuits DL and latch circuit XDL.

[0090] [1-6. Cross-sectional structure and some planar shapes of transistors (Tr)] The cross-sectional structure of transistor Tr will be explained using Figure 6. As shown in Figure 6, transistor Tr has a semiconductor layer 591, a gate insulating layer 581, a gate electrode 582, a sidewall 583, an insulating layer 584, a via 593, and a contact 596. An insulating layer 597 is provided below the semiconductor layer 591. A trench 598 is provided between adjacent transistors Tr. An insulating layer 599 is provided inside the trench 598. Figure 6 shows transistors 1 to 4, but only the top of the third transistor Tr3 is shown in plan view.

[0091] The gate electrode 582 is positioned opposite the semiconductor layer 591, which functions as the channel region of the transistor Tr. The gate insulating layer 581 is provided between the semiconductor layer 591 and the gate electrode 582. An insulating layer 584 is provided on top of the gate electrode 582, and vias 593 are provided in openings in the insulating layer 584. Vias 593 are connected to the gate electrode 582. When a voltage is applied to the gate electrode 582 via vias 593, carriers that constitute a current path are generated in the semiconductor layer 591 opposite the gate electrode 582. The sidewall 583 is provided so as to cover the side wall of the gate electrode 582. The contacts 596 function as the source electrode and drain electrode of the transistor Tr.

[0092] As described above, the thickness of the semiconductor layer 591 is between 10 nm and 1 μm, which is about the same as the thickness of the active layer in a typical SOI substrate. In other words, the transistors Tr in this embodiment (transistor 1 to transistor 4) have the same function as transistors formed on an SOI substrate. In the transistors Tr, an insulating layer 597 is provided on the underside of the semiconductor layer 591, and trenches 598 are provided between adjacent semiconductor layers 591 in the X and Y directions, so the semiconductor layer 591 is floating. Therefore, charge accumulates in the semiconductor layer 591. The threshold value of the transistor Tr changes depending on the amount of charge accumulated in the semiconductor layer 591, so the transistors Tr in this embodiment have both the function of a switching element and a memory element. In other words, the transistors Tr function as floating body cells.

[0093] Because transistor Tr possesses the above functions, the functions of the latch circuits DL and XDL shown in Figure 3 can be realized with a simplified circuit configuration (see Figure 18). The latch circuits DL and XDL shown in Figure 3 are composed of two transistors Tr41 and Tr42 and two inverters IVa and IVb. However, because transistor Tr5 shown in Figure 18 possesses both switching element and memory element functions, the two transistors and two inverters shown in Figure 3 can be replaced with two transistors Tr5 and Tr41 as shown in Figure 18. As shown in Figure 18, the first terminal of transistor Tr5 is connected to the first terminal of transistor Tr41. The second terminal of transistor Tr5 is connected to the ground voltage VSS (source line of the floating body cell). The gate terminal of transistor Tr5 is connected to the word line of the floating body cell. For example, transistor Tr5 is a transistor provided in the sense amplifier module 530 as shown in Figure 6, and is a transistor that functions as a floating body cell, similar to transistor Tr3. Therefore, transistors Tr5 and Tr41 possess the functions of a latch circuit DL. Note that transistor Tr41 may be a transistor that functions as a floating body cell, or it may not be a transistor that functions as a loading body cell.

[0094] Conventional memory devices used transistors had a problem where the operating speed of the transistor was reduced due to junction capacitance at the junction between the diffusion layer and the well. However, the transistor Tr in this embodiment has the same function as a transistor formed on an SOI substrate. Therefore, in the transistor Tr in this embodiment, the effect of junction capacitance between the diffusion layer and the well is suppressed, enabling high-speed operation and low power consumption of the transistor Tr. Furthermore, in the transistor Tr in this embodiment, junction leakage between the diffusion layer and the well does not occur, so the power consumption of the transistor Tr can be reduced, mainly in the standby state.

[0095] As shown in Figure 6, the Y-width of the trench 598 provided between the transistors Tr aligned in the Y direction is 200 nm or less. The Y-width of the trench 598 may be 150 nm or less, or 100 nm or less. The Z-depth of the trench 598 is the same as the thickness of the semiconductor layer 591. For example, if the thickness of the semiconductor layer 591 is 300 nm or less, the depth of the trench 598 is also 300 nm or less.

[0096] Furthermore, as shown in the upper plan view of the third transistor Tr3 in Figure 6, the trench 598 is provided so as to surround the transistor Tr. In other words, the semiconductor layers 591 of adjacent transistors Tr in the X and Y directions are insulated by the insulating layer 599 provided in the trench 598 and the insulating layer 597 provided on the lower surface of the semiconductor layer 591. Therefore, the width of the trench 598 in this embodiment can be made smaller than the width of a conventional trench.

[0097] For reference, Figure 7 shows a cross-sectional view of a memory device relating to a comparative example. In conventional memory devices, since transistors are formed on a silicon wafer, the semiconductor layers 591 of adjacent transistors are continuous below the trench 598. Therefore, for example, in a row decoder 520 that supplies voltage to a word line, a voltage of 20V or more is applied, so in order to electrically isolate the semiconductor layers 591 of adjacent transistors, the width of the trench 598 needed to be 600nm or more. Note that even in circuits such as input / output circuits 310 or sense amplifier modules 530 where the voltage applied to the circuit is 5V or less, or 2V or less, the width of the trench 598 needs to be 200nm or more in order to electrically isolate the semiconductor layers 591 of adjacent transistors.

[0098] For example, if the storage device 10 according to this embodiment is a flash memory, a voltage of 20V to 30V is applied to the first word line W1 and the second word line W2, respectively, in order for the control circuit to drive the memory cell MC. In conventional storage devices, the width of the trench 598 had to be 600nm or more in order to withstand the high voltage supplied during operation. As a result, there were limitations on the miniaturization of the circuit.

[0099] On the other hand, in the memory device 10 according to this embodiment, as shown in Figure 6, the semiconductor layers 591 of adjacent transistors Tr in the Y direction are separated by trenches 598 (insulating layer 599) provided between them and insulating layer 597 provided on the lower surface of the semiconductor layer 591. Therefore, in the memory device 10, as described above, the width of the trenches 598 in the X and Y directions can be made smaller compared to conventional memory devices. As a result, the size of circuits such as the input / output circuit 310, the row decoder 520, and the sense amplifier module 530 can be reduced. In particular, in the row decoder 520, which requires a transistor Tr for each word line, the size of the circuit can be significantly reduced by reducing the width of the trenches 598.

[0100] [1-7. Method for manufacturing the storage device 10] A method for manufacturing the memory device 10 according to this embodiment will now be described. The memory device 10 is obtained by forming transistors Tr and trenches 598 on a semiconductor layer 591 (for example, a silicon wafer) that is thicker than the depth of the trenches 598, similar to Figure 7, and forming an insulating layer 599 inside the trenches 598. Subsequently, the semiconductor layer 591 is thinned from the bottom side to obtain the memory device 10 shown in Figure 6. Specifically, transistors Tr and the like are formed on a silicon wafer, and with trenches 598 formed near the top surface of the silicon wafer between adjacent transistors Tr, the semiconductor layer 591 is thinned from the bottom side to form the memory device 10 shown in Figure 6. Note that the insulating layer 599 may be formed after the formation of the transistors Tr, or it may be formed during the process of forming the transistors Tr.

[0101] As described above, since the trench 598 is formed before the semiconductor layer 591 (silicon wafer) is thinned, the side walls of the trench 598 have a tapered shape with the slope facing upwards. In other words, the distance between opposing side walls in the trench 598 gradually increases from bottom to top.

[0102] As described above, the memory device 10 according to this embodiment allows for a reduction in the width of the trench 598, thereby reducing the circuit size. Furthermore, in the memory device 10 according to this embodiment, since there is no junction between the diffusion layer and the well, it becomes possible to increase the speed and power consumption of the transistor Tr.

[0103] [2. Second Embodiment] The storage device according to the second embodiment will be described using Figure 8. Figure 8 is a cross-sectional view showing an overview of the storage device according to the first embodiment. The storage device 10 shown in Figure 8 is similar to the storage device 10 shown in Figure 6, but differs from the storage device 10 shown in Figure 6 in that the semiconductor layers 591-2 and 591-3 in the input / output circuit 310 and sense amplifier module 530 are thicker than the semiconductor layer 591-1 in the low decoder 520.

[0104] [2-1. Cross-sectional structure of a transistor (Tr)] In Figure 8, the configuration of the raw decoder 520 is the same as that of the raw decoder 520 shown in Figure 6, so the explanation is omitted. However, in Figure 8, the semiconductor layer of the raw decoder 520 is labeled as semiconductor layer 591-1.

[0105] The semiconductor layer of transistor Tr3 provided in sense amplifier module 530 is semiconductor layer 591-2. An insulating layer 573 is provided on the underside of semiconductor layer 591-2. A trench 575 is provided near the top surface of semiconductor layer 591-2. The semiconductor layer of transistor Tr4 provided in input / output circuit 310 is semiconductor layer 591-3. An insulating layer 574 is provided on the underside of semiconductor layer 591-3. A trench 576 is provided near the top surface of semiconductor layer 591-3.

[0106] The thicknesses of semiconductor layer 591-2 and semiconductor layer 591-3 are both greater than the thickness of semiconductor layer 591-1. Insulating layers 573 and 574 are made of the same material and have the same film thickness as insulating layer 597. Insulating layers 573, 574, and 597 are formed by the same process. In the Y direction, the widths of trenches 575 and 576 are greater than the width of trench 598. The relationship between the thicknesses of each semiconductor layer is not limited to the above relationship. The thicknesses of at least some of the semiconductor layers, such as semiconductor layer 591-1, semiconductor layer 591-2, and semiconductor layer 591-3, may be smaller than the thicknesses of the other semiconductor layers. In the configuration of the first embodiment described above, it can be said that the thicknesses of semiconductor layer 591-1, semiconductor layer 591-2, and semiconductor layer 591-3 are the same.

[0107] The insulating layer 573 is sometimes referred to as the "third insulating layer." The semiconductor layer 591-2 is sometimes referred to as the "second semiconductor layer." In this case, the sense amplifier module 530 (second circuit) can be said to include the third transistor Tr3 and the insulating layer 573 (third insulating layer). The semiconductor layer 591-2 (second semiconductor layer) can be said to function as the channel for the third transistor Tr3. The underside of the semiconductor layer 591-2 (second semiconductor layer) (the side furthest from the memory cell array 510) can be said to be covered by the insulating layer 573 (third insulating layer). Referring to Figures 5 and 8, the third transistor Tr3 can be said to be connected to the bit line BL via the connecting electrodes P1-3 (third connecting electrodes) and P2-6 (sixth connecting electrodes).

[0108] The insulating layer 574 is sometimes referred to as the "fourth insulating layer." The semiconductor layer 591-3 is sometimes referred to as the "third semiconductor layer." In this case, the input / output circuit 310 (third circuit) can be said to include the fourth transistor Tr4 and the insulating layer 574 (fourth insulating layer). The semiconductor layer 591-3 (third semiconductor layer) can be said to function as the channel for the fourth transistor Tr4. The underside of the semiconductor layer 591-3 (third semiconductor layer) (the side furthest from the memory cell array 510) can be said to be covered by the insulating layer 574 (fourth insulating layer).

[0109] [2-2. Method for manufacturing the storage device 10] A method for manufacturing the memory device 10 according to this embodiment will now be described. Similar to the memory device 10 according to the first embodiment, the memory device 10 according to this embodiment is formed by thinning the semiconductor layer 591 from the bottom side. However, when the semiconductor layer 591 is thinned, a mask such as a resist is formed on the bottom surfaces of the semiconductor layers 591-2 and 591-3 in the regions where the input / output circuit 310 and sense amplifier module 530 are formed, so that the bottom surface of the semiconductor layer 591-1 in the region where the low decoder 520 is formed is exposed. In this state, by performing the thinning, the semiconductor layer 591-1 in the region where the low decoder 520 is formed can be selectively thinned.

[0110] In this embodiment, a configuration in which the semiconductor layer 591-1 corresponding to the row decoder 520 is thinned is illustrated, but the configuration is not limited to this. For example, the semiconductor layer 591-1 in the region where at least one of the input / output circuit 310, the row decoder 520, and the sense amplifier module 530 is formed may be selectively thinned. That is, the semiconductor layer 591-1 corresponding to the input / output circuit 310 may be thinned, the semiconductor layer 591-1 corresponding to the sense amplifier module 530 may be thinned, or two or more of the semiconductor layers 591-1 corresponding to the input / output circuit 310, the row decoder 520, and the sense amplifier module 530 may be thinned.

[0111] As described above, the storage device 10 according to this embodiment can obtain the same effects as the storage device 10 according to the first embodiment. Furthermore, the thickness of the semiconductor layer 591 can be adjusted as needed.

[0112] [3. Third Embodiment] A storage device according to the third embodiment will be described using Figures 9 to 11. Figure 9 is a cross-sectional view showing an overview of a storage device according to one embodiment. Figures 10 and 11 are cross-sectional views illustrating a method for manufacturing a storage device according to one embodiment. The storage device 10 shown in Figure 9 is similar to the storage device 10 shown in Figure 6, but differs from the storage device 10 shown in Figure 6 in that an etching stopper layer 600 is provided between the semiconductor layer 591 and the insulating layer 597.

[0113] [3-1. Cross-sectional structure of a transistor (Tr)] In Figure 9, the same configuration as in Figure 6 will not be explained, and the differences from Figure 6 will be explained in detail. As shown in Figure 9, the lower surface of the semiconductor layer 591 is covered by the etching stopper layer 600. The trench 598 is provided so as to reach the etching stopper layer 600. In other words, the lower surface of the insulating layer 599 provided inside the trench 598 is in contact with the etching stopper layer 600.

[0114] As the etching stopper layer 600, a material that functions as a stopper for the process of thinning the semiconductor layer 591 is used. For example, when the semiconductor layer 591 is formed by thinning a silicon wafer by CMP (Chemical Mechanical Polishing) and then further thinning it by wet etching, the etching rate of the semiconductor layer 591 should be sufficiently larger than the etching rate of the etching stopper layer 600 for the etchant used in the wet etching.

[0115] For example, a silicon-germanium layer is used as the etching stopper layer 600. The thickness of the silicon-germanium layer is, for example, 10 nm to 50 nm. When a silicon layer is used as the semiconductor layer 591 and a silicon-germanium layer is used as the etching stopper layer 600, the semiconductor layer 591 and the etching stopper layer 600 are sometimes collectively referred to as the "semiconductor layer." This "semiconductor layer" can also be said to be composed of multiple different semiconductor layers. In addition, since the etching stopper layer 600 also functions as a stopper when forming the trench 598, the bottom of the trench 598 is located in the etching stopper layer 600. A silicon oxide layer may also be used as the etching stopper layer 600.

[0116] [3-2. Method for manufacturing the storage device 10] A method for manufacturing the memory device 10 according to this embodiment will be described with reference to Figures 10 and 11. As shown in Figure 10, a substrate is prepared on which an etching stopper layer 600 and a semiconductor layer 591 are formed on a silicon wafer 610. A transistor Tr is formed on the substrate in the same manner as in the first embodiment, a trench 598 is formed above the semiconductor layer 591, and an insulating layer 599 is formed inside the trench 598.

[0117] Next, as shown in Figure 11, the silicon wafer 610 is thinned from its underside. As described above, this thinning process includes at least two steps. The first step is mechanical thinning. The second step is chemical thinning. For this chemical processing method, the etching rate of the silicon wafer 610 is sufficiently larger than the etching rate of the etching stopper layer 600. As described above, CMP is used for mechanical thinning. As described above, wet etching is used for chemical processing. However, methods other than those described above may be used for mechanical and chemical processing.

[0118] As described above, the storage device 10 according to this embodiment can obtain the same effects as the storage device 10 according to the first embodiment. Furthermore, the etching stopper layer 600 can increase the process margin in thinning the semiconductor layer 591.

[0119] [4. Fourth Embodiment] A storage device according to the fourth embodiment will be described using Figures 12 to 14. Figure 12 is a cross-sectional view showing an overview of a storage device according to one embodiment. Figures 13 and 14 are cross-sectional views illustrating a method for manufacturing a storage device according to one embodiment. The storage device 10 shown in Figure 12 is similar to the storage device 10 shown in Figure 6, but differs from the storage device 10 shown in Figure 6 in that the shape of the side wall of the trench 598 is different.

[0120] [4-1. Cross-sectional structure of a transistor (Tr)] In Figure 12, the same configuration as in Figure 6 will not be explained, and the differences from Figure 6 will be explained in detail. As shown in Figure 12, the side walls of the trench 598 in this embodiment have a tapered shape with the slope facing downwards. In other words, the distance between opposing side walls in the trench 598 gradually increases from top to bottom. Referring to Figure 5, the shape of the trench 598 in cross-sectional view is such that the width of the trench 598 in the direction parallel to the bonding surface B decreases as it approaches the memory cell array 510.

[0121] [4-2. Method for manufacturing the storage device 10] A method for manufacturing the memory device 10 according to this embodiment will be described with reference to Figures 13 and 14. In the first to third embodiments, a trench 598 was formed from above the semiconductor layer 591 before the semiconductor layer 591 was thinned. However, in this embodiment, as shown in Figure 13, the trench 598 is formed from below the semiconductor layer 591 using a mask 630 after the semiconductor layer 591 has been thinned, as shown in Figure 14. By forming the trench 598 from below the semiconductor layer 591 in this way, a trench 598 having the shape described above can be formed. Subsequently, an insulating layer 599 is formed inside the trench 598.

[0122] As described above, the storage device 10 according to this embodiment can obtain the same effects as the storage device 10 according to the first embodiment.

[0123] [5. Fifth Embodiment] The storage device according to the fifth embodiment will be described using Figures 15 to 17. Figure 15 is a cross-sectional view showing an overview of the storage device according to one embodiment. Figures 16 and 17 are cross-sectional views illustrating the manufacturing method of the storage device according to one embodiment. The storage device 10 shown in Figure 15 is similar to the storage device 10 shown in Figure 6, but differs from the storage device 10 shown in Figure 6 in that the shape of the trench 598 is different.

[0124] [5-1. Cross-sectional structure of a transistor (Tr)] In Figure 15, the same configuration as in Figure 6 will not be explained, and the differences from Figure 6 will be explained in detail. As shown in Figure 15, the trench 598 of this embodiment is composed of a first trench 598-1 and a second trench 598-2. An insulating layer 599-1 is provided inside the first trench 598-1, and an insulating layer 599-2 is provided inside the second trench 598-2. Referring to Figures 5 and 15, the second trench 598-2 is located further from the memory cell array 510 than the first trench 598-1. The first trench 598-1 has a tapered shape with the bevels of its side walls facing upwards. In other words, the distance between opposing side walls in the first trench 598-1 gradually increases from bottom to top. The second trench 598-2 has a tapered shape with the bevels of its side walls facing downwards. In other words, in the second trench 598-2, the distance between opposing side walls gradually decreases from bottom to top.

[0125] Figure 15 illustrates a configuration in which the width of the bottom (lower end) of the first trench 598-1 is greater than the width of the bottom (upper end) of the second trench 598-2, but the configuration is not limited to this. For example, the width of the bottom of the first trench 598-1 may be less than the width of the bottom of the second trench 598-2, or the width of the bottom of the first trench 598-1 may be the same as the width of the bottom of the second trench 598-2.

[0126] [5-2. Method for manufacturing the storage device 10] A method for manufacturing the memory device 10 according to this embodiment will be described with reference to Figures 16 and 17. First, as shown in Figure 16, a first trench 598-1 is formed from above the semiconductor layer 591 before thinning the semiconductor layer 591, and an insulating layer 599-1 is formed inside the first trench 598-1. Then, the thinning of the semiconductor layer 591 is stopped before the lower surface of the semiconductor layer 591 reaches the first trench 598-1. After stopping the thinning, a second trench 598-2 is formed from below the semiconductor layer 591, as shown in Figure 17, and an insulating layer 599-2 is formed inside the second trench 598-2. In this way, by forming the first trench 598-1 from above the semiconductor layer 591 and forming the second trench 598-2 from below the semiconductor layer 591 using a mask 630, a trench 598 having the shape described above can be formed.

[0127] As described above, the storage device 10 according to this embodiment can obtain the same effects as the storage device 10 according to the first embodiment.

[0128] Although the present invention has been described above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, a device based on the storage device of this embodiment, to which a person skilled in the art has added, deleted, or modified components as appropriate, is also included in the scope of the present invention as long as it retains the gist of the present invention. Furthermore, the embodiments described above can be combined as appropriate as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even if not explicitly described.

[0129] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0130] 10: Memory device, 21: Address decoder, 22: Block selection circuit, 23: Voltage selection circuit, 220: Block selection unit, 230: Voltage selection unit, 310: Input / output circuit, 320: Logic control circuit, 330: Status register, 340: Address register, 350: Command register, 360: Sequencer, 370: Ready / busy circuit, 380: Voltage generation circuit, 510: Memory cell array, 511, 513, 515, 518: Insulation layer, 512, 516: Via, 514, 517, 519: Wiring, 520: Row decoder, 530: Sense amplifier module, 540: Data register, 550: Column decoder, 573, 574, 584, 595, 597, 599: Insulation layer, 575, 576: Trench, 581: Gate insulating layer, 582: Gate electrode, 583: Sidewall, 590: Peripheral circuitry, 591: Semiconductor layer, 592: Processing circuitry, 593: Via, 594: Wiring, 596: Contact, 598: Trench, 600: Etching stopper layer, 610: Silicon wafer, 630: Mask

Claims

1. A memory cell array comprising a first memory cell, a second memory cell, a first word line connected to the first memory cell, a second word line connected to the second memory cell, bit lines connected to the first and second memory cells, a first connection electrode, a second connection electrode, and a third connection electrode, and The peripheral circuit includes a first circuit, a second circuit, a third circuit connected to the first and second circuits for transmitting and receiving signals with external devices, a fourth connection electrode attached to the first connection electrode, a fifth connection electrode attached to the second connection electrode, and a sixth connection electrode attached to the third connection electrode. The first circuit is, A first transistor and a second transistor, each including a first semiconductor layer, Trench coat, The first insulating layer and Including a second insulating layer, The first transistor is connected to the first word line via the first connecting electrode and the fourth connecting electrode, The second transistor is connected to the second word line via the second connecting electrode and the fifth connecting electrode, The trench is provided in the first semiconductor layer between the first transistor and the second transistor. The first insulating layer is formed in the trench, The second circuit is connected to the bit line via the third connecting electrode and the sixth connecting electrode, A storage device wherein the second insulating layer is in contact with the first insulating layer at the end of the first insulating layer that is farther from the memory cell array.

2. The storage device according to claim 1, wherein the second insulating layer is in contact with the first semiconductor layer on the side of the first semiconductor layer that is farther from the memory cell array.

3. The first transistor and the second transistor are aligned in the first direction, The storage device according to claim 1, wherein the width of the trench in the first direction is 200 nm or less.

4. The storage device according to claim 3, wherein the depth of the trench is 300 nm or less.

5. The aforementioned second circuit includes a third transistor, The third transistor is connected to the bit line via the third connecting electrode and the sixth connecting electrode, The aforementioned third transistor includes a second semiconductor layer that functions as a channel, The memory device according to claim 1, wherein the side of the second semiconductor layer furthest from the memory cell array is covered by the second insulating layer.

6. The second circuit is, A sense amplifier circuit that determines the data stored in the memory cell to be read, The system includes a latch circuit that holds the result determined by the sense amplifier circuit, The storage device according to claim 5, wherein the latch circuit is comprised of the third transistor.

7. The storage device according to claim 6, wherein the third transistor is a floating body cell.

8. The third circuit includes a fourth transistor, The aforementioned fourth transistor includes a third semiconductor layer that functions as a channel, The memory device according to claim 1, wherein the side of the third semiconductor layer furthest from the memory cell array is covered by the second insulating layer.

9. The aforementioned second circuit includes a third transistor, The third transistor is connected to the bit line via the third connecting electrode and the sixth connecting electrode, The aforementioned third transistor includes a second semiconductor layer that functions as a channel, The side of the second semiconductor layer furthest from the memory cell array is covered by the second insulating layer. The third circuit includes a fourth transistor, The aforementioned fourth transistor includes a third semiconductor layer that functions as a channel, The side of the third semiconductor layer furthest from the memory cell array is covered by the second insulating layer. The memory device according to claim 1, wherein the thickness of the first semiconductor layer, the thickness of the second semiconductor layer, and the thickness of the third semiconductor layer are the same.

10. The second circuit includes a third transistor and a third insulating layer, The third transistor is connected to the bit line via the third connecting electrode and the sixth connecting electrode, The aforementioned third transistor includes a second semiconductor layer that functions as a channel, The side of the second semiconductor layer furthest from the memory cell array is covered by the third insulating layer. The third circuit includes a fourth transistor and a fourth insulating layer, The aforementioned fourth transistor includes a third semiconductor layer that functions as a channel, The side of the third semiconductor layer furthest from the memory cell array is covered by the fourth insulating layer. The memory device according to claim 1, wherein the thickness of at least a portion of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is smaller than the thickness of the other semiconductor layers.

11. The second circuit includes a third transistor and a third insulating layer, The third transistor is connected to the bit line via the third connecting electrode and the sixth connecting electrode, The aforementioned third transistor includes a second semiconductor layer that functions as a channel, The side of the second semiconductor layer furthest from the memory cell array is covered by the third insulating layer. The third circuit includes a fourth transistor and a fourth insulating layer, The aforementioned fourth transistor includes a third semiconductor layer that functions as a channel, The side of the third semiconductor layer furthest from the memory cell array is covered by the fourth insulating layer. The memory device according to claim 1, wherein the thickness of the first semiconductor layer is the same as the thickness of the second semiconductor layer and the thickness of the third semiconductor layer.

12. The first semiconductor layer is composed of multiple different semiconductor layers, The memory device according to claim 1, wherein the bottom of the trench is located in one of the semiconductor layers of the plurality of semiconductor layers.

13. The memory device according to claim 12, wherein the first semiconductor layer is a silicon layer on the side closer to the memory cell array and a silicon-germanium layer on the side farther from the memory cell array.

14. The memory device according to claim 12, wherein the first semiconductor layer is a silicon layer on the side closer to the memory cell array and a silicon oxide layer on the side farther from the memory cell array.

15. The storage device according to any one of claims 1 to 14, wherein the shape of the trench is such that the width of the trench in the direction parallel to the bonding surface between the memory cell array and the peripheral circuit increases as it approaches the memory cell array.

16. The storage device according to any one of claims 1 to 14, wherein the shape of the trench is such that the width of the trench in the direction parallel to the main surface of the peripheral circuit decreases as it approaches the memory cell array.

17. The trench includes a first trench and a second trench located further from the memory cell array than the first trench. The shape of the first trench is such that the width of the trench in the direction parallel to the main surface of the peripheral circuit increases as it approaches the memory cell array. The storage device according to any one of claims 1 to 14, wherein the shape of the second trench is such that the width of the trench in the direction parallel to the main surface of the peripheral circuit decreases as it approaches the memory cell array.

18. The system further includes a control circuit that controls the first circuit, the second circuit, and the third circuit, The storage device according to any one of claims 1 to 14, wherein the control circuit applies a voltage of 20V or more and 30V or less to the first word line and the second word line when driving the first memory cell and the second memory cell.

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