Semiconductor testing equipment

Abstract

To provide semiconductor testing equipment that improves the testing time of semiconductor devices. [Solution] A semiconductor test apparatus according to one embodiment includes a plurality of signal generators that apply a test signal to each of a plurality of IFs of a device under test, and a signal generation controller that compiles a signal including basic timing information and pattern information for the test item to be measured into a data signal, and adjusts the timing of the test signal by setting timing information based on the data signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor test apparatuses.

Background Art

[0002] There are semiconductor devices having multiple IFs in order to achieve high-speed performance. A semiconductor test apparatus for testing whether such a semiconductor device meets a predetermined design specification includes multiple signal generators in order to test multiple IFs simultaneously. In order to perform a test for measuring the timing regulation between multiple IFs, it is necessary to synchronize the time among the multiple signal generators in the semiconductor test apparatus. When performing this synchronization, the device that is ahead among the multiple signal generators is made to wait until the device that is the slowest has completed signal generation, thereby achieving synchronization.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided is a semiconductor test apparatus with improved test time for semiconductor devices.

Means for Solving the Problems

[0005] A semiconductor test apparatus according to one embodiment includes a plurality of signal generators that apply test signals to each of a plurality of interfaces of the device under test, and a signal generation controller that compiles a signal including basic timing information and pattern information for the test item to be measured into a data signal, and adjusts the timing of the test signal by setting timing information based on the data signal. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic diagram of a semiconductor testing apparatus according to one embodiment of the present disclosure. [Figure 2] This is a schematic diagram of a signal generator according to one embodiment of the present disclosure. [Figure 3] This is a flowchart illustrating the execution of a test using a semiconductor test apparatus according to one embodiment of this disclosure. [Figure 4] This is a timing chart illustrating signal generation by a semiconductor test apparatus according to one embodiment of the present disclosure. [Figure 5] This is a timing chart illustrating signal generation by a semiconductor test apparatus according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0007] The semiconductor testing apparatus according to this embodiment will be described in detail below with reference to the drawings. In the following description, elements having substantially the same function and configuration are denoted by the same reference numeral or by a reference numeral followed by an alphabet letter, and will be described redundantly only when necessary. The embodiments shown below illustrate apparatuses and methods for realizing the technical idea of ​​this embodiment. Various modifications can be made to the embodiments without departing from the spirit of the invention. These embodiments and their modifications are included within the scope of the invention and its equivalents as described in the claims.

[0008] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, elements having the same function as those described in previously shown drawings are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] In this specification, expressions such as "α includes A, B, or C" do not exclude cases where α includes multiple combinations of A, B, and C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0010] The following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0011] <First Embodiment> [Structure of semiconductor testing equipment] Figure 1 is a schematic diagram of the semiconductor testing apparatus according to this embodiment.

[0012] The semiconductor test apparatus 1 according to this embodiment includes a signal generator 2 and a signal generation controller 3. The signal generator 2 and the signal generation controller 3 are connected by a bus, and the signal generator 2 and the signal generation controller 3 constitute a waveform generator. The waveform generator is a device that generates and outputs arbitrary waveforms and can be applied to various devices; here, we will describe its application to a semiconductor test apparatus. The semiconductor test apparatus 1 includes a waveform generator to perform pass / fail judgment on the memory cells of the DUT4 (Device Under Test) by sequentially generating patterns from read or write data signals and address signals based on a certain algorithm.

[0013] The signal generation controller 3 is a device that controls the signal generator 2, controlling it to output a desired waveform. The signal generation controller 3 controls the signal generator 2 by outputting control data via a bus. The DUT 4 is the device to which the waveform is input and is pin-connected to the signal generator 2.

[0014] The signal generator 2 is a circuit board equipped with various components for generating waveforms. The semiconductor test apparatus 1 includes a plurality of signal generators 2. In FIG. 1, eight signal generators 2 are arranged, but it is not limited thereto. Each signal generator 2 is equipped with various components for generating and outputting waveforms. The plurality of signal generators 2 can generate different waveforms.

[0015] FIG. 2 shows a schematic configuration of the signal generator 2. As shown in FIG. 2, the signal generator 2 includes a sequence control unit 21, an instruction memory 22, an address generation unit 23, an address press scrambler unit 24, a data generation unit 25, a DUT control signal generation unit 26, a timing control unit 27, and a timer 28.

[0016] The sequence control unit 21 is connected to the signal generation controller 3 and controls from the start to the end of the test according to the description of the test pattern. A timer 28 for time management is connected to the sequence control unit 21.

[0017] The instruction memory 22 stores various control codes for controlling the address calculation instruction of the test pattern, the data calculation instruction, the real-time timing switching in the test pattern, the switching of the pin selector, and the generation of strobe and I / O switching patterns.

[0018] The address generation unit 23 outputs X and Y addresses that are the addresses of the device according to the address calculation instruction of the test pattern. The address press scrambler unit 24 converts the consecutive addresses generated from the address calculation into the addresses of spare cells.

[0019] The data generation unit 25 outputs write data and comparison data for the device according to the data calculation instruction of the test pattern.

[0020] The DUT control signal generation unit 26 generates a swap cycle (SWAP) signal for switching patterns within one cycle.

[0021] The timing control unit 27 outputs a rate signal serving as a reference timing as pulses. The rate signal defines the reference timing for waveform output and outputs pulses at a very short time period. By changing the edge by delaying the predetermined timing with the rate signal as a reference, a waveform is output.

[0022] FIG. 3 is a flowchart for explaining the execution of a device test by the semiconductor test apparatus according to the present embodiment. FIGS. 4 and 5 are timing charts for explaining signal generation by the semiconductor test apparatus according to the present embodiment. The signal generation controller 3 is a control CPU, and a main program is loaded onto a memory, and based on this, a device test is executed.

[0023] As shown in FIG. 3, the signal generation controller 3 first sets basic timing information for test items (contents) to be measured in the basic timing setting S1. The basic timing information may be timing information determined by a standard specification.

[0024] In signal creation S2, a signal of pattern information is created based on the basic timing information set in the basic timing setting S1. The pattern information may be pattern information determined by a standard specification.

[0025] In compilation S3, the source code signal including the basic timing information and the pattern information created in signal creation S2 is compiled into a data signal output to the signal generator 2.

[0026] In timing setting S4, timing information is set based on the data signal compiled in compilation S3. The timing information may be arbitrary timing information, for example, timing information for synchronization with a data signal transmitted to another signal generator 2.

[0027] In execution S5, the timing information set in timing setting S4 and the data signal compiled in compilation S3 are sent to the signal generator 2. The signal generator 2 generates a waveform from the input timing information and data signal and outputs it to DUT4.

[0028] Figure 4 is a timing chart illustrating the signals input to IF1 and IF2 of DUT4. As shown in Figure 4, waveforms (gray) based on different data signals are input to IF1 and IF2 of DUT4. The signal input to IF1 also includes a dummy time (white) set by timing information. In Figure 4, a dummy time is added between arbitration time 1 and arbitration time 2 of IF1 to match the time until synchronization with IF2 at arbitration point 2. However, this is not limited to this, and if the time difference between IF1 and IF2 is short, for example, a dummy time may be added to both the waveforms of IF1 and IF2. The waveforms (gray) based on the data signals input to IF1 and IF2 can be synchronized by adjusting the timing by adding a dummy time (white) set by timing information.

[0029] As shown in Figure 3, the data signals compiled in Compilation S3 can be reused by repeating Timing Setting S4 and Execution S5 until the device test measurement is completed. Each Timing Setting S4 can sequentially adjust the timing by setting the timing information each time based on the compiled data signals, even if the content of the signal changes.

[0030] Figure 5 is a timing chart illustrating the following signals input to IF1 and IF2 of DUT4. As shown in Figure 5, each dummy time is set based on the timing information set in each timing setting S4. By adjusting each dummy time (white) independently of the data signal, synchronization can be performed while maintaining the waveform based on the data signal (gray).

[0031] In this embodiment, the semiconductor test apparatus 1 has a signal generation controller 3 that performs timing setting S4 after compilation S3, which allows for the separation of compiled data signals and timing information, and enables independent adjustment of the dummy time. As a result, the data signals can be reused by adjusting only the dummy time, eliminating the need to repeat signal creation S2 and compilation S3 each time, thus improving the test time of semiconductor devices.

[0032] While embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications are possible without departing from the spirit of the invention. These embodiments are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents. [Explanation of Symbols]

[0033] 1 Semiconductor test equipment, 2 Signal generator, 3 Signal generation controller, 21 Sequence control unit, 22 Instruction memory, 23 Address generation unit, 24 Address / Pre-crambler unit, 25 Data generation unit, 26 Control signal generation unit, 27 Timing control unit, 28 Timer

Claims

1. A signal generation controller that compiles a signal containing basic timing information and pattern information for the test item to be measured into a data signal, and adjusts the timing of the test signal by setting the timing information based on the data signal.

2. Multiple signal generators that apply test signals to each of the multiple interfaces of the device under test, A semiconductor testing apparatus comprising a signal generation controller that compiles a signal containing basic timing information and pattern information for a test item to be measured into a data signal, and adjusts the timing of the test signal by setting timing information based on the data signal.

3. The semiconductor testing apparatus according to claim 2, wherein the signal generator generates the test signal from the data signal and the timing information.

4. The semiconductor testing apparatus according to claim 3, wherein the test signals are synchronized by timing adjustment.

5. The signal containing basic timing information and pattern information for the test item being measured is compiled into a data signal. Based on the aforementioned data signal, set the timing information. A signal generation method, which includes generating a waveform from the data signal and the timing information.

6. The signal containing basic timing information and pattern information for the test item being measured is compiled into a data signal. Based on the aforementioned data signal, set the timing information. A semiconductor test signal generation device that generates a waveform from the aforementioned data signal and the aforementioned timing information.

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