Substrate processing method and substrate processing apparatus

Abstract

To create a desired pattern on a metal oxide resist. [Solution] The substrate processing method includes the steps of: performing a reduction treatment on a substrate on which a resist film is formed, which is made of a metal oxide resist and which has been developed after exposure to form a pattern, in order to reduce the hydrocarbons contained in the resist film; and performing a treatment on the resist film that has undergone the reduction treatment in order to reduce the roughness.

Description

Technical Field

[0006] , ,

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus.

Background Art

[0002] In the manufacturing process of semiconductor devices, a technique of forming a wiring pattern by etching using a resist pattern formed by photolithography as a mask is known. In this photolithography, a negative-type metal-containing resist may be used. Patent Document 1 discloses a wafer processing apparatus including a dry development module for forming a pattern of a metal-containing resist.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a technique for obtaining a desired pattern formed on a metal oxide resist.

Means for Solving the Problems

[0005] The substrate processing method of the present disclosure includes a step of performing a reduction treatment for reducing hydrocarbons contained in a resist film formed of a metal oxide resist and developed after exposure to form a pattern on a substrate, and a step of performing a treatment for reducing roughness on the resist film that has undergone the reduction treatment. and includes.

Effects of the Invention

[0006] This disclosure allows for the formation of a desired pattern on a metal oxide resist. [Brief explanation of the drawing]

[0007] [Figure 1] This is a flowchart illustrating the process in the first embodiment. [Figure 2] This is a schematic diagram showing a top view illustrating the changes in the resist film due to the aforementioned treatment. [Figure 3] This is a schematic diagram showing a top view illustrating the changes in the resist film due to the aforementioned treatment. [Figure 4] This is a schematic side view diagram showing the changes in the resist film due to the aforementioned treatment. [Figure 5] This is a schematic diagram illustrating the changes in the resist film due to plasma treatment. [Figure 6] This is a plan view illustrating a wafer processing system according to the first embodiment. [Figure 7] This is a front view illustrating the wafer processing system described above. [Figure 8] This is a longitudinal cross-sectional side view illustrating a plasma processing module according to the first embodiment. [Figure 9] This is a flowchart illustrating the process in the second embodiment. [Figure 10] This is a schematic diagram showing the reaction when a different process is performed than the one described above. [Figure 11] This is a schematic diagram showing the reaction when the above process is performed. [Figure 12] This is a flowchart illustrating the process in the third embodiment. [Figure 13] This is a schematic diagram showing the changes in the resist film due to the aforementioned process. [Figure 14] This is a longitudinal cross-sectional side view showing the heating device in the fourth embodiment. [Figure 15] This is a schematic diagram showing the change in the resist film due to the processing of the fifth embodiment. [Figure 16] This is a longitudinal cross-sectional side view of a modified wafer. [Figure 17] This is a longitudinal cross-sectional side view showing an example of pattern collapse occurring in a modified wafer. [Figure 18] It is a longitudinal side view illustrating a UV irradiation device. [Figure 19] It is a SEM image showing the test results of Evaluation Test 1. [Figure 20] It is a SEM image showing the test results of Evaluation Test 1. [Figure 21] It is a graph showing the test results of Evaluation Test 2. [Figure 22] It is a graph showing the test results of Evaluation Test 2. [Figure 23] It is a graph showing the test results of Evaluation Test 3. [Figure 24] It is a graph showing the test results of Evaluation Test 3. [Figure 25] It is a figure showing the test results of Evaluation Test 4. [Figure 26] It is a SEM image showing the test results of Evaluation Test 5. [Figure 27] It is a SEM image showing the test results of Evaluation Test 6. [Figure 28] It is a SEM image showing the test results of Evaluation Test 7. [Figure 29] It is a SEM image showing the test results of Evaluation Test 8. [Figure 30] It is a SEM image showing the test results of Evaluation Test 9. [Figure 31] It is a schematic diagram of a SEM image of the side surface of a wafer before gas supply in Evaluation Test 10. [Figure 32] It is a schematic diagram of a SEM image of a part of the side surface of a wafer after the test in Evaluation Test 10.

Mode for Carrying Out the Invention

[0008] 〔First Embodiment〕 FIG. 1 shows the flow of the process in the first embodiment. This process forms a resist pattern on a wafer W as a substrate by photolithography, and uses this resist pattern as a mask to etch the lower layer film 11 formed on the wafer W.

[0009] To explain the processing flow in detail, first, a resist solution or a film-forming gas is supplied to the wafer W to form a resist film 12 composed of a metal oxide resist (MOR) on the underlying film 11 (step S1). This MOR is a negative-type resist containing, for example, tin (Sn) as a metal, and a ligand is attached to this metal during film formation. Note that "containing metal" here means containing metal as a constituent component, not containing metal as an impurity. The above ligand is composed of, for example, hydrocarbons. In the following explanation, unless otherwise specified, the resist film 12 will be assumed to be a resist film formed by MOR.

[0010] In addition to Figure 1, the schematic diagrams in Figures 2 and 3 will also be used for explanation. Figures 2 and 3 are schematic diagrams viewed from above of the region in the resist film 12 where a linear pattern is to be formed. The left side of Figure 2 shows the resist film 12 immediately after step S1 is performed and it is formed on the wafer W. In the figure, Sn atoms are shown as 13, and multiple ligands connected to multiple Sn atoms 13 are collectively shown as 14. After the resist film 12 is formed on the wafer W, a pre-applied bake (PAB) is performed (step S2) to volatilize and remove impurities in the film, thereby strengthening the resist film 12.

[0011] Following PAB, the resist film 12 is exposed to light, for example, EUV (Extreme Ultra Violet) (step S3). Ligand 14 is detached from the Sn atoms 13 in the exposed areas, and the numerous Sn atoms 13 from which the ligand 14 has detached bond to each other via oxygen atoms. In other words, the Sn atoms 13 are oxidized to form a crosslinked structure, and a -Sn-O-Sn-O-Sn- structure is formed in the exposed region of the resist film 12. In reality, the ratio of Sn atoms to O atoms in the crosslinked structure is not necessarily 1:1.

[0012] Then, the wafer W after exposure is subjected to a heat treatment called PEB (Post Exposure Bake) (step S4). This PEB further promotes the detachment of ligand 14 from the exposed areas and the formation of crosslinked structures of Sn atoms 13 via oxygen. In the center of Figure 2, the resist film 12 after PEB is shown, and as described above, the Sn atoms that have been oxidized and formed crosslinked structures (i.e., oxidized Sn) are shown as 15.

[0013] Subsequently, the resist film 12 is developed by supplying a developing gas or developing solution to the wafer W (step S5). As shown on the right side of Figure 2, this development removes Sn atoms 13 that have not been oxidized to Sn 15 and still have ligand 14 bound to them. In other words, the unexposed regions in the resist film 12, which are composed of Sn atoms 13 with ligand 14 bound to them, are removed by reacting with the developing gas or developing solution. Figure 3 shows the resist film 12 at the end of development, and more specifically, it shows the wall portion 16 of the resist pattern formed linearly by development.

[0014] Here, for example, during exposure in step S3 above, the width of the region where Sn oxidized material (Sn15) is formed may differ due to factors such as unavoidable fluctuations in the output of the exposure beam. Therefore, differences in the degree of Sn15 formation occur in each exposed area, which may result in the formation of irregularities in the wall portion 16 of the resist pattern. In Figure 3, the area enclosed by the dotted line on the right side is a region where Sn15 oxidized material was supposed to be formed, but due to the non-uniformity of exposure mentioned above, Sn15 oxidized material was not formed, resulting in a depression in the wall portion 16 of the resist pattern. In addition, it is possible that some Sn atoms 13 within the surface of the wafer W are not removed during development and remain, forming the wall portion 16 of the resist pattern together with Sn15 oxidized material. In Figure 3, the Sn atoms 13 that remain and become protrusions in the wall portion 16 are enclosed by a dashed line. In this way, irregularities in the wall portion 16 of the resist pattern may be formed due to the development not proceeding uniformly within the surface of the wafer W.

[0015] Due to the various factors described above, the roughness (surface roughness) of the wall portion 16 of the resist pattern after development may be relatively large. If the roughness is large, there is a risk that a pattern with the desired width cannot be formed when etching the underlying film 11 using this resist pattern to transfer the pattern. Therefore, in this first embodiment, after development, a heat treatment (HB: hard bake) is performed to increase the hardness of the wall portion 16 of the resist pattern (step S6), and then the resist pattern is exposed to a plasma of an inert gas, He (helium) gas (step S7).

[0016] The explanation will also refer to Figure 4, which is a longitudinal cross-sectional side view of wafer W. The left side of Figure 4 shows wafer W before exposure to He gas plasma, and the center of Figure 4 shows wafer W after exposure to He gas plasma. As shown, exposure to He gas reduces the roughness of the walls 16 of the resist pattern. LER (Line Edge Roughness) and LWR (Line Width Roughness) are known as indicators of pattern roughness, obtained using predetermined calculation formulas. As shown in the evaluation tests described later, both LER and LWR decrease, and the roughness is reduced.

[0017] As shown in Figure 5, the He plasma penetrates the resist film 12 and breaks some of the bonds between the cross-linked Sn atoms 13 and oxygen atoms (shown as 17 in the figure) (left and center of Figure 5). Subsequently, as the Sn atoms 13 and oxygen atoms 17 recombine (right side of Figure 5), it is thought that the atoms are arranged with high uniformity due to the action of intermolecular forces, etc. In other words, due to the plasma treatment, some of the Sn atoms 13 move within the resist film 12 or on the surface of the resist film 12. For example, as shown on the left side of Figure 3, the Sn atoms that formed the convex parts of the wall portion 16 of the resist pattern move to the concave parts of the wall portion 16, as shown on the right side of Figure 3, thereby reducing roughness.

[0018] The underlying film 11 is etched using the resist pattern with reduced roughness (step S8), and the pattern is transferred to the underlying film 11 as shown on the right side of Figure 4. Because the irregularities of the wall portions 16 of the resist pattern are reduced, a pattern with a desired width can be formed on the underlying film 11, as described above. Incidentally, as shown in the evaluation test, the strength of the resist film 12 increases when exposed to He plasma in step S7. Therefore, during etching in step S8, the opening width of the resist pattern between the wall portions 16 does not widen easily. From this point of view as well, a pattern with a desired width can be formed on the underlying film 11.

[0019] In addition to He gas plasma, N2 (nitrogen) gas plasma or Ar (argon) gas plasma may also be used as the inert gas plasma. However, since the molecular weight of these gases is relatively large, there is a risk that when the plasma molecules collide with the resist film 12, they may erode the resist film 12 to a relatively large extent. Therefore, in order to suppress the reduction in the thickness of the resist film 12, it is preferable to use He gas plasma, which has a relatively small molecular weight.

[0020] Next, an example of a wafer processing system 2 capable of performing steps S1 to S7 of the flow described in Figure 1 will be explained with reference to the plan view in Figure 6 and the front view in Figure 7. This wafer processing system 2 is configured by connecting a coating and developing apparatus 20 that performs all steps except S3 of steps S1 to S7, and an exposure apparatus 2A that performs step S3. In describing the coating and developing apparatus 20, the left-right direction will be referred to as the X direction, and the front-back direction perpendicular to the X direction will be referred to as the Y direction. The coating and developing apparatus 20 consists of a carrier block D1, a processing block D2, and an atmospheric transport block D3, which are arranged from the left side (-X side) to the right side (+X side), and the exposure apparatus 2A is connected to the right side of the atmospheric transport block D3. Vacuum blocks D4 are connected to the rear side (-Y side) and the front side of the atmospheric transport block D3, respectively. The interiors of the carrier block D1, processing block D2, and atmospheric transport block D3 are at atmospheric pressure or approximately atmospheric pressure.

[0021] The carrier block D1 comprises multiple carrier stages 31 arranged in the front-to-back direction, and a transport mechanism 32 for loading and unloading wafers W to and from carriers C placed on each stage 31. Carrier C is a transport container capable of storing multiple wafers W, such as a Front Opening Unity Pod (FOUP). A transport region 33 is formed on each stage 31, extending in the front-to-back direction in a plan view, allowing the transport mechanism 32 to access the carrier C, and the transport mechanism 32 moves within this transport region 33. In addition, an inspection module 34 is provided in the transport region 33 at a different height from the position where the transport mechanism 32 accesses the carrier C, and the transport mechanism 32 can also access the inspection module 34. The inspection module 34, for example, uses a camera to image the wafer W before it is returned to the carrier C after completing the processing in step S7, and transmits the image data to the control unit 100 described later. Based on this image data, the control unit 100 determines whether or not there are any abnormalities in the resist pattern.

[0022] Processing block D2 has a configuration in which multiple layers are stacked, each having a region R1 where a liquid processing module is installed and a region R2 where a non-liquid processing module is installed. The liquid processing region R1 and the non-liquid processing region R2 are located on the front and rear sides, respectively, of the transport region 41 which extends to the left and right. A transport mechanism 42 is provided in the transport region 41.

[0023] The multiple layers include layer E1 for forming the resist film 12 and layer E2 for developing. In the illustrated example, two layers E2 are stacked on top of two layers E1. Layer E1 for forming the resist film 12 is provided with resist film formation modules 43 and 44 in regions R1 and R2, respectively. The resist film formation module 44, which performs gas processing, is equipped with a processing container that processes the wafer W by exhausting the inside and supplying gas to the inside, similar to the plasma processing module 7 described later. In addition, a heating module 46 for performing PAB is provided in region R2 of layer E1. The heating module 46 is equipped with a hot plate on which the wafer W is placed and heated. An example of the configuration of this heating module 46 is the same as the heating module 46a of the fourth embodiment described later.

[0024] The resist film formation module 43, which performs liquid processing, comprises a cup 45A, a movable nozzle 45B for supplying various chemical solutions to the wafer W housed in the cup 45A for processing, and a moving mechanism 45C for moving the nozzle 45B in this manner. These various chemical solutions include a resist solution as well as a resist solvent. This solvent is a chemical solution that can dissolve the already formed resist film 12 and remove it from the wafer W in order to reform the resist film 12, which will be described later. The resist film formation module 43 is equivalent to an integrated resist film removal module that supplies a solvent to remove the resist film and a resist film formation module that supplies a resist solution to form the resist film.

[0025] Since the resist film formation can be performed at any location in layer E1, the resist film formation module 43 for liquid processing may be configured as a film removal module by supplying only the solvent from the resist and solvent. Furthermore, the resist film formation module 44 may be used to form the resist film, so that the resist film formation module and the film removal module are configured as separate units. That is, the wafer W may be transferred between the resist film formation module and the film removal module by a transport mechanism. In addition, if the resist film formation module 43 can supply the resist, the resist film formation module 44 for gas processing does not need to be provided.

[0026] For the development layer E2, development modules 47 and 48 are provided in regions R1 and R2, respectively. The development module 47 for liquid treatment and the development module 48 for gas treatment have the same configuration as the resist film formation module 43 and the resist film formation module 44, except for the difference in chemicals and gases, respectively. Note that since development can be performed at any location in layer E2, it is acceptable to provide only one of these development modules 47 or 48. In addition, a heating module 49 for PEB and a heating module 40 for HB are provided in region R2, and these heating modules 49 and 40 have the same configuration as the heating module 46 for PAB.

[0027] At the left end of the transport area 41, a tower T1 is provided that spans from the lowest to the highest level. Numerous temporary storage modules (not shown) are stacked on the tower T1, each capable of temporarily holding a wafer W. A vertically movable transport mechanism 35 is provided at the rear of the tower T1, which can transport wafers W between the temporary storage modules. The transport mechanism 32 of the carrier block D1 and the transport mechanisms 42 of the processing block D2 are accessible from the tower T1. Through the temporary storage modules and transport mechanisms 35, wafers W can be transported between each level E1, E2 and the carrier block D1. Although the transport mechanism 42 is shown as being provided for each level, it may be common to multiple levels. In other words, multiple transport areas 41 of different levels may be interconnected.

[0028] The atmospheric transport block D3 is equipped with a transport area 51 that extends to the left and right, and a transport mechanism 52 is provided in the transport area 51. The transport mechanisms 32, 35, 42, and 52 described above are equipped with a base that can rotate and move up and down around a vertical axis, and a support part for the wafer W that moves back and forth on the base, and the transport mechanisms 32, 42, and 52 are connected to a moving mechanism that moves the base along the transport area. A tower T2, configured similarly to tower T1, is provided at the left end of the transport area 51, and wafers W can be transferred between each level of the processing block D2 and the transport mechanism 52 via a temporary storage module of tower T2. In addition to tower T2, the transport mechanism 52 also accesses the LLM61 of the vacuum block D4 and the exposure apparatus 2A, which will be described later, to transfer wafers W.

[0029] The vacuum block D4 includes a load lock module (LLM) 61 whose internal pressure is changed, a vacuum transport module 62 whose internal pressure is maintained at a vacuum, and a plasma processing module 7 whose internal pressure is maintained at a vacuum. These modules are arranged in this order from left to right. In this example, the left-to-right arrangement of these modules is reversed between the front vacuum block D4 and the rear vacuum block D4. Each LLM 61 is connected to the atmospheric transport block D3 via a gate valve G. Gate valves G are also interposed between the LLM 61 and the vacuum transport module 62, and between the vacuum transport module 62 and the plasma processing module 7.

[0030] Each gate valve G is opened only when necessary for the transfer of wafers W between modules. In the case of LLM61, with each connected gate valve G closed, the internal pressure is switched between atmospheric pressure and vacuum pressure, and transfer to the atmospheric transfer block D3 and transfer to the vacuum transfer module 62 are performed in the atmospheric pressure state and the vacuum pressure state, respectively. LLM61 has multiple stages 63 on which wafers W are placed, for example, two stages. Stage 63 is equipped with pins 64 that move up and down for the transfer of wafers W. The vacuum transfer module 62 is equipped with a transfer mechanism 65 which is a multi-joint arm, and transfers wafers W between stage 63 and stage 73 of plasma processing module 7.

[0031] Next, the plasma processing module 7 will be described with reference to the longitudinal cross-sectional side view in Figure 8. The plasma processing module 7 includes a processing container 71. In the figure, 72 is a transport port provided on the side wall of the processing container 71. Inside the processing container 71 is a stage 73 on which the wafer W is placed. The upper central part of the stage 73 is configured as an electrostatic chuck 74, which attracts the back surface of the wafer W during plasma processing. A focus ring 75 is provided on the upper peripheral edge of the stage 73, surrounding the wafer W on the electrostatic chuck 74, and the distribution of plasma formed in the processing space 70 on the wafer W is adjusted.

[0032] The stage 73 has a temperature control unit 76 embedded in it for adjusting the temperature of the wafer W on the electrostatic chuck 74. The temperature control unit 76 consists of a flow path to which a fluid whose temperature has been adjusted by, for example, a heater or chiller is supplied. The stage 73 is also provided with pins similar to the pins 64 of the LLM 61, which protrude into the wafer W mounting surface of the stage 73 (the upper surface of the electrostatic chuck 74) to transfer the wafer W between the transport mechanism 65 and the stage 73, but these are not shown in Figure 8.

[0033] In Figure 8, 78 is a support column that supports the stage 73 inside the processing container 71. 79 in Figure 8 is an exhaust pipe, with its upstream end opening at the bottom of the processing container 71 and its downstream end connected to an exhaust mechanism 81 consisting of a turbomolecular pump or a dry pump. The exhaust mechanism 81 creates a vacuum atmosphere at the desired pressure inside the processing container 71. To improve the uniformity of exhaust around the stage 73, a baffle plate 83 is provided, which has numerous through-holes 82 drilled in the thickness direction. This baffle plate 83 surrounds the stage 73 and divides the processing container 71 vertically.

[0034] The downstream end of the gas supply pipe 84 is connected to the ceiling of the processing container 71, and a discharge port 77c is formed therein. In this example, a shower head 77 is provided on the ceiling of the processing container 71, which contains a gas diffusion space and to which the downstream end of the gas supply pipe 84 is connected. Multiple discharge ports 77c are formed at the bottom of the shower head 77, which connect the gas diffusion space and the processing space 70. In another example, a nozzle may be provided on the ceiling of the processing container 71, to which the downstream end of the gas supply pipe 84 is connected, forming, for example, one discharge port 77c. The processing gas supplied from the gas supply mechanism 85 provided on the upstream side of the gas supply pipe 84 is discharged into the processing space 70 through the discharge port 77c formed on the ceiling via the gas supply pipe 84. This processing gas is the He gas described above.

[0035] In the plasma processing module 7, a capacitively coupled plasma is formed using the ceiling of the processing vessel 71 (shower head 77 in this example) as the upper electrode and the stage 73 as the lower electrode. High-frequency power of different frequencies is applied to the stage 73 from a first high-frequency power supply 86 and a second high-frequency power supply 87. The first high-frequency power supply 86 supplies high-frequency power to the stage 73 at a relatively low frequency (LF, Low Frequency), for example, 13 MHz. The second high-frequency power supply 87 supplies high-frequency power to the stage 73 at a higher frequency (HF, High Frequency), for example, 100 MHz, than the power supplied by the first high-frequency power supply 86. By supplying high-frequency power from either the first high-frequency power supply 86 or the second high-frequency power supply 87, an electric field is formed in the processing space 70, causing the processing gas to be plasma-generated. High-frequency power may also be supplied from both the first high-frequency power supply 86 and the second high-frequency power supply 87. In that case, the second high-frequency power supply 87 is used as a high-frequency power supply for plasma formation, and the first high-frequency power supply 86 is used as a high-frequency power supply for applying a bias to draw ions contained in the plasma toward the stage 73. As will be shown later in the description of the evaluation test, when high-frequency power is supplied from only the second high-frequency power supply 87 of the first high-frequency power supply 86 and the second high-frequency power supply 87, the high-frequency power is preferably, for example, 100W or more and 1000W or less in this first embodiment. In the plasma processing module 7 of this example, at least one of the first and second high-frequency power supplies 86 and 87 and the upper and lower electrodes described above correspond to the plasma formation mechanism.

[0036] The processing procedure for the wafer W in the plasma processing module 7 is as follows: The wafer W is transported into a processing container 71, which is maintained at a predetermined vacuum pressure, and placed on an electrostatic chuck 74. Then, processing gas is supplied to the processing space 70, and power is supplied to the stage 73 from the first high-frequency power supply 86 and / or the second high-frequency power supply 87. As a result, the processing gas is turned into plasma, and the wafer W is exposed to this plasma. After that, the processing is completed when the supply of processing gas is stopped and the power supply from the first high-frequency power supply 86 and / or the second high-frequency power supply 87 is stopped, and the wafer W is removed from the processing container 71.

[0037] Returning to Figure 6, the coating and developing apparatus 20, which constitutes the wafer processing system 2, is equipped with a control unit 100. The control unit 100 is a computer and includes a program, memory, and CPU. The program incorporates a set of steps that enable the execution of a series of operations in the coating and developing apparatus 20, which will be described later. The control unit 100 outputs control signals to each part of the coating and developing apparatus 20 based on this program, and these control signals control the operation of each transport mechanism and each module, thereby enabling the transport of the wafer W and the processing of the wafer W in each module. The above program is stored on a storage medium such as a compact disc, hard disk, or DVD and installed in the control unit 100.

[0038] Next, the processing procedure for wafer W and the transport path for wafer W in the wafer processing system 2 will be explained in correspondence with the flow chart in Figure 1. The wafer W of carrier C is transported to the resist film formation module 43 or 44 of layer E1 of processing block D2, and then to the heating module 46 for PAB, thereby performing steps S1 and S2 on wafer W. After that, wafer W is transported to the exposure apparatus 2A via the air transport block D3, and exposure in step S3 is performed on wafer W. Subsequently, wafer W is transported to layer E2 of processing block D2 via the air transport block D3, and is transported in order to the heating module 49 for PEB, the developing module 47 or 48, and the heating module 40 for HB, thereby performing steps S4 to S6 on wafer W.

[0039] Subsequently, the wafer W is returned to the atmospheric transport block D3, transported to the plasma processing module 7 via the LLM 61 and vacuum transport module 62 of the vacuum block D4, and placed on the stage 73, where step S7 is performed. Next, the wafer W returns to the atmospheric transport block D3 via the reverse path from when it was transported to the plasma processing module 7, passes through one of the levels of the processing block D2, and returns to the carrier block D1. Then, the wafer W is transported to the inspection module 34, imaged, and then returned to the carrier C. Based on the image data, the control unit 100 determines whether or not there are any abnormalities in the resist pattern formed on the wafer W. Specifically, for example, it determines whether or not LER and LWR are below a certain threshold. Then, the carrier C to which the wafer W with the formed resist pattern has been returned is transported to the etching apparatus, and etching in step S8 is performed on the wafer W.

[0040] According to the wafer processing system 2 in the first embodiment described above, after development processing, the wafer W is transported to the plasma processing module 7 and the resist pattern is exposed to He gas plasma, thereby improving LER and LEW as shown in the test results described later, and increasing the intensity of the pattern.

[0041] Incidentally, based on the imaging data from the inspection module 34, the control unit 100 determines that there is an abnormality in the resist pattern of the wafer W, for example, either after it is returned to the carrier C or before it is returned to the carrier C, and then transports it again to the resist film formation module 43 at level E1 of the processing block D2. After the wafer W is transported back to the resist film formation module 43, a solvent is supplied to it to remove the resist film 12 (i.e., the resist pattern), and then the resist film formation modules 43 and 44 form a new resist film 12 on the wafer W. In this way, before the wafer W is transported from the wafer processing system 2 to another system or device along with the transport of the carrier C, a new resist film 12 is formed on the wafer W within the wafer processing system 2. The wafer W on which the resist film 12 has been reformed is then transported to the series of modules described above and processed again to form a new resist pattern.

[0042] As described above, according to the wafer processing system 2 of this disclosure, a wafer W that is judged to have an abnormal resist pattern is not discarded, but the resist pattern is remade and inspected until it is determined to be free of abnormalities. By reforming the resist pattern in this way, the occurrence of etching defects due to defects in the resist pattern can be suppressed.

[0043] Furthermore, the inspection of the resist pattern (determination of whether or not there are abnormalities) is not limited to being performed using the inspection module 34; it may also be performed after returning the wafer W to the carrier C and then transporting the carrier C to the inspection device. If the inspection device determines that there are abnormalities in the wafer W, the carrier C may be transported back to the wafer processing system 2 to reshape the resist pattern on the wafer W.

[0044] Although a wafer processing system 2 capable of forming and reforming resist patterns in steps S1 to S7 has been illustrated, the system is not limited to using such a wafer processing system 2, and the system configuration (device configuration) may be changed as appropriate. Each process for forming and reforming resist patterns may be carried out by transporting the carrier C between a plurality of substrate processing devices, each equipped with at least one of various modules for removing the resist film, forming the resist film, heating (PAB, PEB, HB), exposure, and developing, and these substrate processing devices may be configured as a system that performs steps S1 to S7. In other words, the system configuration is not limited to the formation of the resist pattern occurring when the wafer W is unloaded from the carrier C and returned to the carrier C.

[0045] Furthermore, the wafer processing system 2 may also be configured to perform the etching process in step S8. Therefore, the system configuration may be such that the wafer W is processed in steps S1 to S8 before it is removed from the carrier C and returned to the carrier C. Specifically, an example of this system configuration is provided in the wafer processing system 2 described above, in which one of the two plasma processing modules 7 is changed to an etching module. This etching module can have the same configuration as the plasma processing module 7, except that, for example, the gas supply mechanism 85 supplies an etching gas to the processing space 70 from the gas supply mechanism 85, depending on the material of the underlying film 11 formed on the wafer W. The underlying film 11 is etched in a vacuum atmosphere using this etching gas. Depending on the material of the underlying film and the type of etching gas, the etching may be performed without plasma being formed in the processing space 70.

[0046] [Second Embodiment] Next, the second embodiment will be described, focusing on the differences from the first embodiment. Figure 9 is a flowchart of the process in the second embodiment. After forming the resist pattern by development, before performing the He plasma treatment in step S7, the resist pattern is exposed to O2 (oxygen) gas plasma as step S7A. In the figure, step S7A is shown as being performed after the heat treatment in step S6, but the heat treatment in step S6 is not required. By performing this step S7A, both LER and LWR are reduced, as will be shown in the evaluation test later, and the roughness is reduced.

[0047] To demonstrate the effect of performing step S7A described above, the reactions that are presumed to occur in the resist film 12 forming the resist pattern when the process shown in Figure 9 is performed without performing step S7A will be explained with reference to Figure 10. The left side of Figure 10 shows the state before exposure to He plasma (before performing step S7), and the right side of Figure 10 shows the state after exposure to He plasma (after performing step S7).

[0048] As described in the first embodiment, Sn atoms are crosslinked via oxygen to form Sn15 oxide. However, as shown on the left side of Figure 10, some of the Sn atoms constituting Sn15 oxide have ligands 91 made of hydrocarbons bonded to them. The He plasma breaks the coordination bond, and the ligands 91 separate from the Sn atoms as hydrocarbon compound molecules 92. Metal particles tend to separate relatively easily from each other due to carbon. Therefore, the hydrocarbon compound molecules 92 become grain boundary material for Sn15 oxide, causing migration of Sn15 oxide particles 93. Specifically, as shown on the right side of Figure 10, the molecules 92 surround the particles 93 that are formed by the aggregation of Sn15 oxide molecules, preventing contact and bonding between the particles 93. Therefore, the dense arrangement of particles 93 in the film is hindered, which is thought to be the cause of roughness.

[0049] Therefore, by performing step S7A, the bond between the Sn atom and the hydrocarbon ligand 91 is broken, and the ligand 91 (hydrocarbon compound molecule 92) is ashing. The left side of Figure 11 shows the resist film 12 after ashing, and the right side of Figure 11 shows the resist film 12 after the He plasma treatment in step S7 following this ashing. Since much of the ligand 91 is removed by the ashing in step S7A, the generation of hydrocarbon compound molecules 92 is suppressed in step S7 after ashing. Consequently, the migration of the oxidized Sn 15 particles 93, as explained in Figure 10, is suppressed, and the particles 93 come into contact and bond together, resulting in a dense arrangement and suppression of roughness.

[0050] If the flow shown in Figure 9 is performed using the wafer processing system 2 in the same manner as in the first embodiment, step S7A can be performed using the plasma processing module 7. When performing step S7A, the gas supply mechanism 85 of the plasma processing module 7 is configured to also supply O2 gas. The processing conditions, such as the temperature of the wafer W and the pressure of the processing space 70, may be the same or different for the formation of the O2 plasma and the formation of the He plasma. As will be explained later in the evaluation test, when performing He plasma processing in this second embodiment by supplying high-frequency power from only the first high-frequency power supply 86 of the two high-frequency power supplies 87, it is preferable to set the high-frequency power to a value greater than, for example, 1000W. Since the wafer processing system 2 is provided with two plasma processing modules 7, the O2 plasma processing in step S7A and the He plasma processing in step S7 may be performed in separate plasma processing modules 7.

[0051] In step S7A, an example was shown using O2 gas plasma as the oxidizing gas plasma. However, since the goal is to remove hydrocarbons by ashing, the oxidizing gas is not limited to O2 gas. For example, ozone gas, nitric oxide, nitrogen dioxide, or other oxidizing gases composed of oxygen atoms may be used instead of O2 gas to create a plasma and then step S7A may be performed.

[0052] Furthermore, matters shown in the first embodiment that are also applicable to the second embodiment can be applied as appropriate. Therefore, in the second embodiment, the resist pattern may be reformed based on the inspection, or the steps of the flow in Figure 9 may be performed sequentially by transporting the carrier C between devices. In the embodiments described thereafter, applicable matters described up to that point can be applied as appropriate.

[0053] [Third Embodiment] Figure 12 shows the processing flow in the third embodiment. In this processing flow, after the PAB in step S2 and before the exposure in step S3, the resist film 12 is exposed to an inert gas plasma in step S7B. As this inert gas plasma, for example, a He gas plasma can be used, as in the first embodiment.

[0054] Figure 13 is a schematic diagram showing the changes within the resist film before and after plasma treatment with an inert gas. As shown on the left side of Figure 13, before plasma treatment, multiple Sn atoms 13 gather to form clusters 18, and there is a bias in the distribution (stochastics) of Sn atoms 13 in the resist film 12. Therefore, since there are regions in the film with a relatively low content of Sn atoms 13, if exposure and development are performed without the plasma treatment in step S7B, there is a risk of chipping occurring in the walls 16 of the resist pattern formed by development. Furthermore, this chipping may cause unintended breaks in the linear walls 16, known as pinching. In addition, because clusters 18 are formed and Sn atoms 13 become denser, if exposure and development are performed without the plasma treatment in step S7B, minute protrusions caused by the shape of the clusters 18 may be formed on the surface of the walls 16 of the resist pattern, worsening the roughness.

[0055] To suppress these issues, according to the third embodiment, the resist film 12 before exposure for forming the resist pattern is exposed to the inert gas plasma in step S7B, as described above. This decomposes the clusters 18 and disperses the Sn atoms 13, improving the uniformity of the distribution of the Sn atoms 13 (right side of Figure 13). Then, by performing the aforementioned post-exposure processing (steps S3-S6, S8) on the resist film 12, the roughness of the resist pattern is reduced, and chipping of the wall portion 16 forming the pattern and the occurrence of minute protrusions are suppressed.

[0056] In the flow chart of Figure 12, the resist film 12 is exposed to He gas plasma after the PAB in step S2. However, the resist film 12 may be formed in step S1 and then exposed to He gas plasma before the PAB in step S2. Therefore, after forming the resist film 12 on the wafer W, plasma treatment with an inert gas can be performed before the Sn crosslinking structure (Sn oxide 15) is formed by exposure in step S3.

[0057] As described above, the resist film 12 may be plasma-treated before exposure, or the resist film 12 may be plasma-treated after pattern formation, as described in the first and second embodiments. In other words, the third embodiment may be combined with the first or second embodiment described above. In this description of the third embodiment, "before exposure" means before exposure, before a pattern is formed on the resist film by development. Therefore, for example, the plasma treatment with inert gas of the third embodiment may be performed after exposure to remove unwanted resist film from the peripheral edge of the wafer W.

[0058] [Fourth Embodiment] The processing in the fourth embodiment is the same as the flow in the first embodiment. In this flow, the PAB in step S2 is performed by creating a vacuum atmosphere and an inert gas atmosphere around the wafer W. The reason for this is explained below. Performing PAB in a vacuum atmosphere promotes the release of impurities that are unnecessary for pattern formation contained in the resist film 12 to the outside of the resist film 12. When impurities are removed in this way, substances necessary for pattern formation, such as Sn atoms 13 remaining in the resist film 12, diffuse into the space where the impurities have been removed, thereby increasing the uniformity of the distribution. This makes it possible to reduce roughness. The above-mentioned impurities are, for example, the solvent of the resist. When the resist film 12 is formed by liquid processing (when using a resist film formation module 43 that processes with resist), the solvent will be contained in a relatively large amount in the film, so performing PAB in a vacuum atmosphere is particularly effective in this case.

[0059] Furthermore, when oxygen acts on the wafer W on which the resist film 12 is formed before exposure, the Sn atoms 13 to which the ligand 14 remains bound form a cross-linked structure via the oxygen atom. In this process, the ligand 14 acts as a steric hindrance, making it difficult for the arrangement of Sn atoms 13 to become dense, resulting in a relatively irregular molecular structure for the cross-linked structure. After development, this molecular structure appears as irregularities on the wall portion 16 that forms the resist pattern, increasing the roughness of the pattern. To suppress this unintended reaction between the Sn atoms 13 to which the ligand 14 is bound, it is preferable to shorten the time the wafer W is exposed to an oxygen atmosphere between the formation of the resist film and exposure, or to keep the oxygen concentration of the atmosphere surrounding the wafer W relatively low. Therefore, by making the atmosphere surrounding the wafer W an inert gas atmosphere during PAB, the unintended reaction described above can be suppressed during the execution of PAB, and the roughness of the resist pattern can be reduced.

[0060] Figure 14 is a longitudinal cross-sectional side view showing a heating module 46a, which is a heating device for performing the PAB in step S2 of the fourth embodiment. In the heating module 46a shown in this figure, the same reference numerals are used for components similar to those in the plasma processing module 7 shown in Figure 8, such as the processing vessel 71a, and the differences from the plasma processing module 7 will be explained in detail. The processing vessel 71a consists of a bottom container 77m and an upper lid 77n, and a stage 73a is provided at the upper opening of the bottom container 77m via an annular support 78a. This stage 73a is configured as a hot plate including, for example, a heater 76a.

[0061] The top lid 77n moves up and down by a lifting mechanism 77p, and in the lowered position, it covers the bottom container 77m, thereby making the inside of the processing container 71a airtight. Inside the top lid 77n, there is a shower head 80 to which a gas supply mechanism 85a that supplies inert gas is connected via a gas supply pipe 84a. The shower head 80 is supplied with inert gas into its internal space, and the inert gas is supplied to the processing space 70a through a plurality of through holes provided at its lower part. An exhaust mechanism 81a is connected to the gap between the shower head 80 and the top lid 77n via an exhaust pipe 79a, and the processing space 70a is exhausted through this gap to create a vacuum atmosphere.

[0062] With the processing container 71a sealed, inert gas is supplied from the shower head 80 and exhaust is performed by the exhaust mechanism 81a, creating a vacuum and inert gas atmosphere inside the processing container 71a. In this state, the wafer W placed on the stage 73a is heated and PAB is performed. The vacuum atmosphere inside the processing container 71a is lower than atmospheric pressure, but it is preferable to set the pressure to, for example, 102 Pa or less to efficiently remove the impurities mentioned above.

[0063] For the reasons stated above, it is preferable that the processing container 71a during the heat treatment of the wafer W be in a vacuum atmosphere and an inert gas atmosphere. However, by adjusting the exhaust volume and the supply volume of inert gas, the processing container 71a may be treated to atmospheric pressure, the same as the outside of the processing container 71a, and PAB may be performed on the wafer W. In other words, the wafer W may be treated with only the inert gas atmosphere formed inside the processing container 71a, of the vacuum atmosphere and the inert gas atmosphere. Alternatively, air may be supplied from the gas supply mechanism 85a, and the wafer W may be treated with only the vacuum atmosphere formed inside the processing container 71a, of the vacuum atmosphere and the inert gas atmosphere.

[0064] While it has been explained that impurities are removed by creating a vacuum atmosphere around the wafer W when performing PAB, it would suffice if impurities could be removed by creating a vacuum atmosphere around the wafer W at any time after the formation of the resist film 12 on the wafer W and before the cross-linking structure of Sn atoms 13 is formed by exposure by the exposure apparatus 2A. Specifically, for example, in the wafer processing system 2, a standby module for holding the wafer W can be provided in the wafer W transport path from the resist film formation modules 43 and 44 to the exposure apparatus 2A. This standby module can be configured to include a housing, an opening / closing mechanism for opening and closing a wafer W transport port provided in the housing, and a mounting section for placing the wafer W inside the housing, thereby creating a sealed space within the housing for placing and waiting the wafer W. Furthermore, the standby module can be configured to include a mechanism for exhausting the sealed space so that a vacuum atmosphere is formed around the waiting wafer W.

[0065] Furthermore, a mechanism for supplying an inert gas to the transport path from the resist film formation modules 43 and 44 to the exposure apparatus 2A may be provided to create an inert gas atmosphere in the transport path, thereby reducing the amount of oxygen the resist film 12 comes into contact with and the time it is exposed to oxygen before exposure, and thus suppressing the unwanted reactions described above. In this fourth embodiment, for example, N2 (nitrogen) gas is used as the inert gas to form the inert gas atmosphere, but other inert gases such as Ar gas or He gas may also be used. Although the PAB of this fourth embodiment has been described as applicable to the first embodiment, it is not limited to that and may also be applied to the second and third embodiments and other embodiments described later.

[0066] [Fifth Embodiment] This fifth embodiment is a modification of the first embodiment, and the processing on the wafer W proceeds according to the flow described in Figure 1. In the fifth embodiment, by setting the high-frequency power supplied for plasma formation during the inert gas plasma processing in step S7 to a relatively high level, directed self-assembly (DSA) is induced in the resist film 12 forming the resist pattern. This changes the shape of the resist pattern. More specifically, the pinching described above is intentionally generated and used to shape the resist pattern. The inert gas plasma used in this fifth embodiment is, for example, a He gas plasma, as in the first embodiment.

[0067] The deformation of the resist pattern described above will be explained in detail with reference to the plan view in Figure 15. The left side of Figure 15 shows the resist film 12 before step S7, and the right side of Figure 15 shows the resist film 12 after step S7. As shown on the left side of Figure 15, before step S7, the walls 16 of the resist pattern are formed in a linear shape in plan view. Step S7 causes DSA to occur, and the walls 16 split in the lengthwise direction in plan view, resulting in granulation, and as shown on the right side of Figure 15, a large number of circular granular walls 19 are formed. This splitting of the walls 16 is thought to be due to the migration of oxidized Sn 15 particles 93 via hydrocarbon compound molecules 92, as explained in Figure 10, by the He plasma treatment. Therefore, in this fifth embodiment, the plasma treatment with oxidizing gas in step S7A, as explained in the second embodiment, is not performed, and the plasma treatment with He gas in step S7 is performed instead.

[0068] Then, in step S8, after the resist pattern has been deformed in this way, the underlying film 11 is etched using the resist pattern formed by the wall portion 19. As a result, the underlying film 11 is etched so that the wall portion remains in a granular form. In step S7 of this fifth embodiment, the high-frequency power supplied to the stage 73 which forms the electrode is set to a different value from that of the first embodiment, and is set to a value greater than 1000W, as will be shown in the evaluation test described later.

[0069] [Differentiation] Furthermore, the inert gas plasma treatment shown in embodiments other than the third embodiment may be performed before HB by the heating module 40. Also, HB may be omitted in each of the above embodiments. Moreover, the inert gas plasma treatment is not limited to being performed in the plasma treatment module 7, but may be performed in other modules capable of generating inert gas plasma, provided inside or outside the wafer processing system 2. An example of such other modules that generate inert gas plasma is a gas processing developing module 48. In this case, the developing module 48 is capable of supplying plasma as shown in the plasma treatment module 7 in Figure 8, and the gas supply mechanism is configured to supply inert gas. Therefore, it can be said that the plasma treatment module 7, configured so that the gas supply mechanism 85 can supply inert gas and developing gas to the processing space 70, is provided as the developing module 48. The developing gas includes, for example, at least one of HBr (hydrogen bromide) gas, BCl3 (boron trichloride) gas, and acetic acid (CH3COOH) gas.

[0070] As previously described, the process is not limited to performing HB between the developing process and the plasma treatment with inert gas. Therefore, if the developing module 48 is configured to enable plasma treatment with inert gas as described above, in embodiments other than the third embodiment, the developing process and the plasma treatment can be performed sequentially in the developing module 48. In other words, the developing process and the plasma treatment with inert gas can be performed consecutively on the wafer W in the same processing container 71. When performing the second embodiment with the developing module 48, the gas supply mechanism 85 of the developing module 48 can also supply an oxidizing gas such as oxygen gas, so that the developing process, plasma treatment with oxidizing gas, and plasma treatment with inert gas are performed in this order within the same processing container 71. That is, steps S5, S7A, and S7 of the flow in Figure 9 should proceed sequentially within the same processing container 71.

[0071] During the development process in this development module 48, the processing space 70 is set to a predetermined pressure, and a developing gas is supplied to the wafer W, which is placed on the stage 73 and adjusted to a predetermined temperature, to perform the development process. The temperature of the wafer W and the pressure of the processing space 70 during the development process may be appropriately changed from the temperature and pressure during the plasma processing, respectively. The pressure is not limited to vacuum pressure; atmospheric pressure may also be used. Plasma may be formed in the processing space 70 during the development process, but for example, the process may be performed without forming such plasma.

[0072] In this configuration, where the developing module 48 can perform plasma processing with an inert gas, plasma processing with an inert gas can be performed in the developing module 48 without the need to arrange the plasma processing module 7. Furthermore, since plasma processing can be performed immediately after the developing process within the same processing container, the time required for transporting the wafer W between modules is reduced, thereby improving the throughput of the system that advances the flow in each embodiment.

[0073] Incidentally, while the plasma processing module 7 processes the wafer W by forming a capacitively coupled plasma, the module is not limited to such a configuration. For example, it may be configured to form an inductively coupled plasma in the processing space 70 and perform the processing, or it may be configured to form a plasma by irradiating the processing space 70 with microwaves and then performing the processing. Furthermore, the plasma formation is not limited to being performed inside the processing vessel; the module may also be configured to perform so-called remote plasma processing, where the plasma formed in a channel communicating with the processing vessel is introduced into the processing vessel for processing.

[0074] Furthermore, although the electrode to which 100 MHz power is applied from the second high-frequency power supply 87 in the plasma processing module 7 is shown to be located on the stage 73, it is not limited to being located there. Power may also be supplied from the second high-frequency power supply 87 to the electrode on the ceiling of the processing vessel 71 so that a capacitively coupled plasma is formed.

[0075] As mentioned above, exposure in step S3 removes hydrocarbon ligands bound to Sn atoms, thereby promoting Sn bonding via oxygen. However, in the exposed areas of the resist film 12, some of these hydrocarbons remain bound to Sn. As previously described, in the second embodiment, as step S7A, ashing is performed by exposing the resist film 12 of the wafer W to an O2 plasma to remove hydrocarbons that remain bound to Sn after exposure. That is, by exposing the wafer W to an O2 plasma, a reduction treatment is performed to reduce the concentration of hydrocarbons in the resist film 12. This promotes the formation of Sn-to-Sn bonding via oxygen, strengthening the exposed areas, i.e., the resist pattern, while suppressing migration caused by hydrocarbon compound molecules 92 and reducing the roughness of the resist pattern.

[0076] The explanation continues with reference to the longitudinal cross-sectional side view of wafer W in Figure 16. In this wafer W, an SiO2 film 21 formed from TEOS (tetraethoxysilane), an ODL film 22 which is an insulating film made of organic material, and a lower film 23 are stacked in order upwards on film 24, with a resist film 12 formed on the lower film 23. The lower film 23 may be an inorganic film, such as SOG which is mainly composed of Si. In this case, the ODL film 22 is less affected by the oxygen plasma treatment described above. However, the lower film 23 may be composed of an organic film, that is, a film containing carbon. Note that "containing carbon" does not mean containing it as an impurity, but as a main component. An example of a specific organic film is an amorphous carbon film.

[0077] When the underlying film 23 is an organic film, and the O2 plasma treatment in step S7A of the second embodiment is performed, depending on the processing conditions, the amount of ashing of the underlying film 23 may become relatively large, which may cause the walls constituting the resist pattern to collapse, a phenomenon known as pattern collapse. Figure 17 shows an example where pattern collapse occurred because the ODL film 22 was also ashed in addition to the underlying film 23. Therefore, the processing conditions in this second embodiment are set to suppress such excessive ashing. These processing conditions will be explained later in the evaluation test.

[0078] In the second embodiment, instead of performing ashing with O2 plasma in step S7A, a non-plasma oxidizing gas may be supplied to the wafer W placed in the processing vessel 71 to remove hydrocarbons, which are ligands for Sn, from the resist pattern, i.e., to reduce the concentration of hydrocarbons in the resist film 12. When supplying the oxidizing gas, for example, the pressure inside the processing vessel 71 is reduced. That is, a vacuum atmosphere is formed inside the processing vessel 71, and the reduction process is performed by supplying the non-plasma oxidizing gas from the processing vessel 71.

[0079] As the oxidizing gas, various gases as exemplified above can be used, but for example, O2 gas can be used. Evaluation tests have shown that by supplying O2 gas to the wafer W under a vacuum atmosphere, hydrocarbons, i.e., carbon, are removed from the resist film 12. When performing such non-plasma O2 gas processing, for example, an apparatus or module configured similarly to the plasma processing module 7 can be prepared and used, except that each high-frequency power supply is not provided and plasma is not formed in the processing container 71.

[0080] Furthermore, as a treatment to reduce the hydrocarbon concentration in the resist pattern, in the second embodiment, instead of performing the O2 plasma treatment in step S7A (hereinafter sometimes referred to as O2 ashing), the resist pattern may be irradiated with UV (ultraviolet) light. An example of a UV irradiation apparatus for performing this treatment, the UV irradiation apparatus 8, will be described with reference to the longitudinal cross-sectional side view in Figure 18. The UV irradiation apparatus 8 has a rectangular housing 53, a moving mechanism 54, a support part 55, and a light source module 60 provided inside the housing 53. A transport port 53a, which is an opening for loading and unloading wafers W, is provided in the side wall of the housing 53. The moving mechanism 54 is provided on the bottom surface inside the housing 53, and the support part 55 is attached to the moving mechanism 54. The support part 55 has a support base 55a fixed to the moving mechanism 54, a rotating part 55b extending vertically upward from the support base 55a, and a disc-shaped mounting base 55c attached to the upper end of the rotating part 55b. The wafer W introduced from the transport port 53a is placed on the mounting platform 55c. The mounting platform 55c holds the wafer W by suction. The housing 53 is usually positioned so that the bottom surface on which the moving mechanism 54 is provided is horizontal, and the wafer W is held on the mounting platform 55c so that its main surface is horizontal.

[0081] The light source module 60 is located inside the housing 53, above the moving mechanism 54 and the support 55. The light source module 60 includes a housing 56 and a light source 57 located inside the housing 56. The light source 57 is a light source that generates, for example, EUV light as UV light used for exposure. The housing 56 has an opening 56a formed directly below the light source 57, and is also provided with a shutter 58 for opening and closing the opening 56a. The shutter 58 moves between a closed position that blocks the opening 56a and an open position that opens the opening 56a, by a shutter moving mechanism 58a located inside the housing 56.

[0082] With the light source 57 turned on and the shutter 58 moved to the open position so that the opening 56a is open, the support part 55 is moved horizontally inside the housing 53 by the moving mechanism 54, thereby irradiating the entire resist film 12 of the wafer W with ultraviolet light. During this time, the rotating part 55b rotates, causing the wafer W to rotate around its central axis.

[0083] Furthermore, as a treatment to reduce the hydrocarbon concentration in the resist pattern, the resist film 12 may be treated by irradiation with an oxygen ion beam. In such a treatment, the same effect as when the O2 plasma ashing treatment in step S7A is performed can be expected. As an example of an apparatus for performing these treatments, a representative example of an ion implantation apparatus that performs oxygen ion beam irradiation will be briefly described. The ion implantation apparatus has, for example, a housing, an oxygen gas supply mechanism that supplies, for example, oxygen gas as an oxidizing gas, and an ion generation mechanism that converts the supplied oxygen gas into plasma. It may also have an acceleration unit, a focusing lens, and a deflection unit. The oxygen gas is converted into plasma by the ion generation mechanism, ions are extracted from the oxygen plasma and accelerated in the acceleration unit, the beam is focused by the focusing lens, and the beam is scanned in the deflection unit to irradiate the wafer W with oxygen ions and implant oxygen ions into the resist film 12.

[0084] The non-plasma O2 gas supply device, UV irradiation device 8, and oxygen ion implantation device described above may be incorporated into the wafer processing system 2 as modules, or they may be separate devices or modules within the wafer processing system 2. When provided as modules in the wafer processing system 2, for example, the non-plasma O2 gas supply device may be replaced with at least one of the two plasma processing modules 7. The UV irradiation device 8 may be replaced with one of the resist film formation module 44, heating module 46, and inspection module 34. When provided as separate devices or modules within the wafer processing system 2, the wafer W stored in carrier C should be transported between the device and the wafer processing system 2.

[0085] Furthermore, the hydrocarbon concentration reduction treatment in the various resist patterns described above can be performed whether the underlying film 23 beneath the resist film 12, as explained in Figure 16, is an organic film or an inorganic film.

[0086] Furthermore, when the hydrocarbon concentration reduction process is performed by supplying a non-plasma oxidizing gas (not plasma-generated) to the wafer W, the processes from development to plasma treatment with an inert gas can be carried out within the same processing container 71, similar to the case where the wafer W is exposed to plasma-generated oxidizing gas. Specifically, the development module 48 can be configured to also supply oxidizing gas from the gas supply mechanism 85, and the development process, supply of oxidizing gas, and plasma treatment with an inert gas can be performed on the wafer W in this order within the processing container 71 of the development module 48.

[0087] Incidentally, instead of the treatment of exposing the resist film 12 to the inert gas plasma in steps S7 and S7B of each embodiment described above, it is thought that the same effect as when the resist film is exposed to the inert gas plasma can be obtained by irradiating or implanting an ion beam generated from the inert gas onto the resist film. Therefore, the ion implantation treatment may be performed in this way, and the treatment is not limited to exposing the resist film 12 to the inert gas plasma. The inert gas ion implantation device may be incorporated into the wafer processing system 2 as a module, similar to the oxygen ion implantation device, or it may be a separate device from the wafer processing system 2 or a module within the device.

[0088] By the way, the substrate processing method is, for example, a step of placing a substrate on which a resist film made of metal oxide resist has been formed into a processing container, The process includes the step of forming an inert gas plasma in the processing container and exposing the resist film to the plasma. In the substrate processing method, for example, the resist film is developed and a pattern is formed, and the inert gas may be helium gas, in which case the method includes a step of supplying high-frequency power of 1000 W or less to an electrode for forming the plasma in order to form the plasma of the inert gas. Furthermore, in the substrate processing method, for example, the resist film is a resist film before exposure is performed to form a pattern by development, and in that case, for example, the method includes a step of creating a vacuum atmosphere or an inert gas atmosphere around the substrate after the resist film has been formed and before the exposure is performed.

[0089] Furthermore, the substrate processing apparatus includes a processing container on which a substrate with a resist film made of metal oxide resist is placed, A gas supply mechanism that supplies an inert gas into the processing container, A plasma formation mechanism for generating plasma from the gas supplied by the gas supply mechanism, such that the resist film is exposed to the plasma of the inert gas, Includes.

[0090] In the substrate processing apparatus, for example, the resist film is developed after exposure to form a pattern. The gas supply mechanism supplies the oxidizing gas and the inert gas into the processing container. The system includes a control unit that controls the operation of the gas supply mechanism and the plasma formation mechanism so that the resist film is exposed to the plasma of the oxidizing gas and the plasma of the inert gas in that order. In the substrate processing apparatus, for example, the resist film is exposed, and the gas supply mechanism supplies a developing gas for developing the resist film and the inert gas into the processing container. The system includes a control unit that controls the operation of the gas supply mechanism so that it supplies gas to the processing container in the order of developing gas and then inert gas. In that substrate processing apparatus, for example, the resist film is developed after exposure to form a pattern. A film removal module for removing the resist film from the substrate, A resist film forming module for forming the resist film, A developing module that develops the resist film after exposure to form a pattern, An inspection module that acquires data for detecting anomalies in the aforementioned pattern, The system includes a control unit that determines whether or not there is an abnormality in the pattern based on the aforementioned data, If the control unit determines that there is an abnormality in the pattern, it controls the operation of the film removal module, the resist film formation module, and the developing module so that the resist film is removed by the film removal module, the resist film is formed again on the substrate from which the resist film has been removed by the resist film formation module, and the resist film after exposure is developed by the developing module to reform the pattern.

[0091] Furthermore, in each embodiment, the substrate to be processed is not limited to a wafer, but may be, for example, a substrate for manufacturing a flat panel display or a mask substrate for manufacturing a mask for exposure. Therefore, a rectangular substrate may also be processed. The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The above embodiments may be omitted, replaced, modified and combined in various ways without departing from the scope and spirit of the appended claims.

[0092] The following describes the evaluation tests conducted in relation to the technology of this disclosure. In each of these evaluation tests, plasma processing is performed on a resist pattern using the plasma processing module 7 described in the embodiment. When performing plasma processing with He gas, the 100 MHz high-frequency power supply from the second high-frequency power supply 87 is not supplied, and the amount of 13 MHz high-frequency power supply from the first high-frequency power supply 86 is adjusted. Therefore, the first high-frequency power supply 86 is used as a power source for plasma formation of inert gas.

[0093] [Evaluation Test 1] In this evaluation test, the shape change of the resist pattern due to the change in high-frequency power for plasma formation described above was confirmed for the processing in the first embodiment (PAB → exposure → PEB → development → HB → plasma processing). In this evaluation test, a wafer W with the same resist pattern formed by PAB to HB was first divided into multiple chips, and nine bare wafers without a resist film were prepared. Each chip was then placed one by one in the central region of the surface of each bare wafer to create a test substrate, and then plasma processing with different high-frequency powers was performed on each.

[0094] Plasma processing conditions other than high-frequency power were kept the same for all substrates. Specifically, the pressure in the processing space 70 was set to 300 mTorr (40 Pa), the He gas flow rate supplied to the processing space 70 was set to 900 sccm, the substrate temperature during plasma processing was set to 20°C, and the plasma formation time was set to 10 seconds. The high-frequency power supplied from the first high-frequency power supply 86 was changed for each substrate, and was set to 100W, 200W, 300W, 500W, 1000W, 1500W, 2000W, and 3000W respectively. Of the multiple test substrates prepared as described above, one was not subjected to plasma processing as a comparative example. In the following explanation, this comparative example substrate may be described as having supplied high-frequency power of 0W. Images of each substrate after plasma processing and the comparative example substrate were acquired using an SEM (Scanning Electron Microscope) to observe the presence or absence of defects in the resist pattern such as bridging and pinching, and to calculate the LER (Laser Emission Reduction).

[0095] Figures 19 and 20 are images showing the test results of Evaluation Test 1, and represent the top surface of the resist film. In each image, the walls (convex parts) of the resist pattern are shown with higher brightness than the openings (concave parts) of the resist pattern. Figure 19 shows SEM images of each sample with high-frequency power from 0W to 500W. Images for high-frequency powers of 200W and 400W are not shown in the figure because there is no significant difference from the images for high-frequency powers of 100W and 300W. Figure 20 shows SEM images of each sample with high-frequency powers from 1000W to 3000W.

[0096] In the substrate with a high-frequency power of 0W shown in Figure 19, the surface roughness of the wall portion 16 is large, and it can be confirmed that this roughness causes defects (so-called bridge defects) where an unwanted resist film remains between the wall portions 16. The LER of this 0W substrate was 2.48 nm. In contrast, in the substrates with high-frequency powers of 100W to 1000W shown in Figures 19 and 20, the roughness of the wall portion 16 is significantly reduced, and it can be confirmed that bridge formation is suppressed. The LERs of the substrates with 100W, 200W, 300W, 400W, 500W, and 1000W were 2.19, 2.17, 2.22, 1.99, 2.00, and 3.00, respectively. Therefore, the LER of the 100W to 500W substrates is smaller than that of the 0W substrate, and the LER of the 1000W substrate is larger than that of the 0W substrate. However, the image of the substrate with 1000W shows reduced roughness and suppressed occurrence of bridge defects compared to the image of the substrate with 0W. As shown above, in order to suppress the roughness of the resist pattern, it is preferable to set the high-frequency power for plasma formation to 1000W or less, and more preferable to 500W or less.

[0097] Furthermore, as shown in Figure 20, for substrates supplied with high-frequency power of 1500W to 3000W, it can be confirmed that the wall portion of the resist pattern described in Figure 15 of the fifth embodiment has changed compared to the substrate supplied with 0W. In other words, circular wall portions are formed by the splitting of linear wall portions. From the brightness and darkness of the image, it can be confirmed that the higher the power in the range of 1500W to 3000W, the more clearly the wall portions are separated from each other. From the results of this evaluation test 1, it can be seen that in order to deform the resist pattern as described in the fifth embodiment, it is preferable to set the high-frequency power for plasma formation to a setting higher than 1000W, and to a setting of 1500W or higher.

[0098] [Evaluation Test 2] In this evaluation test, the effects of plasma treatment in the first embodiment were examined by comparing a resist pattern without plasma treatment (a comparative example) with a resist pattern with plasma treatment (an example). The comparison here was made with respect to the width CD (Critical Dimension), LWR, and LER of each resist pattern. Although this evaluation test performed the same processing as Evaluation Test 1, different samples were prepared separately, so the values ​​differed slightly. The high-frequency power setting during plasma treatment with inert gas for the example pattern was 300W.

[0099] Figures 21 and 22 are graphs showing the test results of evaluation test 2. Figure 21 shows the CD and LWR for each resist pattern with and without He plasma treatment, and Figure 22 shows the CD and LER for each resist pattern. In Figures 21 and 22, CD is shown by a bar graph, and LWR or LER is shown by a dot. For CD, the normalized value is shown by dividing the measured value by a predetermined positive number. Note that this CD represents the width of the wall portion of the resist pattern, within the wall portion and space portion.

[0100] As shown in Figures 21 and 22, when the CD of the pattern without plasma treatment (comparative example pattern) is set to 100%, the CD of the plasma-treated resist pattern (example pattern) is 3.5% lower than that of the pattern without plasma treatment. In contrast, as shown in Figure 21, when the LWR of the pattern without plasma treatment is set to 100%, the LWR of the plasma-treated pattern is 14.4% lower than that of the pattern without plasma treatment. Furthermore, as shown in Figure 22, when the LER of the pattern without plasma treatment is set to 100%, the LER of the plasma-treated pattern is 15.2% lower than that of the pattern without plasma treatment.

[0101] As a result of this plasma treatment, CD is slightly reduced. In other words, relatively large etching of the walls forming the resist pattern is prevented by the plasma treatment. On the other hand, LWR and LER are reduced relatively significantly, which is a favorable result. These test results are thought to be due to the high uniformity of the arrangement of each atom by breaking and recombining the bonds between some Sn atoms 13 and oxygen atoms 17, as shown in the first embodiment, and the suppression of pattern abrasion by using plasma generated from relatively lightweight He molecules.

[0102] [Evaluation Test 3] In this evaluation test, the patterns of the underlying film 11 etched using the resist pattern without plasma treatment (comparative example) and the resist pattern with plasma treatment (example) are examined, and the properties of each resist pattern are compared. In this evaluation test 3, as in evaluation tests 1 and 2, the resist pattern with plasma treatment is a pattern formed by performing steps S1 to S7 of the flow in Figure 1, while the resist pattern without plasma treatment is a pattern in which only step S7 (plasma treatment) of steps S1 to S7 has not been performed.

[0103] The exposure amount during exposure in step S3 was varied for each wafer W to form resist patterns for the example having multiple CD sizes and resist patterns for the comparative example having multiple CD sizes. Then, each wafer W was etched under the same conditions to transfer the resist pattern to the underlying film 11. The CD of the pattern on the underlying film 11 thus etched was measured. This CD of the pattern on the underlying film 11 is sometimes expressed as the CD of AEI (After Etch Inspection). This CD of AEI, like the CD of the resist pattern, represents the width of the wall portion of the wall portion and space that form the pattern. In this evaluation test 3, the values ​​of each CD are shown in a normalized form, similar to evaluation test 2.

[0104] Figure 23 is a graph showing the CD of the AEI relative to the CD of the resist pattern for each of the comparative example and the example. The solid line in the graph connects the points where the CD of the resist pattern and the CD of the AEI are the same. Comparing the AEI of the comparative example and the example from this graph, the AEI of the example is larger when the CD of the resist pattern is the same or approximately the same. In other words, the width of the wall portion of the lower layer film 11 is larger in the example. Therefore, the opening width of the resist pattern between the walls does not widen as much in the example when the lower layer film 11 is etched, indicating that the resist pattern of the example has higher etching resistance than the resist pattern of the comparative example. Thus, it was shown that the resist film was modified by the He plasma treatment.

[0105] Figure 24 is a graph showing the CD of AEI against exposure for both the comparative example and the example. Compared to the plot representing the comparative example in the graph, when the exposure is low, the AEI is relatively small for that exposure. In other words, the correlation between exposure and the CD of AEI is low in the comparative example. On the other hand, compared to the plot representing the example in the graph, when the exposure is low, the AEI is larger than in the comparative example. As a result, the correlation between exposure and the CD of AEI is higher in the example compared to the comparative example. Therefore, performing He plasma treatment as in the example is preferable because it allows for control of the CD of AEI over a wider range of exposures when controlling the exposure.

[0106] [Evaluation Test 4] In this evaluation test, the comparative example and the example were processed under the same conditions as in Evaluation Test 3. Specifically, the formation of a resist pattern including plasma treatment with an inert gas, following the processing flow of the first embodiment, and the formation of a resist pattern without plasma treatment were performed. However, in this Evaluation Test 4, the HB step in the processing flow of the example was performed after the plasma treatment. Then, the number of defects such as bridges and pinching in each part of the wafer W where the resist pattern was formed by the respective processing of the example and comparative example was counted and evaluated.

[0107] The counting of defects was performed for each region obtained by dividing the surface of a 300 mm diameter wafer W into a matrix, as shown in Figure 25. Figure 25 shows the number of defects in the divided regions of the wafer W treated in the embodiment. In the figure, the regions shown in white are regions where the number of defects is 0 or approximately 0, and the regions with dots are regions where a small number of defects were measured. In contrast, although the figure showing the number of defects is omitted for the wafer W treated in the comparative example, defects were confirmed in all of the regions divided into a matrix. Furthermore, the average value of the number of defects across the entire surface of the wafer W, and 3σ, were lower in the embodiment than in the comparative example. From these test results, it was confirmed that the plasma treatment of the first embodiment can effectively suppress defects over a wide area of ​​the wafer W surface.

[0108] [Evaluation Test 5] In this evaluation test, wafers W processed according to the second embodiment without HB were chipped in the same manner as in evaluation test 1, and SEM images were acquired to evaluate the presence or absence of defects and LER. The O2 plasma processing conditions in step S7A in the flow chart of Figure 9 are as follows: the pressure in the processing space 70 is 10 mTorr (1.33 Pa), the power supplied from the second high-frequency power supply 87 at 100 MHz is 500 W, the power supplied from the first high-frequency power supply 86 at 13 MHz is 100 W, the flow rate of O2 gas supplied to the processing space 70 is 120 sccm, the temperature of wafer W during plasma formation is 20°C, and the plasma formation time is 5 seconds. Then, for each chip after O2 plasma processing, the He plasma processing in step S7 was performed by varying the power supplied from the first high-frequency power supply 86 to 1500 W, 2000 W, and 3000 W. Other He plasma processing conditions were the same as in evaluation test 1. Furthermore, one of the chips that underwent O2 plasma treatment was not subjected to He plasma treatment as a comparative example.

[0109] Figure 26 shows SEM images of the test results for each sample (chip) in Evaluation Test 5, and displays a top view of the resist pattern. According to the image of the comparative example sample, which underwent only O2 plasma treatment and no He plasma treatment, the LER was 2.36. According to the images of the He plasma treatment at high-frequency powers of 1500W, 2000W, and 3000W, the splitting of the resist pattern wall portion 16 due to DSA (Figure 20), which occurred in the example of Evaluation Test 1, did not occur. This is thought to be because, as explained in Figure 11, the hydrocarbon compound molecules 92 were removed by the O2 gas plasma, preventing the migration of oxidized Sn15 particles 93, as explained in Figure 10, during He plasma treatment. Furthermore, when the high-frequency power during He plasma treatment was 1500W, 2000W, and 3000W, the LER was 1.70, 1.76, and 1.59, respectively, which are lower values ​​than the LER when He plasma was not performed in Evaluation Test 5 and the aforementioned Evaluation Test 1, indicating a favorable result.

[0110] In the first embodiment, it was stated that the high-frequency power supplied during He plasma treatment should be greater than 1000W in order to induce DSA. However, from this evaluation test 5, it can be seen that if O2 plasma treatment is performed, DSA can be prevented even if the supplied high-frequency power is set to a value greater than 1000W. In other words, it can be seen that it is preferable to set the high-frequency power to greater than 1000W in order to avoid DSA and reduce the roughness of the resist pattern. Furthermore, from the images obtained in this evaluation test 5, it can be confirmed that good results were obtained with a setting of 1500W or more, so it is even more preferable to set the high-frequency power to 1500W or more.

[0111] [Evaluation Test 6] In this evaluation test, etching was performed using a resist pattern produced by the fifth embodiment. SEM images were acquired of the resist pattern before etching and the underlying film 11 of the wafer W after etching to confirm the effectiveness of the etching process using the resist pattern.

[0112] Figure 27 shows SEM images of the resist pattern before etching and the underlying film of wafer W after etching. The imaging positions in the plan view are not the same and do not correspond. This indicates that multiple cylindrical patterns are formed in the underlying film after etching, confirming that the processing of the fifth embodiment is effective when the formation of such patterns is desired.

[0113] [7th Evaluation Test] The seventh evaluation test was conducted using the plasma processing module 7 to verify the preferred processing conditions for the O2 ashing in step S7A of the second embodiment, which prevent the pattern collapse described in Figure 17. In this evaluation test 7, different processing conditions were applied to wafers on which a developed resist film 12 was provided on the organic film, and the state of the organic film and resist pattern was confirmed. Specifically, the combination of the pressure inside the processing container 71 during wafer W processing, the power supplied from the second high-frequency power supply 87 (100 MHz) (HF power), the flow rate of O2 gas supplied into the processing container 71, and the flow rate of the gas (Ar gas or He gas) supplied into the processing container 71 along with the O2 gas was changed for each wafer W. Tests with different combinations of these conditions are designated as evaluation tests 7-1 to 7-5. The processing conditions for evaluation tests 7-1 to 7-5 are shown in Table 1 below. In this evaluation test 7, power (LF power) was not supplied from the first high-frequency power supply 86 (13 MHz). The processing time (plasma formation time) was set to 5 seconds. As Comparative Example 7, the state of the organic film and resist pattern on a wafer that had a developed resist film 12 on the organic film and had not undergone plasma treatment was also confirmed by acquiring SEM images, similar to wafer W in evaluation tests 7-1 to 7-5.

[0114] [Table 1]

[0115] Compared to wafer W of Comparative Example 7, the organic film on wafer W in evaluation tests 7-1 to 7-4 was etched relatively extensively. However, the organic film on wafer W in evaluation test 7-5 showed relatively suppressed etching, which was a favorable result. Figure 28 shows SEM images of the wafer top surface after testing for Comparative Example 7 and evaluation tests 7-1 to 7-5. The pattern in evaluation test 7-5 showed no pinching, similar to the pattern in Comparative Example 7, indicating a favorable condition.

[0116] Therefore, the results of this evaluation test 7 confirmed that good processing is possible by forming a plasma without supplying any gas other than O2 gas. Furthermore, the results of this evaluation test 7 indicated that it is preferable to set the pressure inside the processing container 71 higher than 10 mTorr, to 100 mTorr (13.3 Pa) or higher. It is thought that the etching of the underlying organic film was suppressed by setting the pressure inside the processing container 71 to a relatively high level because the amount of molecules in the gas remaining inside the processing container 71 is relatively large due to the high pressure, and the active species generated from the O2 gas by plasma formation collide with these molecules and the active species that have been plasma-formed from those molecules. In other words, it is thought that the active species generated from the O2 gas have difficulty reaching the organic film due to these collisions.

[0117] [8th Evaluation Test] In the eighth evaluation test, the range of power supplied by the second high-frequency power supply (HF) for O2 ashing that could reduce damage to the organic film on wafer W, as confirmed in the seventh evaluation test, was verified. In this evaluation test, the settings of the first high-frequency power supply (LF) of 0W, processing pressure of 13.3 Pa (100 mTorr), and O2 gas supply flow rate of 120 sccm, which yielded good results in the seventh evaluation test (7-5), were used as is, and the power supplied by the second high-frequency power supply 86 (100 MHz) was varied for each wafer W, with a processing time of 5 seconds. In this evaluation test, the power of the second high-frequency power supply 86 was set to 300W, 75W, 100W, 200W, and 500W.

[0118] Figure 29 shows SEM images of the wafer surface after each processing step of the 8th evaluation test. When O2 ashing was performed with the second high-frequency power supply 86 set to 300W and 500W, the organic film between patterns was significantly etched, and the alignment of the patterns was disrupted due to pattern collapse. When O2 ashing was performed with the second high-frequency power supply 86 set to 75W, 100W, and 200W, the pattern alignment of the resist film was maintained, and the removal of the organic film between patterns was suppressed. From the SEM image of the longitudinal section of wafer W (not shown), the amount of etching of the organic film improved as the HF power decreased. In other words, the 75W setting yielded the most favorable results. From the above, it was found that the power supplied to the plasma formation electrode by the second high-frequency power supply 87 is preferably 200W or less, and should be as low as possible. However, although not shown here, when the power of the second high-frequency power supply 87 was set to 50W, the plasma did not ignite, and no processing occurred. Therefore, it is preferable to set the power to, for example, greater than 50W.

[0119] [9th Evaluation Test] In the ninth evaluation test, tests were conducted to verify the effect of the O2 ashing treatment confirmed in the above evaluation tests. As evaluation tests 9-1 to 9-4, the O2 ashing treatment was performed on multiple wafers with the following settings: pressure in the treatment container 71 of 100 mTorr (13.3 Pa), power supplied from the first high-frequency power supply 86 of 0 W, power supplied from the second high-frequency power supply 87 of 100 W, flow rate of O2 gas supplied into the treatment container of 120 sccm, and processing time of 5 seconds. As evaluation tests 9-1 to 9-4, after the O2 ashing treatment, the He plasma treatment described as step S7 of the embodiment was performed. This He plasma treatment was performed with the following settings: processing time of 10 seconds, pressure in the treatment container 71 of 40000 Pa (300 Torr), flow rate of He gas supplied into the treatment container 71 of 900 sccm, and power supplied from the second high-frequency power supply 87 (HF) of 0 W. The power supplied from the first high-frequency power supply 86 (LF) was set to 3000W, 1500W, 1000W, and 500W in evaluation tests 9-1, 9-2, 9-3, and 9-4, under different conditions. SEM images of the wafer W after He plasma treatment were then acquired and verified.

[0120] Furthermore, as evaluation test 9-5, O2 ashing was performed on wafer W in the same manner as evaluation tests 9-1 to 9-4, and an SEM image of wafer W was acquired. Therefore, wafer W was not exposed to He gas plasma in evaluation test 9-5. Also, as evaluation test 9-6, wafer W was exposed to He gas plasma formed with the same settings as evaluation test 9-1. Therefore, the power supplied from the first high-frequency power supply 86 was set to 3000W to form the He gas plasma. Then, an SEM image of wafer W after processing was acquired. Therefore, O2 ashing was not performed in evaluation test 9-6. As comparative example 9, an SEM image was also acquired of a wafer in which a resist pattern was formed under the same conditions as evaluation tests 9-1 to 9-6, but without plasma processing.

[0121] Figure 30 shows SEM images of the wafer top surface for evaluation tests 9-1 to 9-6 and comparative example 9, respectively. In evaluation test 9-6, where He plasma treatment was performed without O2 ashing, the resist film was etched relatively extensively, and the resist pattern disappeared. However, in evaluation tests 9-1 to 9-4, where plasma treatment was performed after O2 ashing, the resist pattern remained, although pinching was observed compared to comparative example 9. This pinching became more pronounced as the power supplied from the first high-frequency power supply 86 increased. In evaluation test 9-5, where only O2 ashing was performed, the resist pattern remained. These results confirm that O2 ashing strengthened the resist pattern and increased its resistance to He plasma treatment. This increase in resistance is thought to be due to the promotion of Sn-synthesizing bond formation via oxygen by the detachment of hydrocarbon ligands from Sn, as described in the embodiment.

[0122] [10th Evaluation Test] In the 10th evaluation test, the processing container was kept under vacuum, and O2 gas was supplied to the wafer W stored in the processing container without plasma generation. SEM images of the wafer W were obtained before and after this gas supply, and Figure 31 is a schematic diagram of the side view of the wafer W before gas supply. The wafer W has a resist pattern formed on an amorphous carbon film underlayer 23. Specifically, the gas treatment described above involved supplying O2 gas for 5 seconds under vacuum. The pressure inside the processing container was set to 13.3 Pa, which is a suitable processing pressure for O2 ashing, and the wafer W was processed with different O2 gas concentrations and O2 gas flow rates. Although it was stated that O2 gas was supplied to the wafer W in this 10th evaluation test, some wafers W were supplied with a gas that did not contain O2 gas for comparison.

[0123] To evaluate the O2 gas concentration, the flow rates of O2 gas and N2 gas supplied to the processing container were varied to create different O2 gas concentrations within the container. The specific conditions were: O2 gas concentration 0% (O2 gas 0 sccm, N2 gas 120 sccm), O2 gas concentration 2% (O2 gas 2.4 sccm, N2 gas 117.6 sccm), O2 gas concentration 12.5% ​​(O2 gas 15 sccm, N2 gas 105 sccm), O2 gas concentration 25% (O2 gas 30 sccm, N2 gas 90 sccm), O2 gas concentration 50% (O2 gas 60 sccm, N2 gas 60 sccm), and O2 gas concentration 100% (O2 gas 120 sccm, N2 gas 0 sccm). In addition, the O2 gas flow rate was evaluated by supplying only O2 gas to the processing container and changing the O2 gas flow rate for each wafer W during processing. The flow rates of the O2 gas were set to 60 sccm, 90 sccm, 120 sccm, and 180 sccm. In the evaluation of these flow rates, only when the O2 gas flow rate was set to 60 sccm was the pressure inside the processing container set to 70 mTorr to 80 mTorr, and the processing time set to 1 minute, because the flow rate of the gas supplied in that manner was relatively small.

[0124] Figure 32 is a schematic diagram of an SEM image of the side surface of some wafers W. As shown in the figure, for some wafers W, a decrease in the thickness of the underlayer film 23 after processing compared to before processing was observed, resulting in a downward displacement of the upper surface position L1 of the underlayer film 23. As mentioned above, the underlayer film 23 is composed of carbon (amorphous carbon), so if a decrease in the thickness of this underlayer film 23 is confirmed, it can be presumed that the hydrocarbons in the resist film 12 have also been reduced.

[0125] Regarding the evaluation results of the O2 gas concentration, no change in the upper surface position L1 was observed when the O2 gas concentration was 0% (when N2 gas was supplied instead of O2 gas) and 2%. In treatments with high O2 concentrations of 12.5% ​​or higher, a downward displacement of the upper surface position L1 was confirmed. Furthermore, the amount of downward displacement increased as the O2 gas concentration increased. Therefore, it is estimated that the hydrocarbon reduction effect of the resist film 12 can be obtained when the O2 gas concentration is 12.5% ​​or higher, and that the hydrocarbon removal effect of the resist film 12 is enhanced by increasing the O2 gas concentration.

[0126] Furthermore, it has been confirmed that when air (i.e., gas with an O2 gas concentration of 20%) is supplied to the wafer W shown in Figure 31 under atmospheric pressure, no reduction in the thickness of the underlayer film 23 occurs. Therefore, in order to obtain the hydrocarbon reduction effect of this resist film 12, it has been found from these test results that it is effective to create a vacuum atmosphere inside the processing container where the wafer W is stored, at least when the O2 gas concentration is 20% or less.

[0127] Regarding the evaluation results of the O2 gas supply flow rate, a downward displacement of the upper surface position L1 was observed under each flow rate setting condition, and the amount of downward displacement increased as the O2 gas flow rate increased. As described above, the results suggest that the same effect as the O2 ashing treatment can be obtained by supplying non-plasma O2 gas instead of the O2 ashing treatment. [Explanation of Symbols]

[0128] W wafer 12. Resist film

Claims

1. A step of performing a reduction treatment on a substrate on which a resist film composed of a metal oxide resist has been formed after exposure and development to form a pattern, in order to reduce the hydrocarbons contained in the resist film, The process involves performing a treatment on the resist film that has undergone the reduction treatment in order to reduce its roughness, A substrate processing method including the following.

2. The reduction process described above is A process in which the resist film of the substrate placed in the processing container is exposed to a plasma-generated oxidizing gas, A process in which the resist film of the substrate placed in the processing container is exposed to an oxidizing gas that has not been plasma-treated. A process of irradiating the resist film with ultraviolet light, The substrate processing method according to claim 1, which is either a process of irradiating the resist film with an ion beam containing ions generated from an oxidizing gas.

3. The resist film is provided on the substrate on a carbon-containing underlayer film. The substrate processing method according to claim 2, wherein the reduction process involves exposing the resist film of the substrate, which is placed in the processing container at a pressure of 13.3 Pa or higher, to a plasma-generated oxidizing gas.

4. The resist film is provided on the substrate on a carbon-containing underlayer film. The reduction process involves exposing the resist film of the substrate placed in the processing container to a plasma-generated oxidizing gas. The substrate processing method according to claim 2, further comprising the step of supplying high-frequency power of 200 W or less to an electrode for forming the oxidizing gas plasma in order to form the plasma.

5. The reduction process described above is The substrate processing method according to claim 2, wherein an oxidizing gas that has not been plasma-formed is supplied to the resist film of the substrate placed in a processing container in which a vacuum atmosphere has been formed.

6. The substrate processing method according to any one of claims 1 to 5, wherein the oxidizing gas is oxygen gas.

7. The process for reducing the aforementioned roughness is: A process in which the resist film of the substrate placed in the processing container is exposed to a plasma-generated inert gas, The substrate processing method according to claim 1, which is either a process of irradiating the resist film with an ion beam of ions generated from an inert gas.

8. The substrate processing method according to claim 7, wherein the inert gas is helium gas.

9. The process for reducing the aforementioned roughness is: The process involves exposing the resist film of the substrate placed in the processing container to a plasma-generated inert gas. The substrate processing method according to claim 8, further comprising the step of supplying a high-frequency power greater than 1000 W to an electrode for forming the helium gas plasma in order to form the helium gas plasma.

10. A step of determining whether or not there is an abnormality in the aforementioned pattern, If it is determined that there is an abnormality in the pattern, the process of removing the resist film from the substrate, The substrate processing method according to claim 1, comprising the step of reforming the pattern on the substrate from which the resist film has been removed by forming the resist film again, exposing it, and developing it.

11. A process of placing a substrate on which a resist film, composed of a metal oxide resist and developed after exposure to form a pattern, is formed, into a processing container, The process of supplying an inert gas into the processing container, A step of supplying high-frequency power greater than 1000W to an electrode for plasma formation, forming the plasma of the inert gas, splitting the pattern, and shaping the pattern, A substrate processing method including the following.

12. The substrate processing method according to claim 11, further comprising the step of etching a lower layer film formed in the lower layer of the resist film on the substrate using the resist film having the shaped pattern as a mask.

13. A first processing unit performs a reduction treatment on a substrate on which a resist film is formed, which is composed of a metal oxide resist and which has a pattern formed on it after exposure and development, in order to reduce the hydrocarbons contained in the resist film. A second processing unit performs a process to reduce the roughness of the resist film that has undergone the reduction treatment, A substrate processing apparatus equipped with the following:

14. The reduction process described above is A process in which the resist film of the substrate placed in the processing container is exposed to a plasma-generated oxidizing gas, A process in which the resist film of the substrate placed in the processing container is exposed to an oxidizing gas that has not been plasma-treated. A process of irradiating the resist film with ultraviolet light, The substrate processing apparatus according to claim 13, which is either a process of irradiating the resist film with an ion beam of ions generated from an oxidizing gas.

15. The reduction process involves exposing the resist film of the substrate placed in the processing container to a plasma-generated oxidizing gas. The process for reducing the roughness involves exposing the resist film of the substrate placed in the processing container to a plasma-generated inert gas. The first processing unit and the second processing unit are: A gas supply mechanism that supplies the oxidizing gas and the inert gas into the processing container, A plasma formation mechanism for converting the gas supplied from the gas supply mechanism into plasma, Equipped with, The substrate processing apparatus according to claim 14, further comprising a control unit that controls the operation of the gas supply mechanism and the plasma formation mechanism so that the resist film is exposed to the plasma of the oxidizing gas and the plasma of the inert gas in that order.

16. The gas supply mechanism supplies a developing gas for developing the resist film, oxygen gas, and the inert gas into the processing container. The substrate processing apparatus according to claim 15, further comprising a control unit that controls the operation of the gas supply mechanism so that the gas supply mechanism supplies gas into the processing container in the order of developing gas, oxygen gas, and inert gas.

17. A film removal module for removing the resist film from the substrate, A resist film forming module for forming the resist film, A developing module that develops the resist film after exposure to form a pattern, An inspection module that acquires data for detecting anomalies in the aforementioned pattern, The system includes a control unit that determines whether or not there is an abnormality in the pattern based on the aforementioned data, The substrate processing apparatus according to claim 13, wherein, when it is determined that there is an abnormality in the pattern, the control unit controls the operation of the film removal module, the resist film formation module, and the developing module so that the resist film is removed by the film removal module, the resist film is formed again on the substrate from which the resist film has been removed by the resist film formation module, and the pattern is reformed by developing the exposed resist film by the developing module.

Images