Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can prevent semiconductor chips from being bonded in a tilted position. [Solution] The semiconductor device of the embodiment includes a semiconductor chip having a first chip surface and a second chip surface, a connector member having a joint and a connecting portion facing the first chip surface, and a lead frame facing the second chip surface. The connecting portion is connected to one end of the joint in the second direction and is located on the other side of the first direction as it moves toward the one side of the second direction. The joint has a first joint surface which is joined to the first chip surface by a first bonding material. The lead frame has a second joint surface which is joined to the second chip surface by a second bonding material. The first joint surface is provided with a first recess which is recessed on one side of the first direction and open on the other side of the second direction. A part of the first bonding material is housed in the first recess. The ratio of the dimension of the first recess in the second direction to the dimension of the joint in the second direction is 40% or more and 60% or less.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices are known in which one surface of a chip is joined to a lead frame by a bonding material such as solder, and the other surface of the chip is joined to a connector. In such a semiconductor device, when the connector has a bent portion that bends toward the lead frame side, when the bonding material is reflowed in the manufacturing process of the semiconductor device, the melted bonding material tends to flow toward the bent portion. If the chip is pulled by the bonding material flowing toward such a bent portion, there is a risk that the chip will be joined to the lead frame and the connector in a tilted state.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the joining of a semiconductor chip to a lead frame and a connector member in a tilted state.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a semiconductor chip having a first chip surface facing one side in a first direction and a second chip surface facing the other side in the first direction; a connector member having a bonding portion facing the first chip surface in a first direction and a connecting portion connected to the bonding portion; and a lead frame facing the second chip surface in a first direction. The connecting portion is connected to one end of the bonding portion in a second direction perpendicular to the first direction, and is located on the other side of the first direction as it moves toward one side of the second direction. The bonding portion has a first bonding surface that is bonded to the first chip surface by a first bonding material. The lead frame has a second bonding surface that is bonded to the second chip surface by a second bonding material. The first bonding surface is provided with a first recess that is recessed on one side in the first direction and open on the other side in the second direction. A part of the first bonding material is housed inside the first recess. The ratio of the dimension of the first recess in the second direction to the dimension of the bonding portion in the second direction is 40% or more and 60% or less. [Brief explanation of the drawing]

[0006] [Figure 1] A plan view showing a semiconductor device of one embodiment. [Figure 2] A cross-sectional view showing a semiconductor device of one embodiment, the II-II cross-sectional view of Figure 1. [Figure 3] A cross-sectional view showing a semiconductor device of one embodiment, specifically the cross-sectional view taken along line III-III in Figure 1. [Figure 4] A first cross-sectional view showing the manufacturing process of a semiconductor device according to one embodiment. [Figure 5] A first cross-sectional view showing the manufacturing process of a comparative example semiconductor device. [Figure 6] A second cross-sectional view showing the manufacturing process of the semiconductor device in the comparative example. [Figure 7] A second cross-sectional view showing the manufacturing process of a semiconductor device according to one embodiment. [Figure 8] A third cross-sectional view showing the manufacturing process of a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described below with reference to the drawings.

[0008] The first direction D1 shown in each drawing is the vertical direction of the semiconductor device. The side in which the arrow of the first direction D1 points (+D1 side) is the upper side of the semiconductor device. The side opposite to the direction in which the arrow of the first direction D1 points (-D1 side) is the lower side of the semiconductor device. In the following explanation, the vertical direction of the semiconductor device will be referred to as the "vertical direction" or "first direction D1", the upper side of the semiconductor device will be referred to as the "upper side" or "one side of the first direction D1", and the lower side of the semiconductor device will be referred to as the "lower side" or "the other side of the first direction D1".

[0009] The second direction D2 shown in each drawing is perpendicular to the first direction D1. In the following explanation, the side in which the arrow of the second direction D2 points (+D2 side) will be referred to as "one side of the second direction D2," and the side opposite to the side in which the arrow of the second direction D2 points (-D2 side) will be referred to as "the other side of the second direction D2."

[0010] The third direction D3 shown in each drawing is perpendicular to both the first direction D1 and the second direction D2. In the following explanation, the side to which the arrow of the third direction D3 points (+D3 side) will be referred to as "one side of the third direction D3," and the side opposite to the side to which the arrow of the third direction D3 points (-D3 side) will be referred to as "the other side of the third direction D3."

[0011] In this specification, terms such as "orthogonal," "identical," and "similar," as well as values ​​for length and angle, which specify the shape of each part constituting a semiconductor device and the degree of the relative arrangement between each part, shall not be strictly interpreted, but shall be interpreted to include a range within which similar functions can be expected and the range of design tolerances. Furthermore, each drawing is schematic and conceptual, and the dimensions of each part constituting the semiconductor device, as well as the ratios of dimensions between each part, are not necessarily identical to those of actual devices. Moreover, even when representing the same part, the dimensions and ratios may be represented differently in each drawing.

[0012] Figure 1 is a plan view showing the semiconductor device 10 of this embodiment. Figure 2 is a cross-sectional view showing the semiconductor device 10 of this embodiment, and is a cross-sectional view taken along line II-II in Figure 1. Figure 3 is a cross-sectional view showing the semiconductor device 10 of this embodiment, and is a cross-sectional view taken along line III-III in Figure 1. The semiconductor device 10 of this embodiment is a semiconductor device such as a MOSFET (metal-oxide-semiconductor field-effect transistor) and an IGBT (Insulated Gate Bipolar Transistor). As shown in Figure 1, the semiconductor device 10 comprises a semiconductor chip 20, a lead frame 30, a connector member 40, a second connector member 70, and electrode terminals 71 and 72. As shown in Figure 2, the semiconductor device 10 comprises a resin part 80.

[0013] In the vertical direction, the semiconductor chip 20 is positioned between the lead frame 30 and the connector member 40. The semiconductor chip 20 is plate-shaped, extending in a direction perpendicular to the vertical direction. The plate surface of the semiconductor chip 20 is oriented in the vertical direction. As shown in Figure 1, when viewed from the vertical direction, the semiconductor chip 20 is substantially rectangular, with two sides extending in a second direction D2 and the other two sides extending in a third direction D3. As shown in Figure 2, the semiconductor chip 20 has a substrate 21, a first electrode 22, a second electrode 23, a first chip surface 20a, and a second chip surface 20c. As shown in Figure 1, the semiconductor chip 20 has a third electrode 24.

[0014] The substrate 21 shown in Figure 2 is a semiconductor substrate made of semiconductor materials such as silicon, silicon carbide, gallium arsenide, and gallium nitride. Although not shown in the figure, when viewed from above, the substrate 21 has a roughly rectangular shape with two sides extending in a second direction D2 and the other two sides extending in a third direction D3.

[0015] The first electrode 22 is formed on the upper side of the substrate 21. In this embodiment, the first electrode 22 is the source electrode. The second electrode 23 is formed on the lower side of the substrate 21. As shown in Figure 1, the third electrode 24 is formed on the upper side of the substrate. The first electrode 22 and the third electrode 24 are spaced apart from each other in the second direction D2 and the third direction D3. As a result, the first electrode 22 and the third electrode 24 are insulated from each other. In this embodiment, the third electrode 24 is the gate electrode.

[0016] As shown in Figure 2, the first chip surface 20a is the upper surface of the outer surface of the semiconductor chip 20, that is, the surface facing one side of the first direction D1 (+D1 side). In this embodiment, the first chip surface 20a is composed of surfaces facing the upper side of the substrate 21, the first electrode 22, and the third electrode 24, respectively. The second chip surface 20c is the lower surface of the outer surface of the semiconductor chip 20, that is, the surface facing the other side of the first direction D1 (-D1 side). In this embodiment, the second chip surface 20c is composed of surfaces facing the lower side of the substrate 21 and the second electrode 23, respectively.

[0017] The lead frame 30 is plate-shaped, extending in a direction perpendicular to the vertical direction. The surface of the lead frame 30 is oriented in the vertical direction. The lead frame 30 is located below the semiconductor chip 20. The lead frame 30 faces the second chip surface 20c in the vertical direction, i.e., the first direction D1. As shown in Figure 1, when viewed from the vertical direction, the lead frame 30 is substantially rectangular, with two sides extending in the second direction D2 and the other two sides extending in the third direction D3. In this embodiment, the dimension of the lead frame 30 in the second direction D2 is larger than the dimension of the semiconductor chip 20 in the second direction D2, and the dimension of the lead frame 30 in the third direction D3 is larger than the dimension of the semiconductor chip 20 in the third direction D3. When viewed from the vertical direction, the outer edge of the lead frame 30 surrounds the outer edge of the semiconductor chip 20. The end of the lead frame 30 on the other side (-D2 side) of the second direction D2 is located on the other side of the second direction D2 than the end of the semiconductor chip 20 on the other side of the second direction D2. The lead frame 30 is conductive. In this embodiment, the lead frame 30 is made of copper. The lead frame 30 is manufactured, for example, by press-forming a copper sheet. The lead frame 30 may also be made of other metallic materials such as silver and gold. As shown in Figure 2, the lead frame 30 has a second bonding surface 30a.

[0018] The second bonding surface 30a is the surface facing upward among the outer surfaces of the lead frame 30. The second bonding surface 30a is bonded to the second chip surface 20c by the second bonding material 60. Thereby, the lead frame 30 and the semiconductor chip 20 are bonded. In the present embodiment, the second bonding material 60 is solder. The second bonding material 60 is an alloy containing metals such as tin and lead. As will be described later, the second bonding material 60 is formed by solidifying the liquid second bonding material 60L melted by reflowing the paste-like second bonding material 60P. Note that the second bonding material 60 may be solder containing other metal materials such as antimony and gold. Further, the second bonding material 60 may be a bonding material composed of, for example, resins such as epoxy resin and polyimide resin, and metal particles such as copper and silver dispersed in such resins. The second bonding material 60 has conductivity. Therefore, the lead frame 30 and the second electrode 23 are electrically connected via the second bonding material 60.

[0019] A second recess 31 is provided in the second bonding surface 30a. The second recess 31 is a depression that recesses downward from the second bonding surface 30a, that is, to the other side (-D1 side) in the first direction D1. A part of the second bonding material 60 is accommodated inside the second recess 31. The second recess 31 is provided in a portion on the other side (-D2 side) in the second direction D2 of the second bonding surface 30a. As shown in FIGS. 1 and 2, when viewed from the first direction D1, the second recess 31 overlaps with the edge portion on the other side in the second direction D2 of the semiconductor chip 20.

[0020] As shown in FIG. 3, the second recess 31 extends in the third direction D3. In the present embodiment, the dimension L23 of the second recess 31 in the third direction D3 is equal to or less than the dimension Lc3 of the semiconductor chip 20 in the third direction D3. In the present embodiment, the dimension L23 of the second recess 31 in the third direction D3 is the same as the dimension Lc3 of the semiconductor chip 20 in the third direction D3. The dimension L23 of the second recess 31 in the third direction D3 may be smaller than the dimension Lc3 of the semiconductor chip 20 in the third direction D3. Further, in the present embodiment, when viewed from the vertical direction, the edge on one side (+D3 side) of the second recess 31 in the third direction D3 overlaps with the edge on one side of the semiconductor chip 20 in the third direction D3, and when viewed from the vertical direction, the edge on the other side (-D3 side) of the second recess 31 in the third direction D3 overlaps with the edge on the other side of the semiconductor chip 20 in the third direction D3. When the dimension L23 of the second recess 31 in the third direction D3 is smaller than the dimension Lc3 of the semiconductor chip 20 in the third direction D3, it is preferable that the edge on one side of the second recess 31 in the third direction D3 is located on the other side in the third direction D3 than the edge on one side of the semiconductor chip 20 in the third direction D3, and the edge on the other side of the second recess 31 in the third direction D3 is located on the one side in the third direction D3 than the edge on the other side of the semiconductor chip 20 in the third direction D3. Thereby, in the reflow process P02 described later, it is possible to suppress the liquid second bonding material 60L from leaking out from the gap between the second recess 31 and the semiconductor chip 20 to the second bonding surface 30a. Therefore, it is possible to suppress a decrease in the adhesive strength between the lead frame 30 and the resin portion 80. The dimension L23 of the second recess 31 in the third direction D3 may be larger than the dimension Lc3 of the semiconductor chip 20 in the third direction D3. As shown in FIG. 2, the second recess 31 has a first portion 31a, a second portion 31c, and a second inner surface 33.

[0021] The first portion 31a is the portion of the second recess 31 on one side (+D2 side) in the second direction D2. More specifically, the first portion 31a is the portion of the second recess 31 that overlaps with the semiconductor chip 20 when viewed from the vertical direction, i.e., the first direction D1. In this embodiment, one end of the first portion 31a in the second direction D2 is located on the other side (-D2 side) of the second direction D2 than the central part of the semiconductor chip 20 in the second direction D2 and the central part of the lead frame 30 in the second direction D2. In this embodiment, the third ratio R3, which is the ratio of the dimension Lp1 of the first portion 31a in the second direction D2 to the dimension Lc2 of the semiconductor chip 20 in the second direction D2, is 25% or more and 33% or less. The third ratio R3 may be less than 25% or greater than 33%.

[0022] The second portion 31c is the portion of the second recess 31 on the other side (-D2 side) of the second direction D2. More specifically, the second portion 31c is the portion of the second recess 31 that is located on the other side of the second direction D2 from the semiconductor chip 20 when viewed from the vertical direction, i.e., the first direction D1. In other words, the second portion 31c is located on the other side of the second direction D2 from the semiconductor chip 20. The second portion 31c is connected to the first portion 31a in the second direction D2. In this embodiment, the dimension Lp2 of the second portion 31c in the second direction D2 is 0.05 mm or more and 0.15 mm or less. The dimension Lp2 of the second portion 31c in the second direction D2 may be less than 0.05 mm or greater than 0.15 mm.

[0023] The second inner surface 33 is the upper surface of the inner surface of the second recess 31, that is, the surface facing one side of the first direction D1 (+D1 side). As shown in Figure 3, the second inner surface 33 extends in the third direction D3. As shown in Figure 2, the second inner surface 33 has a third inner surface portion 33a and a fourth inner surface portion 33c.

[0024] The third inner surface portion 33a is the portion of the second inner surface portion 33 on one side (+D2 side) of the second direction D2. The third inner surface portion 33a is an inclined surface located on the lower side, i.e., on the other side (-D1 side) of the first direction D1, as it extends from the end of the second inner surface portion 33 on one side of the second direction D2 toward the other side (-D2 side) of the second direction D2. In this embodiment, the third inner surface portion 33a is a flat surface that extends linearly between the lower side and the other side of the second direction D2 when viewed from the third direction D3. The third inner surface portion 33a may also be a curved surface that extends curvely between the lower side and the other side of the second direction D2 when viewed from the third direction D3.

[0025] The fourth inner surface portion 33c is the portion of the second inner surface portion 33 on the other side (-D2 side) of the second direction D2. The fourth inner surface portion 33c is an inclined surface located on the other side (-D1 side) of the first direction D1, as it extends downward from the other end of the second inner surface portion 33 toward one side (+D2 side) of the second direction D2. In this embodiment, the fourth inner surface portion 33c is a flat surface that extends linearly between the downward side and one side of the second direction D2 when viewed from the third direction D3. The end of the fourth inner surface portion 33c on one side of the second direction D2 connects to the other end of the third inner surface portion 33a on the second side of the second direction D2. Therefore, in this embodiment, the second inner surface portion 33 has a V-shape that protrudes downward when viewed from the third direction D3. The fourth inner surface portion 33c may also be a curved surface that extends curvely between the downward side and one side of the second direction D2 when viewed from the third direction D3.

[0026] In this embodiment, the maximum dimension L2max of the second recess 31 in the first direction D1 is 15 μm or more. The maximum dimension L2max of the second recess 31 in the first direction D1 is the maximum depth of the second recess 31. In this embodiment, the maximum dimension L2max is the distance in the first direction D1 between the portion where the third inner surface 33a and the fourth inner surface 33c connect and the second bonding surface 30a. In this embodiment, in the second direction D2, the portion where the third inner surface 33a and the fourth inner surface 33c connect is located near the edge of the semiconductor chip 20 and the second electrode 23 on the other side (-D2 side) of the second direction D2. In other words, the deepest part of the second recess 31 is located near the edge of the second electrode 23 on the other side of the second direction D2.

[0027] The connector member 40 is plate-shaped and extends in the second direction D2. The connector member 40 is conductive. In this embodiment, the connector member 40 is made of copper. The connector member 40 is manufactured, for example, by press-forming a copper plate. The connector member 40 may also be made of other metallic materials such as silver and gold. The connector member 40 has a joint portion 41, a connecting portion 46, and a terminal portion 47.

[0028] The junction 41 is located above the semiconductor chip 20. The surface of the junction 41 is oriented in the vertical direction. The junction 41 faces the first chip surface 20a in the vertical direction, i.e., the first direction D1. As shown in Figure 1, the junction 41 extends in the second direction D2. One end of the junction 41 in the third direction D3 (+D3 side) is located on the other side of the third direction D3 (-D3 side) than one end of the semiconductor chip 20 in the third direction D3. The other end of the junction 41 in the third direction D3 is located on one side of the third direction D3 than the other end of the semiconductor chip 20 in the third direction D3. The other end of the junction 41 in the second direction D2 (-D2 side) is located on one side of the second direction D2 (+D2 side) than the other end of the semiconductor chip 20 in the second direction D2. One end of the junction 41 in the second direction D2 is located one side in the second direction D2 than one end of the semiconductor chip 20 in the second direction D2. A notch is provided on one side of the junction 41 in the second direction D2 and the other side in the third direction D3. As a result, when viewed from above, the junction 41 does not overlap with the third electrode 24. As shown in Figure 2, the junction 41 has a first bonding surface 41a.

[0029] The first bonding surface 41a is the downward-facing surface of the outer surface of the bonding portion 41. The first bonding surface 41a is bonded to the first chip surface 20a by the first bonding material 50. This bonds the connector member 40 and the semiconductor chip 20. In this embodiment, the first bonding material 50 is solder. The first bonding material 50 is an alloy containing metals such as tin and lead. As will be described later, the first bonding material 50 is formed by solidifying a molten liquid first bonding material 50L obtained by reflowing a paste-like first bonding material 50P. The first bonding material 50 is conductive. Therefore, the connector member 40 and the first electrode 22 are electrically connected via the first bonding material 50. In other words, the connector member 40 is electrically connected to the semiconductor chip 20 via the first bonding material 50.

[0030] A first recess 42 is provided in the first joint surface 41a. The first recess 42 is a recess that extends upward from the first joint surface 41a, i.e., to one side in the first direction D1 (+D1 side). The first recess 42 is provided in the portion of the first joint surface 41a on the other side in the second direction D2 (-D2 side). The first recess 42 is open to the other side in the second direction D2. As shown in Figure 3, the first recess 42 is open to both sides in the third direction D3. As shown in Figure 2, a part of the first joint material 50 is housed inside the first recess 42. As shown in Figure 3, the first ratio R1, which is the ratio of the vertical dimension L11 of the first recess 42 to the vertical dimension Lj1 of the joint 41, i.e., the dimension Lj1 in the first direction D1, is 40% or more and 60% or less. The first ratio R1 may be less than 40% or greater than 60%. As shown in Figure 2, in this embodiment, the second ratio R2, which is the ratio of the dimension L12 of the first recess 42 in the second direction D2 to the dimension Lj2 of the joint 41 in the second direction D2, is 40% or more and 60% or less. The second ratio R2 may be less than 40% or greater than 60%. The first recess 42 has a first inner surface 43.

[0031] The first inner surface 43 is the lower side of the inner surface of the first recess 42, that is, the surface facing the other side of the first direction D1 (-D1 side). The first inner surface 43 extends in the second direction D2. As shown in Figure 3, the first inner surface 43 has a first inner surface portion 43a and a second inner surface portion 43c.

[0032] The first inner surface portion 43a is the portion of the first inner surface 43 on one side (+D3 side) in the third direction D3. The first inner surface portion 43a is an inclined surface located on the lower side, i.e., on the other side (-D1 side) of the first direction D1, as it extends from the end of the first inner surface 43 on one side in the third direction D3 toward the other side (-D3 side) of the third direction D3. In this embodiment, the first inner surface portion 43a is a flat surface that extends linearly between the lower side and the other side of the third direction D3 when viewed from the second direction D2. The first inner surface portion 43a may also be a curved surface that extends curvely between the lower side and the other side of the third direction D3 when viewed from the second direction D2.

[0033] The second inner surface portion 43c is the portion of the first inner surface portion 43 on the other side (-D3 side) of the third direction D3. The second inner surface portion 43c is an inclined surface located on the other side (-D1 side) of the first inner surface portion 43, as it extends downward from the other end of the first inner surface portion 43 toward one side (+D3 side) of the third direction D3, i.e., toward the other side (-D1 side) of the first direction D1. In this embodiment, the second inner surface portion 43c is a flat surface that extends linearly between the downward side and one side of the third direction D3 when viewed from the second direction D2. One end of the second inner surface portion 43c toward the third direction D3 connects to the other end of the first inner surface portion 43a toward the third direction D3. In this embodiment, the portion where the first inner surface portion 43a and the second inner surface portion 43c connect is located in the central part of the first inner surface portion 43 toward the third direction D3. In this embodiment, the first inner surface portion 43 is V-shaped, projecting downward when viewed from the second direction D2. Furthermore, the second inner surface portion 43c may be a curved surface that extends in a curved shape between the lower side and one side of the third direction D3 when viewed from the second direction D2.

[0034] The first inner surface 43 does not necessarily have to have either the first inner surface portion 43a or the second inner surface portion 43c. For example, if the first inner surface 43 does not have the second inner surface portion 43c, it is preferable that the first inner surface portion 43a is an inclined surface connected to one end of the first inner surface 43 in the third direction D3 (+D3 side) and the other end of the first inner surface 43 in the third direction D3 (-D3 side). Similarly, for example, if the first inner surface 43 does not have the first inner surface portion 43a, it is preferable that the second inner surface portion 43c is an inclined surface connected to the other end of the first inner surface 43 in the third direction D3 and the one end of the first inner surface 43 in the third direction D3.

[0035] As shown in Figure 2, the connecting portion 46 is plate-shaped and is located on the lower side as it moves toward one side of the second direction D2 (+D2 side), that is, on the other side of the first direction D1 (-D1 side). The end of the connecting portion 46 on the other side of the second direction D2 (-D2 side) is connected to the end of the joint portion 41 on one side of the second direction D2.

[0036] The terminal portion 47 is plate-shaped and extends from one end of the connection portion 46 in the second direction D2 (+D2 side) to the other end in the second direction D2. The plate surface of the terminal portion 47 is oriented in the vertical direction. The terminal portion 47 is joined to the electrode terminal 71 by a bonding material (not shown). As a result, the connector member 40 is electrically connected to the electrode terminal 71. In this embodiment, the electrode terminal 71 is, for example, a source terminal used for connecting the semiconductor device 10 to the outside. The electrode terminal 71 is spaced apart from the lead frame 30 in the second direction D2. The electrode terminal 71 is made of metal. The electrode terminal 71 is conductive. As described above, the connector member 40 is electrically connected to the semiconductor chip 20. Therefore, the semiconductor chip 20 is electrically connected to the electrode terminal 71.

[0037] As shown in Figure 1, the second connector member 70 is plate-shaped and extends in the second direction D2. The second connector member 70 is conductive. In this embodiment, the second connector member 70 is made of copper. The second connector member 70 is manufactured, for example, by press-forming a copper plate. One end of the second connector member 70 is joined to the third electrode 24 of the semiconductor chip 20 by a bonding material (not shown). The other end of the second connector member 70 is joined to the electrode terminal 72 by a bonding material (not shown). In this way, the semiconductor chip 20 and the electrode terminal 72 are electrically connected via the second connector member 70. In this embodiment, the electrode terminal 72 is, for example, a gate terminal used for connection to the outside of the semiconductor device 10. The electrode terminal 72 is spaced apart from the lead frame 30 and the electrode terminal 71, respectively. The electrode terminal 72 is made of metal. The electrode terminal 72 is conductive.

[0038] The resin portion 80 shown in Figures 2 and 3 covers the semiconductor chip 20, the parts of the lead frame 30 other than the downward-facing surface, the connector member 40, the second connector member 70, and the parts of the electrode terminals 71 and 72 other than the downward-facing surfaces. The resin portion 80 is adhesively fixed to the semiconductor chip 20, the parts of the lead frame 30 other than the downward-facing surface, the connector member 40, the second connector member 70, and the parts of the electrode terminals 71 and 72 other than the downward-facing surfaces. The resin portion 80 insulates the various parts that constitute the semiconductor device 10 from each other. In addition, the resin portion 80 seals the various parts that constitute the semiconductor device 10 from the outside air. This prevents the various parts that constitute the semiconductor device 10 from deteriorating due to corrosion, etc. As the resin portion 80, for example, known epoxy resins, ultraviolet curable resins, and thermosetting resins can be used, but are not limited to these. In this embodiment, the resin portion 80 is made of epoxy resin.

[0039] Figure 4 is a first cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 5 is a first cross-sectional view showing the manufacturing process of a comparative example semiconductor device 110. Figure 6 is a second cross-sectional view showing the manufacturing process of a comparative example semiconductor device 110. Figure 7 is a second cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 8 is a third cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment.

[0040] Next, the manufacturing process of the semiconductor device 10 of this embodiment will be described. The manufacturing process of the semiconductor device 10 of this embodiment includes a coating step P01 in which a paste-like first bonding material 50P is applied to the first chip surface 20a of the semiconductor chip 20 and a paste-like second bonding material 60P is applied to the second chip surface 20c, a reflow step P02 in which the first bonding material 50P and the second bonding material 60P are reflowed, and a resin part molding step P03 in which the resin part 80 is molded. In the following description, "workers, etc." includes workers who perform the work in each step and assembly equipment, etc. The work in each step may be performed by workers alone, by assembly equipment alone, or by workers and assembly equipment.

[0041] In coating step P01, the worker first applies a paste-like first bonding material 50P to the first chip surface 20a of the semiconductor chip 20, as shown in Figure 4, and then applies a paste-like second bonding material 60P to the second chip surface 20c. In this embodiment, each of the first bonding material 50P and the second bonding material 60P is composed of solder particles containing tin and lead and flux. In this embodiment, the flux is, for example, rosin. The flux plays a role in increasing the wettability between the semiconductor chip 20, the lead frame 30, and the connector member 40 and the molten first bonding material 50L and second bonding material 60L.

[0042] Next, the worker places the semiconductor chip 20 on the second bonding surface 30a of the lead frame 30. This causes the second bonding material 60P to come into contact with the second chip surface 20c and the second bonding surface 30a, respectively. Next, the worker places the connector member 40 on the first chip surface 20a of the semiconductor chip 20. This causes the first bonding material 50P to come into contact with the first chip surface 20a and the first bonding surface 41a, respectively. Once the worker places the connector member 40 on the first chip surface 20a, the coating process P01 is completed. In the following description, the semiconductor device 10 at the end of the coating process P01 may be referred to as the semiconductor device 10b before bonding.

[0043] In the reflow process P02, the first bonding material 50P and the second bonding material 60P are reflowed. This bonds the semiconductor chip 20 to the lead frame 30 and the connector member 40 to the semiconductor chip 20. In the reflow process P02, the operator heats the semiconductor device 10b before bonding in a heating furnace (not shown), for example in a vacuum, to melt the paste-like first bonding material 50P and the second bonding material 60P. Then, the semiconductor device 10b before bonding is removed from the heating furnace and cooled, causing the liquid first bonding material 50L and the second bonding material 60L to solidify, thereby bonding the semiconductor chip 20 to the lead frame 30 and the connector member 40 to the semiconductor chip 20.

[0044] In the comparative example semiconductor device 110 shown in Figure 5, the second bonding surface 130a of the lead frame 130 does not have a second recess. Furthermore, in the semiconductor device 110, the first bonding surface 141a of the bonding portion 141 of the connector member 140 does not have a first recess. Therefore, in the reflow process P02 of the semiconductor device 110b before bonding in the comparative example, as shown in Figure 6, the molten liquid first bonding material 50L flows easily toward the connection portion 46, and the semiconductor chip 20 is pulled by the liquid first bonding material 50L flowing toward the connection portion 46. As a result, the semiconductor chip 20 becomes tilted, with the orientation of the first chip surface 20a facing from the top toward one side of the second direction D2 (+D2 side). In this state, when the first bonding material 50L and the second bonding material 60L solidify, the semiconductor chip 20 is bonded to the lead frame 30 and the connector member 40 in a tilted state. In this case, the amount of the second bonding material 60L in the portion of the second chip surface 20c on the other side (-D2 side) of the second direction D2 is likely to be insufficient. Therefore, there is a risk that the adhesive strength between the portion of the second chip surface 20c on the other side (-D2 side) of the second direction D2 and the second bonding surface 30a will decrease. Consequently, there is a risk that the bonding strength between the semiconductor chip 20 and the lead frame 30 will decrease.

[0045] Furthermore, during the reflow process P02, when the flux and water (not shown) contained in the paste-like first bonding material 50P and the second bonding material 60P vaporize, voids B1 (air gaps) are generated inside the liquid first bonding material 50L, and voids B2 (air gaps) are generated inside the liquid second bonding material 60L. During the reflow process P02, voids B2 tend to accumulate on the other side (+D2 side) of the second direction D2 of the second bonding material 60L. As described above, since the reflow of the first bonding material 50P and the second bonding material 60P is performed in a vacuum, voids B1 move to the end of the first bonding material 50L and are released to the outside of the first bonding material 50L. Similarly, voids B2 move to the end of the second bonding material 60L and are released to the outside of the second bonding material 60L. However, in the reflow process P02, when the semiconductor chip 20 is tilted as described above, the vertical distance between the semiconductor chip 20 on the other side (-D2 side) of the second direction D2 and the connector member 40 becomes smaller. Therefore, void B1 is less likely to move to the other side of the second direction D2 and is less likely to be released from the other end of the first bonding material 50L in the second direction D2. As a result, there is a risk that a large amount of void B1 will remain inside the hardened first bonding material 50. As described above, since voids B1 and B2 are air gaps, the electrical resistivity of voids B1 and B2 is greater than the electrical resistivity of solder. As a result, if a large amount of void B1 remains inside the first bonding material 50, the electrical resistance of the first bonding material 50 increases, and the current that can be conducted decreases. Consequently, the operating area of ​​the semiconductor device 110 becomes narrower. In the comparative example semiconductor device 110, the void B2 is emitted from the other end of the second bonding material 60L in the second direction D2.

[0046] In contrast to these, in the semiconductor device 10 of this embodiment, as described above, a first recess 42 is provided on the first bonding surface 41a of the joint portion 41 of the connector member 40. Therefore, in the reflow process P02, as shown in Figure 7, the molten liquid first bonding material 50L flows into the first recess 42, which suppresses the flow of the first bonding material 50L toward the connection portion 46. This prevents the semiconductor chip 20 from becoming tilted. Consequently, it is possible to suppress a shortage of the amount of the second bonding material 60L in the other side (-D2 side) of the second chip surface 20c in the second direction D2, and thus suppress a decrease in the bonding strength between the semiconductor chip 20 and the lead frame 30.

[0047] Furthermore, in this embodiment, since a first recess 42 is provided in the first bonding surface 41a, the vertical distance between the first inner surface 43 and the first chip surface 20a can be increased. As a result, voids B1 can easily move into the first recess 42. As described above, since voids B1 are air gaps, the specific gravity of voids B1 is smaller than that of solder. Therefore, in the reflow process P02, voids B1 that have moved into the first recess 42 move along the first inner surface 43 to the other side (-D2 side) of the second direction D2. Also, as described above, the first recess 42 is open to the other side of the second direction D2. As a result, voids B1 that have moved to the other end of the first bonding material 50L in the second direction D2 are released to the outside of the first bonding material 50L from the other end of the first bonding material 50L in the second direction D2. Therefore, in this embodiment, the amount of voids B1 remaining inside the first bonding material 50 can be suitably reduced. This effectively suppresses an increase in the electrical resistance of the first bonding material 50.

[0048] Furthermore, as described above, the first inner surface 43 has a first inner surface portion 43a. Therefore, as shown in Figure 8, in the reflow process P02, a portion of the void B1 that has moved into the first recess 42 is more likely to move along the first inner surface portion 43a to one side of the third direction D3 (+D3 side). In other words, the first inner surface portion 43a guides the movement of the void B1 to one side of the third direction D3. As a result, the void B1 moves to one end of the first bonding material 50L in the third direction D3 and is released to the outside of the first bonding material 50L from that end. Therefore, in this embodiment, the amount of void B1 remaining inside the first bonding material 50 can be more effectively reduced. This makes it more effective to suppress an increase in the electrical resistance of the first bonding material 50.

[0049] Furthermore, as described above, the first inner surface 43 has a second inner surface portion 43c. Therefore, in the reflow process P02, a portion of the void B1 that has moved into the first recess 42 is more likely to move along the second inner surface portion 43c to the other side of the third direction D3 (-D3 side). In other words, the second inner surface portion 43c guides the movement of the void B1 to the other side of the third direction D3. As a result, the void B1 moves to the other end of the first bonding material 50L in the third direction D3 and is released to the outside of the first bonding material 50L from the other end of the first bonding material 50L in the third direction D3. Therefore, in this embodiment, the amount of void B1 remaining inside the first bonding material 50 can be more effectively reduced. This effectively suppresses an increase in the electrical resistance of the first bonding material 50.

[0050] As shown in Figure 7, in this embodiment, a burr 23a protruding downward is formed on the edge of the second electrode 23 on the other side (-D2 side) of the second direction D2. The burr 23a is formed, for example, when dicing the semiconductor chip 20. The vertical dimension of the burr 23a is approximately 15 μm at most. Although not shown in the figure, if the second recess 31 is not provided on the second bonding surface 30a, the vertical distance between the burr 23a and the second bonding surface 30a becomes small, making it difficult for the void B2 to move to the other side of the second direction D2 inside the second bonding material 60L. Therefore, it is difficult to release the void B2 to the outside of the second bonding material 60L, and there is a risk that a large amount of void B2 will remain inside the second bonding material 60. In contrast, in this embodiment, the second recess 31 is provided on the second bonding surface 30a. Therefore, in the reflow process P02, the molten liquid second bonding material 60L flows into the interior of the second recess 31. Also, as described above, when viewed from above, the second recess 31 overlaps with the other edge of the semiconductor chip 20 in the second direction D2. As a result, even if a burr 23a is formed on the second electrode 23, the vertical distance between the burr 23a and the second inner surface 33 can be increased, so that the void B2 can bypass the underside of the burr 23a and move toward the other end of the second bonding material 60L in the second direction D2. As a result, the void B2 is released to the outside of the second bonding material 60L from the other end of the second direction D2. Therefore, in this embodiment, the amount of void B2 remaining inside the second bonding material 60 can be suitably reduced. As a result, the increase in the electrical resistance of the second bonding material 60 can be suitably suppressed. As described above, in this embodiment, the increase in the electrical resistance of the first bonding material 50 can be suitably suppressed. These measures prevent a decrease in the current that can be conducted through the semiconductor device 10, thereby preventing a narrowing of the operating range of the semiconductor device 10.

[0051] Next, the workers reflow the paste-like first bonding material 50P and the second bonding material 60P, respectively, and then remove the semiconductor device 10b from the heating furnace and let it cool. As a result, the liquid first bonding material 50L and the second bonding material 60L solidify, and the semiconductor chip 20 is bonded to the lead frame 30, and the connector member 40 is bonded to the semiconductor chip 20. Once the semiconductor chip 20 is bonded to the lead frame 30 and the connector member 40 is bonded to the semiconductor chip 20, the reflow process P02 is completed.

[0052] In the resin part molding process P03, the worker molds the resin part 80. In this embodiment, as shown in Figures 2 and 3, the semiconductor chip 20, the parts of the lead frame 30 other than the downward-facing surface, the connector member 40, the second connector member 70, and the parts of the electrode terminals 71 and 72 other than the downward-facing surfaces are covered with the resin part 80 by a molding method such as transfer molding, and then the resin part 80 is formed by hardening it, for example by heating. As described above, the resin part 80 is adhesively fixed to the semiconductor chip 20, the parts of the lead frame 30 other than the downward-facing surface, the connector member 40, the second connector member 70, and the parts of the electrode terminals 71 and 72 other than the downward-facing surfaces. Once the resin part 80 has hardened, the resin part molding process P03 is completed. When the resin part molding process P03 is completed, the manufacturing process of the semiconductor device 10 is completed, and the semiconductor device 10 shown in Figures 2 and 3 is manufactured.

[0053] According to this embodiment, the semiconductor device 10 comprises a semiconductor chip 20 having a first chip surface 20a facing upward, i.e., one side of the first direction D1 (+D1 side) and a second chip surface 20c facing downward, i.e., the other side of the first direction D1 (-D1 side); a connector member 40 having a joint portion 41 facing the first chip surface 20a in the first direction D1 and a connecting portion 46 connected to the joint portion 41; and a lead frame 30 facing the second chip surface 20c in the first direction D1. The connecting portion 46 is connected to the end of the joint portion 41 on one side of the second direction D2 (+D2 side) and is located downward as it moves toward one side of the second direction D2. The joint portion 41 has a first joint surface 41a which is joined to the first chip surface 20a by a first bonding material 50, and the lead frame 30 has a second joint surface 30a which is joined to the second chip surface 20c by a second bonding material 60. The first bonding surface 41a is provided with a first recess 42 that is recessed on the upper side and open to the other side in the second direction (-D2 side), and a portion of the first bonding material 50 is contained inside the first recess 42. Therefore, as described above, in the reflow process P02, the molten liquid first bonding material 50L flows into the first recess 42, so that the flow of the first bonding material 50L toward the connection portion 46 can be suppressed. Thus, it is possible to suppress the semiconductor chip 20 from being bonded to the lead frame 30 and connector member 40 in a tilted state. Furthermore, as described above, it is possible to suppress the amount of the second bonding material 60L in the portion of the second chip surface 20c on the other side in the second direction D2, so that the bonding strength between the semiconductor chip 20 and the lead frame 30 does not decrease.

[0054] Furthermore, in this embodiment, the first bonding surface 41a is provided with a first recess 42 that is open to the other side (-D2 side) of the second direction D2. Therefore, even if the semiconductor chip 20 is tilted during the reflow process P02, it is possible to prevent the vertical distance between the portion of the first chip surface 20a on the other side (-D2 side) of the second direction D2 and the first inner surface 43 from becoming too small. This allows the voids B1 generated inside the first bonding material 50L during the reflow process P02 to be suitably moved to the other end of the first bonding material 50L in the second direction D2. As a result, the voids B1 can be suitably released to the outside of the first bonding material 50L from the other end of the first bonding material 50L in the second direction D2. Consequently, the amount of voids B1 remaining inside the first bonding material 50 can be suitably reduced, thus suitably suppressing an increase in the electrical resistance of the first bonding material 50. These measures prevent a decrease in the current that can be conducted through the semiconductor device 10, thereby preventing a narrowing of the operating range of the semiconductor device 10.

[0055] In this embodiment, the second ratio R2, which is the ratio of the dimension L12 of the first recess 42 in the second direction to the dimension Lj2 of the joint 41 in the second direction D2, is 40% or more and 60% or less. In the reflow process P02, voids B1 generated inside the liquid first bonding material 50L tend to accumulate near the center of the first bonding material 50L. In contrast, in this embodiment, since the second ratio R2 is 40% or more and 60% or less, the end of one side (+D2 side) of the first recess 42 in the second direction D2 can be positioned near the center of the first bonding material 50L. As a result, in the reflow process P02, the voids B1 inside the first bonding material 50L can be suitably moved into the first recess 42, and the amount of voids B1 released from the first bonding material 50L can be more suitably increased. Therefore, the amount of void B1 remaining inside the first bonding material 50 can be more effectively reduced, and thus the increase in the electrical resistance of the first bonding material 50 can be more effectively suppressed.

[0056] According to this embodiment, the first recess 42 is open on both sides in the third direction D3, and the first inner surface 43, which is the lower side of the inner surface of the first recess 42, that is, the surface facing the other side of the first direction D1 (-D1 side), has a first inner surface portion 43a that is located downwards as it moves from the end of the first inner surface 43 on one side in the third direction D3 (+D3 side) toward the other side in the third direction D3 (-D3 side). Therefore, as described above, in the reflow process P02, the void B1 generated inside the molten liquid first bonding material 50L is easily moved along the first inner surface portion 43a toward one side in the third direction D3. This makes it possible to suitably increase the amount of void B1 released from the end of the first bonding material 50L on one side in the third direction D3 toward the outside of the first bonding material 50L. Therefore, the amount of void B1 remaining inside the first bonding material 50 can be more effectively reduced, and thus the increase in the electrical resistance of the first bonding material 50 can be more effectively suppressed.

[0057] According to this embodiment, the first inner surface 43 has a second inner surface portion 43c located on the other side (-D3 side) of the first inner surface 43 as it moves from the other side (-D3 side) of the third direction D3 toward one side (+D3 side) of the third direction D3, i.e., on the other side (-D1 side) of the first direction D1. The end of the second inner surface portion 43c toward one side of the third direction D3 connects to the other end of the first inner surface portion 43a toward the third direction D3. Therefore, as described above, in the reflow process P02, voids B1 generated inside the molten liquid first bonding material 50L are easily moved toward the other side of the third direction D3 along the second inner surface portion 43c. This makes it possible to suitably increase the amount of voids B1 released from the other end of the first bonding material 50L toward the outside of the first bonding material 50L toward the other side (-D1 side). Therefore, the amount of void B1 remaining inside the first bonding material 50 can be more effectively reduced, and thus the increase in the electrical resistance of the first bonding material 50 can be more effectively suppressed.

[0058] According to this embodiment, the first ratio R1, which is the ratio of the vertical dimension L11 of the first recess 42 to the vertical dimension Lj1 of the joint 41, i.e., the dimension in the first direction D1, is 40% or more and 60% or less. If the first ratio R1 is less than 40%, the volume of the first recess 42 becomes too small, making it difficult for the molten liquid first bonding material 50L to flow into the first recess 42 during the reflow process P02. Therefore, it is difficult to suppress the flow of the first bonding material 50L toward the connection portion 46, making it difficult to prevent the semiconductor chip 20 from being bonded to the lead frame 30 and connector member 40 in a tilted state. Also, if the first ratio R1 is greater than 60%, the vertical dimension of the side surface 41c (see Figure 3) of the joint 41 facing the third direction D3 becomes too small. Therefore, in the reflow process P02, the first bonding material 50L that leaks out from the first recess 42 in the third direction D3 is more likely to adhere to the upper surface 41d (see Figure 3) of the connector member 40. As a result, the area in which the upper surface 41d of the connector member 40 and the resin part 80 are directly bonded decreases, which may reduce the adhesive strength between the connector member 40 and the resin part 80. In contrast to these, in this embodiment, since the first ratio R1 is 40% or more, it is possible to suppress the volume of the first recess 42 from becoming too small. Therefore, in the reflow process P02, it is possible to more effectively suppress the semiconductor chip 20 from being joined to the lead frame 30 and the connector member 40 in an inclined state. Also, in this embodiment, since the first ratio R1 is 60% or less, it is possible to suppress the dimension of the side surface 41c in the first direction D1 from becoming too small. As a result, it is possible to effectively suppress the first bonding material 50 from adhering to the upper surface 41d of the connector member 40. Therefore, it is possible to suppress a decrease in the area in which the upper surface 41d of the connector member 40 and the resin part 80 are directly bonded, and thus it is possible to suppress a decrease in the adhesive strength between the connector member 40 and the resin part 80.

[0059] According to this embodiment, the second bonding surface 30a is provided with a second recess 31 that is recessed on the lower side, i.e., on the other side of the first direction D1 (-D1 side). When viewed from the first direction D1, the second recess 31 overlaps with the edge of the semiconductor chip 20 on the other side of the second direction D2 (-D2 side), and a part of the second bonding material 60 is housed inside the second recess 31. As described above, in the reflow process P02, voids B2 tend to accumulate in the portion of the second bonding material 60L on the other side of the second direction D2 (-D2 side). In this embodiment, the second recess 31 can be positioned facing the other side of the semiconductor chip 20 in the second direction D2 in the vertical direction. Therefore, in the reflow process P02, voids B2 accumulated in the other side of the second bonding material 60L in the second direction D2 can be suitably released from the other end of the second bonding material 60L in the second direction D2 via the second bonding material 60L that has flowed into the interior of the second recess 31. Consequently, the amount of voids B2 remaining inside the second bonding material 60 can be suitably reduced, thereby suppressing an increase in the electrical resistance of the second bonding material 60. This makes it more suitably possible to suppress a decrease in the current that can be conducted in the semiconductor device 10, and thus more suitably suppresses a narrowing of the operating area of ​​the semiconductor device 10.

[0060] According to this embodiment, the maximum dimension L2max of the second recess 31 in the first direction D1 is 15 μm or more. Therefore, as described above, even when a burr 23a is formed on the second electrode 23, the vertical gap between the burr 23a and the second inner surface 33 can be increased. As a result, as described above, in the reflow process P02, the void B2 can move towards the other end (-D2 side) of the second bonding material 60L in the second direction D2 by bypassing the underside of the burr 23a. This allows the void B2 to be suitably released to the outside of the second bonding material 60L from the other end in the second direction D2. Therefore, the amount of void B2 remaining inside the second bonding material 60 can be suitably reduced, and the increase in the electrical resistance of the second bonding material 60 can be more suitably suppressed.

[0061] According to this embodiment, the second recess 31 has a first portion 31a that overlaps with the semiconductor chip 20 when viewed from the first direction D1, and the third ratio R3, which is the ratio of the dimension Lp1 of the first portion 31a in the second direction D2 to the dimension Lc2 of the semiconductor chip 20 in the second direction D2, is 25% or more and 33% or less. If the third ratio is less than 25%, the dimension of the second recess 31 in the second direction D2 becomes too small, making it difficult for voids B2 to move into the second recess 31 during the reflow process P02. Therefore, there is a risk that the amount of voids B2 remaining inside the second bonding material 60 will increase. Also, if the third ratio R3 is greater than 33%, the volume of the second recess 31 becomes too large, so the volume of the second bonding material 60 required to fill the second recess 31 increases. Therefore, the material cost of the second bonding material 60 increases, and the manufacturing cost of the semiconductor device 10 increases. In contrast to these, in this embodiment, since the third ratio R3 is 25% or more, it is possible to suppress the dimension of the second recess 31 in the second direction D2 from becoming too small. This makes it possible to increase the amount of voids B2 that move into the second recess 31 during the reflow process P02. Therefore, since the amount of voids B2 released to the outside of the second bonding material 60L can be increased, the amount of voids B2 remaining inside the second bonding material 60 can be more favorably reduced. Also, in this embodiment, since the third ratio R3 is 33% or less, it is possible to suppress the volume of the second recess 31 from becoming too large. This makes it possible to suppress an increase in the volume of the second bonding material 60 required to fill the second recess 31. Therefore, since it is possible to suppress an increase in the material cost of the second bonding material 60, it is possible to suppress an increase in the manufacturing cost of the semiconductor device 10.

[0062] According to this embodiment, the second recess 31 has a second portion 31c located on the other side (-D2 side) of the second direction D2 than the semiconductor chip 20, and the dimension Lp2 of the second portion 31c in the second direction D2 is 0.05 mm or more and 0.15 mm or less. If the dimension Lp2 of the second portion 31c in the second direction D2 is less than 0.05 mm, the gap between the fourth inner surface portion 33c and the semiconductor chip 20 becomes too narrow, making it difficult to release the void B2 that has moved into the second recess 31 to the outside of the second bonding material 60L. Also, if the dimension Lp2 of the second portion 31c in the second direction D2 is greater than 0.15 mm, the distance between the second recess 31 and the other end of the lead frame 30 in the second direction D2 becomes too short. Therefore, the second bonding material 60 that leaks out from the second recess 31 to the other side in the second direction D2 is more likely to adhere to the surface 30c (see Figure 2) of the lead frame 30 facing downwards. In this case, the lead-containing second bonding material 60 is exposed to the outside of the resin part 80, which impairs the environmental characteristics of the semiconductor device 10. In contrast to these, in this embodiment, since the dimension Lp2 of the second portion 31c in the second direction D2 is 0.05 mm or more, it is possible to prevent the gap between the fourth inner surface portion 33c and the semiconductor chip 20 from becoming too narrow. As a result, the void B2 that has moved into the second recess 31 can be suitably discharged to the outside of the second bonding material 60L from the other end of the second bonding material 60L in the second direction D2. Therefore, it is possible to more suitably suppress an increase in the electrical resistance of the second bonding material 60. Also, in this embodiment, since the dimension Lp2 of the second portion 31c in the second direction D2 is 0.15 mm or less, it is possible to prevent the distance between the second recess 31 and the other end of the lead frame 30 in the second direction D2 from becoming too short. As a result, it is possible to prevent the second bonding material 60 from adhering to the surface 30c facing downwards of the lead frame 30. Therefore, it is possible to prevent the environmental characteristics of the semiconductor device 10 from being impaired.

[0063] According to this embodiment, the dimension L23 of the second recess 31 in the third direction D3 is less than or equal to the dimension Lc3 of the semiconductor chip 20 in the third direction D3. Therefore, it is easy to position both ends of the second recess 31 in the third direction D3 close to the edge of the semiconductor chip 20 in the third direction D3. This prevents the gap between both ends of the second recess 31 in the third direction D3 and the semiconductor chip 20 from becoming too large, thus preventing the second bonding material 60L from leaking from the ends of the second recess 31 in the third direction D3 to the second bonding surface 30a. Therefore, it is possible to prevent a decrease in the area where the second bonding surface 30a and the resin part 80 are directly bonded, thus preventing a decrease in the bonding strength between the lead frame 30 and the resin part 80.

[0064] According to this embodiment, the upper side of the inner surface of the second recess 31, that is, the surface facing one side of the first direction D1 (+D1 side), has a third inner surface portion 33a located on the lower side, that is, on the other side of the first direction D1 (-D1 side), as it moves from the end of the second inner surface portion 33 on one side of the second direction D2 (+D2 side) toward the other side of the second direction D2 (-D2 side), and a fourth inner surface portion 33c located on the lower side, as it moves from the end of the second inner surface portion 33 on the other side of the second direction D2 toward one side of the second direction D2, with the end of the fourth inner surface portion 33c on one side of the second direction D2 connecting to the end of the third inner surface portion 33a on the other side of the second direction D2. Therefore, in the reflow process P02, the voids B2 generated inside the molten liquid second bonding material 60L move along the third inner surface 33a into the second recess 31, and then move along the fourth inner surface 33c to the other side of the second direction D2. As a result, the voids B2 are more likely to move toward the other end of the second bonding material 60L in the second direction D2, and thus the amount of voids B2 released to the outside of the second bonding material 60L from the other end of the second bonding material 60L in the second direction D2 can be more favorably increased. Consequently, the amount of voids B2 remaining inside the second bonding material 60 can be more favorably reduced, and the increase in the electrical resistance of the second bonding material 60 can be more favorably suppressed.

[0065] According to the embodiments described above, by providing a first recess on the first bonding surface that is recessed on one side in the first direction and open on the other side in the second direction, it is possible to provide a semiconductor device that can suppress the semiconductor chip from being bonded to the lead frame and connector member in a tilted state.

[0066] The semiconductor device of the embodiment includes the following appended aspects. (Note 1) A semiconductor chip having a first chip surface facing one side of the first direction and a second chip surface facing the other side of the first direction, A connector member having a joint portion facing the first chip surface in the first direction, and a connecting portion connected to the joint portion, The lead frame facing the second chip surface and the first direction, Equipped with, The connecting portion is connected to one end of the joint portion in a second direction perpendicular to the first direction, and is located on the other side of the first direction as it moves toward one side of the second direction. The joint portion has a first joint surface which is joined to the first tip surface by the first jointing material, The lead frame has a second bonding surface which is bonded to the second tip surface by a second bonding material, The first joining surface is provided with a first recess that is recessed on one side in the first direction and open on the other side in the second direction. A portion of the first joining material is housed inside the first recess. A semiconductor device in which the ratio of the dimension of the first recess in the second direction to the dimension of the joint in the second direction is 40% or more and 60% or less. (Note 2) The first recess is open on both sides in a third direction which is perpendicular to both the first and second directions. The semiconductor device according to Appendix 1, wherein the first inner surface of the inner surface of the first recess, which faces the other side in the first direction, has a first inner surface portion located on the other side in the first direction as it extends from one end of the first inner surface in the third direction toward the other side in the third direction. (Note 3) The first inner surface has a second inner surface portion located on the other side in the first direction, extending from the other end of the first inner surface in the third direction toward one side in the third direction, The semiconductor device as described in Appendix 2, wherein one end of the second inner surface in the third direction is connected to the other end of the first inner surface in the third direction. (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the ratio of the dimension of the first recess in the first direction to the dimension of the joint in the first direction is 40% or more and 60% or less. (Note 5) The second joining surface is provided with a second recess that is recessed on the other side in the first direction, Viewed from the first direction, the second recess overlaps with the other edge of the semiconductor chip in the second direction. A semiconductor device according to any one of the appendices 1 to 4, wherein a portion of the second bonding material is housed inside the second recess. (Note 6) The semiconductor device according to Appendix 5, wherein the maximum dimension of the second recess in the first direction is 15 μm or more. (Note 7) The second recess has a first portion that overlaps with the semiconductor chip when viewed from the first direction. The semiconductor device according to Appendix 5 or Appendix 6, wherein the ratio of the dimension of the first portion in the second direction to the dimension of the semiconductor chip in the second direction is 25% or more and 33% or less. (Note 8) The second recess has a second portion located on the other side in the second direction from the semiconductor chip, The semiconductor device described in any one of the appendices 5 to 7, wherein the dimension of the second part in the second direction is 0.05 mm or more and 0.15 mm or less. (Note 9) The semiconductor device according to any one of the appendices 5 to 8, wherein the dimension of the second recess in the third direction, which is perpendicular to both the first and second directions, is less than or equal to the dimension of the semiconductor chip in the third direction. (Note 10) The second inner surface of the second recess, which is the surface facing one side in the first direction, A third inner surface portion located on the other side in the first direction, extending from one end of the second inner surface in the second direction toward the other side in the second direction, A fourth inner surface portion located on the other side in the first direction, extending from the other end of the second inner surface in the second direction toward one side in the second direction, It has, The semiconductor device according to any one of the appendices 5 to 9, wherein one end of the fourth inner surface in the second direction is connected to the other end of the third inner surface in the second direction.

[0067] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0068] 10...Semiconductor device, 20...Semiconductor chip, 20a...First chip surface, 20c...Second chip surface, 30...Lead frame, 30a...Second bonding surface, 31...Second recess, 31a...First part, 31c...Second part, 33...Second inner surface, 33a...Third inner surface, 33c...Fourth inner surface, 40...Connector member, 41...Bond, 41a...First bonding surface, 42...First recess, 43...First inner surface, 43a...First inner surface, 43c...Second inner surface, 46...Connection part, 50, 50L, 50P...First bonding material, 60, 60L ,60P…Second bonding material, D1…First direction, D2…Second direction, D3…Third direction, L11…Dimension of the first recess in the first direction, L12…Dimension of the first recess in the second direction, L23…Dimension of the second recess in the third direction, L2max…Maximum dimension of the second recess in the first direction, Lc2…Dimension of the semiconductor chip in the second direction, Lc3…Dimension of the semiconductor chip in the third direction, Lj1…Dimension of the joint in the first direction, Lj2…Dimension of the joint in the second direction, Lp1…Dimension of the first part in the second direction, Lp2…Dimension of the second part in the second direction

Claims

1. A semiconductor chip having a first chip surface facing one side of the first direction and a second chip surface facing the other side of the first direction, A connector member having a joint portion facing the first chip surface in the first direction, and a connecting portion connected to the joint portion, The lead frame facing the second chip surface and the first direction, Equipped with, The connecting portion is connected to one end of the joint portion in a second direction perpendicular to the first direction, and is located on the other side of the first direction as it moves toward one side of the second direction. The joint portion has a first joint surface which is joined to the first tip surface by the first jointing material, The lead frame has a second bonding surface which is bonded to the second tip surface by a second bonding material, The first joining surface is provided with a first recess that is recessed on one side in the first direction and open on the other side in the second direction. A portion of the first joining material is housed inside the first recess. A semiconductor device in which the ratio of the dimension of the first recess in the second direction to the dimension of the joint in the second direction is 40% or more and 60% or less.

2. The first recess is open on both sides in a third direction which is perpendicular to both the first and second directions. The semiconductor device according to claim 1, wherein the first inner surface of the inner surface of the first recess, which faces the other side in the first direction, has a first inner surface portion located on the other side in the first direction as it extends from one end of the first inner surface in the third direction toward the other side in the third direction.

3. The first inner surface has a second inner surface portion located on the other side in the first direction as it extends from the other end of the first inner surface in the third direction toward one side in the third direction, The semiconductor device according to claim 2, wherein one end of the second inner surface in the third direction is connected to the other end of the first inner surface in the third direction.

4. The semiconductor device according to claim 1, wherein the ratio of the dimension of the first recess in the first direction to the dimension of the joint in the first direction is 40% or more and 60% or less.

5. The second joining surface is provided with a second recess that is recessed on the other side in the first direction, Viewed from the first direction, the second recess overlaps with the other edge of the semiconductor chip in the second direction. A semiconductor device according to any one of claims 1 to 4, wherein a part of the second bonding material is housed inside the second recess.

6. The semiconductor device according to claim 5, wherein the maximum dimension of the second recess in the first direction is 15 μm or more.

7. The second recess has a first portion that overlaps with the semiconductor chip when viewed from the first direction. The semiconductor device according to claim 5, wherein the ratio of the dimension of the first portion in the second direction to the dimension of the semiconductor chip in the second direction is 25% or more and 33% or less.

8. The second recess has a second portion located on the other side in the second direction from the semiconductor chip, The semiconductor device according to claim 5, wherein the dimension of the second portion in the second direction is 0.05 mm or more and 0.15 mm or less.

9. The semiconductor device according to claim 5, wherein the dimension of the second recess in a third direction, which is perpendicular to both the first and second directions, is less than or equal to the dimension of the semiconductor chip in the third direction.

10. The second inner surface of the second recess, which is the surface facing one side in the first direction, A third inner surface portion located on the other side in the first direction, extending from one end of the second inner surface in the second direction toward the other side in the second direction, A fourth inner surface portion located on the other side in the first direction, extending from the other end of the second inner surface in the second direction toward one side in the second direction, It has, The semiconductor device according to claim 5, wherein one end of the fourth inner surface in the second direction is connected to the other end of the third inner surface in the second direction.

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