Semiconductor equipment
The semiconductor device integrates insulating columns and conductors to enhance structural strength and thermal management, addressing the challenges of high voltage handling and heat dissipation.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-09-17
- Publication Date
- 2026-03-30
AI Technical Summary
Existing semiconductor devices face challenges in achieving high strength and effective heat dissipation, particularly when handling high voltages.
The semiconductor device incorporates a first circuit board, a first semiconductor chip, a second conductor, a second semiconductor chip, a third conductor, a first column, a second circuit board, a plurality of insulating columns, and an encapsulant, with the insulating columns connecting the circuit boards and guiding heat dissipation paths to enhance structural integrity and thermal management.
The solution provides a semiconductor device with enhanced strength and reliability by mitigating pressure and uneven heat distribution, ensuring high strength and efficient heat dissipation.
Smart Images
Figure 2026054791000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to semiconductor devices.
Background Art
[0002] Semiconductor devices that handle high voltages are known. Such semiconductor devices include devices having a substrate, a semiconductor chip, a resin, and terminals. The semiconductor chip includes semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The semiconductor chip is disposed on the substrate. The resin covers the substrate, the semiconductor chip, and the terminals. The terminals are connected to the electrodes of the semiconductor chip via conductors and are partially exposed from the resin.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Summary of the Invention
Problems to be Solved by the Invention
[0004] To provide a semiconductor device having high strength and heat dissipation.
Means for Solving the Problems
[0005] A semiconductor device according to one embodiment includes a first circuit board, a first semiconductor chip, a second conductor, a second semiconductor chip, a third conductor, a first column, a second circuit board, a plurality of insulating columns, and a encapsulant. The first circuit board includes an insulating first substrate and a first conductor comprising a plurality of first portions provided on the surface of the first substrate and separated from each other. The first semiconductor chip has a first surface and a second surface facing each other, and the first surface is in contact with one of the plurality of first portions. The second conductor is on the second surface of the first semiconductor chip. The second semiconductor chip has a third surface and a fourth surface facing each other, and the third surface is in contact with one of the plurality of first portions. The third conductor is on the fourth surface of the second semiconductor chip. The first column has a fifth surface and a sixth surface facing each other, and the fifth surface is in contact with one of the plurality of first portions. The second circuit board includes an insulating second substrate and a fourth conductor comprising a plurality of second portions provided on the surface of the second substrate and separated from each other, wherein one of the plurality of second portions is in contact with the surface of the second conductor opposite to the first semiconductor chip, one of the plurality of second portions is in contact with the surface of the third conductor opposite to the second semiconductor chip, and one of the plurality of second portions is in contact with the sixth surface of the first column. The plurality of insulating columns extend in the direction connecting the first circuit board and the second circuit board, and each is in contact with the first circuit board and the second circuit board. The encapsulant surrounds the first semiconductor chip, the second semiconductor chip, the first column, and the plurality of insulating columns, and includes the surface of the semiconductor device. [Brief explanation of the drawing]
[0006] [Figure 1] Figure 1 shows an example of the external appearance of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 shows an example of the internal components and electrical connections of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a plan view of the interior of the semiconductor device of the first embodiment. [Figure 6] Figure 6 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 7] Figure 7 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 8] Figure 8 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 9] Figure 9 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 10] Figure 10 shows another example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 11] Figure 11 shows the thermal pathways in the semiconductor device of the first embodiment. [Figure 12] Figure 12 is a schematic plan view of the interior of a semiconductor device of a first modification of the first embodiment. [Figure 13] Figure 13 shows an example of the appearance of a semiconductor device of a second modification of the first embodiment. [Figure 14] Figure 14 shows an example of the cross-sectional structure of a semiconductor device of a second modification of the first embodiment. [Figure 15] Figure 15 is a plan view of the interior of a semiconductor device of a second modified example of the first embodiment. [Figure 16] Figure 16 is a plan view of the interior of a semiconductor device of a second modified example of the first embodiment. [Modes for carrying out the invention]
[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may be denoted by additional numbers or letters at the end of their reference numerals to distinguish them from one another.
[0008] Drawings are schematic representations, and the relationship between thickness and planar dimensions, as well as the dimensional ratios between constituent elements, may differ from reality. Furthermore, there may be differences in dimensional relationships and ratios between drawings.
[0009] Hereinafter, embodiments will be described using a three-dimensional orthogonal coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, and up points to the Z direction. The direction opposite to the Z direction is referred to as the -Z direction, and down points to the -Z direction.
[0010] 1. First Embodiment FIG. 1 shows an example of the appearance of a semiconductor device according to the first embodiment. The semiconductor device 1 can function as a semiconductor module that forms part of another device.
[0011] The semiconductor device 1 includes a sealing body 2, a circuit board 20, and terminals TP, TN, TOUT, TD1, TS1, TG1, TD2, TS2, and TG2.
[0012] The sealing body 2 is an insulator that covers the internal structure of the semiconductor device 1. The sealing body 2 extends along the xy plane. Examples of the shape of the sealing body 2 include a hexahedron, a frustum of a cone, and a rectangular parallelepiped. Some sides of these structures may be curved or chamfered. The following description is based on an example where the sealing body 2 has the shape of a rectangular parallelepiped. The sealing body 2 extends along the xz plane and has two opposing surfaces. The sealing body 2 extends along the xy plane and has two opposing surfaces. Of the two surfaces extending along the xy plane, the surface located on the +Z direction side is referred to as the upper surface of the sealing body 2 or the semiconductor device 1, and the surface located on the -Z direction side is referred to as the lower surface of the sealing body 2 or the semiconductor device 1. The sealing body 2 covers the internal structure of the semiconductor device 1. In one example, the sealing body 2 contains resin.
[0013] The circuit board 20 is a printed circuit board including a plate-like insulator and a conductor on the insulator. The conductor 22 of the circuit board 20 partially protrudes from the upper surface of the sealing body 2.
[0014] The terminals TP, TN, TOUT, TD1, TS1, TG1, TD2, TS2, and TG2 are conductors that electrically connect the inside and outside of the semiconductor device 1.
[0015] The terminals TP, TN, and TOUT have a plate-like shape. Each of the terminals TP, TN, and TOUT is located inside the sealing body 2 at one end. Each of the terminals TP, TN, and TOUT is located outside the sealing body 2 at the other end. The terminals TP, TN, and TOUT have an L-shaped form at the portion located outside the sealing body 2. The terminals TP and TN protrude from the surface along the xz plane of the sealing body 2 and are arranged in the X direction. The terminal TOUT protrudes from the surface along the xz plane while facing the surface from which the terminals TP and TN of the sealing body 2 protrude.
[0016] Each of the terminals TD1, TS1, TG1, TD2, TS2, and TG2 has a linear shape. Each of the terminals TD1, TS1, TG1, TD2, TS2, and TG2 is located inside the sealing body 2 at one end. Each of the terminals TD1, TS1, TG1, TD2, TS2, and TG2 is located outside the sealing body 2 at the other end. The terminals TD1, TS1, TG1, TD2, TS2, and TG2 protrude from the surface from which the terminal TOUT protrudes. The terminals TD1, TS1, and TG1 are located in the -X direction from the terminal TOUT and are arranged in the +X direction. The terminals TD2, TS2, and TG2 are located on the +X direction side from the terminal TOUT and are arranged in the -X direction.
[0017] FIG. 2 shows an example of the internal components and the electrical connections of the components of the semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor device 1 includes a half-bridge circuit. More specifically, the semiconductor device 1 includes n-type MOSFETs NM1 and NM2.
[0018] The terminals TP and TN are the power supply terminals of the semiconductor device 1. While the semiconductor device 1 is in use, the terminal TP receives a positive power supply voltage, and the terminal TN receives a negative power supply voltage.
[0019] Terminal TOUT is an output terminal of a semiconductor device.
[0020] Terminals TD1, TD2, TS1, and TS2 are terminals used to monitor the operation of semiconductor device 1.
[0021] Transistor NM1 is connected to terminals TP and TD1 at its drain. Transistor NM1 is connected to terminals TOUT and TS1 at its source. Transistor NM1 is connected to terminal TG1 at its gate.
[0022] Transistor NM2 is connected to terminals TOUT and TD2 at its drain. Transistor NM2 is connected to terminals TN and TS2 at its source. Transistor NM2 is connected to terminal TG2 at its gate.
[0023] Figure 3 shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. Figure 3 shows the structure along the line III-III in Figure 1 and the structure along the xz plane.
[0024] As shown in Figure 3, the semiconductor device 1 further includes circuit boards 10 and 20, semiconductor chips 30 and 50, inter-substrate spacers 70, and bonding layers 31, 41, 42, 51, 61, 71, and 72.
[0025] The circuit board 10 includes a substrate 11, a conductor 12, and a conductor 13. The substrate 11 is an insulating substrate. In one example, the substrate 11 contains or is made of ceramics. The substrate 11 extends along the xy plane.
[0026] The conductor 12 has a plate-like shape. The conductor 12 is provided on the -Z-direction side (bottom surface) of the substrate 11. In one example, the conductor 12 contains copper.
[0027] The conductor 13 has a plate-like shape extending along the xy-plane and has a pattern of a certain shape. The conductor 13 is provided on the surface (top surface) of the substrate 11 on the +Z side. The conductor 13 includes a plurality of parts. Each part of the conductor 13 functions as a circuit pattern and is hereinafter referred to as a circuit pattern. That is, in one example, the conductor 13 includes circuit patterns 13a, 13b, and 13c. The circuit patterns 13a, 13b, and 13c are separated from each other and electrically insulated from each other. In one example, the conductor 13 contains copper.
[0028] The circuit board 20 includes a substrate 21, a conductor 22, and a conductor 23. The substrate 21 is an insulating substrate. In one example, the substrate 21 contains or is made of ceramics. The substrate 21 extends along the xy plane.
[0029] The conductor 22 has a plate-like shape. The conductor 22 is provided on the upper surface of the substrate 21 on the +Z direction side. In one example, the conductor 22 contains copper.
[0030] The conductor 23 has a plate-like shape extending along the xy-plane and has a pattern of a certain shape. The conductor 23 is provided on the lower surface of the substrate 21. The conductor 23 includes multiple parts. Each part of the conductor 23 functions as a circuit pattern and is hereinafter referred to as a circuit pattern. The circuit patterns are separated from each other and electrically insulated from each other. In one example, the conductor 23 contains copper.
[0031] The bonding layer 31 is conductive and contains a conductor. The bonding layer 31 fixes the semiconductor chip 30 and the circuit pattern 13a and electrically connects them. In one example, the bonding layer 31 contains solder.
[0032] The semiconductor chip 30 is a chip containing semiconductor elements. Examples of semiconductor elements include n-type MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). The following description is based on the example of a MOSFET, and therefore the semiconductor chip 30 includes a gate electrode, a source electrode, and a drain electrode. The semiconductor chip 30 is bonded to the upper surface of the circuit pattern 13a by a junction layer 31. The semiconductor chip 30 is in contact with the junction layer 31 at the drain electrode.
[0033] The bonding layer 41 is conductive and contains a conductor. The bonding layer 41 fixes the semiconductor chip 30 and the chip spacer 40 and electrically connects them. In one example, the bonding layer 41 contains solder. The bonding layer 41 is in contact with the source electrode of the semiconductor chip 30.
[0034] The chip spacer 40 is conductive and contains a conductive material. On its lower surface, the chip spacer 40 is in contact with the bonding layer 41 and is electrically connected to the source electrode of the semiconductor chip 30 via the bonding layer 41. The chip spacer 40 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 30 to the circuit board 20. The chip spacer 40 may be referred to as a column.
[0035] The bonding layer 42 is conductive and contains a conductor. The bonding layer 42 fixes and electrically connects the chip spacer 40 and the circuit pattern of the conductor 23 (i.e., a part of the conductor 23). The bonding layer 42 is in contact with the chip spacer 40 on its lower surface. The bonding layer 42 is in contact with the circuit pattern (i.e., a part of the conductor 23) on its upper surface. In other words, the chip spacer 40 and the circuit pattern (i.e., a part of the conductor 23) are connected via the bonding layer 42. In one example, the bonding layer 42 contains solder.
[0036] The bonding layer 51 is conductive and contains a conductor. The bonding layer 51 fixes the semiconductor chip 50 and the circuit pattern 13c and electrically connects them. In one example, the bonding layer 51 contains solder.
[0037] The semiconductor chip 50 is a chip containing semiconductor elements. Examples of semiconductor elements include n-type MOSFETs and IGBTs. The following description is based on the example of a MOSFET, and therefore the semiconductor chip 50 includes a gate electrode, a source electrode, and a drain electrode. The semiconductor chip 50 is bonded to the upper surface of the circuit pattern 13c by a junction layer 51. The semiconductor chip 50 is in contact with the junction layer 51 at the drain electrode.
[0038] The bonding layer 61 is conductive and contains a conductor. The bonding layer 61 fixes the semiconductor chip 50 and the chip spacer 60 and electrically connects them. In one example, the bonding layer 61 contains solder. The bonding layer 61 is in contact with the source electrode of the semiconductor chip 50.
[0039] The chip spacer 60 is conductive and contains a conductive material. On its lower surface, the chip spacer 60 is in contact with the bonding layer 61 and is electrically connected to the source electrode of the semiconductor chip 50 via the bonding layer 61. The chip spacer 60 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 50 to the circuit board 20. The chip spacer 60 may be referred to as a column.
[0040] The bonding layer 62 is conductive and contains a conductor. The bonding layer 62 fixes and electrically connects the chip spacer 60 and the circuit pattern of the conductor 23 (i.e., a part of the conductor 23). The bonding layer 62 is in contact with the chip spacer 60 on its lower surface. The bonding layer 62 is in contact with the circuit pattern (i.e., a part of the conductor 23) on its upper surface. In other words, the chip spacer 60 and the circuit pattern (i.e., a part of the conductor 23) are connected via the bonding layer 62. In one example, the bonding layer 62 contains solder.
[0041] The bonding layer 71 is conductive and contains a conductor. It fixes the substrate spacer 70 and the circuit pattern 13b and electrically connects them. The bonding layer 71 is in contact with the circuit pattern 13b on its lower surface. In one example, the bonding layer 71 contains solder.
[0042] The inter-substrate spacer 70 is conductive and contains a conductor. The inter-substrate spacer 70 electrically connects the circuit pattern 13b to the circuit pattern of the conductor 23 (i.e., a part of the conductor 23). The inter-substrate spacer 70 is in contact with the bonding layer 71 on its lower surface. In other words, the circuit pattern 13b and the inter-substrate spacer 70 are connected via the bonding layer 71. The inter-substrate spacer 70 is electrically connected to the circuit pattern 13b via the bonding layer 71. The inter-substrate spacer 70 also functions as a heat dissipation path that releases heat generated in the semiconductor chips 30 and 50 to the circuit board 20. In one example, the inter-substrate spacer 70 has a hardness higher than the hardness of the material of the encapsulant 2. In one example, the inter-substrate spacer 70 contains a combination of silicon carbide (SiC) and aluminum (Al).
[0043] The bonding layer 72 is conductive and contains a conductor. The bonding layer 72 fixes and electrically connects the inter-substrate spacer 70 and the circuit pattern of the conductor 23 (i.e., a part of the conductor 23). The bonding layer 72 is in contact with the inter-substrate spacer 70 on its lower surface. The bonding layer 72 is in contact with the circuit pattern of the conductor 23 (i.e., a part of the conductor 23) on its upper surface. In other words, the inter-substrate spacer 70 and the circuit pattern (i.e., a part of the conductor 23) are connected via the bonding layer 72. In one example, the bonding layer 72 contains solder.
[0044] Figure 4 shows an example of the cross-sectional structure of the semiconductor device of the first embodiment. Figure 4 shows the structure along the line IV-IV in Figure 1 and the structure along the xz plane.
[0045] As shown in Figure 4, the semiconductor device 1 further includes a substrate spacer 80. The bonding layer 71 (71b) fixes and electrically connects the substrate spacer 80 and the circuit pattern 13c. The bonding layer 71b is in contact with the circuit pattern 13c on its lower surface.
[0046] The inter-substrate spacer 80 is conductive and contains a conductor. The inter-substrate spacer 80 electrically connects the circuit pattern 13c to the circuit pattern of the conductor 23 (i.e., a part of the conductor 23). The inter-substrate spacer 80 is in contact with the bonding layer 71b on its lower surface. In other words, the circuit pattern 13c and the inter-substrate spacer 80 are connected via the bonding layer 71b. The inter-substrate spacer 80 is electrically connected to the circuit pattern 13c via the bonding layer 71b. The inter-substrate spacer 80 also functions as a heat dissipation path that releases heat generated in the semiconductor chips 30 and 50 to the circuit board 20. In one example, the inter-substrate spacer 70 has a hardness higher than the hardness of the material of the encapsulant 2. In one example, the inter-substrate spacer 80 contains a combination of silicon carbide and aluminum.
[0047] The bonding layer 72 (72b) fixes and electrically connects the inter-substrate spacer 80 and the circuit pattern of the conductor 23. The bonding layer 72b is in contact with the inter-substrate spacer 80 on its lower surface. The bonding layer 72b is in contact with the circuit pattern of the conductor 23 (i.e., a part of the conductor 23) on its upper surface. In other words, the inter-substrate spacer 80 and the circuit pattern (i.e., a part of the conductor 23) are connected via the bonding layer 72b.
[0048] Figure 5 is a plan view of the interior of the semiconductor device of the first embodiment. Figure 5 shows the interior of the semiconductor device 1 along the xy plane. The structure shown in Figure 3 is the cross-sectional structure along the line III-III shown in Figure 5.
[0049] In the descriptions of Figure 5, "up," "upper side," and "upward" refer to the +Z direction, while "down," "lower side," and "downward" refer to the -Z direction. Therefore, in the descriptions of Figure 5, the "upper surface" of a component refers to the surface on the +Z side of that component, and the "lower surface" of a component refers to the surface on the -Z side of that component.
[0050] The semiconductor chip 30 and the chip spacer 40 have a quadrilateral shape. The semiconductor chip 30 has a larger shape than the chip spacer 40. The semiconductor chip 30 further includes electrode pads 33 and 34. Electrode pad 33 is the source electrode pad of the semiconductor chip 30. Electrode pad 34 is the gate electrode pad of the semiconductor chip 30. Electrode pads 33 and 34 are not covered by the chip spacer 40.
[0051] The semiconductor chip 50 and the chip spacer 60 have a quadrilateral shape. The semiconductor chip 50 has a larger shape than the chip spacer 60. The semiconductor chip 50 further includes electrode pads 53 and 54. Electrode pad 53 is the drain electrode pad of the semiconductor chip 50. Electrode pad 54 is the source electrode pad of the semiconductor chip 50. Electrode pads 53 and 54 are not covered by the chip spacer 60.
[0052] The substrate spacer 70 has a columnar shape. In one example, the substrate spacer 70 has a cylindrical or rectangular prism shape.
[0053] The substrate spacer 80 has a columnar shape. In one example, the substrate spacer 80 has a cylindrical or rectangular prism shape.
[0054] The circuit pattern 13a extends across the region below the semiconductor chip 30 (i.e., on the -Z side), the region below terminal TP, and the region below terminal TD1. On its upper surface, the circuit pattern 13a is in contact with the lower surface of terminal TP and the lower surface of terminal TD1.
[0055] Circuit pattern 13b extends across the region below the substrate spacer 70 and the region below terminal TN. Below the region between the semiconductor chip 30 and the substrate spacer 70, circuit pattern 13b faces circuit pattern 13a with a gap between them. Below the region between terminal TP and terminal TN, circuit pattern 13b faces circuit pattern 13a with a gap between them. On its upper surface, circuit pattern 13b is in contact with the lower surface of terminal TN. Circuit pattern 13b overlaps with the substrate spacer 70.
[0056] The circuit pattern 13c extends across the area below the semiconductor chip 50, the area below terminal TOUT, and the area below terminal TG2. The circuit pattern 13c is located below the area on the +Y direction side of the inter-substrate spacer 70 and includes a portion of the circuit pattern 13b that faces the portion below the inter-substrate spacer 70 with a gap between them. On its upper surface, the circuit pattern 13c is in contact with the lower surface of terminal TOUT and the lower surface of terminal TG2. The circuit pattern 13c overlaps with the inter-substrate spacer 80.
[0057] The conductor 13 further includes circuit patterns 13d, 13e, 13f, and 13g. The circuit patterns 13d, 13e, 13f, and 13g are separated from each other and electrically insulated from each other. The circuit patterns 13d, 13e, 13f, and 13g are separated from and electrically insulated from any of the circuit patterns 13a, 13b, and 13c.
[0058] Circuit pattern 13d faces the lower portion of terminal TD1 and the lower portion of semiconductor chip 30 of circuit pattern 13a with a gap between them. Circuit pattern 13d is located below terminal TS1. On its upper surface, circuit pattern 13d is in contact with the lower surface of terminal TS1. Circuit pattern 13d is connected to electrode pad 33 by bonding wire 36.
[0059] Circuit pattern 13e is located in the +X direction relative to circuit pattern 13d and faces the lower portion of the semiconductor chip 30 with a gap between them. Circuit pattern 13e is located below terminal TG1. On its upper surface, circuit pattern 13e is in contact with the lower surface of terminal TG1. Circuit pattern 13e is connected to electrode pad 34 by bonding wire 37.
[0060] Circuit pattern 13f faces the lower portion of terminal TOUT and the lower portion of semiconductor chip 50 of circuit pattern 13c with a gap between them. Circuit pattern 13f is located below terminal TD2. On its upper surface, circuit pattern 13f is in contact with the lower surface of terminal TD2. Circuit pattern 13f is connected to electrode pad 53 by bonding wire 36.
[0061] Circuit pattern 13g is located in the +X direction relative to circuit pattern 13f and faces the lower portion of circuit pattern 13c of the semiconductor chip 50 with a gap between them. Circuit pattern 13g is located below terminal TS2. On its upper surface, circuit pattern 13g is in contact with the lower surface of terminal TS2. Circuit pattern 13g is connected to electrode pad 54 by bonding wire 57.
[0062] The shapes and arrangements of the circuit patterns 13a, 13b, 13c, 13d, 13e, 13f, and 13g shown in Figure 5 are merely examples. The circuit patterns 13a, 13b, 13c, 13d, 13e, 13f, and 13g may have any shape and arrangement, as long as the circuit intended to be realized by the semiconductor device 1 is realized, including the circuit shown as an example in Figure 2.
[0063] The semiconductor device 1 further includes a substrate spacer 80 and an insulator 90 (90a, 90b, 90c, and 90d).
[0064] The insulators 90a and 90b are positioned around the semiconductor chip 30. In one example, the insulators 90a and 90b are positioned so that the region enclosed by the insulators 90a and 90b and the inter-substrate spacers 70 and 80 surrounds the semiconductor chip 30, and does not overlap with the semiconductor chip 30, terminals TP, TD1, TS1, and TG1, and bonding wires 36 and 37. In this case, the directions from the semiconductor chip 30 to the insulators 90a and 90b and the inter-substrate spacers 70 and 80 are all different from each other. In other words, the four directions from the semiconductor chip 30 to the insulators 90a and 90b and the inter-substrate spacers 70 and 80 are all different from each other. In one example, the insulators 90a and 90b are positioned so that the semiconductor chip 30 is contained within the region enclosed by the straight lines connecting two adjacent insulators 90a and 90b and the inter-substrate spacers 70 and 80. The insulators 90a and 90b only need to be located around the semiconductor chip 30, and it is not necessary for the area enclosed by the insulators 90a and 90b and the inter-substrate spacers 70 and 80 to completely enclose the semiconductor chip 30. In one example, the insulators 90a and 90b are located near the corners of the substrate 11. The insulators 90a and 90b have shapes and dimensions that allow the area enclosed by the insulators 90a and 90b and the inter-substrate spacers 70 and 80 to be located around the semiconductor chip 30, but without overlapping with the semiconductor chip 30, terminals TP, TD1, TS1, and TG1, and bonding wires 36 and 37. The insulators 90a and 90b contribute to maintaining the structure of the semiconductor device 1 and function as heat dissipation paths, as will be described later. These advantages are greater when the insulators 90a and 90b have a larger volume. Examples of the shapes, arrangements, and dimensions of the insulators 90a and 90b are described below. The insulators 90a and 90b may each be referred to as columns.
[0065] In one example, the insulator 90a is located near the corner formed by the -X side edge and the -Y side edge of the substrate 11 (hereinafter sometimes referred to as the lower left corner). In one example, all or part of the insulator 90a overlaps with the conductor 13 near the lower left corner of the substrate 11, and in one example, overlaps with the circuit pattern 13a. The insulator 90a has the shape of a column extending along the z axis, and in one example, it has the shape of a cylinder or a rectangular prism. The insulator 90a extends to the vicinity of the semiconductor chip 30 and terminal TP. The insulator 90a may have a wall-like shape by extending along the xy plane. In this case, the insulator 90a may be referred to as a wall. The insulator 90a may also be referred to as a column.
[0066] In one example, the insulator 90b is located near the corner (which may be referred to as the upper left corner) formed by the -X side edge and the +Y side edge of the substrate 11. In one example, all or part of the insulator 90b overlaps with the conductor 13 near the upper left corner of the substrate 11, and in one example, overlaps with the circuit pattern 13a. In one example, based on the location of terminal TD1 near the upper left corner of the substrate 11, the insulator 90b has a shape that conforms to the region between terminal TD1 and the edge of the substrate 11. In one example, the insulator 90b extends along the y-axis. The insulator 90b extends along the z-axis.
[0067] The insulators 90c and 90d are positioned around the semiconductor chip 50. In one example, the insulators 90c and 90d are positioned so that the area enclosed by the insulators 90c and 90d and the inter-substrate spacers 70 and 80 surrounds the semiconductor chip 50, and does not overlap with the semiconductor chip 50, terminals TN, TD2, TS2, and TG2, and bonding wires 56 and 57. In other words, the directions from the semiconductor chip 50 to the insulators 90c and 90d and the inter-substrate spacers 70 and 80 are all different from each other. That is, the four directions from the semiconductor chip 50 to the insulators 90c and 90d and the inter-substrate spacers 70 and 80 are all different from each other. In one example, the insulators 90c and 90d are positioned so that the semiconductor chip 50 is contained within the area enclosed by the straight lines connecting two adjacent insulators 90c and 90d and the inter-substrate spacers 70 and 80. The insulators 90c and 90d only need to be located around the semiconductor chip 50, and it is not necessary for the area enclosed by the insulators 90c and 90d and the inter-substrate spacers 70 and 80 to completely enclose the semiconductor chip 50. In one example, the insulators 90c and 90d are located near the corners of the substrate 11. The insulators 90c and 90d have a shape and dimensions that allow the area enclosed by the insulators 90c and 90d and the inter-substrate spacers 70 and 80 to be located around the semiconductor chip 50, but without overlapping with the semiconductor chip 50, terminals TP, TD2, TS2, and TG2, and bonding wires 56 and 57. The insulators 90c and 90d contribute to maintaining the structure of the semiconductor device 1 and function as heat dissipation paths, as will be described later. These advantages are greater when the insulators 90c and 90d have a larger volume. Examples of the shape, arrangement, and dimensions of the insulators 90c and 90d are described below. The insulators 90c and 90d may be referred to as walls or columns.
[0068] In one example, the insulator 90c is located near the corner formed by the +X side and the -Y side of the substrate 11 (hereinafter sometimes referred to as the lower right corner). In one example, all or part of the insulator 90c overlaps with the conductor 13 near the lower left corner of the substrate 11, and in one example, overlaps with the circuit pattern 13a. The insulator 90c has the shape of a column extending along the z axis, and in one example, it has the shape of a cylinder or a rectangular prism. The insulator 90c extends to the vicinity of the semiconductor chip 30 and terminal TN. The insulator 90c may have a wall-like shape by extending along the xy plane.
[0069] In one example, the insulator 90d is located near the corner formed by the +X side edge and the +Y side edge of the substrate 11 (hereinafter sometimes referred to as the upper right corner). In one example, all or part of the insulator 90d overlaps with the conductor 13 near the upper left corner of the substrate 11, and in one example, overlaps with the circuit pattern 13c. In one example, based on the location of terminal TG2 near the upper left corner of the substrate 11, the insulator 90d has a shape that conforms to the region between terminal TG2 and the edge of the substrate 11. In one example, the insulator 90d extends along the y-axis. The edge 90d extends along the z-axis.
[0070] The insulators 90a, 90b, 90c, and 90d contain materials different from those of the sealant 2. In one example, the insulators 90a, 90b, 90c, and 90d include ceramics. An example of a ceramic is alumina.
[0071] Figure 6 is a cross-sectional view of the semiconductor device according to the first embodiment. Specifically, Figure 6 shows a cross-section along the xy plane and illustrates the structure of the layer in which the conductor 23 is located.
[0072] As shown in Figure 6, the conductor 23 overlaps with the semiconductor chips 30 and 50, the substrate spacers 70 and 80, and the insulators 90a, 90b, 90c, and 90d. In one example, the entirety of each of the insulators 90a, 90b, 90c, and 90d overlaps with the conductor 23.
[0073] Figure 7 is a cross-sectional view of the semiconductor device according to the first embodiment. Specifically, Figure 7 shows a cross-section along the xy plane and illustrates the structure of the layer in which the conductor 13 is located.
[0074] As shown in Figure 7, the conductor 13 overlaps with the semiconductor chips 30 and 50, the substrate spacers 70 and 80, and the insulators 90a, 90b, 90c, and 90d. In one example, the entirety of each of the insulators 90a, 90b, 90c, and 90d overlaps with the conductor 13.
[0075] Figures 8 and 9 show examples of the cross-sectional structure of the semiconductor device of the first embodiment. Figure 8 shows a cross-section along line VIII-VIII in Figures 5, 6, and 7, and a cross-section along the xz plane. Figure 9 shows a cross-section along line IX-IX in Figures 5, 6, and 7, and a cross-section along the xz plane.
[0076] As shown in Figures 8 and 9, the insulators 90a, 90b, 90c, and 90d are in contact with the upper surface of the conductor 13 on their lower surfaces. The insulators 90a, 90b, 90c, and 90d may not be in contact with the conductor 13 in part on their lower surfaces by being located outside the conductor 13 and / or above the circuit pattern of the conductor 13 (i.e., part of the conductor 13).
[0077] The insulators 90a, 90b, 90c, and 90d are in contact with the lower surface of the conductor 23 on their upper surfaces. The insulators 90a, 90b, 90c, and 90d are not in contact with the conductor 23 by being located outside the conductor 23 and / or below the circuit pattern of the conductor 23 (i.e., a portion of the conductor 23) on a portion of their upper surfaces.
[0078] The sides of the insulators 90a, 90b, 90c, and 90d are covered by the sealant 2.
[0079] As shown in Figure 10, the insulators 90a, 90b, 90c, and 90d may be provided on the conductor 13 via solder 95. Alternatively, or in addition to this, solder 96 may be provided between the insulators 90a, 90b, 90c, and 90d and the conductor 13. Figure 10 shows the same region as Figure 8. In the structure shown in Figure 10, the insulators 90a, 90b, 90c, and 90d may include a layer of copper between them and the solder 95.
[0080] According to the first embodiment, a semiconductor device having high reliability and high strength is provided, as described below.
[0081] A semiconductor device, such as semiconductor device 1, may be sandwiched between coolers from above and below in an apparatus containing the semiconductor device. Although the semiconductor device includes a encapsulant, the strength of the encapsulant may not be very high and may not have sufficient strength to withstand the pressure from the cooler. According to the first embodiment, semiconductor device 1 includes an inter-substrate spacer 70 and an insulator 90 that are in contact with circuit boards 10 and 20, and the inter-substrate spacer 70 and the insulator 90 are arranged to surround semiconductor chips 30 and 50. As a result, semiconductor device 1 has high strength in the region between the circuit boards 10 and 20, and in particular, the pressure applied from above and below to the region surrounded by the inter-substrate spacer 70 and the insulator 90 is mitigated. Thus, the pressure applied to semiconductor chips 30 and 50 located in the region surrounded by the inter-substrate spacer 70 and the insulator 90 is suppressed, and damage and / or deformation of semiconductor chips 30 and 50 are suppressed.
[0082] Furthermore, in a semiconductor device such as semiconductor device 1, heat generated in the semiconductor chip is transferred to the lower and upper circuit boards, where it is dissipated. The upper circuit board is in contact with the semiconductor chip via a spacer, while the lower circuit board is in direct contact with the semiconductor chip. Therefore, more heat is dissipated from the lower circuit board than from the upper circuit board. Although the inter-substrate spacer guides the heat generated at the bottom of the semiconductor chip to the upper circuit board, an uneven distribution of heat can still occur within the semiconductor device. This can lead to a decrease in the reliability of the semiconductor device. According to the first embodiment, semiconductor device 1 includes an insulator 90 in contact with circuit boards 10 and 20. As shown by the arrows in Figure 11, the insulator 90 guides the heat generated in the semiconductor chips 30 and 50 to the circuit board 20 via itself, just as the heat generated in the semiconductor chips 30 and 50 is guided to the circuit board 20 via the inter-substrate spacer 70. Therefore, more heat generated by the semiconductor chips 30 and 50 is induced into the circuit board 20, thereby suppressing uneven distribution of heat within the semiconductor device 1. As a result, the semiconductor device 1 has high reliability.
[0083] As described above, the insulator 90 only needs to surround the semiconductor chips 30 and 50 together with the inter-substrate spacers 70 and 80. Therefore, it can be placed in various positions depending on the arrangement of the semiconductor chips 30 and 50 and the inter-substrate spacers 70 and 80. Figure 12 is a schematic plan view of the inside of a semiconductor device of a first modification of the first embodiment. Figure 12 omits the details of the circuit pattern of the conductor 13.
[0084] As shown in Figure 12, the semiconductor chip 30 and the substrate spacer 70 are aligned in the +Y direction. The semiconductor chip 50 and the substrate spacer 80 are aligned in the +Y direction. Based on the arrangement of the semiconductor chips 30 and 50 and the substrate spacers 70 and 80, the insulator 90a is located near the lower left corner of the substrate 11, and the insulator 90c is located near the lower right corner of the substrate 11.
[0085] The semiconductor chips 30 and 50 may be aligned in the +Z direction. Figure 13 shows such an example, illustrating the appearance of a semiconductor device of a second modification of the first embodiment. As shown in Figure 13, terminals TNB and TPB protrude from the same plane of the encapsulant 2B. Terminals TNB and TPB are aligned in the +Z direction. The portion of terminal TNB located outside the encapsulant 2B has a plate-like shape that extends along the xy plane. The portion of terminal TPB located outside the encapsulant 2B has a plate-like shape that extends along the xy plane.
[0086] Terminals TT1, TT2, and TOUTB (not shown) protrude from the surface of the encapsulant 2B opposite to the surface on which terminals TNB and TPB protrude.
[0087] Figure 14 shows an example of the cross-sectional structure of a semiconductor device of a second modification of the first embodiment. Figure 14 shows a cross-section along the line XIV-XIV in Figure 13 and a cross-section along the xz plane.
[0088] As shown in Figure 14, the conductor 13 includes portions (i.e., circuit patterns) 13h and 13i. Terminal TNB is located on the upper surface of circuit pattern 13h. Circuit pattern 13i is in contact with terminal TT1 on its upper surface. Terminal TT1 protrudes from the plane along the yz plane on the +X side of the sealant 2B.
[0089] The semiconductor chip 30 is connected to the circuit pattern 13i via bonding wires 101 at electrodes (not shown) on its upper surface.
[0090] Terminal TOUTB contacts the upper surface of the semiconductor chip 30 on its lower surface. Terminal TOUTB has a first portion TOUTB1 that contacts the semiconductor chip 30 and a second portion TOUTB2. The second portion TOUTB2 is continuous with the first portion TOUTB1 and is located in the +X direction from the first portion TOUTB1. The second portion TOUTB2 protrudes from the plane along the yz plane on the +X side of the encapsulant 2B. The second portion TOUTB2 is located in the +Z direction from terminal TT1.
[0091] The bonding layer 51 is provided on the upper surface of the second portion TOUTB2 of the terminal TOUTB.
[0092] The circuit board 20 is provided on the upper surface of the bonding layer 61. The conductor 23 includes portions (circuit patterns) 23h and 23i. Terminal TPB is provided on the lower surface of the circuit pattern 23h. On its lower surface, the circuit pattern 23i is in contact with the upper surface of an electrode (not shown) of the semiconductor chip 50 and the upper surface of terminal TT2 via the bonding layer 61. Terminal TT2 protrudes from a plane along the yz plane on the +X side of the encapsulant 2B. Terminal TT2 is located in the +Z direction from the second portion TOUTB2 of terminal TOUTB.
[0093] Figure 15 is a plan view of the interior of a semiconductor device of a second modification of the first embodiment. Figure 15 shows the structure of the interior of the semiconductor device 1 as seen from the +Z direction, and shows the structure along the XV-XV line in Figure 14. Figure 15 shows the region between the substrate 11 and the semiconductor chip 30.
[0094] As shown in Figure 15, terminal TNB overlaps with circuit pattern 13h in the portion including the end on the +X side. The entire semiconductor chip 30 overlaps with circuit pattern 13h. The semiconductor chip 30 is located in the +X direction from terminal TNB.
[0095] Circuit pattern 13i is located in the +X direction relative to circuit pattern 13h. Circuit patterns 13i extend in the +X direction and are spaced apart in the +Y direction. Each circuit pattern 13i is in contact with one bonding wire 101. Each circuit pattern 13i overlaps with one terminal TT1 and is in contact with one terminal. Each terminal TT1 is one of terminals TD1, TG1, and TS1.
[0096] The insulators 90a, 90b, 90c, and 90d surround the semiconductor chip 30. In one example, insulator 90a is located near the lower left corner of the substrate 11. In one example, insulator 90b is located near the upper left corner of the substrate 11. In one example, insulator 90c is located near the lower right corner of the substrate 11. In one example, insulator 90d is located near the upper right corner of the substrate 11. Each of the insulators 90a, 90b, 90c, and 90d is in contact with the upper surface of the substrate 11 and / or the upper surface of the conductor 13, either entirely or partially, on its lower surface.
[0097] Figure 16 is a plan view of the interior of a semiconductor device of a second modification of the first embodiment. Figure 16 shows the structure of the interior of the semiconductor device 1 as seen from the -Z direction, and shows the structure along the line XVI-XVI in Figure 14. Figure 16 shows the region between the semiconductor chip 50 and the substrate 21.
[0098] As shown in Figure 16, terminal TPB overlaps with circuit pattern 23h in the portion including the end on the +X side. Semiconductor chip 50 overlaps with circuit pattern 23h in the portion including the end on the -X side. Semiconductor chip 50 is located in the +X direction relative to terminal TPB.
[0099] Circuit pattern 23i is located in the +X direction relative to circuit pattern 23h. Circuit patterns 23i extend in the +X direction and are spaced apart in the +Y direction. Each circuit pattern 23i overlaps with the semiconductor chip 50 in a portion including the -X side. Each circuit pattern 23i overlaps with one terminal TT2 and is in contact with one terminal TT2. Each terminal TT2 is one of terminals TD2, TG2, and TS2.
[0100] The insulators 90a, 90b, 90c, and 90d surround the semiconductor chip 50. Each of the insulators 90a, 90b, 90c, and 90d is in contact with the lower surface of the substrate 21 or the lower surface of the conductor 23, either entirely or partially, on its upper surface.
[0101] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]
[0102] 1… Semiconductor equipment, 2... Sealing body, 10, 20... Circuit board, TP, TN, TOUT, TD1, TS1, TG1, TD2, TS2, TG2...terminals, 11... Circuit board, 12, 13, 22, 23... Conductors, 13a, 13b, 13c... circuit patterns, 21... Circuit board, 30, 50... Semiconductor chips, 40, 60... chip spacers, 70, 80... Spacers between circuit boards, 90...Insulator
Claims
1. A semiconductor device, A first circuit board comprising an insulating first substrate and a first conductor including a plurality of first portions provided on the surface of the first substrate and separated from each other, A first semiconductor chip having a first surface and a second surface facing each other, the first surface in contact with one of the plurality of first parts, The second conductor on the second surface of the first semiconductor chip, A second semiconductor chip having a third and fourth surface facing each other, and the third surface in contact with one of the plurality of first portions, The third conductor on the fourth surface of the second semiconductor chip, It has a fifth and sixth face that face each other, and a first column that is in contact with one of the plurality of first parts on the fifth face, A second circuit board comprising an insulating second substrate and a fourth conductor comprising a plurality of second portions provided on the surface of the second substrate and spaced apart from each other, wherein one of the plurality of second portions is in contact with the surface of the second conductor opposite to the first semiconductor chip, one of the plurality of second portions is in contact with the surface of the third conductor opposite to the second semiconductor chip, and one of the plurality of second portions is in contact with the sixth surface of the first column, A plurality of insulating columns extending in the direction connecting the first circuit board and the second circuit board, each of which is in contact with the first circuit board and the second circuit board, A encapsulant comprising the first semiconductor chip, the second semiconductor chip, the first column, the plurality of insulating columns, and including the surface of the semiconductor device, A semiconductor device equipped with a semiconductor device.
2. The first column, and the first plurality of insulating columns among the plurality of insulating columns, are located around the first semiconductor chip. The first column and the second plurality of insulating columns among the plurality of insulating columns are located around the second semiconductor chip. The semiconductor device according to claim 1.
3. The first column and the first set of insulating columns surround the first semiconductor chip. The first column and the set of the second plurality of insulating columns surround the second semiconductor chip. The semiconductor device according to claim 2.
4. The first column is located between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 3.
5. It further comprises a second column having a seventh and an eighth face that are opposite to each other, the seventh face being in contact with one of the plurality of first parts, and the eighth face being in contact with one of the plurality of second parts, The first column, the second column, and the first plurality of insulating columns among the plurality of insulating columns are located around the first semiconductor chip, The first column, the second column, and the second plurality of insulating columns among the plurality of insulating columns are located around the second semiconductor chip. The semiconductor device according to claim 1.
6. The first column, the second column, and the first set of insulating columns surround the first semiconductor chip. The first column, the second column, and the second set of multiple insulating columns surround the second semiconductor chip. The semiconductor device according to claim 5.
7. The first column and the second column are located between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 6.
8. The first plurality of insulating columns includes at least a first insulating column and a second insulating column, The second plurality of insulating columns includes at least a third insulating column and a fourth insulating column. The semiconductor device according to any one of claims 2 to 7.
9. The plurality of insulating columns and the sealing body include different materials. The semiconductor device according to any one of claims 1 to 7.
10. A semiconductor device, A first circuit board comprising an insulating first substrate and a first conductor including a plurality of first portions provided on the surface of the first substrate and separated from each other, A first semiconductor chip having a first surface and a second surface facing each other, the first surface in contact with one of the plurality of first parts, A second circuit board comprising an insulating second substrate and a second conductor including a plurality of second portions provided on the surface of the second substrate and separated from each other, A second semiconductor chip having a third and fourth surface facing each other, and the fourth surface in contact with one of the plurality of second parts, A third conductor in contact with the second surface of the first semiconductor chip and the third surface of the second semiconductor chip, A plurality of insulating columns extending in the direction connecting the first circuit board and the second circuit board, each of which is in contact with the first circuit board and the second circuit board, The first semiconductor chip, the second semiconductor chip, and the plurality of insulating pillars are surrounded by a encapsulant that includes the surface of the semiconductor device, A semiconductor device equipped with a semiconductor device.
Citation Information
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