Semiconductor equipment

Abstract

To provide a semiconductor device having a highly reliable terminal structure. [Solution] The semiconductor device of this embodiment comprises a circuit board 10, a circuit board 20 provided above the circuit board 10, a semiconductor chip 30 provided between the circuit board 10 and the circuit board 20, a first column 70 provided between the circuit board 10 and the circuit board 20, and a main terminal TP provided at one end of the circuit board 10 in the Y direction and having a notch 90a. The notch 90a of the main terminal TP has a first portion 90aa, a second portion 90ab, and a third portion 90ac. The first portion 90aa extends in the Y direction from one end of the main terminal TP, the second portion 90ab is continuous with the first portion 90aa and extends in the X direction, and the third portion 90ac is continuous with the second portion 90ab and extends in the Y direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] A semiconductor device including an insulating circuit board on which a semiconductor chip is mounted is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device having a highly reliable terminal structure.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a first circuit board, a second circuit board provided above the first circuit board, a first semiconductor chip provided between the first circuit board and the second circuit board, a first pillar provided between the first circuit board and the second circuit board, and a first terminal provided at one end of the first circuit board in a first direction and having a first cut. The first cut that the first terminal has includes a first portion, a second portion, and a third portion. The first portion extends in the first direction from one end of the first terminal, the second portion is continuous with the first portion and extends in a second direction intersecting the first direction, and the third portion is continuous with the second portion and extends in the first direction.

Brief Description of the Drawings

[0006] [Figure 1] It is a perspective view showing an external structure of a semiconductor device according to an embodiment. [Figure 2]This is a perspective view of the main terminal of the semiconductor device according to the embodiment. [Figure 3] This is a circuit diagram showing the circuit configuration of a semiconductor device according to an embodiment. [Figure 4] This is a plan view showing the internal structure of a semiconductor device according to an embodiment. [Figure 5] This is a cross-sectional view showing the internal structure of a semiconductor device according to an embodiment. [Figure 6] This is a cross-sectional view showing the internal structure of a semiconductor device according to an embodiment. [Figure 7] This is a plan view of the main terminal of the semiconductor device according to the embodiment. [Figure 8] This is a cross-sectional view of the main terminal of the semiconductor device according to the embodiment. [Figure 9] This is a plan view of another main terminal of the semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be denoted by the same reference numerals. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this embodiment, and do not specify the materials, shapes, structures, and arrangements of the components as described below.

[0008] (Embodiment) A semiconductor device of an embodiment will now be described. The semiconductor device has a package structure in which a semiconductor chip and two insulating circuit boards sandwiching the semiconductor chip from above and below are held together with a molding material. The semiconductor device is a power module and is used, for example, for driving the motor of an electric vehicle.

[0009] 1. External structure of a semiconductor device First, the external structure of the semiconductor device 1 of the embodiment will be described with reference to Figures 1 and 2. Figure 1 is a perspective view showing the external structure of the semiconductor device 1 of the embodiment. In the following description, the XYZ Cartesian coordinate system will be used. The X direction corresponds to the longitudinal direction of the external shape of the semiconductor device 1, excluding the terminals. The Y direction corresponds to the width direction of the external shape of the semiconductor device 1, excluding the terminals. The Z direction corresponds to the thickness direction of the external shape of the semiconductor device 1, excluding the terminals, and is also referred to as the upward direction and downward direction.

[0010] The semiconductor device 1 comprises a main body 2, main terminals TP, TN, and TAC, and a plurality of lead terminals TG1, TG2, TD1, TD2, TS1, and TS2. The main body 2 includes a molded material 3, a lower insulating circuit board 10, an upper insulating circuit board 20, semiconductor chips (or semiconductor elements) 30 and 40, chip spacers (or columns) 50 and 60, and inter-board spacers (or columns) 70 and 80.

[0011] Figure 2 is a perspective view showing the main terminals TP, TN, and TAC of the semiconductor device 1 of the embodiment. In Figure 2, the main terminals TP, TN, and TAC are shown as seen through the molding material 3.

[0012] The main terminals TP and TN are provided at one end of the main body 2 in the Y direction. The main terminal TAC, and lead terminals TG1, TG2, TD1, TD2, TS1, and TS2 are provided at the other end of the main body 2 in the Y direction. The lead terminals TG1, TD1, TS1 and TG2, TD2, TS2 are arranged so as to sandwich the main terminal TAC. Each of the main terminals TP, TN, and TAC has notches 90a and 90b.

[0013] 2. Circuit configuration of semiconductor device Next, the circuit configuration of the semiconductor device 1 of the embodiment will be described with reference to Figure 3. Figure 3 is a circuit diagram showing the circuit configuration of the semiconductor device of the embodiment.

[0014] The semiconductor device 1 includes, for example, a half-bridge circuit. The semiconductor device 1 includes transistors NM1 and NM2, and, as described above, main terminals TP, TN, TAC, and lead terminals TG1, TG2, TD1, TD2, TS1, and TS2.

[0015] Each of the transistors NM1 and NM2 is, for example, an n-type MOS field-effect transistor.

[0016] Each of the main terminals TP and TN is a power supply terminal in the semiconductor device 1. A positive power supply voltage is supplied to the main terminal TP. The main terminal TP is also referred to as the P terminal. A negative power supply voltage is supplied to the main terminal TN. The main terminal TN is also referred to as the N terminal. The main terminal TAC is an output terminal in the semiconductor device 1. An AC voltage is output from the main terminal TAC. The main terminal TAC is also referred to as the AC terminal.

[0017] Each of the lead terminals TG1 and TG2 is a control terminal in the semiconductor device 1. Each of the lead terminals TD1, TD2, TS1, and TS2 is a terminal for monitoring the operation of the semiconductor device 1. The lead terminal TD1 senses the voltage of the drain of the transistor NM1. The lead terminal TS1 senses the voltage of the source of the transistor NM1. The lead terminal TD2 senses the voltage of the drain of the transistor NM2. The lead terminal TS2 senses the voltage of the source of the transistor NM2.

[0018] The drain of the transistor NM1 is connected to the main terminal TP. The source of the transistor NM1 is connected to the main terminal TAC. The gate of the transistor NM1 is connected to the lead terminal TG1. The drain of the transistor NM2 is connected to the main terminal TAC. The source of the transistor NM2 is connected to the main terminal TN. The gate of the transistor NM2 is connected to the lead terminal TG2.

[0019] The drain of transistor NM1 is connected to lead terminal TD1. The source of transistor NM1 is connected to lead terminal TS1. The drain of transistor NM2 is connected to lead terminal TD2. The source of transistor NM2 is connected to lead terminal TS2.

[0020] 3. Internal structure of semiconductor device Next, the internal structure of the semiconductor device 1 of the embodiment will be described with reference to Figures 4, 5, and 6. Figure 4 is a plan view showing the internal structure of the semiconductor device 1 of the embodiment. Figure 5 is a cross-sectional view along the line VV in Figure 4. Figure 6 is a cross-sectional view along the line VI-VI in Figure 4. Note that the plan view shown in Figure 4 shows the configuration on the insulating circuit board 10 when viewed through the insulating circuit board 20 and the molding material 3. Furthermore, in the following figures, the arrow directions in the X, Y, and Z directions will be referred to as the +X direction, +Y direction, and +Z direction, respectively, and the directions opposite to the arrow directions will be referred to as the -X direction, -Y direction, and -Z direction, respectively.

[0021] As shown in Figure 4, a semiconductor chip 30 is provided on one end of the insulating circuit board 10 in the X direction, and a semiconductor chip 40 is provided on the other end of the insulating circuit board 10. Inter-substrate spacers 70 and 80 are provided between semiconductor chip 30 and semiconductor chip 40 in the Y direction. As shown in Figures 5 and 6, inter-substrate spacers 70 and 80 are provided between insulating circuit board 10 and insulating circuit board 20.

[0022] The insulating circuit board 10 includes a conductive plate (or conductive layer) 11, a conductive plate (or conductive layer) 12, and a ceramic substrate 13. The ceramic substrate 13 is provided between the conductive plate 11 and the conductive plate 12. That is, the conductive plate 11 is placed on the upper surface of the ceramic substrate 13, and the conductive plate 12 is placed on the lower surface of the ceramic substrate 13. The thickness of each of the conductive plates 11 and 12 is, for example, about 0.4 mm. The conductive plates 11 and 12 include, for example, copper. The ceramic substrate 13 is formed from an insulating material and has electrical insulating properties.

[0023] The conductive plate 11 is provided with slits 14 formed by removing a portion of the conductive plate 11 in a certain pattern. In other words, the slits 14 are grooves provided in the conductive plate 11, where a portion of the conductive plate 11 has been removed.

[0024] The conductive plate 11 is separated into three conductive patterns (or circuit patterns, conductive layers) 11a, 11b, and 11c by a slit 14. The conductive patterns 11a, 11b, and 11c are electrically insulated from each other.

[0025] Similarly, the insulating circuit board 20 includes a conductive plate (or conductive layer) 21, a conductive plate (or conductive layer) 22, and a ceramic substrate 23. The ceramic substrate 23 is provided between the conductive plate 21 and the conductive plate 22. That is, the conductive plate 21 is placed on the upper surface of the ceramic substrate 23, and the conductive plate 22 is placed on the lower surface of the ceramic substrate 23. The thickness of each of the conductive plates 21 and 22 is, for example, about 0.4 mm. The conductive plates 21 and 22 include, for example, copper. The ceramic substrate 23 is formed from an insulating material and has electrical insulating properties.

[0026] The conductive plate 22 is separated into multiple conductive patterns (or circuit patterns, conductive layers) that are electrically insulated from each other by slits, although this is not shown in the figure.

[0027] A semiconductor chip 30 is provided on the conductive pattern 11a via a conductive member, such as solder material 31. A chip spacer 50 is provided on the semiconductor chip 30 via a conductive member, such as solder material 51. Furthermore, a conductive pattern of the conductive plate 22 is provided on the chip spacer 50 via a conductive member, such as solder material 52.

[0028] The semiconductor chip 30 includes a transistor NM1. The semiconductor chip 30 has the gate, source, and drain of the transistor NM1 as electrodes.

[0029] For example, the drain of the semiconductor chip 30 is electrically connected to the conductive pattern 11a via solder material 31. The source of the semiconductor chip 30 is electrically connected to the chip spacer 50 via solder material 51.

[0030] The semiconductor chip 30 and the chip spacer 50 are provided between the insulating circuit board 10 and the insulating circuit board 20. The chip spacer 50 is provided between the insulating circuit board 20 and the semiconductor chip 30. The chip spacer 50 has, for example, a rectangular shape when viewed from the Z direction and has a column shape with thickness in the Z direction. The chip spacer 50 contains a conductive material and is conductive. Therefore, the source of the semiconductor chip 30 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 51, the chip spacer 50, and the solder material 52. The chip spacer 50 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 30 to the insulating circuit board 20.

[0031] A substrate spacer 70 is provided on the conductive pattern 11b via a conductive member, such as solder material 71. A conductive pattern of the conductive plate 22 is provided on the substrate spacer 70 via a conductive member, such as solder material 72.

[0032] The inter-substrate spacer 70 has, for example, a cylindrical shape that is circular when viewed from the Z direction and has thickness in the Z direction. In one example, the inter-substrate spacer 70 has the shape of a cylinder or a rectangular prism. The inter-substrate spacer 70 contains a conductive material and is conductive. Therefore, the conductive pattern 11b is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 71, the inter-substrate spacer 70, and the solder material 72.

[0033] A semiconductor chip 40 is provided on the conductive pattern 11c via a conductive member, such as solder material 41. A chip spacer 60 is provided on the semiconductor chip 40 via a conductive member, such as solder material 61. Furthermore, a conductive pattern of the conductive plate 22 is provided on the chip spacer 60 via a conductive member, such as solder material 62.

[0034] The semiconductor chip 40 includes a transistor NM2. The semiconductor chip 40 has the gate, source, and drain of the transistor NM2 as electrodes.

[0035] For example, the drain of the semiconductor chip 40 is electrically connected to the conductive pattern 11c via solder material 41. The source of the semiconductor chip 40 is electrically connected to the chip spacer 60 via solder material 61.

[0036] The semiconductor chip 40 and chip spacer 60 are provided between the insulating circuit board 10 and the insulating circuit board 20. The chip spacer 60 is provided between the insulating circuit board 20 and the semiconductor chip 40. The chip spacer 60 has, for example, a rectangular shape when viewed from the Z direction and has a column shape with thickness in the Z direction. The chip spacer 60 contains a conductive material and is conductive. Therefore, the source of the semiconductor chip 40 is electrically connected to the conductive pattern of the conductive plate 22 via solder material 61, chip spacer 60, and solder material 62. The chip spacer 60 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 40 to the insulating circuit board 20.

[0037] A substrate spacer 80 is provided on the conductive pattern 11c via a conductive member, such as solder material 81. A conductive pattern of the conductive plate 22 is provided on the substrate spacer 80 via a conductive member, such as solder material 82.

[0038] The inter-substrate spacer 80 has, for example, a cylindrical shape that is circular when viewed from the Z direction and has thickness in the Z direction. In one example, the inter-substrate spacer 80 has the shape of a cylinder or a rectangular prism. The inter-substrate spacer 80 contains a conductive material and is conductive. Therefore, the conductive pattern 11c is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 81, the inter-substrate spacer 80, and the solder material 82.

[0039] Furthermore, as shown in Figure 4, main terminals TP and TN are provided at one end of the insulating circuit board 10 in the Y direction. Main terminal TAC is provided at the other end of the insulating circuit board 10 in the Y direction. Each of the main terminals TP, TN, and TAC has a conductive material, such as a metal material including copper. The thickness of each of the main terminals TP, TN, and TAC is, for example, 0.8 mm.

[0040] A main terminal TP is located on one end of the conductive pattern 11a in the Y direction. The main terminal TP is joined to the conductive pattern 11a via a conductive member, such as solder. That is, the main terminal TP is electrically connected to the conductive pattern 11a via solder. A main terminal TN is located on one end of the conductive pattern 11b in the Y direction. The main terminal TN is joined to the conductive pattern 11b via a conductive member, such as solder. That is, the main terminal TN is electrically connected to the conductive pattern 11b via solder. Furthermore, a main terminal TAC is located on the other end of the conductive pattern 11c in the Y direction. The main terminal TAC is joined to the conductive pattern 11c via a conductive member, such as solder. That is, the main terminal TAC is electrically connected to the conductive pattern 11c via solder.

[0041] Furthermore, multiple lead terminals TG1, TG2, TD1, TD2, TS1, and TS2 are provided at the other end of the insulating circuit board 10 in the Y direction.

[0042] Conductive patterns 11a, 11d, and 11e are arranged on the other end of the insulating circuit board 10 in the Y direction relative to the semiconductor chip 30. Each of the conductive patterns 11d and 11e is an island-shaped pattern.

[0043] The lead terminal TG1 is bonded to the conductive pattern 11d via a conductive material, such as solder. The conductive pattern 11d is connected to the pad 33g of the semiconductor chip 30 by a bonding wire 32g. The pad 33g is connected to the gate of the semiconductor chip 30. Thus, the lead terminal TG1 is electrically connected to the gate of the semiconductor chip 30 via the conductive pattern 11d, the bonding wire 32g, and the pad 33g.

[0044] The lead terminal TD1 is joined to the conductive pattern 11a via a conductive material, such as solder. The conductive pattern 11a is connected to the drain of the semiconductor chip 30. Thus, the lead terminal TD1 is electrically connected to the drain of the semiconductor chip 30 via the conductive pattern 11a.

[0045] The lead terminal TS1 is bonded to the conductive pattern 11e via a conductive material, such as solder. The conductive pattern 11e is connected to the pad 33s of the semiconductor chip 30 by a bonding wire 32s. The pad 33s is connected to the source of the semiconductor chip 30. Thus, the lead terminal TS1 is electrically connected to the source of the semiconductor chip 30 via the conductive pattern 11e, the bonding wire 32s, and the pad 33s.

[0046] Furthermore, conductive patterns 11c, 11f, and 11h are arranged on the other end of the insulating circuit board 10 in the Y direction relative to the semiconductor chip 40. Each of the conductive patterns 11f and 11h is an island-shaped pattern.

[0047] The lead terminal TG2 is bonded to the conductive pattern 11f via a conductive material, such as solder. The conductive pattern 11f is connected to the pad 43g of the semiconductor chip 40 by a bonding wire 42g. The pad 43g is connected to the gate of the semiconductor chip 40. Thus, the lead terminal TG2 is electrically connected to the gate of the semiconductor chip 40 via the conductive pattern 11f, the bonding wire 42g, and the pad 43g.

[0048] The lead terminal TD2 is joined to the conductive pattern 11c via a conductive material, such as solder. The conductive pattern 11c is connected to the drain of the semiconductor chip 40. Thus, the lead terminal TD2 is electrically connected to the drain of the semiconductor chip 40 via the conductive pattern 11c.

[0049] The lead terminal TS2 is bonded to the conductive pattern 11h via a conductive material, such as solder. The conductive pattern 11h is connected to the pad 43s of the semiconductor chip 40 by a bonding wire 42s. The pad 43s is connected to the source of the semiconductor chip 40. Thus, the lead terminal TS2 is electrically connected to the source of the semiconductor chip 40 via the conductive pattern 11h, the bonding wire 42s, and the pad 43s.

[0050] As shown in Figure 4, each of the main terminals TP, TN, and TAC is provided with notches 90a, 90b, and a hole 90c. In Figure 4, when viewed from the Z direction, that is, when viewed from above (or from a direction perpendicular to) the surface of the conductive plate 11 of the insulating circuit board 10, the notch 90a of the main terminal TP extends from one end of the main terminal TP in the Y direction in the -Y direction, then in the -X direction, and further in the -Y direction. The notch 90b of the main terminal TP extends from one end of the main terminal TP in the Y direction in the -Y direction, then in the +X direction, and further in the -Y direction. The notches 90a and 90b of the main terminal TN have substantially the same shape as the notches 90a and 90b of the main terminal TP.

[0051] In Figure 4, viewed from the Z direction, the notch 90a of the main terminal TAC extends from one end of the main terminal TAC in the Y direction in the +Y direction, then in the +X direction, and further in the +Y direction. The notch 90b of the main terminal TAC extends from one end of the main terminal TAC in the Y direction in the +Y direction, then in the -X direction, and further in the +Y direction.

[0052] In Figure 4, viewed from the Z direction, the holes 90c of the main terminals TP, TN, and TAC are circular in shape. The holes 90c are located between the notches 90a and 90b in the X direction.

[0053] The notches 90a and 90b of the main terminals TP, TN, and TAC are described in detail below.

[0054] 4. Structure of the main terminal Next, the structures of the main terminals TP, TN, and TAC in the semiconductor device 1 of the embodiment will be described in detail with reference to Figures 7, 8, and 9. Figure 7 is a plan view of the main terminal TP (or TN) in the semiconductor device 1 of the embodiment. Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7, showing the main terminal TP and the cross-sectional structure of the insulating circuit board 10 including the conductive pattern 11a.

[0055] The main terminal TP has a shape in which a flat metal member along the XY plane extends in the -Y direction, is slightly bent in the +Z direction, then extends in the -Y direction, and is further bent in the +Z direction.

[0056] When viewed from the Z direction, the main terminal TP has a rectangular (or polygonal) shape. As described above, the main terminal TP has notches 90a and 90b and a hole 90c.

[0057] As shown in Figure 7, the notch 90a has a first portion 90aa extending in the -Y direction from one end of the main terminal TP in the Y direction, a second portion 90ab extending in the -X direction, and a third portion 90ac extending in the -Y direction. The second portion 90ab is positioned continuously with the end of the first portion 90aa. The third portion 90ac is positioned continuously with the end of the second portion 90ab.

[0058] The first part 90aa has a first width in the X direction and a first length in the Y direction. The second part 90ab has a second width in the Y direction and a second length in the X direction. The third part 90ac has a third width in the X direction and a third length in the Y direction. The first width, second width, and third width may be the same or different. The first length, second length, and third length may be different or the same. For example, the first length may be longer than the second and third lengths, and the third length may be longer than the second length.

[0059] The notch 90b is positioned close to the notch 90a in the X direction. The notch 90b has a structure that is line-symmetric with respect to the notch 90a, with respect to a line along the Y direction as the axis of symmetry.

[0060] The notch 90b has a first portion 90ba extending in the -Y direction from one end of the main terminal TP in the Y direction, a second portion 90bb extending in the +X direction, and a third portion 90bc extending in the -Y direction. The second portion 90bb is positioned continuously with the end of the first portion 90ba. The third portion 90bc is positioned continuously with the end of the second portion 90bb.

[0061] Similar to the cut 90a, the first part 90ba has a first width in the X direction and a first length in the Y direction. The second part 90bb has a second width in the Y direction and a second length in the X direction. The third part 90bc has a third width in the X direction and a third length in the Y direction. The first width, second width, and third width may be the same or different. The first length, second length, and third length may be different or the same. For example, the first length may be longer than the second and third lengths, and the third length may be longer than the second length.

[0062] Furthermore, as shown in Figures 7 and 8, a conductive member, such as solder material 91, is provided between the main terminal TP and the conductive pattern 11a. In region A shown in Figure 7, the main terminal TP is connected to the conductive pattern 11a via the solder material 91. A fillet 91a of the solder material 91 is formed on the side surface of the main terminal TP.

[0063] The first portions 90aa and 90ba of the notches 90a and 90b of the main terminal TP are provided in region A where the main terminal TP and the conductive pattern 11a are connected by solder material 91. For this reason, fillets 91a are formed not only on the outer surface of the main terminal TP, but also on the side surface of the first portion 90aa of the notch 90a and the side surface of the first portion 90ba of the notch 90b.

[0064] The first length of the first portion 90aa in the Y direction is greater than or equal to the length of region A in the Y direction. In other words, the first length of the first portion 90aa in the Y direction is greater than or equal to the length of the solder material 91 between the conductive pattern 11a and the main terminal TP in the Y direction. Similarly, the first length of the first portion 90ba in the Y direction is greater than or equal to the length of region A in the Y direction. In other words, the first length of the first portion 90ba in the Y direction is greater than or equal to the length of the solder material 91 between the conductive pattern 11a and the main terminal TP in the Y direction.

[0065] The structure of the main terminal TN is almost the same as that of the main terminal TP. When viewed from the Z direction, the main terminal TN has a rectangular (or polygonal) shape. The main terminal TN is provided with notches 90a, 90b, and a hole 90c. The structure of the notches 90a, 90b, and hole 90c of the main terminal TN is almost the same as that of the notches 90a, 90b, and hole 90c of the main terminal TP.

[0066] Figure 9 is a plan view of the main terminal TAC in the semiconductor device 1 of the embodiment. The structure of the main terminal TAC is almost the same as that of the main terminal TP. The main terminal TAC has a structure that is line-symmetric with respect to the main terminal TP with respect to a line along the X direction as the axis of symmetry, and is further positioned near the center of the insulating circuit board 10 in the X direction.

[0067] The main terminal TAC has a shape in which a flat metal member along the XY plane extends in the +Y direction, is slightly bent in the +Z direction, then extends again in the +Y direction, and is further bent in the +Z direction.

[0068] Viewed from the Z direction, the main terminal TAC has a rectangular (or polygonal) shape. The main terminal TAC is provided with notches 90a, 90b, and a hole 90c. The structure of the notches 90a, 90b, and hole 90c of the main terminal TAC is substantially the same as that of the notches 90a, 90b, and hole 90c of the main terminal TP.

[0069] According to the embodiments described above, a semiconductor device having a highly reliable terminal structure can be provided.

[0070] In the configuration of this embodiment, the first portions 90aa and 90ba of the notches 90a and 90b of the main terminal TP are provided in region A where the main terminal TP (or TN, TAC) and the conductive pattern 11a (or 11b, 11c) are connected. As a result, fillets 91a of the solder material 91 are formed on the outer surface of the main terminal TP and on the side of the main terminal TP where the first portions 90aa and 90ba are provided. This increases the area on the side of the main terminal TP where fillets 91a are formed, making it possible to securely connect the main terminal TP to the conductive pattern 11a of the insulating circuit board 10.

[0071] Furthermore, in the configuration of this embodiment, notches 90a and 90b are provided in the main terminal TP (or TN, TAC). When current flows through the semiconductor device 1, the semiconductor device 1 may become hot due to heat generation. As a result, deformation due to stress occurs in the insulating circuit boards 10 and 20, as well as the main terminal TP, and delamination may occur in the solder material joining the main terminal TP and the conductive pattern 11a. As described above, since the main terminal TP has notches 90a and 90b, the stress generated in the main terminal TP can be relieved. This prevents delamination of the solder material joining the main terminal TP and the conductive pattern 11a.

[0072] Furthermore, in the configuration of this embodiment, the notches 90a and 90b provided in the main terminal TP (or TN, TAC) are covered with the molding material 3. As a result, the molding material 3 fits into the notches 90a and 90b, strengthening the adhesion or bonding between the molding material 3 and the main terminal TP. This makes it possible to form a strong structure that reduces the likelihood of damage to the main terminal TP or the molding material 3 even when force is applied to the main terminal TP due to external or internal stress. For example, even when an external force is applied to the main terminal TP to pull it outwards, or when an internal stress is applied to the main terminal TP to pull it, a strong structure that reduces deformation of the main terminal TP or the molding material 3 can be formed, that is, the durability against tensile force can be improved.

[0073] As described above, according to the semiconductor device 1 of the embodiment, it is possible to form a highly reliable terminal structure.

[0074] In the embodiments described above, an example was explained in which the semiconductor device constitutes a MOS-type field-effect transistor (i.e., a MOSFET). However, the semiconductor device may also constitute other switching elements, such as an IGBT (insulated gate bipolar transistor). When the semiconductor device constitutes an IGBT, the source corresponds to the emitter and the drain corresponds to the collector.

[0075] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0076] 1...Semiconductor device, 2...Main body, 3...Molding material, 10...Insulating circuit board, 11...Conductive plate (conductive layer), 11a...Conductive pattern, 11b...Conductive pattern, 11c...Conductive pattern, 11d...Conductive pattern, 11e...Conductive pattern, 11f...Conductive pattern, 11h...Conductive pattern, 12...Conductive plate (conductive layer), 13...Ceramic substrate, 14...Slit, 20...Insulating circuit board, 21...Conductive plate (conductive layer), 22...Conductive plate (conductive layer), 23...Ceramic substrate, 30...Semiconductor chip, 31...Solder material, 32g...Bonding wire, 32s...Bonding wire, 33 g...pad, 33s...pad, 40...semiconductor chip, 41...solder material, 42g...bonding wire, 42s...bonding wire, 43g...pad, 43s...pad, 50...chip spacer, 51...solder material, 52...solder material, 60...chip spacer, 61...solder material, 62...solder material, 70...inter-board spacer, 71...solder material, 72...solder material, 80...inter-board spacer, 90a...notch, 90b...notch, 90c...hole, 91...solder material, 91a...fillet, NM1...transistor, NM2...transistor, TP...main terminal, TN...main terminal, TAC...main terminal.

Claims

1. First circuit board and A second circuit board is provided above the first circuit board, A first semiconductor chip provided between the first circuit board and the second circuit board, A first column provided between the first circuit board and the second circuit board, A first terminal is provided at one end of the first circuit board in the first direction and has a first notch, It is equipped with, The first notch of the first terminal has a first portion, a second portion, and a third portion. The first portion extends from one end of the first terminal in the first direction, The second portion is continuous with the first portion and extends in a second direction intersecting the first direction. The third portion is continuous with the second portion and extends in the first direction. Semiconductor equipment.

2. The device further comprises a conductive member provided between the first circuit board and the first terminal, connecting the first circuit board and the first terminal. The first portion of the first notch of the first terminal is arranged in the region where the conductive member is provided. The semiconductor device according to claim 1.

3. In the first direction, the length of the first portion of the first cut is greater than or equal to the length of the conductive member. The semiconductor device according to claim 2.

4. The side surface of the first terminal having the first portion of the first notch is provided with a fillet of the conductive member, The semiconductor device according to claim 2.

5. The device further comprises a molding material that covers the first circuit board and the second circuit board, The first notch of the first terminal is covered by the molding material. The semiconductor device according to claim 1.

6. The first circuit board comprises a first conductive layer, a second conductive layer, and a first insulating substrate provided between the first conductive layer and the second conductive layer. The second circuit board comprises a third conductive layer, a fourth conductive layer, and a second insulating substrate provided between the third conductive layer and the fourth conductive layer. The semiconductor device according to claim 1.

7. The first terminal has a second notch provided in the second direction relative to the first notch, The second cut has a fourth portion, a fifth portion, and a sixth portion. The fourth portion extends from one end of the first terminal in the first direction, The fifth portion is continuous with the fourth portion and extends in the second direction, The sixth portion is continuous with the fifth portion and extends in the first direction. The semiconductor device according to claim 1.

8. A second semiconductor chip is provided between the first circuit board and the second circuit board, A second column is provided between the first circuit board and the second circuit board, A third column is provided between the first semiconductor chip and the second circuit board, A fourth column is provided between the second semiconductor chip and the second circuit board, The semiconductor device according to claim 1, further comprising:

9. The first column has a circular shape when viewed from a third direction perpendicular to the first and second directions, and has thickness in the third direction. The semiconductor device according to claim 1.

10. The first column electrically connects the first circuit board and the second circuit board. The semiconductor device according to claim 1.

11. Each of the first and second columns has a circular shape when viewed from a third direction perpendicular to the first and second directions, and has thickness in the third direction. Each of the third and fourth columns has a rectangular shape when viewed from the third direction and has thickness in the third direction. The semiconductor device according to claim 8.

12. Each of the first column and the second column electrically connects the first circuit board and the second circuit board, The third column electrically connects the first semiconductor chip and the second circuit board. The fourth column electrically connects the second semiconductor chip and the second circuit board. The semiconductor device according to claim 8.

13. The first circuit board is further provided with a second terminal having a notch at one end in the first direction, provided in the second direction relative to the first terminal. The notch in the second terminal has a seventh portion, an eighth portion, and a ninth portion. The seventh portion extends from one end of the second terminal in the first direction, The eighth portion is continuous with the seventh portion and extends in the second direction, The ninth portion is continuous with the eighth portion and extends in the first direction. The semiconductor device according to claim 1.

14. The first circuit board is provided at the other end in the first direction and further comprises a third terminal having a notch, The notch in the third terminal has a tenth portion, an eleventh portion, and a twelfth portion, The tenth portion extends from one end of the third terminal in the first direction, The 11th portion is continuous with the 10th portion and extends in the second direction, The 12th portion is continuous with the 11th portion and extends in the first direction. The semiconductor device according to claim 13.

15. The system further comprises a second semiconductor chip provided between the first circuit board and the second circuit board, The first semiconductor chip includes a first MOS-type field-effect transistor, The second semiconductor chip includes a second MOS-type field-effect transistor, The first terminal is electrically connected to the drain of the first MOS field-effect transistor. The second terminal is electrically connected to the source of the second MOS field-effect transistor. The third terminal is electrically connected to the source of the first MOS field-effect transistor and the drain of the second MOS field-effect transistor. The semiconductor device according to claim 14.

16. The semiconductor device according to claim 1, wherein the first semiconductor chip includes a MOS-type field-effect transistor.

17. The semiconductor device according to claim 1, wherein the first semiconductor chip includes an IGBT (insulated gate bipolar transistor).

18. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer contain copper. The semiconductor device according to claim 6.

19. The semiconductor device according to claim 6, wherein the first insulating substrate and the second insulating substrate include ceramic substrates.

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