Semiconductor equipment

Abstract

By accurately measuring the current flowing through power transistors, the reliability of semiconductor devices can be improved. [Solution] The semiconductor chip CHP1 has a power transistor and a source electrode SE1 electrically connected to the source region of the power transistor. The source electrode SE1 and the lead terminal LD1 are electrically connected by a wire BW1. The source electrode SE1 includes detection points 13 and 14 for detecting the value of the current flowing through the power transistor. Detection points 13 and 14 are positioned to sandwich the junction BW1a of the wire BW1 which is joined to the source electrode SE1.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a source electrode having a detection location for detecting a current flowing through a transistor.

Background Art

[0002] A semiconductor device in which a power semiconductor chip having a power transistor and a control semiconductor chip having a control circuit for controlling the gate potential of the power transistor are encapsulated is known. Further, the control semiconductor chip may have a function of detecting the value of the load current of the power transistor. In order to detect the value of the load current, a sense transistor for current sensing is provided in addition to the power transistor used as a main cell in the power semiconductor chip, and a detection location for detecting the value of the current is provided at a part of the source electrode of the power transistor. In the sense circuit provided in the control semiconductor chip, the value of the current flowing through the power transistor is measured based on the value of the current flowing through the sense transistor and a preset sense ratio.

[0003] For example, Patent Document 1 discloses a technique of laminating a control semiconductor chip on a power semiconductor chip, and a semiconductor device in which these semiconductor chips are encapsulated. Further, the source electrode of the power semiconductor chip of Patent Document 1 is electrically connected to a lead terminal via a wire.

[0004] Patent Document 2 discloses a technique of arranging a power semiconductor chip and a control semiconductor chip side by side, and a semiconductor device in which these semiconductor chips are encapsulated. The control semiconductor chip of Patent Document 2 has a sense circuit. Further, the source electrode of the power semiconductor chip of Patent Document 2 is electrically connected to a lead terminal via a clip.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0369278 [Patent Document 2] Japanese Patent Publication No. 2023-69756 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As described above, in order to detect the load current, a detection point for detecting the current value is provided on a part of the source electrode of the power transistor. However, when the source electrode is electrically connected to the lead terminal via a wire, assembly variations such as misalignment of the wire connection position or variations in the connection area may occur.

[0007] The detection point is positioned to obtain a representative (average) value of the power transistor's potential. However, a voltage drop occurs as the distance from the source electrode and wire junction increases, causing a gradient in the surface potential distribution of the source electrode. Therefore, due to the effects of assembly variations, it becomes difficult to stably obtain the same potential from the detection point for each semiconductor device, making it difficult to accurately measure the current flowing through the power transistor. Consequently, this presents a challenge in terms of reduced reliability of the semiconductor device.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0009] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0010] A semiconductor device in one embodiment comprises a die pad, a first semiconductor chip mounted on the die pad, and a first lead terminal positioned away from the die pad. The first semiconductor chip has a power transistor and a first source electrode electrically connected to the source region of the power transistor. The first source electrode is electrically connected to the first lead terminal via a conductive first bonding member. The first source electrode includes a first detection location and a second detection location for detecting the value of the current flowing through the power transistor. The first detection location and the second detection location are positioned to sandwich a first bonding location of the first bonding member bonded to the first source electrode. [Effects of the Invention]

[0011] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is an equivalent circuit diagram showing the semiconductor device in Embodiment 1. [Figure 2] Figure 2 is a plan view showing the mounting configuration of the semiconductor device in Embodiment 1. [Figure 3A] Figure 3A is a cross-sectional view along line AA shown in Figure 2. [Figure 3B] Figure 3B is a cross-sectional view along line BB shown in Figure 2. [Figure 4] Figure 4 is a plan view of the main part, which is an enlarged portion of Figure 2. [Figure 5] Figure 5 is a plan view of the main part, which is an enlarged portion of Figure 2. [Figure 6] Figure 6 is a plan view illustrating the location of the detection point in Embodiment 1. [Figure 7] Figure 7 is a cross-sectional view showing the power transistor and sense transistor in Embodiment 1. [Figure 8] Figure 8 is a cross-sectional view showing the MOSFET in Embodiment 1. [Figure 9] FIG. 9 is a partial plan view showing a semiconductor device in a study example. [Figure 10] FIG. 10 is experimental data obtained by the inventors of the present application. [Figure 11A] FIG. 11A is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1 along the line A-A shown in FIG. 2. [Figure 11B] FIG. 11B is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1 along the line B-B shown in FIG. 2. [Figure 12A] FIG. 12A is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11 along the line A-A shown in FIG. 2. [Figure 12B] FIG. 12B is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11 along the line B-B shown in FIG. 2.

MODE FOR CARRYING OUT THE INVENTION

[0013] Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0014] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane composed of the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0015] (Embodiment 1) <Equivalent circuit of semiconductor device> Hereinafter, the semiconductor device PKG in Embodiment 1 will be described with reference to FIG. 1. The semiconductor device PKG is a semiconductor package including a semiconductor chip CHP1 and a semiconductor chip CHP2.

[0016] As shown in Figure 1, the semiconductor chip CHP1 has a power transistor 11 and a sense transistor 12. The power transistor 11 constitutes the main cell of the semiconductor chip CHP1. The sense transistor 12 is used to detect the value of the current flowing through the power transistor 11.

[0017] For example, the power transistor 11 and the sense transistor 12 form a current mirror circuit such that the ratio of the current flowing through the power transistor 11 to the current flowing through the sense transistor 12 is 10000:1 (sense ratio).

[0018] Furthermore, the source electrode SE1 of the power transistor 11 includes detection points 13 and 14 for detecting the value of the current flowing through the power transistor 11. The main feature of Embodiment 1 is that it includes not only detection point 13 but also detection point 14, which will be explained in detail later.

[0019] The semiconductor chip CHP2 has a gate potential control circuit 21 and a sense circuit 22. The gate potential control circuit 21 is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. The gate potential control circuit 21 controls the gate potential supplied to the power transistor 11, thereby controlling the on / off state of the power transistor 11.

[0020] The sense circuit 22 is electrically connected to the source electrode SE1 via detection points 13 and 14, and is also electrically connected to the source region of the sense transistor 12. The sense circuit 22 measures the value of the current flowing through the power transistor 11 based on the value of the current flowing through the sense transistor 12 and a preset sense ratio.

[0021] In detail, the sense circuit 22 receives the source voltage of the sense transistor 12 from pad PD2, which is electrically connected to the sense transistor 12, and the source voltage of the power transistor 11 from pad PD1, which is electrically connected to the source electrode SE1. The sense circuit 22 then corrects the difference between the source voltage of the sense transistor 12 and the source voltage of the power transistor 11 so that it becomes zero. In other words, the sense circuit 22 corrects the source voltage of the sense transistor 12 and the source voltage of the power transistor 11 so that they become equal. After that, the sense circuit 22 converts the sense current input from pad PD2 into a voltage signal. In this way, the value of the current flowing through the power transistor 11 is measured based on the voltage signal and a preset sense ratio.

[0022] The sense ratio is calculated as "the value of the current flowing through power transistor 11 / the value of the current flowing through sense transistor 12". The "value of the current flowing through sense transistor 12" can be calculated by substituting it with "the source voltage of power transistor 11 input from pad PD1 / the resistance value of sense transistor 12".

[0023] If an abnormal value, such as an overcurrent, is detected in the current flowing through the power transistor 11, the gate potential control circuit 21 controls the gate potential supplied to the power transistor 11, for example, by turning off the power transistor 11.

[0024] <Implementation configuration of semiconductor device> The mounting configuration of the semiconductor device package will be described below with reference to Figures 2 and 3. Figure 3A shows a cross-sectional view along line AA shown in Figure 2. Figure 3B also shows a cross-sectional view along line BB shown in Figure 2.

[0025] As shown in Figures 2 and 3, the semiconductor device package comprises a semiconductor chip CHP1, a semiconductor chip CHP2, a die pad DP, a lead terminal LD1, a lead terminal LD2, multiple lead terminals LD3, a wire BW1, a wire BW2, multiple wires BW3, and a sealing resin MR.

[0026] The die pad DP, lead terminal LD1, lead terminal LD2, and multiple lead terminals LD3 are arranged apart from each other and are made of a metallic material such as a copper alloy.

[0027] The semiconductor chip CHP1 has an upper surface TS1 and a lower surface BS1. The semiconductor chip CHP1 has a source electrode SE1, a gate pad GP, a pad PD1, and a pad PD2 formed on the upper surface TS1. The source electrode SE1 and pad PD1 are electrically connected to the source region of the power transistor 11, respectively. The gate pad GP is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. Pad PD2 is electrically connected to the source region of the sense transistor 12.

[0028] Furthermore, the semiconductor chip CHP1 has a drain electrode DE formed on its lower surface BS1. The drain electrode DE is electrically connected to the drain regions of the power transistor 11 and the sense transistor 12, respectively.

[0029] The semiconductor chip CHP1 is mounted on the die pad DP via a conductive bonding material BD1, with its lower surface BS1 facing the die pad DP. That is, the drain electrode DE is electrically connected to the die pad DP via the conductive bonding material BD1. The conductive bonding material BD1 is, for example, silver paste.

[0030] The semiconductor chip CHP2 has an upper surface TS2 and a lower surface BS2. The semiconductor chip CHP2 has a plurality of pads PD3 formed on the upper surface TS2. The semiconductor chip CHP2 is mounted on the source electrode SE1 via an insulating bonding material BD2 such that the lower surface BS2 faces the upper surface TS1 of the semiconductor chip CHP1. The insulating bonding material BD2 is, for example, a DAF (Die Attach Film) material.

[0031] The source electrode SE1 is electrically connected to the lead terminal LD1 via a conductive bonding wire BW1. The source electrode SE1 is electrically connected to the lead terminal LD2 via a conductive bonding wire BW2. As shown in Figure 2, the semiconductor chip CHP2 is located between wires BW1 and BW2. The gate pad GP, pad PD1, and pad PD2 are each electrically connected to a portion of a plurality of pads PD3 via a conductive bonding wire BW3. The remaining portions of the plurality of pads PD3 are each electrically connected to a plurality of lead terminals LD3 via wire BW3.

[0032] To reduce the resistance component connected to the source electrode SE1, wires BW1 and BW2 are each thicker than wire BW3. That is, the diameters of wires BW1 and BW2 are larger than the diameter of wire BW3. Wires BW1 and BW2 are each made of, for example, aluminum or an aluminum alloy. Wire BW3 is made of, for example, gold.

[0033] The semiconductor chips CHP1 and CHP2, die pad DP, lead terminals LD1 and LD2, multiple lead terminals LD3, wires BW1, BW2, and multiple wires BW3 are sealed by a sealing resin MR. A portion of each of the die pad DP, lead terminals LD1, LD2, and multiple lead terminals LD3 is exposed to the outside of the sealing resin MR. The sealing resin MR is made of a thermosetting resin material, such as epoxy resin.

[0034] The detailed structure around detection points 13 and 14 will be described below using Figure 4. Note that the joint point BW1a shown in Figure 4 is the point where wire BW1 is joined to source electrode SE1.

[0035] As shown in Figure 4, the source electrode SE1 includes detection points 13 and 14 near the junction BW1a for detecting the value of the current flowing through the power transistor 11. Detection points 13 and 14 are positioned to sandwich the junction BW1a.

[0036] The source wiring SW1, drawn from detection points 13 and 14, is routed around the source electrode SE1 and electrically connected to the pad PD1. A portion of the source electrode SE1 is machined to secure an area for arranging the source wiring SW1. In other words, the parts of the source electrode SE1 to which the source wiring SW1 is connected are detection points 13 and 14. For convenience, separate symbols are used here, but the source electrode SE1, source wiring SW1, and pad PD1 are made of the same conductive film and are integrated.

[0037] The source electrode SE1 is electrically connected to the sense circuit 22 of the semiconductor chip CHP2 via detection point 13, detection point 14, source wiring SW1, pad PD1, wire BW3, and pad PD3.

[0038] The detailed structure around the sense transistor 12 is described below using Figure 5. Note that the junction BW2a shown in Figure 5 is where wire BW2 is connected to the source electrode SE1.

[0039] As shown in Figure 5, the semiconductor chip CHP1 has a source electrode SE2 formed on its upper surface TS1. The source electrode SE2 is physically separated from the source electrode SE1. The power transistor 11 is formed below the source electrode SE1. The sense transistor 12 is formed below the source electrode SE2. The source region of the sense transistor 12 is electrically connected to the source electrode SE2.

[0040] The source wiring SW2, which is drawn from the source electrode SE2, is electrically connected to the pad PD2. Note that the source electrode SE2, source wiring SW2, and pad PD2 are made of the same conductive film and are integrated together.

[0041] The source region of the sense transistor 12 is electrically connected to the sense circuit 22 of the semiconductor chip CHP2 via the source electrode SE2, source wiring SW2, pad PD2, wire BW3, and pad PD3.

[0042] Furthermore, as shown in Figures 4 and 5, the gate wiring GW drawn from the gate pad GP is routed around the source electrode SE1. Although not shown, the gate wiring GW is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. The gate pad GP and the gate wiring GW are made of the same conductive film and are integrated together.

[0043] The gate electrodes of the power transistor 11 and the sense transistor 12 are electrically connected to the gate potential control circuit 21 of the semiconductor chip CHP2 via gate wiring GW, gate pad GP, wire BW3, and pad PD3.

[0044] Furthermore, the semiconductor chip CHP2 is mounted on the source electrode SE1 so as to be located between junction BW1a and junction BW2a.

[0045] The locations of detection points 13 and 14 will be explained below using Figure 6.

[0046] As shown in Figure 6, distance D1 is the distance from detection point 13 to the center BW1b of joint point BW1a. Distance D2 is the distance from detection point 14 to the center BW1b of joint point BW1a. Distance D3 is the distance from detection point 13 to the center BW2b of joint point BW2a. Distance D4 is the distance from detection point 14 to the center BW2b of joint point BW2a. Distances D1 and D2 are shorter than distances D3 and D4, respectively, for example, 0.5 mm or more and 1.1 mm or less.

[0047] During the design phase, distances D1 and D2 are the same. However, due to assembly variations, distances D1 and D2 may differ.

[0048] <Cross-sectional structure of power transistors and sense transistors> The cross-sectional structures of the multiple MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) constituting the power transistor 11 and sense transistor 12 will be described below with reference to Figures 7 and 8.

[0049] As shown in Figure 7, multiple n-type MOSFETs 1Q are formed on the semiconductor substrate SUB. The power transistor 11 shown in Figure 1 is composed of multiple MOSFETs 1Q connected in parallel. The sense transistor 12 shown in Figure 1 is composed of at least one MOSFET 1Q. The sense transistor 12 may also be composed of multiple MOSFETs 1Q connected in parallel, in which case the number of MOSFETs 1Q constituting the sense transistor 12 is less than the number of MOSFETs 1Q constituting the power transistor 11.

[0050] The sense ratio is substantially determined by the ratio of the area on which the MOSFET1Q constituting the power transistor 11 is formed to the area on which the MOSFET1Q constituting the sense transistor 12 is formed.

[0051] The detailed structure of MOSFET1Q is described below with reference to Figure 8.

[0052] As shown in Figure 8, the semiconductor substrate SUB has an upper surface TS3 and a lower surface BS3 and is made of n-type silicon. The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The drain region ND is formed in the semiconductor substrate SUB with a predetermined thickness extending from the lower surface BS3 to the upper surface TS3 of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV.

[0053] The semiconductor substrate SUB may be a single-crystal n-type silicon substrate, or it may be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate by epitaxial growth while introducing phosphorus (P).

[0054] A drain electrode DE is formed beneath the lower surface BS3 of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed across the entire lower surface BS3 of the semiconductor substrate SUB. Drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0055] A trench TR is formed in the semiconductor substrate SUB, extending to a predetermined depth from the upper surface TS3 of the semiconductor substrate SUB. Inside the trench TR, a gate electrode GE is formed via a gate insulating film GI. The gate insulating film GI is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0056] A p-type body region PB is formed on the semiconductor substrate SUB, extending to a predetermined depth from the top surface TS3 of the semiconductor substrate SUB. The depth of the body region PB from the top surface TS3 of the semiconductor substrate SUB is shallower than the depth of the trench TR from the top surface TS3 of the semiconductor substrate SUB. An n-type source region NS is formed within the body region PB. The source region NS has a higher impurity concentration than the drift region NV. Of the body region PB, the portion adjacent to the gate electrode GE via the gate insulating film GI and located between the source region NS and the drift region NV constitutes the channel region of MOSFET1Q.

[0057] An interlayer insulating film IL is formed on the upper surface TS3 of the semiconductor substrate SUB, covering the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0058] Pores CH are formed in the interlayer insulating film IL. The pores CH penetrate the interlayer insulating film IL and the source region NS, and reach the body region PB. Although not shown here, pores CH reaching the gate electrode GE are also formed in the interlayer insulating film IL. A plug PG is embedded inside the pores CH. The plug PG consists of, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film consists of, for example, a laminate of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0059] A source electrode SE1 is formed on the interlayer insulating film IL. The source electrode SE1 is electrically connected to the source region NS and the body region PB via a plug PG, supplying a source potential to these impurity regions. A source electrode SE2 is formed above the MOSFET 1Q that constitutes the sense transistor 12.

[0060] Although not shown here, the interlayer insulating film IL also has a gate pad GP, gate wiring GW, pad PD1, source wiring SW1, pad PD2, and source wiring SW2, as shown in Figures 4 and 5. The gate pad GP is electrically connected to the gate electrode GE via the gate wiring GW and plug PG, supplying the gate potential to the gate electrode GE.

[0061] Source electrode SE1, source electrode SE2, gate pad GP, gate wiring GW, pad PD1, source wiring SW1, pad PD2, and source wiring SW2 each consist of, for example, a second barrier metal film and a second conductive film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium-tungsten film. The second conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0062] <Regarding the arrangement of detection points 13 and 14> As described above, the detection points (detection points 13 and 14) are positioned to obtain a representative value (average value) of the potential of the power transistor 11. However, a voltage drop occurs as the distance from the junction BW1a increases, causing a slope in the surface potential distribution of the source electrode SE1. Therefore, if assembly variations occur, it becomes difficult to stably obtain the same potential from the detection points for each semiconductor device package. In other words, variations occur in the source voltage of the power transistor 11 input from the pad PD1, resulting in variations in the sense ratio. As a result, it becomes difficult to accurately measure the value of the current flowing through the power transistor 11.

[0063] For example, a large-area clip, such as the one shown in Patent Document 2, could be used as a bonding member to join the source electrode SE1 and the lead terminal LD1. Since the clip can be made wider than the wire BW1, it can be bonded to most of the source electrode SE1. As a result, it is easier to select a location as a detection location where there is almost no slope in the surface potential distribution. However, when a semiconductor chip CHP2 is mounted on the source electrode SE1, as in Embodiment 1, the area to which the bonding member can be bonded is limited. Therefore, in Embodiment 1, a wire BW1 with a width narrower than the clip is used.

[0064] On the other hand, market demands for semiconductor device packages equipped with power transistors 11 require a reduction in on-resistance. Therefore, the on-resistance of power transistors 11 is reduced by optimizing the channel region and drift region NV of MOSFET 1Q and making MOSFET 1Q less resistive.

[0065] However, by reducing the resistance of MOSFET1Q, the resistance component of the source electrode SE1 becomes relatively more influential as it moves away from the junction BW1a. As a result, even if the chip size is the same and the junction state of wire BW1 is the same, the slope of the surface potential distribution of source electrode SE1 becomes larger. Therefore, for example, if the position of the junction BW1a of wire BW1 shifts, the variation in the source voltage of the power transistor 11 input from pad PD1 also increases. In other words, by reducing the resistance of MOSFET1Q, the variation in the sense ratio is now more heavily influenced by assembly variations.

[0066] Figure 9 shows a semiconductor device of a study example that the inventors of the present invention have investigated. As can be seen by comparing Figure 9 with Figure 4, in the study example, only detection location 13 is provided, and detection location 14 is not provided.

[0067] Figure 10 shows the relationship between the magnitude of the misalignment of the junction point BW1a of wire BW1 and the rate of change of the sense ratio. As shown in Figure 10, in the example examined, the larger the misalignment of the junction point BW1a, the larger the rate of change of the sense ratio, making it difficult to accurately measure the value of the current flowing through the power transistor 11.

[0068] In contrast, in Embodiment 1, detection points 13 and 14 are provided so as to sandwich the joint point BW1a. As explained in Figure 6, distances D1 and D2 are the same during the design phase. However, if assembly variations occur, distances D1 and D2 will differ. For example, if the position of the joint point BW1a shifts in the Y direction (upward direction in Figure 6), distance D2 will increase, but distance D1 will decrease accordingly. Therefore, as shown in Figure 10, by averaging the voltages detected at the two points, detection point 13 and detection point 14, fluctuations in the rate of change of the sense ratio can be suppressed.

[0069] Thus, in Embodiment 1, even if assembly variations occur while the on-resistance of the power transistor 11 is reduced, a stable and nearly identical potential can be obtained from detection points 13 and 14 for each semiconductor device package. Therefore, it becomes easier to accurately measure the value of the current flowing through the power transistor 11, and the reliability of the semiconductor device package can be improved.

[0070] Furthermore, two detection points, such as detection point 13 and detection point 14, may be provided around the joint point BW2a, so as to sandwich the joint point BW2a. Also, the number of detection points is not limited to two, but may be three or more.

[0071] However, when providing detection points, lead wires are required to draw wires from the detection points, such as the source wiring SW1, but MOSFET1Q cannot be formed below these lead wires. In other words, increasing the number of detection points reduces the area available for forming MOSFET1Q. As a result, the on-resistance of the power transistor 11 increases. Therefore, it is preferable to provide only the necessary number of detection points.

[0072] In Embodiment 1, in order to accurately measure the value of the current flowing through the power transistor 11 and to suppress the increase in the on-resistance of the power transistor 11, two detection points (detection point 13 and detection point 14) are provided around the junction BW1a, while no detection points are provided around the junction BW2a.

[0073] <Manufacturing method for semiconductor devices> The following describes each manufacturing process included in the manufacturing method of a semiconductor device package, using Figures 11A, 11B, 12A, and 12B.

[0074] As shown in Figures 11A and 11B, first, semiconductor chip CHP1, semiconductor chip CHP2, and lead frame LF are prepared. The lead frame LF includes lead terminals LD1, LD2, LD3, and die pad DP.

[0075] Next, semiconductor chip CHP1 is mounted on die pad DP via conductive bonding material BD1 so that its lower surface BS1 faces die pad DP. Then, semiconductor chip CHP2 is mounted on source electrode SE1 via insulating bonding material BD2 so that its lower surface BS2 faces the upper surface TS1 of semiconductor chip CHP1.

[0076] Next, wire bonding is performed as shown in Figures 12A and 12B. Wire BW1 electrically connects the source electrode SE1 and the lead terminal LD1. Wire BW3 electrically connects the pad PD3, which is electrically connected to the gate potential control circuit 21, and the gate pad GP. Although not shown here, wire BW2 electrically connects the source electrode SE1 and the lead terminal LD2. Wire BW3 electrically connects the pad PD3, which is electrically connected to the gate potential control circuit 21, and the pad PD1. Wire BW3 electrically connects the pad PD3, which is electrically connected to the sense circuit 22, and the pad PD2. Multiple wires BW3 electrically connect multiple other pads PD3 and multiple lead terminals LD3.

[0077] Subsequently, the semiconductor device package shown in Figures 2, 3A, and 3B is manufactured by following the manufacturing process described below. First, semiconductor chips CHP1 and CHP2, die pad DP, lead terminal LD1, lead terminal LD2, multiple lead terminals LD3, wire BW1, wire BW2, and multiple wires BW3 are sealed with sealing resin MR. Note that a portion of each of the die pad DP, lead terminal LD1, lead terminal LD2, and multiple lead terminals LD3 is exposed to the outside of the sealing resin MR.

[0078] Next, the die pad DP, lead terminals LD1, LD2, and LD3 are cut out from the lead frame LF. Then, lead terminals LD1, LD2, and LD3 are bent. This completes the manufacturing of the semiconductor device package.

[0079] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention.

[0080] For example, in the above embodiment, a wire was described as being used as a conductive bonding member to connect to the lead terminal. However, if the width (area) of the part that connects to the source electrode SE1 or pad PD3 is small, a clip may be used as a conductive bonding member to connect to the lead terminal. [Explanation of Symbols]

[0081] 1Q MOSFET 11 Power Transistors 12 sense transistors 13, 14 Detection locations 21 Gate potential control circuit 22 Sense Circuit BD1 Conductive bonding material BD2 insulating bonding material BS1, BS2, BS3 bottom side BW1, BW2, BW3 Wire BW1a, BW2a joint Center of the joint between BW1b and BW2b CH hole CHP1, CHP2 semiconductor chips DE drain electrode DP Die Pad GE Terminal GI gate insulating film GP Gate Pad GW gate wiring IL interlayer film LD1, LD2, LD3 lead terminals LF Lead Frame MR sealing resin ND drain area NS source area NV drift region PB Body Area PD1, PD2, PD3 pads PKG Semiconductor Equipment PG Plug SE1, SE2 source electrodes SW1, SW2 Source Wiring SUB Semiconductor Substrate TR Trench TS1, TS2, TS3 top side

Claims

1. Die pad and, A first semiconductor chip mounted on the die pad, A first lead terminal positioned away from the die pad, Equipped with, The first semiconductor chip is Power transistors and A first source electrode electrically connected to the source region of the power transistor, It has, The first source electrode is electrically connected to the first lead terminal via a conductive first bonding member. The first source electrode includes a first detection point and a second detection point for detecting the value of the current flowing through the power transistor. A semiconductor device in which the first detection location and the second detection location are arranged to sandwich the first bonding location of the first bonding member which is bonded to the first source electrode.

2. In the semiconductor device described in claim 1, The second semiconductor chip, A second lead terminal positioned away from the die pad and the first lead terminal, Furthermore, The first source electrode is electrically connected to the second lead terminal via a conductive second bonding member. A semiconductor device, wherein, in a plan view, the second semiconductor chip is mounted on the first source electrode such that it is located between the second bonding location of the second bonding member, which is bonded to the first source electrode, and the first bonding location.

3. In the semiconductor device described in claim 2, A semiconductor device in which no detection points for detecting the value of the current flowing through the power transistor are provided around the second junction.

4. In the semiconductor device described in claim 2, A semiconductor device in which the distance from the first detection point to the center of the first bonding point, or the distance from the second detection point to the center of the first bonding point, is shorter than the distance from the first detection point to the center of the second bonding point, or the distance from the second detection point to the center of the second bonding point.

5. In the semiconductor device described in claim 2, A semiconductor device in which the distance from the first detection point to the center of the first bonding point, or the distance from the second detection point to the center of the first bonding point, is 0.5 mm or more and 1.1 mm or less.

6. In the semiconductor device described in claim 2, The first semiconductor chip is The first source wiring drawn out from the first detection location and the second detection location, A first pad electrically connected to the first source wiring, A semiconductor device further having the following.

7. In the semiconductor device described in claim 6, The first semiconductor chip includes a sense transistor and A second pad electrically connected to the source region of the sense transistor, It further possesses, The second semiconductor chip is A sense circuit for measuring the value of the current flowing through the power transistor based on the value of the current flowing through the sense transistor and a preset sense ratio, The third pad and the fourth pad are electrically connected to the sense circuit, respectively. It has, The first pad is electrically connected to the third pad via a conductive third bonding member. A semiconductor device wherein the second pad is electrically connected to the fourth pad via a conductive fourth bonding member.

8. In the semiconductor device described in claim 7, A semiconductor device in which the diameters of the first and second bonding members are each larger than the diameters of the third and fourth bonding members.

9. In the semiconductor device described in claim 7, Each of the first and second joining members is a wire made of aluminum or an aluminum alloy. A semiconductor device in which the third and fourth joining members are each made of gold wire.

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