Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can ensure clearance between wires. [Solution] According to one embodiment, the semiconductor device comprises a wiring board, a first semiconductor element, a second semiconductor element, a first wire, and a second wire. The wiring board is provided with electrodes comprising a first portion and a second portion having a step between it and the first portion, and being higher than the first portion from the underlying layer. The first semiconductor element is arranged on the wiring board. The second semiconductor element is arranged on the first semiconductor element. One end of the first wire is connected to a first connection point on the first portion, and the other end is connected to the first semiconductor element. One end of the second wire is connected to a second connection point on the second portion, and the other end is connected to the second semiconductor element.

Description

Technical Field

[0005] , , , ,

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same.

Background Art

[0002] With the miniaturization of semiconductor packages, it has become common to shorten the length of finger electrodes connected to semiconductor chips via wires. However, when the length of the finger electrodes is shortened, it becomes difficult to secure a clearance between a plurality of wires, and as a result, there is a concern that the wires may short-circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device and a method of manufacturing the same that can secure a clearance between wires.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a first wire, and a second wire. The wiring substrate is provided with an electrode having a step between a first portion and a second portion that is higher than the first portion in height from an underlying layer. The first semiconductor element is disposed on the wiring substrate. The second semiconductor element is disposed on the first semiconductor element. One end of the first wire is connected to a first connection point on the first portion, and the other end is connected to the first semiconductor element. One end of the second wire is connected to a second connection point on the second portion, and the other end is connected to the second semiconductor element.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view showing a finger electrode in a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment, following Figure 3. [Figure 5] Figure 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment, following Figure 4. [Figure 6] Figure 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment, following Figure 5. [Figure 7] Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment, following Figure 6. [Figure 8] Figure 8 is a plan view showing a semiconductor device according to a first modification of the first embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. [Figure 10] Figure 10 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment, which differs from that shown in Figure 9. [Figure 11] Figure 11 is a plan view showing a semiconductor device according to a second modification of the first embodiment. [Figure 12] Figure 12 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. [Figure 13] Figure 13 is a cross-sectional view showing a semiconductor device according to a fourth modification of the first embodiment. [Figure 14] Figure 14 is a cross-sectional view showing a semiconductor device according to a fifth modification of the first embodiment. [Figure 15] Figure 15 is a cross-sectional view showing a semiconductor device according to a sixth modification of the first embodiment. [Figure 16]Figure 16 is a cross-sectional view showing a semiconductor device according to a seventh modification of the first embodiment. [Figure 17] Figure 17 is a plan view showing a finger electrode in a semiconductor device according to a seventh modification of the first embodiment. [Figure 18] Figure 18 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. To facilitate understanding of the explanation, the same reference numerals are used for identical components in each drawing whenever possible, and redundant explanations are omitted.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first embodiment. Figure 2 is a plan view showing the finger electrode 211 in the semiconductor device 1 according to the first embodiment. In Figure 1, the Z direction along the thickness direction of the semiconductor device 1 is defined as the upward direction, and the direction opposite to the Z direction is defined as the downward direction.

[0009] The semiconductor device 1 comprises a wiring board 2, a first semiconductor element 31, and a second semiconductor element 32. The semiconductor device 1 further comprises a first wire 41, a second wire 42, a first conductive layer 51, a second conductive layer 52, a sealing layer 6, and a bump electrode 7. The semiconductor device 1 is, for example, a package for a NAND flash memory.

[0010] The wiring board 2 includes a plurality of wiring layers 21 and 22. The uppermost wiring layer 21 includes finger electrodes 211. That is, the wiring board 2 is provided with finger electrodes 211. The finger electrodes 211 are an example of electrodes. The finger electrodes 211 can also be referred to as bonding fingers, lead electrodes, or lead terminals. The wiring board 2 further includes an interlayer insulating film 23 disposed between the plurality of wiring layers 21 and 22, and a solder resist film 24 provided on the uppermost wiring layer 21. The interlayer insulating film 23 is an example of an underlying layer. The solder resist film 24 is an example of an insulating film. The solder resist film 24 protects the wiring layer 21 and reduces short-circuit failures. The interlayer insulating film 23 may be made of glass epoxy resin, ceramics, or the like. The wiring layers 21 and 22 contain, for example, copper. The upper and lower wiring layers 21 and 22 are electrically connected via vias (not shown) that penetrate the interlayer insulating film 23. Under the wiring board 2, bump electrodes 7 are electrically connected. Note that in FIG. 1, the wiring board 2 is shown in a simplified manner. That is, under the wiring layer 22, other interlayer insulating films and wiring layers may be provided.

[0011] The first semiconductor element 31 is disposed on the wiring board 2. The first semiconductor element 31 is joined, for example, on the solder resist film 24 via an adhesive layer (not shown). The adhesive layer may be a paste-like or film-like resin such as NCP (Non Conductive Paste) or DAF (Die Attach Film). The first semiconductor element 31 is, for example, a NAND-type flash memory.

[0012] The second semiconductor element 32 is disposed on the first semiconductor element 31. The second semiconductor element 32 is joined, for example, on the first semiconductor element 31 via an adhesive layer (not shown) such as NCP and DAF. Similar to the first semiconductor element 31, the second semiconductor element 32 is, for example, a NAND-type flash memory. As the second semiconductor element 32, a controller chip that controls the first semiconductor element 31 may be disposed instead of the NAND-type flash memory.

[0013] As described above, the finger electrode 211 is provided on the wiring board 2. More specifically, the finger electrode 211 forms part of the uppermost wiring layer 21. In the examples shown in FIGS. 1 and 2, the finger electrode 211 extends along the X direction. The finger electrode 211 is electrically connected to both the first semiconductor element 31 and the second semiconductor element 32 via the wires 41, 42. One finger electrode 211 has first connection point P1 and second connection point P2 as two dots for connecting both the first semiconductor element 31 and the second semiconductor element 32 via the wires 41, 42. That is, two semiconductor elements 31, 32 are multi-bonded via two wires 41, 42 respectively connected to two dots P1, P2 of one finger electrode 211.

[0014] As shown in FIGS. 1 and 2, the finger electrode 211 has an upper layer portion 211a and a lower layer portion 211b. The upper layer portion 211a is an example of the second portion. The lower layer portion 211b is an example of the first portion. The height of the lower layer portion 211b from the interlayer insulating film 23 which is the base layer is lower than that of the upper layer portion 211a. More specifically, the height of the upper surface of the lower layer portion 211b from the upper surface of the interlayer insulating film 23 is lower than that of the upper layer portion 211a. That is, the upper surface of the lower layer portion 211b has a smaller separation distance in the Z direction from the upper surface of the interlayer insulating film 23 than the upper surface of the upper layer portion 211a. The upper layer portion 211a has a step ST with the lower layer portion 211b. The height of the upper layer portion 211a from the interlayer insulating film 23 is higher than that of the lower layer portion 211b. More specifically, the height of the upper surface of the upper layer portion 211a from the upper surface of the interlayer insulating film 23 is higher than that of the lower layer portion 211b. That is, the upper surface of the upper layer portion 211a has a larger separation distance in the Z direction from the upper surface of the interlayer insulating film 23 than the upper surface of the lower layer portion 211b. More specifically, the upper surface of the upper layer portion 211a is located above the upper surface of the lower layer portion 211b. The upper layer portion 211a is partially provided on the lower layer portion 211b so as to have a step ST between the upper layer portion 211a and the lower layer portion 211b.

[0015] The first connection point P1 is located on the lower layer 211b. More specifically, in the example shown in Figures 1 and 2, the first conductive layer 51 is provided on the lower layer 211b in the portion where the upper layer 211a is not provided. The first conductive layer 51 may be made of the same material as the first wire 41. The first conductive layer 51 may contain gold. The first connection point P1 is located on the first conductive layer 51.

[0016] The second connection point P2 is located on the upper layer 211a. More specifically, in the example shown in Figures 1 and 2, a second conductive layer 52 is provided on the upper layer 211a. Similar to the first conductive layer 51, the second conductive layer 52 may contain gold. The second connection point P2 is located on the second conductive layer 52.

[0017] The upper layer 211a is directly provided on the lower layer 211b without any other layer (e.g., an insulating layer) in between. In other words, the first wire 41 connected to the first connection point P1 on the lower layer 211b and the second wire 42 connected to the second connection point P2 on the upper layer 211a have the same potential. Furthermore, the upper layer 211a is not a separate structure from the finger electrodes 211, such as a bump, but is part of the finger electrodes 211. Therefore, the upper layer 211a can be formed simultaneously with the finger electrodes 211 (i.e., the wiring layer 21) using the same material.

[0018] As described above, one end 41a of the first wire 41 is connected to the first connection point P1 on the lower layer 211b. More specifically, one end 41a of the first wire 41 is connected to the first connection point P1 on the first conductive layer 51. Note that the dimensional ratio of one end 41a of the first wire 41 to the finger electrode 211 in the X direction may differ from that shown in Figure 1. For example, as shown in Figure 2, the finger electrode 211 may be formed to be sufficiently larger than one end 41a of the first wire 41 in the X direction.

[0019] On the other hand, the other end 41b of the first wire 41 is connected to the first semiconductor element 31. For example, the other end 41b of the first wire 41 is connected to a pad (not shown) provided on the upper surface of the first semiconductor element 31. The pad is made of, for example, aluminum, gold, copper, or a composite material thereof. In the example shown in Figure 1, the first wire 41 connects the finger electrode 211 and the first semiconductor element 31 by reverse bonding, where the finger electrode 211 side is the first bonding and the pad side of the first semiconductor element 31 is the second bonding. The first bonding is performed, for example, by ball bonding. The second bonding is performed, for example, by wedge bonding. In the example shown in Figure 1, the portion of the first wire 41 on the one end 41a side has a smaller inclination with respect to the Z direction than the portion of the first wire 41 on the other end 41b side. The first wire 41 contains, for example, gold.

[0020] Furthermore, as described above, one end 42a of the second wire 42 is connected to the second connection point P2 on the upper layer 211a. More specifically, one end 42a of the second wire 42 is connected to the second connection point P2 on the second conductive layer 52. Since the second connection point P2 is located on the upper layer 211a, the second connection point P2 is at a higher position than the first connection point P1. Therefore, one end 42a of the second wire 42 is at a higher position than one end 41a of the first wire 41.

[0021] On the other hand, the other end 42b of the second wire 42 is connected to the second semiconductor element 32. For example, the other end 42b of the second wire 42 is connected to a pad (not shown) provided on the upper surface of the second semiconductor element 32. In the example shown in Figure 1, the second wire 42 connects the finger electrode 211 and the second semiconductor element 32 by reverse bonding, where the finger electrode 211 side is the first bonding and the pad side of the second semiconductor element 32 is the second bonding. In the example shown in Figure 1, the portion of the second wire 42 at one end 42a has a smaller inclination with respect to the Z direction than the portion of the second wire 42 at the other end 42b. The second wire 42 contains, for example, gold.

[0022] One end 42a of the second wire 42 is connected to the finger electrode 211 by the upper layer 211a at a higher position than one end 41a of the first wire 41. Therefore, when connecting one end 42a of the second wire 42 using a capillary, contact between the capillary and the first wire 41 can be suppressed.

[0023] The upper layer 211a is located at a position further away from the first semiconductor element 31 and the second semiconductor element 32 than the first connection point P1. In other words, the upper layer 211a is located at a position further away from the first semiconductor element 31 and the second semiconductor element 32 than the lower layer 211b in the portion where the upper layer 211a is not provided. In the example shown in Figures 1 and 2, the upper layer 211a is located on the -X end side of the finger electrode 211.

[0024] The other end 41b of the first wire 41 is connected to the first semiconductor element 31 at a position closer to the first connection point P1 than the other end 42b of the second wire 42. The length of the first wire 41 is shorter than the length of the second wire 42.

[0025] As shown in Figure 2, in a plan view, in the direction connecting the first connection point P1 and the second connection point P2 (i.e., the X direction), the width W1 of the upper layer 211a occupies half the width W2 of the lower layer 211b.

[0026] The first wire 41 and the second wire 42 are, for example, power lines. The first wire 41 and the second wire 42 may also be ground lines.

[0027] Although only one finger electrode 211 is shown in Figure 1, in reality, multiple finger electrodes 211 may be arranged in alignment along the Y direction. Accordingly, multiple first wires 41 and second wires 42 corresponding to the finger electrodes 211 may also be arranged in alignment along the Y direction.

[0028] Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. Figure 3 is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0029] First, as shown in Figure 3, a wiring substrate 2 is formed, which includes a conductive layer 20 on which the uppermost wiring layer 21 is formed (step S1). The conductive layer 20 is formed to be thicker than the uppermost wiring layer 21.

[0030] Next, the conductive layer 20 is processed by etching to form the finger electrodes 211 together with the uppermost wiring layer 21 (step S2). The finger electrodes 211 are formed to have an upper portion 211a and a lower portion 211b. In processing the conductive layer 20, the shape of the upper portion 211a may be formed first, and then the shape of the lower portion 211b and the wiring pattern may be formed.

[0031] After forming the finger electrode 211 together with the uppermost wiring layer 21, a solder resist film 24 is formed on the finger electrode 211 and the uppermost wiring layer 21 (step S3). In the example shown in Figure 3, the solder resist film 24 is formed to a thickness that covers the upper end of the upper layer portion 211a of the finger electrode 211.

[0032] After forming the solder resist film 24, the solder resist film 24 is processed by etching so that the finger electrodes 211 are exposed (step S4).

[0033] After processing the solder resist film 24, conductive layers 51 and 52 are formed on the finger electrode 211 by gold plating (step S5). The first conductive layer 51 is formed on the lower layer 211b in the portion where the upper layer 211a is not provided. The second conductive layer 52 is formed on the upper layer 211a.

[0034] Figure 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment following Figure 3. After forming the conductive layers 51 and 52, as shown in Figure 4, a first bonding is performed by connecting one end 41a of the first wire 41 to a first connection point P1 on the first conductive layer 51 using a capillary 100 (step S6). The first bonding of the first wire 41 is performed, for example, by ball bonding.

[0035] Figure 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment following Figure 4. After connecting one end 41a of the first wire 41, the capillary 100 is raised from the first connection point P1 and moved so that the first wire 41 of the desired shape (loop) is obtained. Next, as shown in Figure 5, a second bonding is performed to connect the other end 41b of the first wire 41 to a pad (not shown) of the first semiconductor element 31 (step S7). The second bonding of the first wire 41 is performed, for example, by wedge bonding. In this way, the first wire 41 connects the finger electrode 211 and the first semiconductor element 31 by reverse bonding, with the finger electrode 211 side being the first bonding and the pad side of the first semiconductor element 31 being the second bonding.

[0036] Figure 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment, following Figure 5. After connecting the first wire 41, as shown in Figure 6, a first bonding is performed using a capillary 100 to connect one end 42a of the second wire 42 to a second connection point P2 on the second conductive layer 52 (step S8). The first bonding of the second wire 42 is performed, for example, by ball bonding. At this time, the second connection point P2 is located higher than one end 41a of the first wire 41 due to the upper layer 211a. Therefore, contact between the capillary 100 and the first wire 41 can be suppressed. Because contact between the capillary 100 and the first wire 41 can be suppressed, deformation of the first wire 41 can be suppressed. Because deformation of the first wire 41 can be suppressed, the yield can be improved. In addition, since there is no need to separately perform a step of forming a gold bump to raise the second connection point P2, one end 42a of the second wire 42 can be connected simply and quickly. Furthermore, by raising the second connection point P2, the length of the second wire 42 can be shortened.

[0037] Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment following Figure 6. After connecting one end 42a of the second wire 42, the capillary 100 is raised from the second connection point P2 and moved so that the second wire 42 of the desired shape is obtained. Next, as shown in Figure 7, a second bonding is performed to connect the other end 42b of the second wire 42 to a pad (not shown) of the second semiconductor element 32 (step S9). The second bonding of the second wire 42 is performed, for example, by wedge bonding. In this way, the second wire 42 connects the finger electrode 211 and the second semiconductor element 32 by reverse bonding, with the finger electrode 211 side being the first bonding and the pad side of the second semiconductor element 32 being the second bonding.

[0038] As described above, the semiconductor device 1 according to the first embodiment comprises a wiring board 2, a first semiconductor element 31, a second semiconductor element 32, a first wire 41, and a second wire 42. The wiring board 2 is provided with a finger electrode 211 which has a lower layer 211b and an upper layer 211a having a step ST between it and the lower layer 211b, and whose height from the interlayer insulating film 23 is higher than that of the lower layer 211b. The first semiconductor element 31 is arranged on the wiring board 2. The second semiconductor element 32 is arranged on the first semiconductor element 31. One end 41a of the first wire 41 is connected to a first connection point P1 on the lower layer 211b, and the other end 41b is connected to the first semiconductor element 31. One end 42a of the second wire 42 is connected to a second connection point P2 on the upper layer 211a, and the other end 42b is connected to the second semiconductor element 32.

[0039] This allows one end 42a of the second wire 42 to be connected at a higher position than one end 41a of the first wire 41, thereby ensuring clearance between the first wire 41 and the second wire 42. This clearance prevents short circuits between the first wire 41 and the second wire 42. Furthermore, the length of the second wire 42 can be shortened, reducing the cost associated with the second wire 42. Additionally, when connecting the first wire 41 and the second wire 42 by reverse bonding, contact of the capillary 100 with the first wire 41 can be suppressed. This prevents deformation of the first wire 41 and improves yield.

[0040] Furthermore, according to the first embodiment, the upper layer 211a is provided at a position further away from the first semiconductor element 31 and the second semiconductor element 32 than the first connection point P1.

[0041] This ensures adequate clearance between the first wire 41 and the second wire 42.

[0042] Furthermore, according to the first embodiment, the other end 41b of the first wire 41 is connected to the first semiconductor element 31 at a position closer to the first connection point P1 than the other end 42b of the second wire 42.

[0043] This allows for a more appropriate clearance between the first wire 41 and the second wire 42.

[0044] Furthermore, according to the first embodiment, in a plan view, in the X direction connecting the first connection point P1 and the second connection point P2, the width of the upper layer 211a occupies half the width of the lower layer 211b.

[0045] This ensures that the finger electrode 211 has sufficient width to connect the first wire 41 and the second wire 42, allowing for easy and proper connection of the first wire 41 and the second wire 42.

[0046] Furthermore, according to the first embodiment, the upper layer 211a is formed of the same material as the wiring of the wiring board 2.

[0047] This allows the upper layer 211a to be formed simultaneously with the wiring layer 21, thus enabling efficient formation of the upper layer 211a.

[0048] Furthermore, according to the first embodiment, after forming the finger electrodes 211 and before placing the first semiconductor element 31 on the wiring substrate 2, a solder resist film 24 is formed on the wiring substrate 2, and the solder resist film 24 is processed so that the finger electrodes 211 are exposed. The first semiconductor element 31 is then placed on the processed solder resist film 24.

[0049] This allows the finger electrodes 211 to be formed, and then the solder resist film 24 to be formed and processed to expose the finger electrodes 211. As a result, the finger electrodes 211 and wiring layer 21 can be formed more easily and appropriately compared to the case where the solder resist film 24 formed on the conductive layer 20 (see Figure 3) is processed to expose the conductive layer 20, and then the conductive layer 20 is processed to form the finger electrodes 211 and wiring layer 21.

[0050] Furthermore, according to the first embodiment, the finger electrode 211 is connected to the semiconductor elements 31 and 32 by reverse bonding using the first wire 41 and the second wire 42. That is, the electrical connection between the finger electrode 211 and the wires 41 and 42 includes a first step of connecting one end 41a of the first wire 41 to a first connection point P1 on the lower layer 211b, and a second step of connecting the other end 41b of the first wire 41 to the first semiconductor element 31 after the first step. The electrical connection between the finger electrode 211 and the wires 41 and 42 further includes a third step of connecting one end 42a of the second wire 42 to a second connection point P2 on the upper layer 211a, and a fourth step of connecting the other end 42b of the second wire 42 to the second semiconductor element 32 after the third step.

[0051] This ensures clearance between the first wire 41 and the second wire 42, and also suppresses contact between the capillary 100 and the first wire 41.

[0052] The following modifications can be applied to the first embodiment.

[0053] (First variation) Next, we will describe a first modified example of the first embodiment having a finger electrode with an upper layer 211a located close to the semiconductor elements 31 and 32, focusing on the differences from the embodiment described above. Figure 8 is a plan view showing a semiconductor device 1 according to the first modified example of the first embodiment. In Figure 8, the first wire 41 and the second wire 42 are not shown. Also, in Figure 8, the illustration of the first semiconductor element 31 and the second semiconductor element 32 is simplified. Figure 9 is a cross-sectional view showing a semiconductor device 1 according to the first modified example of the first embodiment. Figure 10 is a cross-sectional view showing a semiconductor device according to the first modified example of the first embodiment, which is different from Figure 9.

[0054] Up to this point, we have described an example of a finger electrode 211 in which the upper layer 211a is provided on the opposite side of the semiconductor elements 31 and 32 (i.e., at a position far from the semiconductor elements 31 and 32). In contrast, in the example shown in Figures 8 and 9, the semiconductor device 1 is provided with a second finger electrode 211A in addition to a plurality of finger electrodes 211 in which the upper layer 211a is provided on the opposite side of the semiconductor elements 31 and 32, and further, the upper layer 211a is provided on the semiconductor elements 31 and 32 side. That is, the upper layer 211a of the second finger electrode 211A is provided at a position close to the semiconductor elements 31 and 32 on the lower layer 211b.

[0055] The second finger electrode 211A is an example of the second electrode. The lower layer 211b of the second finger electrode 211A is an example of the third part. The upper layer 211a of the second finger electrode 211A is an example of the fourth part. In the example shown in Figure 8, the second finger electrode 211A is positioned in the center of a plurality of finger electrodes 211,211A aligned in the Y direction. The configuration of the finger electrodes 211 other than the second finger electrode 211A is the same as in Figure 1.

[0056] Unlike the upper layer 211a of the finger electrode 211, which in part aims to ensure clearance between wires 41 and 42 used for multi-bonding to the finger electrode 211, the upper layer 211a of the second finger electrode 211A does not aim to ensure clearance. In other words, the upper layer 211a of the second finger electrode 211A is primarily intended to shorten the length of the single wire connected to the second finger electrode 211A.

[0057] A first conductive layer 51 is provided on the upper layer 211a of the second finger electrode 211A. One end 43a of the third wire 43 is connected to a third connection point on the first conductive layer 51. The configuration of the third connection point is the same as that of the first connection point P1 on the first conductive layer 51 shown in Figure 2, except that it is located on the upper layer 211a. Therefore, for a diagram of the third connection point on the first conductive layer 51, please refer to the first connection point P1 on the first conductive layer 51 shown in Figure 2. In the example shown in Figure 9, the other end 43b of the third wire 43 is connected to a pad (not shown) of the first semiconductor element 31. In the example shown in Figure 9, the third wire 43 connects the second finger electrode 211A and the first semiconductor element 31 by reverse bonding, where the side of the second finger electrode 211A is the first bonding and the side of the pad of the first semiconductor element 31 is the second bonding.

[0058] No wires are connected to the lower layer 211b opposite to the upper layer 211a. In the example shown in Figure 8, the first wire 41 and the second wire 42 connected to the finger electrodes 211 other than the second finger electrode 211A are, for example, power lines or ground lines. On the other hand, the third wire 43 connected to the second finger electrode 211A is, for example, a signal line.

[0059] As shown in Figure 10, the other end 43b of the third wire 43 may be connected to the second semiconductor element 32 instead of being connected to the first semiconductor element 31. In the example shown in Figure 10, the third wire 43 connects the second finger electrode 211A and the second semiconductor element 32 by reverse bonding, where the side of the second finger electrode 211A is the first bonding and the pad side of the second semiconductor element 32 is the second bonding.

[0060] In the example shown in Figures 8 to 10, the wiring board 2 is further provided with a second finger electrode 211A which has a lower layer 211b and an upper layer 211a which has a step ST between it and the lower layer 211b and is higher in height from the interlayer insulating film 23 than the lower layer 211b. The semiconductor device 1 also further includes a third wire 43, one end 43a of which is connected to the upper layer 211a of the second finger electrode 211A and the other end 43b of which is connected to the first semiconductor element 31 or the second semiconductor element 32. The upper layer 211a of the second finger electrode 211A is provided in a position close to the first semiconductor element 31 and the second semiconductor element 32 of the second finger electrode 211A.

[0061] As shown in the examples in Figures 8 to 10, by having a second finger electrode 211A with an upper layer 211a on the semiconductor element 31, 32 side, the length of the third wire 43 connected between the upper layer 211a of the second finger electrode 211A and the first semiconductor element 31 or the second semiconductor element 32 can be shortened.

[0062] (Second variation) Figure 11 is a plan view showing a semiconductor device 1 according to a second modification of the first embodiment. Figures 8 to 10 described an example of a semiconductor device 1 equipped with only one second finger electrode 211A. In contrast, as shown in Figure 11, there may be multiple second finger electrodes 211A. In the example shown in Figure 11, along the Y direction, a finger electrode 211 with an upper layer 211a on the side opposite to the semiconductor elements 31 and 32, and a second finger electrode 211A with an upper layer 211a on the side of the semiconductor elements 31 and 32 are alternately arranged repeatedly. According to the example shown in Figure 11, the degree of freedom in the arrangement of the finger electrodes 211 and 211A can be improved.

[0063] (Third variation) Next, a third modification of the first embodiment, further comprising a third semiconductor element 33 and a fourth semiconductor element 34, will be described, focusing on the differences from the above-described embodiment. Figure 12 is a cross-sectional view showing the semiconductor device 1 according to the third modification of the first embodiment.

[0064] So far, we have described an example of a semiconductor device 1 in which a first semiconductor element 31 and a second semiconductor element 32 are mounted on a wiring board 2. In contrast, in the example shown in Figure 12, the semiconductor device 1 further includes a third semiconductor element 33 and a fourth semiconductor element 34 in addition to the first semiconductor element 31 and the second semiconductor element 32. The third semiconductor element 33 and the fourth semiconductor element 34 are, for example, NAND flash memory. The third semiconductor element 33 and the fourth semiconductor element 34 may also be controller chips.

[0065] The third semiconductor element 33 is positioned between the first semiconductor element 31 and the second semiconductor element 32. The third semiconductor element 33 is bonded between the first semiconductor element 31 and the second semiconductor element 32 via an adhesive layer (not shown), such as NCP and DAF. The fourth semiconductor element 34 is bonded onto the second semiconductor element 32 via an adhesive layer (not shown), such as NCP and DAF.

[0066] Furthermore, in the example shown in Figure 12, the wiring board 2 has a third finger electrode 211B provided on the electrode layer 21 opposite to the finger electrode 211, with the semiconductor elements 31-34 in between. The third finger electrode 211B is an example of a third electrode. The third finger electrode 211B is positioned on the X-direction side with respect to the semiconductor elements 31-34. The third finger electrode 211B comprises a lower layer 211b and an upper layer 211a that has a step between it and the lower layer 211b and is higher in height from the interlayer insulating film 23 than the lower layer 211b. The lower layer 211b of the third finger electrode 211B is an example of a fifth part. The upper layer 211a of the third finger electrode 211B is an example of a sixth part. The upper layer 211a is provided on the lower layer 211b on the side opposite to the semiconductor elements 31-34.

[0067] One end 44a of the fourth wire 44 is connected to the fourth connection point on the lower layer 211b in the portion where the upper layer 211a is not provided. In the example shown in Figure 12, a third conductive layer 53 is provided on the lower layer 211b. The third conductive layer 53 contains, for example, gold. The fourth connection point is located on the third conductive layer 53. The configuration of the fourth connection point on the third conductive layer 53 is the same as the configuration of the first connection point P1 on the first conductive layer 51 shown in Figure 2, but reversed left and right. Therefore, for a diagram of the fourth connection point, please refer to the first connection point P1 shown in Figure 2. The other end 44b of the fourth wire 44 is connected to a pad (not shown) provided on the upper surface of the third semiconductor element 33. In the example shown in Figure 12, the fourth wire 44 is connected by reverse bonding, with the third finger electrode 211B side being the first bonding and the pad side of the third semiconductor element 33 being the second bonding.

[0068] One end 45a of the fifth wire 45 is connected to the fifth connection point on the upper layer 211a of the third finger electrode 211B. In the example shown in Figure 12, a fourth conductive layer 54 is provided on the upper layer 211a of the third finger electrode 211B. The fourth conductive layer 54 contains, for example, gold. The fifth connection point is located on the fourth conductive layer 54. The configuration of the fifth connection point on the fourth conductive layer 54 is the same as the configuration of the second connection point P2 on the second conductive layer 52 shown in Figure 2, with the left and right sides determined. Therefore, for a diagram of the fifth connection point, please refer to the second connection point P2 shown in Figure 2. The other end 45b of the fifth wire 45 is connected to a pad (not shown) provided on the upper surface of the fourth semiconductor element 34. In the example shown in Figure 12, the fifth wire 45 is connected by reverse bonding, with the third finger electrode 211B side being the first bond and the pad side of the fourth semiconductor element 34 being the second bond. One end 45a of the fifth wire 45 is connected to the third finger electrode 211B at a higher position than one end 44a of the fourth wire 44 by the upper layer 211a. Therefore, contact between the capillary connecting one end 45a of the fifth wire 45 and the fourth wire 44 can be suppressed.

[0069] As shown in the example in Figure 12, even when the number of semiconductor elements 31-34 (i.e., the memory capacity) is increased, clearance between wires 43 and 44 can be secured by adding finger electrodes 211B with an upper layer 211a. Furthermore, contact of the capillary with the fourth wire 44 can be suppressed.

[0070] (Fourth variation) Next, we will describe a fourth modification of the first embodiment, which further increases the number of semiconductor elements mounted, focusing on the differences from the above-described embodiment. Figure 13 is a cross-sectional view showing the semiconductor device 1 according to the fourth modification of the first embodiment.

[0071] In the example shown in Figure 13, a fifth semiconductor element 35 is positioned between the first semiconductor element 31 and the third semiconductor element 33. The fifth semiconductor element 35 is bonded to the first semiconductor element 31 and the third semiconductor element 33 via an adhesive layer (not shown), such as NCP and DAF. A sixth semiconductor element 36 is positioned between the third semiconductor element 33 and the second semiconductor element 32. The sixth semiconductor element 36 is bonded to the third semiconductor element 33 and the second semiconductor element 32 via an adhesive layer (not shown), such as NCP and DAF. A seventh semiconductor element 37 is positioned between the second semiconductor element 32 and the fourth semiconductor element 34. The seventh semiconductor element 37 is bonded to the second semiconductor element 32 and the fourth semiconductor element 34 via an adhesive layer (not shown), such as NCP and DAF. An eighth semiconductor element 38 is positioned on the fourth semiconductor element 34. The eighth semiconductor element 38 is bonded to the fourth semiconductor element 34 via an adhesive layer, such as an NCP and a DAF (not shown).

[0072] Furthermore, in the example shown in Figure 13, the first semiconductor element 31 and the fifth semiconductor element 35 are electrically connected via the sixth wire 46. The fifth semiconductor element 35 may also be electrically connected to the finger electrode 211 via the first wire 41 and the sixth wire 46. Also, the third semiconductor element 33 and the sixth semiconductor element 36 are electrically connected via the seventh wire 47. The sixth semiconductor element 36 may also be electrically connected to the third finger electrode 211B via the fourth wire 44 and the seventh wire 47. Also, the second semiconductor element 32 and the seventh semiconductor element 37 are electrically connected via the eighth wire 48. The seventh semiconductor element 37 may also be electrically connected to the finger electrode 211 via the second wire 42 and the eighth wire 48. Also, the fourth semiconductor element 34 and the eighth semiconductor element 38 are electrically connected via the ninth wire 49. The eighth semiconductor element 38 may be electrically connected to the third finger electrode 211B via the fifth wire 45 and the ninth wire 49.

[0073] As shown in the example in Figure 13, even when the number of semiconductor elements 31-38 is further increased, clearance between wires can be secured.

[0074] (Fifth variation) Next, a fifth modification of the first embodiment, in which the number of steps of the finger electrode 211 is increased, will be described, focusing on the differences from the embodiment described above. Figure 14 is a cross-sectional view showing a semiconductor device 1 according to the fifth modification of the first embodiment. Up to this point, an example of a finger electrode 211 has been described in which an upper layer 211a has a step ST between it and a lower layer 211b. In contrast, as shown in Figure 14, the upper layer 211a itself may also be provided with a step ST2. That is, the upper layer 211a may comprise a first layer 211a1 and a second layer 211a2 that has a step ST2 between it and the first layer 211a1 and is higher in height from the interlayer insulating film 23 than the first layer 211a1. In other words, the finger electrode 211 may have two or more steps.

[0075] In the example shown in Figure 14, the second layer 211a2 of the upper layer 211a is located at the position furthest from the semiconductor elements 31, 32, and 310 on the finger electrode 211. One end 410a of the tenth wire 410 is connected to the second layer 211a2. In the example shown in Figure 14, a conductive layer 510 is provided on the second layer 211a2. The conductive layer 510 contains, for example, gold. One end 410a of the tenth wire 410 is connected to a connection point on the conductive layer 510. A semiconductor element 310 is placed on the second semiconductor element 32. The semiconductor element 310 is bonded to the second semiconductor element 32 via adhesive layers, such as NCP and DAF (not shown). The other end 410b of the tenth wire 410 is connected to a pad (not shown) provided on the upper surface of the semiconductor element 310. In the example shown in Figure 14, the tenth wire 410 connects the finger electrode 211 and the semiconductor element 310 by reverse bonding, where the finger electrode 211 side is used as the first bond and the pad side of the semiconductor element 310 is used as the second bond.

[0076] As shown in the example in Figure 14, by increasing the number of stages of the finger electrode 211, clearance can be secured between the wires 41, 42, and 410 even when three or more wires 41, 42, and 410 are connected to the finger electrode 211, and contact between the capillary 100 and the wires 41 and 42 can be suppressed.

[0077] (Sixth variation) Next, we will explain a sixth modification of the first embodiment, in which the number of semiconductor elements mounted is increased in the planar direction of the wiring substrate 2, focusing on the differences from the embodiments described above. Figure 15 is a cross-sectional view showing a semiconductor device 1 according to the sixth modification of the first embodiment. In Figure 12, an example was described in which the number of semiconductor elements mounted was increased in the planar direction (Z direction), i.e., the thickness direction, of the wiring substrate. In contrast, as shown in Figure 15, the number of semiconductor elements 31 and 32 mounted may be increased in the planar direction (X direction) of the wiring substrate 2. Roughly speaking, the semiconductor device 1 shown in Figure 15 corresponds to a configuration in which the semiconductor device 1 shown in Figure 1 and the semiconductor device obtained by inverting the semiconductor device 1 shown in Figure 1 around the Z axis are coupled along the dashed line L in Figure 15. However, the detailed configuration of the wiring layers 21 and 23 will be a configuration adapted to Figure 15. In the example shown in Figure 15, as in Figure 12, the clearance between wires 41 and 42 can be secured while increasing the number of semiconductor elements mounted.

[0078] (Seventh variation) Next, a modified example of the wiring layer 21 will be described, focusing on the differences from the embodiment described above. Figure 16 is a cross-sectional view showing the semiconductor device 1 according to the seventh modified example of the first embodiment. Figure 17 is a plan view showing the finger electrode 211 in the semiconductor device 1 according to the seventh modified example of the first embodiment.

[0079] Figures 1 and 2 illustrate an example where both ends of the finger electrode 211 in the extension direction (X direction) are connected to the uppermost wiring layer 21. In contrast, as shown in Figures 16 and 17, one end of the finger electrode 211 in the extension direction (the end in the X direction in Figures 16 and 17) may be separated from the wiring layer 21. The example shown in Figures 16 and 17 allows for greater flexibility in the arrangement of the finger electrode 211 and the wiring layer 21.

[0080] (Second Embodiment) Next, we will describe a second embodiment in which the finger electrode 211 and semiconductor elements 31 and 32 are connected by positive bonding, focusing on the differences from the first embodiment. Figure 15 is a cross-sectional view showing the semiconductor device 1 according to the second embodiment. Up to this point, we have described an example of a semiconductor device 1 in which the finger electrode 211 and semiconductor elements 31 and 32 are connected by reverse bonding using wires 41 and 42. In contrast, in the example shown in Figure 15, the finger electrode 211 and semiconductor elements 31 and 32 are connected by positive bonding using wires 41 and 42.

[0081] In other words, in the second embodiment, the electrical connection between the finger electrode 211 and the semiconductor elements 31 and 32 includes a first step of connecting the other end 41b of the first wire 41 to the first semiconductor element 31, and a second step of connecting one end 41a of the first wire 41 to a first connection point P1 (see Figure 2) on the lower layer 211b after the first step. The electrical connection between the finger electrode 211 and the semiconductor elements 31 and 32 further includes a third step of connecting the other end 42b of the second wire 42 to the second semiconductor element 32, and a fourth step of connecting one end 42a of the second wire 42 to a second connection point P2 on the upper layer 211a after the third step.

[0082] More specifically, in the second embodiment, a first bonding is performed using the capillary 100, in which the other end 41b of the first wire 41 is first connected to a pad (not shown) of the first semiconductor element 31. Next, a second bonding is performed, in which one end 41a of the first wire 41 is connected to the lower layer 211b. As a result, the finger electrode 211 and the first semiconductor element 31 are connected by positive bonding.

[0083] Next, a first bonding is performed by connecting the other end 42b of the second wire 42 to a pad (not shown) of the second semiconductor element 32. Then, a second bonding is performed by connecting one end 42a of the second wire 42 to the upper layer 211a. As a result, the finger electrode 211 and the second semiconductor element 32 are connected by positive bonding.

[0084] Furthermore, the variations in the arrangement of the upper layer 211a and the number of semiconductor elements described in the first embodiment may also be applied to the second embodiment.

[0085] According to the second embodiment, the finger electrode 211 has an upper layer 211a, which ensures clearance between the wires 41 and 42, similar to the first embodiment. In addition, it becomes less likely for the second wire 42 to short-circuit even if it sags.

[0086] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0087] 1 Semiconductor device, 2 Wiring board, 211 Finger electrode, 211a Upper layer, 221b Lower layer, 31 First semiconductor element, 32 Second semiconductor element, 41 First wire, 42 Second wire

Claims

1. A wiring board on which electrodes are provided, comprising a first part and a second part having a step between it and the first part, and being at a higher height from the underlying layer than the first part, A first semiconductor element arranged on the aforementioned wiring board, A second semiconductor element disposed on the first semiconductor element, A first wire having one end connected to a first connection point on the first portion and the other end connected to the first semiconductor element, A second wire having one end connected to a second connection point on the second portion and the other end connected to the second semiconductor element, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the second portion is provided at a position further away from the first semiconductor element and the second semiconductor element than the first connection point.

3. The semiconductor device according to claim 1, wherein the other end of the first wire is connected to the first semiconductor element at a position closer to the first connection point than the other end of the second wire.

4. The semiconductor device according to claim 1, wherein, in a plan view, in the direction connecting the first connection point and the second connection point, the width of the second portion occupies half the width of the first portion.

5. The semiconductor device according to claim 1, wherein the second portion is formed of the same material as the wiring of the wiring board.

6. The semiconductor device according to claim 1, wherein the first wire and the second wire have the same potential.

7. The semiconductor device according to claim 6, wherein the first wire and the second wire are power lines.

8. The semiconductor device according to claim 6, wherein the first wire and the second wire are ground lines.

9. The semiconductor device according to any one of claims 1 to 8, wherein the second part is directly provided on the first part.

10. The wiring board is further provided with a second electrode comprising a third portion and a fourth portion having a step between it and the third portion, and the fourth portion being higher in height than the third portion. The semiconductor device further comprises a third wire, one end of which is connected to a third connection point on the fourth portion and the other end of which is connected to the first semiconductor element or the second semiconductor element. The semiconductor device according to claim 1, wherein the fourth portion is provided at a position close to the first semiconductor element and the second semiconductor element among the second electrodes.

11. The semiconductor device according to claim 10, wherein the third wire is a signal line.

12. The wiring board is further provided with a third electrode comprising a fifth portion and a sixth portion having a step between it and the fifth portion, and the sixth portion being higher in height than the fifth portion. The aforementioned semiconductor device is A third semiconductor element disposed between the first semiconductor element and the second semiconductor element, A fourth semiconductor element disposed on the second semiconductor element, A fourth wire, one end of which is connected to the fourth connection point on the fifth portion and the other end of which is connected to the third semiconductor element, A fifth wire, one end of which is connected to the fifth connection point on the sixth portion and the other end of which is connected to the fourth semiconductor element, The semiconductor device according to claim 1, further comprising the above.

13. A wiring substrate is formed on which electrodes are provided, comprising a first part and a second part having a step between it and the first part, and being at a higher height from the underlying layer than the first part. A first semiconductor element is placed on the aforementioned wiring board, A second semiconductor element is placed on the first semiconductor element, One end of the first wire is connected to the first connection point on the first portion, and the other end of the first wire is connected to the first semiconductor element. One end of the second wire is connected to the second connection point on the second portion, and the other end of the second wire is connected to the second semiconductor element. A method for manufacturing a semiconductor device that includes the following features.

14. The process further includes forming an insulating film on the wiring substrate between the formation of the wiring substrate and the arrangement of the first semiconductor element, and processing the insulating film so that the electrodes are exposed. The method for manufacturing a semiconductor device according to claim 13, wherein the first semiconductor element is arranged on the processed insulating film.

15. The connection of one end of the first wire to the first connection point on the first portion is performed after the connection of the other end of the first wire to the first semiconductor element. The method for manufacturing a semiconductor device according to claim 13, wherein the connection of one end of the second wire to the second connection point on the second portion is performed after the connection of the other end of the second wire to the second semiconductor element.

16. The connection of one end of the first wire to the first connection point on the first portion is performed before the connection of the other end of the first wire to the first semiconductor element. The method for manufacturing a semiconductor device according to claim 13, wherein the connection of one end of the second wire to the second connection point on the second portion is performed before the connection of the other end of the second wire to the second semiconductor element.

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