Semiconductor equipment

Abstract

Miniaturize while reducing inductance. [Solution] The semiconductor module 2 included in the semiconductor device 1 is disposed between a conductive circuit pattern layer 22a and a lower wiring pattern layer 32 and has a lower bonding surface 41 that bonds to the conductive circuit pattern layer 22a and an upper bonding surface 42 that bonds to the lower wiring pattern layer 32, and has a conductive spacer 40 that electrically connects the conductive circuit pattern layer 22a and the lower wiring pattern layer 32, and a sealing member 50 that seals the semiconductor chip, the insulating circuit board 20, the wiring board 30 and the conductive spacer 40 by exposing the upper bonding surface 42 of the conductive spacer 40 and the lower surface of the insulating circuit board 20.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a semiconductor module and a cooling module in which the semiconductor modules are arranged. The semiconductor module includes an insulating circuit board having a plurality of conductive circuit pattern plates formed on an upper surface thereof and semiconductor chips arranged on the conductive circuit pattern plates. Such a semiconductor module includes terminals that are conductively connected to the conductive circuit pattern plates and extend vertically above the conductive circuit pattern plates (see, for example, Patent Documents 1 to 4).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a semiconductor device that reduces inductance while being miniaturized.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor chip having an upper electrode and a lower electrode; an insulating circuit substrate having a conductive circuit pattern layer on its upper surface, wherein the conductive circuit pattern layer is on which the lower electrode of the semiconductor chip is disposed; a wiring substrate having a wiring pattern layer on its lower surface, wherein the wiring pattern layer is disposed opposite the upper surface of the insulating circuit substrate, and the wiring pattern layer is electrically connected to the upper electrode of the semiconductor chip; a conductive spacer disposed between the conductive circuit pattern layer and the wiring pattern layer, having a lower bonding surface that bonds to the conductive circuit pattern layer and an upper bonding surface that bonds to the wiring pattern layer, and electrically connecting the conductive circuit pattern layer and the wiring pattern layer; and a sealing member that exposes the upper bonding surface of the conductive spacer and the lower surface of the insulating circuit substrate, thereby sealing the semiconductor chip, the insulating circuit substrate, the wiring substrate, and the conductive spacer.

[0006] Furthermore, the upper joining surface of the conductive spacer may form the bottom surface of an opening that is opened from the upper surface of the sealing member, and may be exposed from the opening. Furthermore, the conductive spacer may have an external connection terminal joined to the upper joint surface of the exposed conductive spacer.

[0007] Furthermore, the external connection terminal may be joined to the upper joining surface of the conductive spacer by laser welding. Furthermore, the wiring board has a through-port formed therein that penetrates the wiring board corresponding to the opening of the sealing member, the opening of the sealing member is configured such that the inner surface of the through-port is covered by the sealing member, and the upper bonding surface of the conductive spacer may be bonded to the opening edge of the through-port of the wiring pattern layer of the wiring board via solder.

[0008] Furthermore, the region of the upper bonding surface of the conductive spacer that faces the opening edge of the through-hole of the wiring board may be recessed below the upper bonding surface. Furthermore, the central region of the upper bonding surface of the conductive spacer may protrude upward.

[0009] Furthermore, the through-hole of the wiring board may be formed by cutting out the edge of the wiring board, and the opening of the sealing member may be formed by cutting out the edge of the sealing member to expose the through-hole.

[0010] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Effects of the Invention]

[0011] According to the disclosed technology, miniaturization is achieved while reducing inductance. [Brief explanation of the drawing]

[0012] [Figure 1] This is a perspective view of a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 3] This is a plan view of an insulating circuit board on which a semiconductor chip and a conductive spacer are arranged according to the first embodiment. [Figure 4] This is a plan view of the printed circuit board according to the first embodiment. [Figure 5] This is a cross-sectional view of the semiconductor device (main part) of the first embodiment. [Figure 6] This is a flowchart of the manufacturing method for a semiconductor module according to the first embodiment. [Figure 7] This is a cross-sectional view illustrating the first set step of the semiconductor module manufacturing method according to the first embodiment. [Figure 8] This is a first cross-sectional view illustrating the second set step of the method for manufacturing a semiconductor module according to the first embodiment. [Figure 9] This is a plan view illustrating the second set step of the semiconductor module manufacturing method according to the first embodiment. [Figure 10] This is another plan view illustrating the second set step of the method for manufacturing a semiconductor module according to the first embodiment. [Figure 11]It is a second cross-sectional view for explaining a second set of steps in the method for manufacturing a semiconductor module according to the first embodiment. [Figure 12] It is a cross-sectional view for explaining the sealing step in the method for manufacturing a semiconductor module according to the first embodiment. [Figure 13] It is a plan view of a semiconductor device according to a reference example. [Figure 14] It is a cross-sectional view of a semiconductor device according to a reference example. [Figure 15] It is a cross-sectional view of a semiconductor device (main part) according to a reference example, in which an external connection terminal is joined. [Figure 16] It is a cross-sectional view of a semiconductor device (main part) according to the first embodiment, in which an external connection terminal is joined. [Figure 17] It is a plan view of a printed circuit board according to the second embodiment. [Figure 18] It is a cross-sectional view of a semiconductor device (main part) according to the second embodiment. [Figure 19] It is a perspective view of a semiconductor device according to the third embodiment. [Figure 20] It is a cross-sectional view of a semiconductor device (main part) according to the third embodiment. [Figure 21] It is a cross-sectional view of a semiconductor device (main part) according to the fourth embodiment. [Figure 22] It is a plan view of an insulating circuit board on which a semiconductor chip and a conductive spacer are arranged according to the fourth embodiment. [Figure 23] It is a cross-sectional view of a semiconductor device (main part) according to the fifth embodiment. [Figure 24] It is a cross-sectional view for explaining a second set of steps in the method for manufacturing a semiconductor module according to the fifth embodiment.

Embodiments for Carrying Out the Invention

[0013] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the XY plane facing upwards (+Z direction) in the semiconductor device 1 shown in Figures 1 and 2. Similarly, "up" refers to the direction upwards (+Z direction) in the semiconductor device 1 shown in Figures 1 and 2. "Back surface" and "bottom surface" refer to the XY plane facing downwards (-Z direction) in the semiconductor device 1 shown in Figures 1 and 2. Similarly, "down" refers to the direction downwards (-Z direction) in the semiconductor device 1 shown in Figures 1 and 2. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," "down," and "side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions "up" and "down" are not limited to the direction of gravity. Furthermore, in the following explanation, "principal component" refers to a component containing 80 vol% or more. Also, "approximately identical" means that the difference is within ±10%. Also, "perpendicular" and "parallel" mean that the difference is within ±10°. "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions "up" and "down" are not limited to the direction of gravity. Furthermore, in the following explanation, "principal component" refers to a component containing 80 vol% or more. In addition, in the following explanation, the same components are denoted by the same symbols, and the explanation for those components may be omitted or simplified.

[0014] [First Embodiment] First, the semiconductor device of the first embodiment will be described using Figure 1. Figure 1 is a perspective view of the semiconductor device of the first embodiment. The semiconductor device 1 includes a semiconductor module 2 and a cooling module 4 on which the semiconductor module 2 is arranged via a bonding member 3. The semiconductor device 1 may also include other necessary components.

[0015] The semiconductor module 2 may be molded into a cubic shape by being entirely sealed by a sealing member 50. The sealing member 50 is covered by an upper surface 51, a lower surface 52 (see Figure 5), and side surfaces 53, 54, 55, and 56.

[0016] The top surface 51 has a rectangular shape when viewed from above. The longer sides of the top surface 51 are aligned in the ±X direction, and the shorter sides are aligned in the ±Y direction. Three openings 51a, 51b, and 51c are formed on the top surface 51.

[0017] The openings 51a, 51b, and 51c each have their long sides aligned along the ±Y direction and their short sides aligned along the ±X direction. The openings 51a and 51b are located on the +X side of the upper surface 51 and are provided along the short side. The opening 51c is located in the center of the -X side of the upper surface 51 and is provided along the short side. Details of the openings 51a, 51b, and 51c will be described later.

[0018] The lower surface 52 has the same shape and size as the upper surface 51, and is located on the opposite side from the upper surface 51. The entire lower surface of the metal plate 23 of the insulating circuit board 20, which will be sealed by a sealing member 50 as described later, is exposed on the lower surface 52, and may be in the same plane as the lower surface of the metal plate 23.

[0019] Sides 53, 54, 55, and 56 surround the respective edges of the top surface 51 and the bottom surface 52 in a clockwise direction. Therefore, in a plan view, sides 53 and 55 are the short sides of the semiconductor module 2 and are aligned in the ±Y direction, while sides 54 and 56 are the long sides of the semiconductor module 2 and are aligned in the ±X direction.

[0020] The connection points and corners on each surface of the sealing member 50 of the semiconductor module 2 may be rounded (R-chamfered) or chamfered (C-chamfered). The opening edges of the openings 51a, 51b, and 51c may also be rounded (R-chamfered) or chamfered (C-chamfered).

[0021] The cooling module 4 has an upper surface, which is the placement surface 4a on which the lower surface 52 of the semiconductor module 2 is placed. The placement surface 4a is wider than the lower surface 52, which is the back surface of the semiconductor module 2, and is substantially flat. The cooling module 4 shown in Figure 1 is only a schematic representation. Specific examples of the cooling module 4 include a heat dissipation base equipped with heat dissipation fins and a cooling device in which a coolant circulates inside. At least the portion of the cooling module 4 including the placement surface 4a on which the semiconductor module 2 is placed is made of a metal with excellent thermal conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. In this case, copper is included. In addition, to improve corrosion resistance, the surface of the placement surface 4a of the cooling module 4 may be plated. In this case, the plating material contains nickel. Such plating materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0022] The bonding member 3 is provided between the lower surface 52 of the semiconductor module 2 and the placement surface 4a of the cooling module 4. That is, the shape and size of the bonding member 3 in a plan view in the -Z direction may be approximately the same as, or slightly larger than, the shape and size of the lower surface 52 of the semiconductor module 2. In other words, the bonding member 3 is in contact with the lower surface 52 of the semiconductor module 2 and in contact with the placement surface 4a of the cooling module 4.

[0023] Such a joint member 3 is a thermally conductive adhesive and may be made of a material that has thermal conductivity, insulation, and adhesive properties. The material may be selected so as to obtain a predetermined thermal conductivity. Such a joint member 3 may, for example, have a resin as its main component and include a filler. The resin may be, for example, an epoxy resin. The filler may have ceramics or metal as its main component. Ceramics have high thermal conductivity and include, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. When the filler is ceramic, the joint member 3 containing such a filler can ensure thermal conductivity in addition to adhesiveness. Metals have both high thermal conductivity and electrical conductivity and include, for example, silver, copper, gold, nickel, chromium, aluminum, or alloys containing at least one of these. When the filler is metal, the joint member 3 containing such a filler ensures thermal conductivity in addition to adhesiveness and also has electrical conductivity. Because the joining member 3 is conductive, the metal plate 23 exposed from the lower surface 52 of the semiconductor module 2 and the cooling module 4 are at the same potential, preventing discharge between the semiconductor module 2 and the cooling module 4. Furthermore, the joining member 3 is not limited to a thermally conductive adhesive, but may also be solder or a sintered body. The solder may be one of the materials listed in solder 12 described later. The sintered material constituting the sintered body may be, for example, powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. The outer corners of the joining member 3 may be rounded. This prevents stress concentration at the corners. As a result, the occurrence of delamination of the joining member 3 from the placement surface 4a can be suppressed.

[0024] Furthermore, the details of the semiconductor module 2 will be explained using Figures 2 to 5, along with Figure 1. Figure 2 is a cross-sectional view of the semiconductor device of the first embodiment. Figure 3 is a plan view of the insulating circuit board on which the semiconductor chip and conductive spacer are arranged, according to the first embodiment. Figure 4 is a plan view of the printed circuit board of the first embodiment. Figure 5 is a cross-sectional view of the semiconductor device (main part) of the first embodiment.

[0025] Figure 2 is a cross-sectional view of the plane indicated by the dashed line in Figure 1, viewed in the direction of arrow I. Figure 3 is a plan view of only the insulating circuit board 20, which is included in the semiconductor device 1 and on which the semiconductor chips 10a, 10b and conductive spacers 40 are arranged. Figure 4 is a plan view of only the wiring board 30, which is included in the semiconductor device 1 and is positioned opposite the insulating circuit board 20. Figure 5 shows a magnified view of the conductive spacer 40 and its surroundings on the +X direction side of the cross-sectional view in Figure 2.

[0026] The semiconductor module 2 included in the semiconductor device 1 comprises semiconductor chips 10a and 10b, an insulating circuit board 20, a wiring board 30, and a conductive spacer 40. These components of the semiconductor module 2 are sealed by a sealing member 50.

[0027] The semiconductor chips 10a and 10b may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) composed mainly of silicon carbide. The power MOSFET may have a body diode that functions as a FWD (Free Wheeling Diode). Such semiconductor chips 10a and 10b may, for example, have an input electrode (drain electrode) which is a bottom electrode on the back surface, and two types of top electrodes, an output electrode (source electrode) and a control electrode (gate electrode), on the front surface. The control electrode may be provided at the center of one side of the front surface of the semiconductor chip 10a and 10b, or offset along the side from the center.

[0028] The semiconductor chips 10a and 10b may include a switching element, which is mainly composed of silicon. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). An RC-IGBT is a semiconductor element in which an IGBT and a FWD are configured in antiparallel within a single chip.

[0029] Such semiconductor chips 10a and 10b are equipped with an input electrode (collector electrode), which is a bottom electrode, on their back surface, and two types of top electrodes, an output electrode (emitter electrode) and a control electrode (gate electrode), on their front surface. The control electrode may be provided at the center of one side of the front surface of the semiconductor chips 10a and 10b, or offset from the center along the side, similar to the case of power MOSFETs.

[0030] Furthermore, for example, semiconductor chips 10a and 10b may be semiconductor chips mainly composed of silicon and each containing a pair of switching elements and diode elements. Specifically, semiconductor chips containing switching elements and diode elements may be placed in place of semiconductor chip 10a, and semiconductor chips containing switching elements and diode elements may be placed in place of semiconductor chip 10b. The switching elements are, for example, power MOSFETs and IGBTs. A semiconductor chip containing switching elements has, for example, an input electrode (drain electrode in the case of a power MOSFET, collector electrode in the case of an IGBT) as a bottom electrode on its back surface, and a gate electrode as a control electrode and an output electrode as a top electrode (source electrode in the case of a power MOSFET, emitter electrode in the case of an IGBT) on its front surface. In addition, for example, an SBD (Schottky Barrier Diode) or a PIN (P-Intrinsic-N) diode may be used as the FWD for the diode element. A semiconductor chip containing a diode element has an output electrode (cathode electrode) as the main electrode on its back side and an input electrode (anode electrode) as the main electrode on its front side.

[0031] Such semiconductor chips 10a and 10b may be joined to conductive circuit pattern layers 22a and 22b, respectively, by solder 12. The solder 12 is composed of solder components. The solder components are substances that make up the solder 12 and include lead-free solder mainly composed of a predetermined alloy. The predetermined alloy contains tin. Such alloys are, for example, at least one of the following alloys: a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, or a tin-antimony alloy. Furthermore, such solder components may contain additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, the solder components may include, for example, tin along with at least one of silver, zinc, copper, bismuth, indium, and antimony. Furthermore, the solder components may include, for example, at least one of nickel, germanium, cobalt, and silicon. Alternatively, a sintered body may be used instead of solder 12. When joining parts using a sintered body, the sintered material can be, for example, powders of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.

[0032] The insulated circuit board 20 includes an insulating layer 21, conductive circuit pattern layers 22a, 22b, and 22c, and a metal plate 23. The insulating layer 21 and the metal plate 23 are rectangular in shape when viewed from above. The corners of the insulating layer 21 and the metal plate 23 may be rounded (R-chamfered) or rounded (C-chamfered). The size of the metal plate 23 is smaller than the size of the insulating layer 21 when viewed from above, and it is formed inside the insulating layer 21.

[0033] The insulating layer 21 may be, for example, a ceramic substrate. The ceramic substrate is made of ceramics with good thermal conductivity. The ceramics are made of materials mainly composed of aluminum oxide, aluminum nitride, and silicon nitride. Furthermore, such an insulating layer 21 has a rectangular shape when viewed from above. Examples of insulating circuit boards 20 including an insulating layer 21 having such a configuration include DCB (Direct Copper Bonding) substrates and AMB (Active Metal Brazed) substrates.

[0034] The insulating layer 21 may be made of a resin. The resin may be a material with low thermal resistance and high insulating properties. Examples of such resins include thermosetting resins. The thermosetting resin may further contain fillers. The thermal resistance of the insulating layer 21 can be further reduced by controlling the material and content of the fillers.

[0035] Examples of such thermosetting resins include at least one of epoxy resins, cyanate resins, polyimide resins, benzoxazine resins, unsaturated polyester resins, phenolic resins, melamine resins, silicone resins, and maleimide resins. The filler is composed of at least one of oxides and nitrides. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, hexagonal boron nitride may also be used as the filler.

[0036] The thickness of such an insulating layer 21 depends on the rated voltage of the semiconductor module 2. That is, the higher the rated voltage of the semiconductor module 2, the greater the thickness of the insulating layer 21 needs to be. On the other hand, it is necessary to make the insulating layer 21 as thin as possible to reduce its thermal resistance.

[0037] The conductive circuit pattern layers 22a, 22b, and 22c are made of a metal with excellent thermal conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. In this case, copper is included. Furthermore, to improve corrosion resistance, the surfaces of the conductive circuit pattern layers 22a, 22b, and 22c may be plated. In this case, the plating material contains nickel. Such plating materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy. If the joining member 3 is a sintered body containing silver, the plating material may also contain silver.

[0038] The conductive circuit pattern layers 22a, 22b, and 22c are formed over the entire surface of the insulating layer 21, excluding the edges. Preferably, in a plan view, the edges of the conductive circuit pattern layers 22a, 22b, and 22c facing the outer periphery of the insulating layer 21 overlap with the outer periphery edge of the metal plate 23. This maintains a stress balance between the insulating circuit board 20 and the metal plate 23 on the back surface of the insulating layer 21. This further suppresses excessive warping, cracking, and other damage to the insulating layer 21. Note that the conductive circuit pattern layers 22a, 22b, and 22c are examples. The conductive circuit pattern layers may be formed on the insulating layer 21 in a number, shape, and size selected to realize a desired circuit.

[0039] The conductive circuit pattern layers 22a, 22b, and 22c are formed on the upper surface of the insulating layer 21, as shown in Figure 3. Specifically, the conductive circuit pattern layer 22a is provided on the +X side of the insulating layer 21, has an L-shape, and includes rectangular notches in the +X and -Y directions. The conductive circuit pattern layer 22b is provided adjacent to the conductive circuit pattern layer 22a on the -X side of the insulating layer 21, and has a rectangular shape in plan view. The conductive circuit pattern layer 22c is formed in the notched region of the conductive circuit pattern layer 22a on the insulating layer 21.

[0040] Furthermore, the conductive circuit pattern layer 22a is joined to the semiconductor chip 10a and conductive spacer 40 via solder 12. The conductive spacer 40 is provided at the +X direction end of the conductive circuit pattern layer 22a. The semiconductor chip 10a is provided in the center of the conductive circuit pattern layer 22a. The conductive circuit pattern layer 22b is joined to the semiconductor chip 10b and conductive spacer 40 via solder 12. The conductive spacer 40 is provided at the -X direction end of the conductive circuit pattern layer 22b. The semiconductor chip 10b is provided in the center of the conductive circuit pattern layer 22b. The conductive circuit pattern layer 22c is provided with conductive spacer 40 via solder 12. Details of the conductive spacer 40 will be described later.

[0041] The metal plate 23 is made of a metal with excellent thermal conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. In this case, copper is included. Furthermore, to improve corrosion resistance, the surface of the metal plate 23 may be plated. In this case, the plating material contains nickel. Such plating materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0042] The wiring board 30 is, for example, a printed circuit board. The wiring board 30 comprises an insulating plate 31, a lower wiring pattern layer 32 formed on the lower surface of the insulating plate 31, and an upper wiring pattern layer 33 formed on the upper surface of the insulating plate 31. Furthermore, the wiring board 30 has connecting members 34a, 34b and connecting wiring member 35 that extend downward. As will be described later, the connecting members 34a, 34b may be electrically connected to the output electrodes of the upper surface electrodes of the semiconductor chips 10a, 10b. Furthermore, although not shown in the figures, the wiring board 30 has connecting members that are electrically connected to the control electrodes of the upper surface electrodes of the semiconductor chips 10a, 10b. The wiring board 30 is arranged such that the lower wiring pattern layer 32 faces the upper surface of the insulating circuit board 20.

[0043] The insulating board 31 is flat and made of an insulating material. Such a material is obtained by immersing a resin in a substrate. This substrate is mainly composed of, for example, paper, glass cloth, or glass nonwoven fabric. Examples of resins include phenolic resin, epoxy resin, and polyimide resin. Specific examples of insulating boards include paper phenolic substrates, paper epoxy substrates, glass epoxy substrates, glass polyimide substrates, and glass composite substrates. Such insulating boards are also rectangular in plan view. The corners of the insulating board may be rounded (R-chamfered) or chamfered (C-chamfered).

[0044] The lower wiring pattern layer 32 and the upper wiring pattern layer 33 have predetermined pattern shapes so as to form a predetermined circuit for realizing a power conversion function. The lower wiring pattern layer 32 and the upper wiring pattern layer 33 are made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, nickel, silver, or alloys containing at least one of these. The surfaces of the lower wiring pattern layer 32 and the upper wiring pattern layer 33 may be plated to improve corrosion resistance. Examples of materials used in this plating process include nickel, nickel-phosphorus alloys, and nickel-boron alloys. Alternatively, solder resist may be applied instead of plating.

[0045] The connecting members 34a and 34b are electrically connected to the lower wiring pattern layer 32 and the upper wiring pattern layer 33 as appropriate, and are further joined to the upper electrodes of the semiconductor chips 10a and 10b via solder 13. In this case, the upper electrodes may be output electrodes. Although not shown in the figures, the wiring board 30 further includes connecting members that are joined to the control electrodes, which are the upper electrodes of the semiconductor chips 10a and 10b, via solder 13.

[0046] The connecting wiring member 35 may, for example, be rectangular in shape, with its longitudinal side aligned in the ±Y direction and its transverse side aligned in the ±X direction in a plan view, and may be in the form of a plate. Such a connecting wiring member 35 is electrically connected to the lower wiring pattern layer 32 and joined to the conductive circuit pattern layer 22b of the insulating circuit board 20 via solder 13.

[0047] The connecting members 34a, 34b and the connecting wiring member 35 are made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, nickel, silver, or alloys containing at least one of these. The surfaces of the connecting members 34a, 34b and the connecting wiring member 35 may be plated to improve corrosion resistance. Examples of materials used in this plating process include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0048] Furthermore, the wiring board 30 has through-holes 36a, 36b, and 36c formed at locations facing the conductive spacer 40 in a plan view. The through-holes 36a, 36b, and 36c penetrate the wiring board 30 in the ±Z direction. The plan view shape of the through-holes 36a, 36b, and 36c may be the same as the shape of the upper bonding surface 42 of the conductive spacer 40, which will be described later. However, the opening area of ​​the through-holes 36a, 36b, and 36c is smaller than the area of ​​the upper bonding surface 42 of the conductive spacer 40. For example, as shown in Figure 4, the upper bonding surface 42 of the conductive spacer 40 is exposed through the through-holes 36a, 36b, and 36c of the wiring board 30. The inner surfaces of the through-holes 36a, 36b, and 36c of the wiring board 30 may be plated.

[0049] The conductive spacer 40 is, for example, shaped like a block (cube), and includes a lower joint surface 41 on its lower surface and an upper joint surface 42 on its upper surface. The conductive spacer 40 is made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, nickel, silver, or an alloy containing at least one of these. The surface of the conductive spacer 40 may be plated to improve corrosion resistance. Examples of materials used in this plating process include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0050] Such conductive spacers 40 are placed between the insulating circuit board 20 and the wiring board 30. For example, as shown in Figure 2, the conductive spacer 40 is placed between the conductive circuit pattern layer 22b of the insulating circuit board 20 and the lower wiring pattern layer 32 of the wiring board 30. Alternatively, the conductive spacer 40 is placed between the conductive circuit pattern layer 22a of the insulating circuit board 20 and the lower wiring pattern layer 32 of the wiring board 30.

[0051] In this case, the lower bonding surface 41 of the conductive spacer 40 is bonded to the conductive circuit pattern layers 22a and 22b of the insulating circuit board 20 via solder 12. The upper bonding surface 42 of the conductive spacer 40 is bonded to the lower wiring pattern layer 32 of the wiring board 30 via solder 13. Figure 5 shows the case where the conductive spacer 40 is placed between the conductive circuit pattern layer 22a of the insulating circuit board 20 and the lower wiring pattern layer 32 of the wiring board 30.

[0052] The solder 13 may be arranged in a ring shape continuously around the outer edge region of the upper bonding surface 42 of the conductive spacer 40. As a result, the upper bonding surface 42 of the conductive spacer 40 is bonded to the opening edges of the through-holes 36a, 36b, and 36c of the lower wiring pattern layer 32 of the wiring board 30 via the solder 13. In this way, the conductive spacer 40 electrically connects the conductive circuit pattern layers 22a and 22b of the insulating circuit board 20 with the lower wiring pattern layer 32 of the wiring board 30.

[0053] In this manner, the conductive spacer 40 is positioned relative to the through-holes 36a, 36b, and 36c of the wiring board 30 from the side of the lower wiring pattern layer 32 of the wiring board 30. As a result, the upper bonding surface 42 of the conductive spacer 40 forms the bottom surface of the through-holes 36a, 36b, and 36c of the wiring board 30 and is exposed from the through-holes 36a, 36b, and 36c.

[0054] Furthermore, the inner surfaces of the through-holes 36a, 36b, and 36c of the wiring board 30 are sealed by the sealing member 50, forming openings 51a, 51b, and 51c of the sealing member 50. As a result, the upper bonding surface 42 of the conductive spacer 40 is exposed from the openings 51a, 51b, and 51c of the sealing member 50, respectively. The sealing member 50 seals not only the inner surfaces of the through-holes 36a, 36b, and 36c of the wiring board 30 but also the openings 51a, 51b, and 51c of the solder 13. In Figure 5, the case of opening 51a is shown, and the inner surface 51a1 of opening 51a covers the inner surface of the through-hole 36a. Although the openings 51b and 51c are not shown, similarly, the inner surfaces of openings 51b and 51c cover the inner surfaces of the through-holes 36b and 36c.

[0055] Next, the manufacturing method of the semiconductor module 2 will be explained using Figure 6. Figure 6 is a flowchart of the manufacturing method of the semiconductor module according to the first embodiment. First, a preparation step is carried out to prepare the components of the semiconductor module 2 (step P1). For example, the components prepared include semiconductor chips 10a and 10b, an insulating circuit board 20, a wiring board 30, a conductive spacer 40, a sealing material, and solder. Other components necessary for the manufacture of the semiconductor module 2 may also be prepared. Furthermore, manufacturing equipment and manufacturing jigs necessary for the manufacture of the semiconductor module 2 may also be prepared.

[0056] Next, a first setting step is performed in which semiconductor chips 10a, 10b and conductive spacers 40 are set on the insulating circuit board 20 (step P2). The first setting step will be explained with reference to Figure 7. Figure 7 is a cross-sectional view illustrating the first setting step of the semiconductor module manufacturing method of the first embodiment. Note that Figure 7 corresponds to the cross-sectional view of Figure 2.

[0057] First, semiconductor chips 10a and 10b are set on the conductive circuit pattern layers 22a and 22b of the insulating circuit board 20 via solder 12a. Also, conductive spacers 40 are set on the conductive circuit pattern layers 22a and 22b of the insulating circuit board 20 via solder 12a. At this time, solder 12a may be set at the positions where the connecting wiring members 35 of the wiring board 30 (described later) will be set. Furthermore, the solder 12a in this case may be, for example, solder paste.

[0058] Next, a second setting process is performed in which the wiring board 30 is set on the insulating circuit board 20 after process P2 (process P3). The second setting process will be explained using Figures 8 to 11. Figure 8 is a first cross-sectional view illustrating the second setting process of the semiconductor module manufacturing method of the first embodiment. Figure 9 is a plan view illustrating the second setting process of the semiconductor module manufacturing method of the first embodiment. Figure 10 is another plan view illustrating the second setting process of the semiconductor module manufacturing method of the first embodiment. Figure 11 is a second cross-sectional view illustrating the second setting process of the semiconductor module manufacturing method of the first embodiment. Note that Figures 8 and 11 correspond to the cross-sectional view of Figure 2, similar to Figure 7. Figure 9 is a plan view of Figure 8. Figure 10 is also a plan view similar to Figure 9.

[0059] After step P2, as shown in Figures 8 and 9, solder 13a is applied to the upper electrodes (output electrode and control electrode) of the semiconductor chips 10a and 10b placed on the insulating circuit board 20. Solder 13a is also applied along the outer edge region of the upper bonding surface 42 of the conductive spacer 40. Furthermore, solder 13a is applied to the placement area of ​​the connecting wiring member 35 of the conductive circuit pattern 22b on the insulating circuit board 20. Note that the solder 13a may be, for example, solder paste. If it is solder paste, the solder 13a is applied in a continuous ring shape along the outer edge region of the upper bonding surface 42 of the conductive spacer 40.

[0060] Furthermore, the upper joint surface 42 of the conductive spacer 40 may have a water-repellent portion 43 formed inside the annular application area of ​​solder 13a before the solder 13a is applied. Figure 10 shows the case where solder 13a is applied to the upper joint surface 42 of the conductive spacer 40 in which the water-repellent portion 43 is formed. The water-repellent portion 43 may be a material that repels solder, or it may be treated with a water-repellent process. The water-repellent material may be, for example, carbon or a resist material. Alternatively, the water-repellent portion 43 may be treated with a blast process as a water-repellent process. By forming a water-repellent portion 43 in an annular shape continuously along the inside of the application area of ​​solder 13a on the upper joint surface 42 of the conductive spacer 40, the wetting spread of solder 13a inward from the water-repellent portion 43 on the upper joint surface 42 can be suppressed.

[0061] A wiring board 30 is then set onto the insulated circuit board 20. Specifically, as shown in Figure 11, the connecting members 34a and 34b of the wiring board 30 are mounted to the upper electrodes of the semiconductor chips 10a and 10b via solder 12a. The lower wiring pattern layer 32 of the wiring board 30 is mounted to the upper bonding surface 42 of the conductive spacer 40 via solder 13a. Furthermore, the connecting wiring member 35 of the wiring board 30 is mounted to the conductive circuit pattern layer 22b of the insulated circuit board 20 via solder 13a.

[0062] Next, a soldering process is performed to join the components using solder (step P4). After step P3, solder reflow is performed to melt the solders 12a and 13a, and then solidify the molten solders 12a and 13a. As a result, the semiconductor chips 10a and 10b and the conductive spacer 40 are joined to the insulating circuit board 20 by the solder 12 formed from the solidified molten solder 12a. Furthermore, the connecting members 34a and 34b of the wiring board 30 are joined to the upper electrodes of the semiconductor chips 10a and 10b via the solder 13 formed from the solidified molten solder 13a. The lower wiring pattern layer 32 of the wiring board 30 is joined to the upper joining surface 42 of the conductive spacer 40 via the solder 13 formed from the solidified molten solder 13a. In addition, the connecting wiring member 35 of the wiring board 30 is joined to the conductive circuit pattern layer 22a of the insulating circuit board 20 via the solder 13.

[0063] Furthermore, as shown in Figure 10, if a water-repellent portion 43 is formed on the upper joint surface 42 of the conductive spacer 40, the molten solder 13a during the soldering process will not penetrate into the area inside the water-repellent portion 43 of the upper joint surface 42.

[0064] Next, a sealing process is performed in which the semiconductor module is sealed with a sealing member (step P5). The sealing process will be explained using Figure 12. Figure 12 is a cross-sectional view illustrating the sealing process of the semiconductor module manufacturing method of the first embodiment. Note that Figure 12 corresponds to the cross-sectional view of Figure 2.

[0065] First, the sealing mold 60 used in process P5 includes a lower mold 61 and an upper mold 62. The lower mold 61 is box-shaped and contains a storage area 61a inside. The upper mold 62 is flat and has a top surface 62a, and further, three rod-shaped opening molding parts (in Figure 12, two opening molding parts 62b are shown) are formed on the top surface 62a. In a plan view, the opening molding parts 62b are formed at locations facing the through-holes 36a, 36b, and 36c of the wiring board 30. The opening molding parts 62b are shaped to fit into the through-holes 36a, 36b, and 36c. Also, when the opening molding parts 62b fit into the through-holes 36a, 36b, and 36c, a gap is created between them and the inner surfaces of the through-holes 36a, 36b, and 36c. When such an upper mold 62 is attached to the top of the lower mold 61, the storage area 61a is closed.

[0066] In step P5, first, an insulating circuit board 20, on which semiconductor chips 10a, 10b and a wiring board 30 are bonded, is set in the storage area 61a of the lower mold 61. At this time, a certain amount of space is left between the insulating circuit board 20 on which the semiconductor chips 10a, 10b and the wiring board 30 are bonded and the inner surface of the lower mold 61 (in the ±X and ±Y directions).

[0067] Next, the top surface 62a of the upper mold 62 is placed on the lower mold 61. At this time, a certain gap (in the ±Z direction) is maintained between the top surface 62a of the upper mold 62 and the upper surface of the wiring board 30. Also, at this time, the opening molding portion 62b of the upper mold 62 is inserted through the through-holes 36a, 36b, and 36c of the wiring board 30, respectively. For example, as shown in Figure 12, the opening molding portion 62b of the upper mold 62 is inserted through the through-holes 36a and 36c of the wiring board 30 and contacts the upper joining surface 42 of the conductive spacer 40. At this time, there is a gap between the opening molding portion 62b of the upper mold 62 and the through-holes 36a and 36c of the wiring board 30. Also, there is a gap between the top surface 62a of the upper mold 62 and the wiring board 30.

[0068] In this way, the insulating circuit board 20, with semiconductor chips 10a, 10b and a wiring board 30 bonded to it, is set in the storage area 61a of the sealing mold 60. Next, sealing material is filled into the storage area 61a to seal the insulating circuit board 20 with the semiconductor chips 10a, 10b and the wiring board 30 bonded to it within the storage area 61a. Once the sealing material solidifies into the sealing member 50, the semiconductor module 2 is formed within the sealing mold 60. By removing the lower mold 61 and upper mold 62 of the sealing mold 60, the semiconductor module 2 included in the semiconductor device 1 shown in Figures 1 and 2 is obtained.

[0069] Here, the semiconductor device of the reference example will be explained using Figures 13 to 15. Figure 13 is a plan view of the semiconductor device of the reference example. Figure 14 is a cross-sectional view of the semiconductor device of the reference example. Figure 15 is a cross-sectional view of the semiconductor device (main part) of the reference example with external connection terminals attached.

[0070] Figure 13 is a plan view of the semiconductor device 100 in Figure 14, showing the case where the upper part of the sealing member 50 has been removed. Also in Figure 13, the position of the wiring board 130 and the positions of the implant pins connected to the semiconductor chips 10a and 10b are indicated by dashed lines. Figure 14 is a cross-sectional view taken along the dashed line II-II in Figure 13. Figure 15 is an enlarged view of the +X direction side of Figure 14, showing the case where the busbar 7 (external connection terminal) is connected to the main terminal 140. Furthermore, in the configuration included in the semiconductor module 200 included in the reference example semiconductor device 100, components that are the same as those included in the semiconductor module 2 of the first embodiment are denoted by the same reference numerals.

[0071] The semiconductor device 100 in the reference example includes a semiconductor module 200 and a cooling module 4 on which the semiconductor module 200 is arranged via a bonding member 3. The semiconductor module 200 may be entirely sealed by a sealing member 50 and molded into a cubic shape. However, the sealing member 50 in the reference example does not have openings 51a, 51b, and 51c formed therein.

[0072] The semiconductor module 200 included in the semiconductor device 100 includes semiconductor chips 10a and 10b, an insulating circuit board 20, a wiring board 130, and a main terminal 140. These components of the semiconductor module 200 are sealed by a sealing member 50.

[0073] The insulating circuit board 20 is provided with main terminals 140 in place of the conductive spacers 40 of the first embodiment. Each main terminal 140 extends outward (in the ±X direction) of the insulating circuit board 20. Accordingly, one main terminal 140 extends outward parallel to the upper surface 51 of the sealing member 50 from the side surface 53, and two main terminals 140 extend outward parallel to the upper surface 51 of the sealing member 50 from the side surface 55.

[0074] The wiring board 130 comprises an insulating plate 31, a lower wiring pattern layer 32 formed on the lower surface of the insulating plate 31, and an upper wiring pattern layer 33 formed on the upper surface of the insulating plate 31. Furthermore, the wiring board 130 has implant pins 134a, 134b and connecting wiring pins 135 that extend downward. As will be described later, the implant pins 134a, 134b may be electrically connected to the output electrodes of the upper surface electrodes of the semiconductor chips 10a, 10b. Furthermore, although not shown in the figures, the wiring board 130 has implant pins that are electrically connected to the control electrodes of the upper surface electrodes of the semiconductor chips 10a, 10b. The wiring board 130 is arranged so that the lower wiring pattern layer 32 faces the upper surface of the insulating circuit board 20. The implant pins 134a, 134b and connecting wiring pins 135 are all pin-shaped and may be connected to the same destinations and perform the same functions as the connecting members 34a, 34b and connecting wiring member 35 of the first embodiment.

[0075] The semiconductor module 200 included in such a semiconductor device 100 may be connected to an external device via an external connection terminal. For example, the semiconductor module 200 can be electrically connected to a capacitor, which is an external device, and function as a power conversion system. As illustrated in Figure 15, this connection is made by joining the busbar 7 included in the capacitor to the main terminal 140 of the semiconductor module 200 by laser welding.

[0076] For example, current flows from the semiconductor module 200 to the capacitor along the solid arrow in Figure 15. During this process, a large current exceeding several hundred amperes flows through the busbar 7. While the capacitor's guaranteed temperature depends on its performance, it is approximately 100°C, so it is necessary to reduce the temperature caused by the large current. This heat is dissipated downwards from the conductive circuit pattern layer 22c, as indicated by the dashed arrow in Figure 15. Increasing the length (area) of the conductive circuit pattern layer 22c is effective in increasing heat dissipation. Consequently, the main terminal 140 also becomes longer, and the wiring path also becomes longer.

[0077] However, extending the wiring path leads to an increase in the size of the semiconductor module 200, and furthermore, an increase in inductance. This increase in inductance can cause surge voltages. If these surge voltages exceed the breakdown voltage of the semiconductor chips 10a and 10b, the semiconductor chips 10a and 10b will be destroyed, causing a failure of the semiconductor module 200.

[0078] Next, the connection of the busbar 7 to the semiconductor module 2 included in the semiconductor device 1 will be explained using Figure 16. Figure 16 is a cross-sectional view of the semiconductor device (main part) to which the external connection terminals are connected, according to the first embodiment. Figure 16 shows the case in which the busbar 7 is provided in the opening 51a of the semiconductor module 2 shown in Figure 5. The busbar 7 may have a shape according to the state of the connection destination, as shown in Figures 15 and 16. Furthermore, this busbar 7 may also be included in a capacitor, for example.

[0079] In the first embodiment, as in the reference example, the semiconductor module 2 included in the semiconductor device 1 may be connected to an external device via an external connection terminal. In this case as well, the semiconductor module 2 can function as a power conversion system by being electrically connected to a capacitor, which is an external device, via a busbar 7. In the first embodiment, the tip of the busbar 7 is brought into contact with the upper bonding surface 42 of the conductive spacer 40 through the opening 51a of the semiconductor module 2 and joined, for example, by laser welding.

[0080] In the semiconductor module 2 of the first embodiment, the main terminal 140 of the reference example is not included, and current flows into the conductive spacer 40 via the wiring board 30 along the solid arrow in Figure 16. In this way, the semiconductor module 2 can be made smaller than the semiconductor module 200 of the reference example.

[0081] Furthermore, because the semiconductor module 2 is miniaturized, the current path from the wiring board 30 to the busbar 7 is shorter than that of the semiconductor module 200 in the reference example. As a result, the generation of inductance can be suppressed in the semiconductor module 2, and the occurrence of failures in the semiconductor module 2 is reduced. In addition, the conductive spacer 40 generates heat due to the current flow from the wiring board 30 to the conductive spacer 40. As shown by the dashed arrows in Figure 16, this heat is dissipated downwards from the conductive spacer 40 through the conductive circuit pattern layer 22c. As a result, the temperature rise of the busbar 7 can also be suppressed, and the occurrence of failures of the capacitor including the busbar 7 can be reduced.

[0082] The semiconductor module 2 included in the semiconductor device 1 described above comprises semiconductor chips 10a and 10b having upper and lower electrodes, an insulating circuit board 20 having conductive circuit pattern layers 22a, 22b, and 22c on its upper surface, on which the lower electrodes of the semiconductor chips 10a and 10b are placed, and a wiring board 30 having a lower wiring pattern layer 32 on its lower surface, on which the lower wiring pattern layer 32 is positioned opposite the upper surface of the insulating circuit board 20 and the lower wiring pattern layer 32 is electrically connected to the upper electrodes of the semiconductor chips 10a and 10b, and conductive circuit The semiconductor module 2 includes a conductive spacer 40 positioned between the path pattern layers 22a, 22b, 22c and the lower wiring pattern layer 32, having a lower bonding surface 41 that bonds to the conductive circuit pattern layers 22a, 22b and an upper bonding surface 42 that bonds to the lower wiring pattern layer 32, and conductively connecting the conductive circuit pattern layers 22a, 22b and the lower wiring pattern layer 32, and a sealing member 50 that seals the semiconductor chips 10a, 10b, the insulating circuit board 20, the wiring board 30 and the conductive spacer 40 by exposing the upper bonding surface 42 of the conductive spacer 40 and the lower surface of the insulating circuit board 20. In such a semiconductor module 2, current can be supplied to the outside in the ±Z direction using the conductive spacer 40 provided between the insulating circuit board 20 and the wiring board 30. As a result, the semiconductor module 2 can be miniaturized. Furthermore, as a result, the current path from the wiring board 30 to the busbar 7 can be shortened, the generation of inductance can be suppressed and the occurrence of semiconductor module 2 failures can be reduced. Furthermore, even if the conductive spacer 40 generates heat due to current flow from the wiring board 30 to the conductive spacer 40, the heat is dissipated downwards from the conductive spacer 40 via the conductive circuit pattern layer 22c. Therefore, the temperature rise of the busbar 7 can also be suppressed.

[0083] [Second Embodiment] The semiconductor module 2a included in the semiconductor device 1a of the second embodiment will be described with reference to Figures 17 and 18. Figure 17 is a plan view of the printed circuit board of the second embodiment. Figure 18 is a cross-sectional view of the semiconductor device (main part) of the second embodiment. Here, we will mainly describe the changes from the semiconductor module 2 of the first embodiment.

[0084] The semiconductor device 1a of the second embodiment also includes a semiconductor module 2a and a cooling module 4 on which the semiconductor module 2a is arranged via a bonding member 3. The semiconductor module 2a includes semiconductor chips 10a, 10b, an insulating circuit board 20, a wiring board 30a, a conductive spacer 40, and a sealing member 50 that seals these together.

[0085] However, in the second embodiment, the wiring board 30a is cut out from the ±X side ends of the wiring board 30 in the first embodiment, including through-portions 36a, 36b, and 36c. Therefore, the opening edges of the through-portions 36a, 36b, and 36c, which are the cutouts of the wiring board 30a in the second embodiment, are each U-shaped.

[0086] In this case, the conductive spacers 40 attached to the through-holes 36a, 36b, and 36c of the wiring board 30a from the lower side of the wiring board 30a may have solder 13 applied along the three sides of the U-shaped opening edges of the through-holes 36a, 36b, and 36c of the upper bonding surface 42.

[0087] Furthermore, the sealing member 50 includes semiconductor chips 10a, 10b, an insulating circuit board 20, a wiring board 30a, and a conductive spacer 40, and, similar to the first embodiment, openings 51a, 51b, and 51c corresponding to the conductive spacer 40 are formed.

[0088] The through-holes 36a, 36b, and 36c of the wiring board 30a in the second embodiment can be easily formed by simply cutting notches into the ±X ends of the wiring board 30a. Therefore, the manufacturing cost of the wiring board 30a can be reduced. In addition, the inner surfaces of the through-holes 36a, 36b, and 36c in the wiring board 30a of the second embodiment may also be plated.

[0089] [Third Embodiment] The semiconductor module 2b included in the semiconductor device 1b of the third embodiment will be described with reference to Figures 19 and 20. Figure 19 is a perspective view of the semiconductor device of the third embodiment. Figure 20 is a cross-sectional view of the semiconductor device (main part) of the third embodiment. Here, we will mainly describe the changes from the semiconductor module 2a of the second embodiment.

[0090] The semiconductor device 1b of the third embodiment also includes a semiconductor module 2b and a cooling module 4 on which the semiconductor module 2b is arranged via a bonding member 3. The semiconductor module 2b includes semiconductor chips 10a, 10b, an insulating circuit board 20, a wiring board 30a, a conductive spacer 40, and a sealing member 50b that seals these together.

[0091] However, in the third embodiment, the openings 51a, 51b, and 51c of the sealing member 50b are formed by cutting out the ends in the ±X direction, as shown in Figure 19. Only the upper bonding surface 42 of the conductive spacer 40 may be exposed from the bottom surface of the openings 51a, 51b, and 51c of the sealing member 50b.

[0092] A busbar 7 is attached to the semiconductor module 2b, which includes such a sealing member 50b, as shown in Figure 20. Specifically, the busbar 7 is attached to the upper bonding surface 42 of the conductive spacer 40 parallel to the upper surface 51 of the sealing member 50b with respect to the openings 51a, 51b, and 51c of the sealing member 50b (opening 51a is shown in Figure 20). Therefore, the attachment of the busbar 7 to the openings 51a, 51b, and 51c of the semiconductor module 2b is facilitated.

[0093] [Fourth Embodiment] The semiconductor module 2c included in the semiconductor device 1c of the fourth embodiment will be described with reference to Figures 21 and 22. Figure 21 is a cross-sectional view of the semiconductor device (main part) of the fourth embodiment. Figure 22 is a plan view of the insulating circuit board of the fourth embodiment on which the semiconductor chip and conductive spacer are arranged. Here, we will mainly describe the changes from the semiconductor module 2 of the first embodiment.

[0094] The semiconductor device 1c of the fourth embodiment also includes a semiconductor module 2c and a cooling module 4 on which the semiconductor module 2c is arranged via a bonding member 3. The semiconductor module 2c includes semiconductor chips 10a, 10b, an insulating circuit board 20, a wiring board 30, a conductive spacer 40c, and a sealing member 50 that seals these together.

[0095] In the fourth embodiment, the region of the upper bonding surface 42 of the conductive spacer 40c that faces the opening edges of the through-ports 36a, 36b, and 36c of the wiring board 30 is lower (recessed) than the upper bonding surface 42. That is, an annular, continuous step 42a is formed in the outer edge region of the upper bonding surface 42 of the conductive spacer 40c.

[0096] Therefore, the thickness of the solder 13 that joins the upper bonding surface 42 of the conductive spacer 40c to the wiring board 30 can be maintained to be thicker than in the reference example. When the semiconductor module 2c experiences repeated temperature changes such as heating and cooling, the thickness of the solder 13 reduces the strain generated in the solder 13. As a result, the reduction in the product life of the semiconductor module 2 is suppressed, and the reliability of the semiconductor module 2 is improved.

[0097] Furthermore, it is most preferable that the step 42a formed on the conductive spacer 40c be formed over the entire outer edge region of the upper joint surface 42, but it is preferable that it be formed on at least a part of the outer edge region. Moreover, it is even more preferable that it be formed on each of the opposing pairs of longitudinal sides of the upper joint surface 42.

[0098] [Fifth Embodiment] The semiconductor module 2c included in the semiconductor device 1c of the fifth embodiment will be described with reference to Figures 23 and 24. Figure 23 is a cross-sectional view of the semiconductor device (main part) of the fifth embodiment. Figure 24 is a cross-sectional view illustrating the second set step of the manufacturing method of the semiconductor module of the fifth embodiment. Here, we will mainly describe the changes from the semiconductor module 2 of the first embodiment.

[0099] The semiconductor device 1d of the fifth embodiment also includes a semiconductor module 2d and a cooling module 4 on which the semiconductor module 2d is arranged via a bonding member 3. The semiconductor module 2d includes semiconductor chips 10a, 10b, an insulating circuit board 20, a wiring board 30, a conductive spacer 40d, and a sealing member 50 that seals these together.

[0100] In the fifth embodiment, the entire portion of the upper bonding surface 42 of the conductive spacer 40d, excluding the region facing the opening edges of the through-ports 36a, 36b, and 36c of the wiring board 30, protrudes upward. That is, as shown in Figure 23, the central region of the upper bonding surface 42 of the conductive spacer 40d, excluding the outer edge region, protrudes toward the wiring board 30. In this case as well, a step 42a is formed that is continuous along the outer edge region of the upper bonding surface 42 of the conductive spacer 40d.

[0101] By using such a conductive spacer 40d, immediately after the second set step (step P3) of the semiconductor module 2d manufacturing method, solder 13a is provided between the step 42a of the conductive spacer 40d and the opening edges of the through-holes 36a, 36b, and 36c of the wiring board 30. In this case, the solder 13a is located below the central region of the conductive spacer 40d. Figure 24 shows the through-holes 36a and 36c of the wiring board 30.

[0102] Subsequently, in the soldering process (process P4), solder reflow is performed to melt solder 12a and solder 13a. At this time, the molten solder 13a is prevented from spreading by the central region that protrudes above the upper joint surface 42 of the conductive spacer 40d.

[0103] In the semiconductor module 2d manufactured through this process, no solder 13 remains on the upper bonding surface 42 of the conductive spacer 40d exposed through the openings 51a, 51b, and 51c. Therefore, the busbar 7 can be reliably bonded to the upper bonding surface 42 of the conductive spacer 40d through the openings 51a, 51b, and 51c.

[0104] Furthermore, the configurations disclosed in the above embodiments can be combined as appropriate, within the bounds of consistency. Thus, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of Symbols]

[0105] 1,1a,1b,1c,1d Semiconductor equipment 2,2a,2b,2c,2d Semiconductor Modules 3. Joining members 4 Cooling Modules 4a Placement surface 7 Bus Bar 10a, 10b semiconductor chips 12,13 solder 12a, 13a solder 20 Insulated circuit board 21 Insulating layer 22a, 22b, 22c Conductive circuit pattern layer 23 Metal plate 30,30a Wiring board 31 Insulating board 32 Lower wiring pattern layer (wiring pattern layer) 33 Upper wiring pattern layer 34a, 34b Connecting members 35 Connecting Wiring Components 36a,36b,36c Penetration 40, 40c, 40d conductive spacers 41 Lower joint surface 42 Upper joint surface 42a Step 43 Water-repellent part 50,50b Sealing member 51 Top side 51a,51b,51c opening 51a1 Inner surface of opening 52 Bottom side 53, 54, 55, 56 Side view 60 Sealing mold 61 Lower mold 61a Storage area 62 Upper mold 62a Top surface 62b Opening molding part

Claims

1. A semiconductor chip having an upper electrode and a lower electrode, An insulating circuit substrate having a conductive circuit pattern layer on its upper surface, wherein the conductive circuit pattern layer is on which the lower electrode of the semiconductor chip is arranged, A wiring substrate having a wiring pattern layer on its lower surface, wherein the wiring pattern layer is positioned opposite the upper surface of the insulating circuit substrate, and the wiring pattern layer is electrically connected to the upper electrode of the semiconductor chip, A conductive spacer is disposed between the conductive circuit pattern layer and the wiring pattern layer, and has a lower bonding surface that bonds to the conductive circuit pattern layer and an upper bonding surface that bonds to the wiring pattern layer, thereby electrically connecting the conductive circuit pattern layer and the wiring pattern layer. A sealing member that seals the semiconductor chip, the insulating circuit board, the wiring board, and the conductive spacer, by exposing the upper bonding surface of the conductive spacer and the lower surface of the insulating circuit board, Semiconductor device.

2. The upper joining surface of the conductive spacer forms the bottom surface of an opening that is opened from the upper surface of the sealing member, and is exposed from the opening. The semiconductor device according to claim 1.

3. The exposed conductive spacer further has an external connection terminal bonded to the upper bonding surface, The semiconductor device according to claim 1 or 2.

4. The external connection terminal is joined to the upper joining surface of the conductive spacer by laser welding. The semiconductor device according to claim 3.

5. The wiring board has a through portion formed therein that penetrates the wiring board, corresponding to the opening of the sealing member. The opening of the sealing member is formed by covering the inner surface of the through portion with the sealing member. The upper bonding surface of the conductive spacer is bonded to the opening edge of the through-hole of the wiring pattern layer of the wiring board via solder. The semiconductor device according to claim 2.

6. The region of the upper bonding surface of the conductive spacer that faces the opening edge of the through-hole of the wiring board is recessed below the upper bonding surface. The semiconductor device according to claim 5.

7. The central region of the upper bonding surface of the conductive spacer protrudes upward. The semiconductor device according to claim 5.

8. The through portion of the wiring board is formed by cutting out the edge of the wiring board. The opening of the sealing member is formed by cutting out the edge of the sealing member to expose the through portion. The semiconductor device according to claim 5.

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