Semiconductor integrated circuit and receiving device

Abstract

One embodiment aims to provide a semiconductor integrated circuit and a receiving device that can properly match impedances. [Solution] According to one embodiment, a semiconductor integrated circuit is provided having a first inductor and a second inductor. The first inductor is inserted into a first signal line. The second inductor is inserted into a loop spaced apart from the first signal line. The second inductor is magnetically coupled to the first inductor. Signal terminals are provided at both ends of the first signal line. No signal terminals are provided on the loop.

Description

Technical Field

[0001] This embodiment relates to a semiconductor integrated circuit and a receiving device.

Background Art

[0002] A receiving device having a semiconductor integrated circuit receives a signal with the semiconductor integrated circuit. Since the path through which the signal is transferred in the semiconductor integrated circuit has a characteristic impedance, it is desirable to properly match the impedance in the semiconductor integrated circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor integrated circuit and a receiving device capable of properly matching impedance.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor integrated circuit having a first inductive element and a second inductive element is provided. The first inductive element is inserted into a first signal line. The second inductive element is inserted into a loop arranged spaced apart from the first signal line. The second inductive element is magnetically coupled to the first inductive element. Signal terminals are arranged at both ends of the first signal line. No signal terminal is arranged on the loop.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing the configuration of a receiving device to which the semiconductor integrated circuit according to the embodiment is applied. [Figure 2]A circuit diagram showing the configuration of a semiconductor integrated circuit according to an embodiment. [Figure 3] A circuit diagram showing the configuration of the matching circuit in the embodiment. [Figure 4] Circuit diagrams showing the configuration of matching circuits and loads in embodiments and comparative configurations. [Figure 5] A figure showing the frequency characteristics of the input resistance in the embodiment and comparative configuration. [Figure 6] A figure showing the frequency characteristics of the input reactance in the embodiment and comparative form. [Figure 7] A figure showing the frequency characteristics of the S11 parameter in the embodiment and comparative form. [Figure 8] A plan view showing the configuration of the matching circuit in a first modified example of the embodiment. [Figure 9] A circuit diagram showing the configuration of a semiconductor integrated circuit according to a second modified example of the embodiment. [Figure 10] A circuit diagram showing the configuration of the matching circuit in a second modified example of the embodiment. [Figure 11] A plan view showing the configuration of the matching circuit in a third modified example of the embodiment. [Figure 12] A plan view and a cross-sectional view showing the configuration of the matching circuit in a fourth modified example of the embodiment. [Figure 13] A plan view and a cross-sectional view showing the configuration of the matching circuit in a fifth modified example of the embodiment. [Figure 14] A plan view and a cross-sectional view showing the configuration of the matching circuit in a sixth modified example of the embodiment. [Figure 15] A plan view and a cross-sectional view showing the configuration of the matching circuit in a seventh modified example of the embodiment. [Figure 16] A plan view and a cross-sectional view showing the configuration of the matching circuit in the eighth modified example of the embodiment. [Figure 17] A perspective view showing the configuration of the matching circuit in the eighth modified embodiment. [Figure 18] A plan view and a cross-sectional view showing the configuration of the matching circuit in the ninth modified embodiment. [Figure 19] A perspective view showing the configuration of the matching circuit in a ninth modified example of the embodiment.

Best Mode for Carrying Out the Invention

[0007] Hereinafter, a semiconductor integrated circuit according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by this embodiment.

[0008] (Embodiment) The semiconductor integrated circuit according to the embodiment has characteristic impedance, and a device for appropriately matching the impedance is provided.

[0009] The semiconductor integrated circuit 1 can be applied to a receiving device 3 as shown in FIG. 1. FIG. 1 is a block diagram showing the configuration of the receiving device 3 to which the semiconductor integrated circuit 1 is applied.

[0010] The receiving device 3 can be connected to a host HA. The receiving device 3 includes a semiconductor integrated circuit 1 and a processing circuit 2. The semiconductor integrated circuit 1 has a terminal group TG. The semiconductor integrated circuit 1 may be connected to a communication path CL via the terminal group TG. The semiconductor integrated circuit 1 can receive information from the host HA by being connected to the host HA via the communication path CL. The host HA is an example of a transmitting device.

[0011] The semiconductor integrated circuit 1 is connected to the processing circuit 2 via internal wiring. The semiconductor integrated circuit 1 can transfer information received from the host HA to the processing circuit 2. The processing circuit 2 can perform predetermined reception processing on the transferred information.

[0012] The semiconductor integrated circuit 1 can be configured as shown in FIG. 2. FIG. 2 is a circuit diagram showing the configuration of the semiconductor integrated circuit 1.

[0013] The semiconductor integrated circuit 1 may have a differential configuration. The signal received by the semiconductor integrated circuit 1 may be a differential signal.

[0014] The semiconductor integrated circuit 1 has a termination circuit 10 and an input buffer 20. If the semiconductor integrated circuit 1 has a differential configuration, the termination circuit 10 and the input buffer 20 each have a P-side configuration and an N-side configuration.

[0015] The termination circuit 10 has terminals Tp and Tn, and transfers the differential signal received at terminals Tp and Tn to the input buffer 20. Terminals Tp and Tn are included in the terminal group TG (see Figure 1).

[0016] The termination circuit 10 further includes ESD protection circuits Esp, ESn, variable resistor elements VRp, VRn, and matching circuit 30.

[0017] Terminal Tp receives the P-side signal of the differential signal from the host HA via the communication channel CL. Terminal Tn receives the N-side signal of the differential signal from the host HA via the communication channel CL.

[0018] Terminal Tp and node Np2 are connected by the P-side signal line SLp1. The ESD protection circuit ESp is connected to node Np1 between terminal Tp and node Np2 on the signal line SLp1. The ESD protection circuit ESp has diodes Dp1 and Dp2. Diode Dp1 has its cathode connected to the power line to which the power supply potential is applied, and its anode connected to node Np1. Diode Dp2 has its cathode connected to node Np1, and its anode connected to the ground line to which the ground potential is applied. The power supply potential is the potential of the power supply voltage for which the semiconductor integrated circuit 1 operates. The ground potential is the potential of the reference voltage for which the semiconductor integrated circuit 1 operates.

[0019] The ESD protection circuit Esp has a parasitic capacitance Cp1. The parasitic capacitance Cp1 is equivalently connected to node Np1 at its first end and to the ground line at its second end.

[0020] Terminal Tn and node Nn2 are connected by the N-side signal line SLn1. The ESD protection circuit ESn is connected to node Nn1 between terminal Tn and node Nn2 on the signal line SLn1. The ESD protection circuit ESn has diodes Dn1 and Dn2. Diode Dn1 has its cathode connected to the power line and its anode connected to node Nn1. Diode Dn2 has its cathode connected to node Nn1 and its anode connected to the ground line.

[0021] The ESD protection circuit ESn has a parasitic capacitance Cn1. The parasitic capacitance Cn1 is equivalently connected to node Nn1 at its first end and to the ground line at its second end.

[0022] Signal lines SLp2 and SLp3 are connected to node Np2, respectively. Signal line SLp2 connects node Np2 and node Np3. Signal line SLp3 electrically connects node Np2 and variable resistor element VRp via matching circuit 30.

[0023] The variable resistor element VRp has its first end connected to the signal line SLp3 and its second end connected to the ground line.

[0024] The variable resistor element VRp has a parasitic capacitance Cp2. The parasitic capacitance Cp2 is equivalently connected to the signal line SLp3 at its first end and to the ground line at its second end.

[0025] Signal lines SLn2 and SLn3 are connected to node Nn2, respectively. Signal line SLn2 connects node Nn2 and node Nn3. Signal line SLn3 electrically connects node Nn2 and the variable resistor element VRn via matching circuit 30.

[0026] The variable resistor element VRn has its first end connected to the signal line SLn3 and its second end connected to the ground line.

[0027] The variable resistor element VRn has a parasitic capacitance Cn2. The parasitic capacitance Cn2 is equivalently connected to the signal line SLn3 at its first end and to the ground line at its second end.

[0028] The matching circuit 30 is inserted between node Np2 and variable resistor element VRp in signal line SLp3, and between node Nn2 and variable resistor element VRn in signal line SLn3.

[0029] The matching circuit 30 has input nodes inp, inn and output nodes outp, outn.

[0030] The input node inp is located between node Np2 and output node outp on signal line SLp3. The output node outp is located between the input node inp and variable resistor element VRp on signal line SLp3.

[0031] The input node inn is located between node Nn2 and output node outn on signal line SLn3. The output node outn is located between the input node inn and variable resistor element VRn on signal line SLn3.

[0032] The input buffer 20 transfers the differential signal received from the termination circuit 10 to the processing circuit 2 (see Figure 1). The input buffer 20 has input transistors TRp and TRn.

[0033] The gate of the input transistor TRp is connected to node Np3 via signal line SLp4. The drain or source of the input transistor TRp is connected to processing circuit 2.

[0034] The input transistor TRp has a parasitic capacitance Cp3. The parasitic capacitance Cp3 is equivalently connected to the signal line SLp4 at its first end and to the ground line at its second end.

[0035] The gate of the input transistor TRn is connected to node Nn3 via signal line SLn4. The drain or source of the input transistor TRn is connected to processing circuit 2.

[0036] The input transistor TRn has a parasitic capacitance Cn3. The parasitic capacitance Cn3 is equivalently connected to the signal line SLn4 at its first end and to the ground line at its second end.

[0037] The semiconductor integrated circuit 1 has a characteristic impedance. The matching circuit 30 is configured to impedance match the semiconductor integrated circuit 1.

[0038] The matching circuit 30 can be configured as shown in Figure 3. Figure 3 is a circuit diagram showing the configuration of the matching circuit 30.

[0039] The matching circuit 30 includes inductive elements Lp1 and Ln1.

[0040] The inductor element Lp1 is inserted between the input node inp and the output node outp in the signal line SLp3. The inductor element Lp1 may also be a coil. The first end of the inductor element Lp1 is connected to node Np2 via the input node inp, and the second end is connected to the variable resistor element VRp via the output node outp (see Figure 2).

[0041] The inductor element Ln1 is inserted between the input node inn and the output node outn in the signal line SLn3. The inductor element Ln1 may also be a coil. The first end of the inductor element Ln1 is connected to node Nn2 via the input node inn, and the second end is connected to the variable resistor element VRn via the output node outn (see Figure 2).

[0042] The configuration in which the input transistor TRp is connected to node Np2 via signal line SLp1, signal line SLp2, node Np3, and signal line SLp4, and the inductor element Lp1 and variable resistor element VRp are connected to node Np2 via signal line SLp3, constitutes a bridged T-coil topology on the P side.

[0043] The resistance value of the variable resistor element VRp is adjusted to suppress signal reflection.

[0044] The inductance value of the inductor Lp1 can be experimentally determined in advance as a value appropriate for reducing the effects of noise caused by parasitic capacitances Cp1 and Cp3 over a relatively wide frequency band. The inductance value of the inductor Lp1 may be 140 pH.

[0045] The bridged T-coil topology on the P side allows for the concealment of the parasitic capacitance Cp1 of the ESD protection circuit ESp and the parasitic capacitance Cp3 of the input transistor TRp.

[0046] Similarly, a configuration in which the input transistor TRn is connected to node Nn2 via signal line SLn4, signal line SLn2, node Nn3, and signal line SLn4, and inductor element Ln1 and variable resistor element VRn are connected via signal line SLn3, constitutes an N-side bridged T-coil topology.

[0047] The resistance value of the variable resistor element VRn is adjusted to suppress signal reflection.

[0048] The inductance value of the inductor Ln1 can be experimentally determined in advance as a value appropriate for reducing the effects of noise caused by parasitic capacitances Cn1 and Cn3 over a relatively wide frequency band. The inductance value of the inductor Ln1 may also be 140 pH.

[0049] The N-side bridged T-coil topology allows for the concealment of the parasitic capacitance Cn1 of the ESD protection circuit ESn and the parasitic capacitance Cn3 of the input transistor TRn.

[0050] However, the bridged T-coil topology on the P side makes it difficult to conceal the parasitic capacitance Cp2 of the variable resistor element VRp, and the bridged T-coil topology on the N side makes it difficult to conceal the parasitic capacitance Cn2 of the variable resistor element VRn.

[0051] In contrast, the matching circuit 30 further includes an inductive element Lp2, an inductive element Ln2, a resistive element R1, and a capacitive element C1.

[0052] The inductors Lp2 and Ln2, the resistor R1, and the capacitor C1 are inserted into the loop LP. The loop LP is spaced apart from the signal lines SLp3 and SLn3. The signal lines SLp3 and SLn3 extend parallel to each other. The loop LP is positioned between the signal lines SLp3 and SLn3. The inductor Lp2 may be inserted in the portion of the loop LP along the signal line SLp3. The inductor Ln2 may be inserted in the portion of the loop LP along the signal line SLn3.

[0053] Inductor Lp2 is magnetically coupled to inductor Lp1, as shown by the solid arrow. The coupling coefficient between inductors Lp1 and Lp2 can be preset to any value suitable for concealing the parasitic capacitance Cp2. The coupling coefficient may be, for example, 0.6.

[0054] The inductance value of the inductor Lp2 can be experimentally determined in advance as a value appropriate for reducing the effects of noise due to parasitic capacitance Cp2 over a relatively wide frequency band. The inductance value of the inductor Lp2 may be 150 pH.

[0055] Inductor Ln2 is magnetically coupled to inductor Ln1, as shown by the solid arrow. The coupling coefficient between inductors Ln1 and Ln2 can be preset to any value suitable for concealing the parasitic capacitance Cn2. The coupling coefficient may be, for example, 0.6.

[0056] The inductance value of the inductor Ln2 can be experimentally determined in advance as a value appropriate for reducing the noise effect due to parasitic capacitance Cn2 over a relatively wide frequency band. The inductance value of the inductor Ln2 may be 150 pH.

[0057] Resistor R1 is inserted into loop LP in series with inductors Lp2 and Ln2. The resistance value of resistor R1 can be determined experimentally in advance depending on the values ​​of the parasitic capacitances Cp2 and Cn2 to be concealed. The resistance value of resistor R1 may be 40Ω.

[0058] Capacitor element C1 is inserted into loop LP in series with inductors Lp2 and Ln2. The capacitance value of capacitor element C1 can be determined experimentally in advance depending on the values ​​of the parasitic capacitances Cp2 and Cn2 to be masked. The capacitance value of capacitor element C1 may be 160 fF.

[0059] In the configuration shown in Figure 2, the load connected to the matching circuit 30 is equivalent to a configuration in which two resistors R2 and R3 and two capacitors C2 and C3 are bridged together, as shown in Figure 4(a). Figure 4 is a circuit diagram showing the configuration of the matching circuit and load in the embodiment and comparative form. Figure 4(a) is a circuit diagram showing the configuration of the matching circuit and load in the embodiment, and Figure 4(b) is a circuit diagram showing the configuration of the matching circuit and load in the comparative form. First, the matching circuit 30 and load in the embodiment will be described.

[0060] Resistors R2 and R3 are connected in series between the P-side output node outp and the N-side output node outn of the matching circuit 30.

[0061] Resistor R2 corresponds to the adjusted resistance value of the variable resistor element VRp and may have a resistance value of, for example, 39Ω.

[0062] Resistor R3 corresponds to the adjusted resistance value of the variable resistor element VRn and may have a resistance value of, for example, 39Ω.

[0063] Capacitors C2 and C3 are connected in parallel with the series connection of resistors R2 and R3, and are connected in series between the P-side output node outp and the N-side output node outn of the matching circuit 30.

[0064] Capacity C2 corresponds to the capacity value of the parasitic capacity Cp2 and may have a capacity value of, for example, 100 fF.

[0065] Capacity C3 corresponds to the capacity value of the parasitic capacity Cn2 and may have a capacity value of, for example, 100 fF.

[0066] The intermediate node Nm1 of resistors R2 and R3 and the intermediate node Nm2 of capacitors C2 and C3 are connected to each other.

[0067] Intermediate nodes Nm1 and Nm2 correspond to the ground line, respectively.

[0068] The matching circuit 30 shown in Figure 4(a) dissipates a portion of the energy of the signal transmitted by the inductive elements Lp1 and Ln1 from the inductive elements Lp1 and Ln1 to the magnetically coupled inductive elements Lp2 and Ln2, respectively, and consumes it with the resistive element R1 and the capacitive element C1.

[0069] As a result, the matching circuit 30 can maintain the input resistance at a desired resistance value Rt (e.g., 40Ω) over a wide frequency range, from low to high frequencies, as shown by the solid line in Figure 5. Figure 5 shows the frequency characteristics of the input resistance. In Figure 5, the vertical axis represents the resistance value and the horizontal axis represents the frequency.

[0070] The matching circuit 30 can maintain the input reactance near the desired reactance value Xt (e.g., 0Ω) over a wide frequency range, from low to high frequencies, as shown by the solid line in Figure 6. Figure 6 shows the frequency characteristics of the input reactance. In Figure 6, the vertical axis represents the reactance value and the horizontal axis represents the frequency.

[0071] The matching circuit 30 can maintain the input resistance near the desired resistance value Rt over a wide frequency range, and maintain the input reactance near the desired reactance value Xt over a wide frequency range, thereby keeping the signal reflection characteristics within an acceptable range over a wide frequency range FR, as shown by the solid line in Figure 7. For example, the S11 parameter value of the signal can be kept below the threshold Rth (e.g., -10 dB) over a wide frequency range FR.

[0072] Figure 7 shows the frequency characteristics of the S11 parameter. In Figure 7, the vertical axis represents the S11 parameter value, and the horizontal axis represents frequency. The S11 parameter represents the reflection of the signal and uses the input impedance rather than the characteristic impedance of the transmission line, but it can approximately represent the degree of impedance matching of the transmission line.

[0073] As described above, in this embodiment, in the matching circuit 30 of the semiconductor integrated circuit 1, an inductor Lp2 that is magnetically coupled to the inductor Lp1 of the signal line SLp3 and an inductor Ln2 that is magnetically coupled to the inductor Ln1 of the signal line SLn3 are provided on a loop LP spaced apart from the signal lines SLp3 and SLn3. A resistive element R1 and a capacitive element C1 are further provided on the loop LP. As a result, the matching circuit 30 can dissipate a portion of the signal energy transmitted on the signal lines Lp1 and Ln1 from the inductors Lp1 and Ln1 to the magnetically coupled inductors Lp2 and Ln2, respectively, and dissipate it in the resistive element R1 and the capacitive element C1. As a result, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7), the parasitic capacitance Cp2 of the variable resistor VRp can be concealed, and the parasitic capacitance Cn2 of the variable resistor VRn can be concealed. Therefore, the impedance in the semiconductor integrated circuit 1 can be properly matched.

[0074] Next, we will describe the matching circuit 30a and load in the comparison configuration. For example, as shown in Figure 4(b), the loop LP is omitted in the matching circuit 30a.

[0075] In this case, the matching circuit 30a transmits most of the energy of the signal transmitted by the inductive elements Lp1 and Ln1 to the load (a configuration in which two resistors R2 and R3 and two capacitors C2 and C3 are connected in a bridge).

[0076] As a result, compared to the characteristics of the matching circuit 30 shown by the solid line in Figure 5, the input resistance of the matching circuit 30a tends to decrease as the frequency increases from the low frequency region to the high frequency region, moving away from the desired resistance value Rt (e.g., 40Ω), as shown by the dashed line in Figure 5.

[0077] In contrast to the characteristics of the matching circuit 30 shown by the solid line in Figure 6, the matching circuit 30a tends to have an input reactance value that moves away from the desired reactance value Xt (e.g., 0Ω) as the frequency increases from the low frequency region to the high frequency region, as shown by the dashed line in Figure 6.

[0078] Compared to the characteristics of the matching circuit 30 shown by the solid line in Figure 7, the matching circuit 30a has a relatively narrow frequency range FRa in which the signal reflection characteristics can be kept within an acceptable range, as shown by the dashed line in Figure 7. This is because the input resistance value decreases away from the desired resistance value Rt as the frequency increases, and the input reactance value increases away from the desired reactance value Xt as the frequency increases. For example, the frequency range FRa in which the signal's S11 parameter value can be kept below the threshold Rth (e.g., -10 dB) is relatively narrow.

[0079] On the other hand, the matching circuit 30 can maintain the input resistance value near the desired resistance value Rt over a wide frequency range, and can maintain the input reactance value near the desired reactance value Xt over a wide frequency range, so that the reflection characteristics of the signal can be kept within an acceptable range over a relatively wide frequency range FR (>FRa), as shown by the solid line in Figure 7. For example, the S11 parameter value of the signal can be kept below the threshold Rth (e.g., -10dB) over a relatively wide frequency range FR.

[0080] As a first modification of the embodiment, the matching circuit 30i may be implemented as shown in Figure 8. Figure 8 is a plan view showing the configuration of the matching circuit 30i in the first modification of the embodiment. The matching circuit 30i shown in Figure 8 corresponds to the matching circuit 30 (see Figure 3) and is implemented in a differential configuration.

[0081] The inductors Lp1, Lp2, Ln1, and Ln2 (see Figure 3) may be implemented as planar coils PLp1, PLp2, PLn1, and PLn2, respectively, as shown in Figure 8.

[0082] Planar coils PLp1, PLp2, PLn1, and PLn2 may be arranged on the same plane. In the following, the direction perpendicular to the plane on which planar coils PLp1, PLp2, PLn1, and PLn2 are arranged will be defined as the Z direction, and the two mutually orthogonal directions within the plane perpendicular to the Z direction will be defined as the X and Y directions.

[0083] Planar coils PLp1 and PLp2 may have a concentric pattern in an XY plane view. Planar coil PLp1 is spaced outward from planar coil PLp2 in an XY plane view. The spacing in the X and Y directions can be determined experimentally in advance depending on the coupling coefficient to be achieved between planar coils PLp1 and PLp2.

[0084] Planar coil PLp1 extends in a ring shape from terminal TM1 on the -X and -Y sides to terminal TM2 on the +X and -Y sides in an XY plane view. Planar coil PLp2 extends in a ring shape from terminal TM11 on the -X and -Y sides to terminal TM12 on the +X and -Y sides, inside planar coil PLp1 in an XY plane view. Terminals TM1 and TM2 may be located outside terminals TM11 and TM12 in an XY plane view. In Figure 8, a pattern of approximately octagonal sides is exemplified for planar coils PLp1 and PLp2, but it may also be approximately 4 to 7 sides, approximately polygonal with 9 or more sides, or approximately circular.

[0085] The planar coil PLp1 has terminal TM1 electrically connected to the input node inp of the matching circuit 30i, and terminal TM2 electrically connected to the output node outp of the matching circuit 30i. The planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 3).

[0086] The planar coil PLp2 has terminal TM11 electrically connected to the first end of the capacitive element C1, and terminal TM12 electrically connected to the first end of the resistive element R1. The planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 3).

[0087] Planar coils PLn1 and PLn2 may have a line-symmetric pattern in the XY plane view with respect to planar coils PLp1 and PLp2, with respect to a symmetric axis in the X direction (a virtual line) in the Y direction, or with respect to a symmetric axis in the Y direction (a virtual line) in the X direction.

[0088] Planar coils PLn1 and PLn2 may have a concentric pattern in an XY plane view. Planar coil PLn1 is spaced outward from planar coil PLn2 in an XY plane view. The spacing in the X and Y directions can be determined experimentally in advance depending on the coupling coefficient to be achieved between planar coils PLn1 and PLn2.

[0089] Planar coil PLn1 extends in a ring shape from terminal TM3 on the -X side and +Y side to terminal TM4 on the +X side and +Y side in an XY plane view. Planar coil PLn2 extends in a ring shape from terminal TM13 on the -X side and +Y side to terminal TM14 on the +X side and +Y side inside planar coil PLn1 in an XY plane view. Terminals TM3 and TM4 may be located outside terminals TM13 and TM14 in an XY plane view. In Figure 8, the patterns of planar coils PLn1 and PLn2 are exemplified as approximately octagonal patterns, but they may also be approximately 4 to 7 sides, approximately polygonal shapes with 9 or more sides, or approximately circular shapes.

[0090] The planar coil PLn1 has terminal TM3 electrically connected to the input node inn of the matching circuit 30i, and terminal TM4 electrically connected to the output node outn of the matching circuit 30i. The planar coil PLn1 functions equivalently as an inductor Ln1 (see Figure 3).

[0091] The planar coil PLn2 has terminal TM13 electrically connected to the second terminal of the capacitive element C1, and terminal TM14 electrically connected to the second terminal of the resistive element R1. The planar coil PLn2 functions equivalently as an inductive element Ln2 (see Figure 3).

[0092] This matching circuit 30i also allows the signal reflection characteristics to be kept within acceptable limits over a wide frequency range FR (see Figure 7).

[0093] Alternatively, as a second modification of the embodiment, the semiconductor integrated circuit 1j may have a single-ended configuration, as shown in Figure 9. The signal received by the semiconductor integrated circuit 1j may also be a single-ended signal. Figure 9 is a circuit diagram showing the configuration of the semiconductor integrated circuit 1j according to the second modification of the embodiment.

[0094] When the semiconductor integrated circuit 1j has a single-ended configuration, the N-side configuration of the termination circuit 10j and input buffer 20j is omitted, respectively, compared to the termination circuit 10 and input buffer 20 (see Figure 2).

[0095] The termination circuit 10j has a matching circuit 30j instead of the matching circuit 30 (see Figure 2). As shown in Figure 10, the inductive element Ln2 (see Figure 3) is omitted in the matching circuit 30j. The inductive element Lp2, the resistive element R1, and the capacitive element C1 are inserted in series in the loop LP.

[0096] The matching circuit 30j shown in Figure 10 allows a portion of the signal energy transmitted by the inductor Lp1 to escape from the inductor Lp1 to the magnetically coupled inductor Lp2, where it is consumed by the resistive element R1 and the capacitive element C1.

[0097] As a result, the matching circuit 30j can maintain the input resistance value near the desired resistance value Rt over a wide frequency range (see solid line in Figure 5), and can maintain the input reactance value near the desired reactance value Xt over a wide frequency range (see solid line in Figure 6), similar to the embodiment.

[0098] Therefore, even with such a matching circuit 30j, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see solid line in Figure 7).

[0099] Alternatively, as a third modification of the embodiment, the matching circuit 30k may be implemented as shown in Figure 11. Figure 11 is a plan view showing the configuration of the matching circuit 30k in the third modification of the embodiment. The matching circuit 30k shown in Figure 11 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0100] Inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 11.

[0101] Planar coils PLp1 and PLp2 may be arranged on the same plane. The configurations of planar coils PLp1 and PLp2 are the same as in the first modified example of the embodiment. The connection relationships between planar coils PLp1 and PLp2 and the surrounding configurations of planar coils PLp1 and PLp2 are also the same as in the first modified example of the embodiment. However, it differs from the first modified example of the embodiment in that the second terminal of the capacitive element C1 and the second terminal of the resistive element R1 are electrically connected. Planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10). Planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0102] Even with such a matching circuit of 30k, the signal reflection characteristics can be kept within acceptable limits over a wide frequency range FR (see Figure 7).

[0103] Alternatively, as a fourth modification of the embodiment, the matching circuit 30n may be implemented as shown in Figure 12. Figure 12 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30n in the fourth modification of the embodiment. Figure 12(a) is an XY plan view showing the configuration of the matching circuit 30n, and Figure 12(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30n, showing a cross-section when Figure 12(a) is cut along line AA. The matching circuit 30n shown in Figure 12 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0104] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 12(a). In Figure 12(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30n are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration.

[0105] Planar coils PLp1 and PLp2 may be arranged on planes with different positions in the Z direction (Z height), as shown in Figure 12(b).

[0106] As shown in Figure 12(a), the planar coils PLp1 and PLp2 may have a concentric pattern in the XY plane view. Planar coil PLp1 is spaced outward from planar coil PLp2 in the XY plane view. The spacing in the X, Y, and Z directions can be experimentally determined in advance according to the coupling coefficient to be achieved between planar coils PLp1 and PLp2.

[0107] Planar coil PLp1 extends in a ring shape from terminal TM1 on the -X and -Y sides to terminal TM2 on the +X and -Y sides in an XY plane view. Planar coil PLp2 extends in a ring shape from terminal TM11 on the -X and -Y sides to terminal TM12 on the +X and -Y sides, inside planar coil PLp1 in an XY plane view. Terminals TM1 and TM2 may be located outside terminals TM11 and TM12 in an XY plane view. In Figure 12(a), a pattern on a roughly quadrilateral is shown as an example for the patterns of planar coils PLp1 and PLp2, but it may also be a roughly polygonal shape with 5 or more angles, or a roughly circular shape.

[0108] As shown in Figure 12(b), the planar coil PLp1 may be arranged as a conductive layer pattern on the +Z side of the substrate SB. The planar coil PLp2 may be arranged as a conductive layer pattern between the substrate SB and the planar coil PLp1 in the Z direction. The substrate SB may be formed from a semiconductor material such as silicon. The planar coils PLp1 and PLp2 may each be formed from a metal material such as copper. An interlayer insulating film IF may be placed between the substrate SB, the planar coils PLp1 and PLp2 to electrically insulate them from each other. The interlayer insulating film IF may be formed from an insulator such as silicon oxide.

[0109] Although not shown in the diagram, the planar coil PLp1 has terminal TM1 electrically connected to the input node inp of the matching circuit 30n, and terminal TM2 electrically connected to the output node outp of the matching circuit 30n. The planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10).

[0110] Although not shown in the diagram, the planar coil PLp2 has terminal TM11 electrically connected to the first end of the capacitive element C1, and terminal TM12 electrically connected to the first end of the resistive element R1. The planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0111] Even with such a matching circuit 30n, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7).

[0112] Alternatively, as a fifth modification of the embodiment, the matching circuit 30p may be implemented as shown in Figure 13. Figure 13 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30p in the fifth modification of the embodiment. Figure 13(a) is an XY plan view showing the configuration of the matching circuit 30p, and Figure 13(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30p, showing a cross-section when Figure 13(a) is cut along the BB line. The matching circuit 30p shown in Figure 13 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0113] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 13(a). In Figure 13(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30p are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration. The configurations of planar coils PLp1 and PLp2 in Figure 13(a) are the same as in the fourth modified example of the embodiment. Furthermore, the connection relationships between planar coils PLp1 and PLp2 and the surrounding configurations of planar coils PLp1 and PLp2 are the same as in the fourth modified example of the embodiment.

[0114] Planar coils PLp1 and PLp2 may be arranged on a plane with equal Z height, as shown in Figure 13(b).

[0115] As shown in Figure 13(b), the planar coil PLp1 and the planar coil PLp2 may each be arranged as conductive layer patterns on the +Z side of the substrate SB. The planar coil PLp2 may be positioned in the Z direction at the same Z height as the planar coil PLp1 on the substrate SB (Z height). The materials of the substrate SB, the planar coil PLp1, the planar coil PLp2, and the interlayer insulating film IF may each be the same as those of the fourth modification of the embodiment.

[0116] Even with such a matching circuit 30p, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7).

[0117] Alternatively, as a sixth modification of the embodiment, the matching circuit 30q may be implemented as shown in Figure 14. Figure 14 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30q in the sixth modification of the embodiment. Figure 14(a) is an XY plan view showing the configuration of the matching circuit 30q, and Figure 14(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30q, showing a cross-section when Figure 14(a) is cut along the CC line. The matching circuit 30q shown in Figure 14 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0118] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 14(a). In Figure 14(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30q are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration.

[0119] Planar coils PLp1 and PLp2 may be arranged on planes with different Z heights, as shown in Figure 14(b).

[0120] As shown in Figure 14(a), the planar coils PLp1 and PLp2 may have a concentric pattern in an XY planar view. When viewed from the Z direction, most of the planar coil PLp1 may overlap with the planar coil PLp2. As shown in Figure 14(b), the planar coil PLp1 is spaced apart from the planar coil PLp2 in the Z direction (+Z side). The Z-direction spacing of this separation can be experimentally determined in advance depending on the coupling coefficient to be achieved between the planar coils PLp1 and PLp2.

[0121] Planar coil PLp1 extends in a ring shape from terminal TM1 on the -X and -Y sides to terminal TM2 on the +X and -Y sides in an XY plane view. Planar coil PLp2 extends in a ring shape from terminal TM11 on the -X and -Y sides to terminal TM12 on the +X and -Y sides, following the same path as planar coil PLp1 in an XY plane view. Terminals TM1 and TM2 may be located outward in the X direction from terminals TM11 and TM12. In Figure 14(a), a roughly quadrilateral pattern is shown as an example for the patterns of planar coils PLp1 and PLp2, but it may also be a roughly polygonal shape with 5 or more angles, or a roughly circular shape.

[0122] As shown in Figure 14(b), the planar coil PLp1 may be arranged as a conductive layer pattern on the +Z side of the substrate SB. The planar coil PLp2 may be arranged as a conductive layer pattern between the substrate SB and the planar coil PLp1 in the Z direction. The materials of the substrate SB, planar coil PLp1, planar coil PLp2, and interlayer insulating film IF may be the same as those of the fourth modification of the embodiment.

[0123] Although not shown in the diagram, the planar coil PLp1 has terminal TM1 electrically connected to the input node inp of the matching circuit 30q, and terminal TM2 electrically connected to the output node outp of the matching circuit 30q. The planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10).

[0124] Although not shown in the diagram, the planar coil PLp2 has terminal TM11 electrically connected to the first end of the capacitive element C1, and terminal TM12 electrically connected to the first end of the resistive element R1. The planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0125] Even with such a matching circuit 30q, the signal reflection characteristics can be kept within acceptable limits over a wide frequency range FR (see Figure 7).

[0126] Alternatively, as a seventh modification of the embodiment, the matching circuit 30r may be implemented as shown in Figure 15. Figure 15 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30r in the seventh modification of the embodiment. Figure 15(a) is an XY plan view showing the configuration of the matching circuit 30r, and Figure 15(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30r, showing a cross-section when Figure 15(a) is cut along the DD line. The matching circuit 30r shown in Figure 15 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0127] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 15(a). In Figure 15(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30r are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration.

[0128] Planar coils PLp1 and PLp2 may be arranged on planes with different Z heights, as shown in Figure 15(b).

[0129] The planar coils PLp1 and PLp2 shown in Figure 15(a) may have a pattern in which their centers are shifted in the X direction relative to each other in an XY planar view. Figure 15 illustrates a configuration in which the center CP2 of planar coil PLp2 is shifted to the +X side relative to the center CP1 of planar coil PLp1. When viewed from the Z direction, a portion of planar coil PLp1 may overlap with planar coil PLp2. Figure 15 illustrates a configuration in which, in an XY planar view viewed from the Z direction, a portion of planar coil PLp2 is located inside planar coil PLp1, and another portion of planar coil PLp2 is located outside planar coil PLp1.

[0130] As shown in Figure 15(b), the planar coil PLp1 is separated from the planar coil PLp2 in the Z direction (+Z side). The amount of the center shift and the Z-direction distance between them can be experimentally determined in advance depending on the coupling coefficient to be achieved between the planar coils PLp1 and PLp2.

[0131] Planar coil PLp1 extends in a ring shape from terminal TM1 on the -X side and -Y side to terminal TM2 on the +X side and -Y side in an XY plane view. Planar coil PLp2 extends in a ring shape from terminal TM11 on the +X side and -Y side to terminal TM12 on the +X side and +Y side, following a trajectory that enters the inside of planar coil PLp1 from the +X side and exits again to the outside of planar coil PLp1 on the +X side. Terminals TM1 and TM2 are located on the -Y side of planar coil PLp1, and terminals TM11 and TM12 may be located on the +X side of planar coil PLp2. In Figure 15(a), a roughly quadrilateral pattern is exemplified as the pattern of planar coil PLp1 and planar coil PLp2, but it may also be a roughly polygonal shape with 5 or more angles, or a roughly circular shape.

[0132] As shown in Figure 15(b), the planar coil PLp1 may be arranged as a conductive layer pattern on the +Z side of the substrate SB. The planar coil PLp2 may be arranged as a conductive layer pattern between the substrate SB and the planar coil PLp1 in the Z direction. The materials of the substrate SB, planar coil PLp1, planar coil PLp2, and interlayer insulating film IF may be the same as those of the fourth modification of the embodiment.

[0133] Although not shown in the diagram, the planar coil PLp1 has terminal TM1 electrically connected to the input node inp of the matching circuit 30r, and terminal TM2 electrically connected to the output node outp of the matching circuit 30r. The planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10).

[0134] Although not shown in the diagram, the planar coil PLp2 has terminal TM11 electrically connected to the first end of the capacitive element C1, and terminal TM12 electrically connected to the first end of the resistive element R1. The planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0135] Even with such a matching circuit 30r, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7).

[0136] Alternatively, as an eighth modification of the embodiment, the matching circuit 30s may be implemented as shown in Figures 16 and 17. Figure 16 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30s in the eighth modification of the embodiment. Figure 17 is a perspective view showing the configuration of the matching circuit 30s in the eighth modification of the embodiment. Figure 16(a) is an XY plan view showing the configuration of the matching circuit 30s, and Figure 16(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30s, showing a cross-section when Figure 16(a) is cut along the EE line. The matching circuit 30s shown in Figure 16 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0137] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 16(a). In Figure 16(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30s are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration.

[0138] Planar coils PLp1 and PLp2 may be arranged across multiple planes with different Z heights, as shown in Figure 16(b).

[0139] As shown in Figure 16(a), the planar coils PLp1 and PLp2 may have a concentric pattern in the XY plane view. Planar coil PLp1 is spaced outward from planar coil PLp2 in the XY plane view. The spacing in the X and Y directions can be experimentally determined in advance according to the coupling coefficient to be achieved between planar coils PLp1 and PLp2. In Figure 16(a), a pattern on an approximately octagon is exemplified as the pattern of planar coils PLp1 and PLp2, but it may also be an approximately 4- to 7-sided shape, an approximately polygonal shape with 9 or more angles, or an approximately circular shape.

[0140] As shown in Figures 16(b) and 17, the planar coil PLp1 may be arranged as a multilayer wiring structure on the +Z side of the substrate SB. The planar coil PLp1 includes a plurality of conductive layers PLp1a, PLp1b with different Z heights and vias VA1 connecting them in the Z direction. The planar coil PLp2 may be arranged as a multilayer wiring structure on the +Z side of the substrate SB. The planar coil PLp2 includes a plurality of conductive layers PLp2a, PLp2b with different Z heights and vias VA11 connecting them in the Z direction. The substrate SB may be formed from a semiconductor material such as silicon. The conductive layers PLp1a, PLp1b and PLp2a, PLp2b may each be formed from a metal material such as copper. The vias VA1 and VA11 may each be formed from a metal material such as tungsten. An interlayer insulating film IF can be placed between the substrate SB, conductive layers PLp1a, PLp1b, and conductive layers PLp2a, PLp2b to electrically insulate them from each other. The interlayer insulating film IF can be formed from an insulator such as silicon oxide.

[0141] As shown in Figures 16(a) and 17, in the planar coil PLp1, the conductive layer PLp1a extends in a ring shape from the -X and -Y terminals TM1 to via VA1 at the +X end of terminal TM1. Via VA1 extends in the -Z direction from the end of conductive layer PLp1a to the starting end of conductive layer PLp1b. Conductive layer PLp1b extends in a ring shape from its starting end to the +X and -Y terminals TM2.

[0142] In the planar coil PLp2, the conductive layer PLp2a extends in a ring shape from the -X and -Y terminals TM11 to via VA11 at the +X end of terminal TM11. Via VA11 extends in the -Z direction from the end of conductive layer PLp2a to the beginning of conductive layer PLp2b. Conductive layer PLp2b extends in a ring shape from its beginning to the +X and -Y terminals TM12. Terminals TM1 and TM2 may be located outside terminals TM11 and TM12 in an XY planar view.

[0143] Although not shown in the diagram, the planar coil PLp1 has terminal TM1 electrically connected to the input node inp of the matching circuit 30s, and terminal TM2 electrically connected to the output node outp of the matching circuit 30s. The planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10).

[0144] Although not shown in the diagram, the planar coil PLp2 has terminal TM11 electrically connected to the first end of the capacitive element C1, and terminal TM12 electrically connected to the first end of the resistive element R1. The planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0145] Even with such a matching circuit 30s, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7).

[0146] Alternatively, as a ninth modification of the embodiment, the matching circuit 30t may be implemented as shown in Figures 18 and 19. Figure 18 is a plan view and a cross-sectional view showing the configuration of the matching circuit 30t in the ninth modification of the embodiment. Figure 19 is a perspective view showing the configuration of the matching circuit 30t in the eighth modification of the embodiment. Figure 18(a) is an XY plan view showing the configuration of the matching circuit 30t, and Figure 18(b) is an XZ cross-sectional view showing the configuration of the matching circuit 30t, showing a cross-section when Figure 18(a) is cut along the FF line. The matching circuit 30t shown in Figure 18 corresponds to the matching circuit 30j (see Figure 10) and is implemented in a single-ended configuration.

[0147] The inductive elements Lp1 and Lp2 (see Figure 10) may be implemented as planar coils PLp1 and PLp2, respectively, as shown in Figure 18(a). In Figure 18(a), for simplification, planar coils PLp1 and PLp2 in the matching circuit 30t are selectively shown, and the signal line SLp3, loop LP, resistor R1, and capacitive element C1 are omitted from the illustration.

[0148] Planar coils PLp1 and PLp2 may be arranged across multiple planes with different Z heights, as shown in Figure 18(b). The multiple planes on which planar coil PLp1 is arranged and the multiple planes on which planar coil PLp2 is arranged may have some of the same planes and some of the other planes that are different.

[0149] As shown in Figure 18(a), the planar coils PLp1 and PLp2 may have a concentric pattern in the XY plane view. Planar coil PLp1 is spaced outward from planar coil PLp2 and also spaced in the Z direction in the XY plane view. The spacing in the X, Y, and Z directions can be experimentally determined in advance according to the coupling coefficient to be achieved between planar coils PLp1 and PLp2. In Figure 18(a), a pattern on an approximately octagon is exemplified as the pattern of planar coils PLp1 and PLp2, but it may also be an approximately 4- to 7-sided shape, an approximately polygonal shape with 9 or more angles, or an approximately circular shape.

[0150] As shown in Figures 18(b) and 19, the planar coil PLp1 may be arranged as a multilayer wiring structure on the +Z side of the substrate SB. The planar coil PLp1 includes a plurality of conductive layers PLp1a, PLp1b with different Z heights and vias VA1 connecting them in the Z direction. The planar coil PLp2 may be arranged as a multilayer wiring structure on the +Z side of the substrate SB. The planar coil PLp2 includes a plurality of conductive layers PLp2a, PLp2b with different Z heights and vias VA11 connecting them in the Z direction. The conductive layer PLp1b of the planar coil PLp1 and the conductive layer PLp2a of the planar coil PLp2 may have the same Z height. The conductive layer PLp1a of the planar coil PLp1 and the conductive layer PLp2b of the planar coil PLp2 may have different Z heights. The conductive layer PLp1a may have a higher Z height than the conductive layers PLp1b and PLp2a, and the conductive layer PLp2b may have a lower Z height than the conductive layers PLp1b and PLp2a.

[0151] The materials for the substrate SB, the planar coil PLp1, the planar coil PLp2, and the interlayer insulating film IF may be the same as those for the eighth modification of the embodiment.

[0152] As shown in Figures 18(a) and 19, in the planar coil PLp1, the conductive layer PLp1a extends spirally from the terminals TM1 on the -X, -Y, and +Z sides to via VA1 at its end. Via VA1 extends in the -Z direction from the end of conductive layer PLp1a to the starting end of conductive layer PLp1b. Conductive layer PLp1b extends linearly in the -Y direction from its starting end to the terminals TM2 on the +X and -Y sides.

[0153] In the planar coil PLp2, the conductive layer PLp2b extends spirally from terminals TM11 on the -X, -Y, and -Z sides to via VA11 at its end. Via VA11 extends in the +Z direction from the end of conductive layer PLp2b to the starting end of conductive layer PLp2a. Conductive layer PLp2a extends linearly in the -Y direction from its starting end to terminals TM12 on the +X and -Y sides. Terminals TM1 and TM2 may be located outside terminals TM11 and TM12 in an XY planar view.

[0154] The connection relationship between the planar coils PLp1 and PLp2 and the surrounding configuration is the same as in the eighth modified example of the embodiment. Planar coil PLp1 functions equivalently as an inductive element Lp1 (see Figure 10). Planar coil PLp2 functions equivalently as an inductive element Lp2 (see Figure 10).

[0155] Even with such a matching circuit 30t, the signal reflection characteristics can be kept within an acceptable range over a wide frequency range FR (see Figure 7).

[0156] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0157] 1 semiconductor integrated circuit, 3 receiving device, C1~C3 capacitive elements, Lp1, Lp2, Ln1, Ln2 inductive elements, R1~R3 ​​resistive elements.

Claims

1. A first inductive element inserted into the first signal line, A second inductive element is inserted into a loop spaced apart from the first signal line and magnetically coupled to the first inductive element, Equipped with, Signal terminals are provided at both ends of the first signal line. No signal terminals are provided on the aforementioned loop. Semiconductor integrated circuit.

2. A resistive element inserted into the loop and connected in series with the second inductive element, A capacitive element is inserted into the loop and connected in series with the second inductive element and the resistive element, Furthermore, it is equipped with The semiconductor integrated circuit according to claim 1.

3. A third inductive element is inserted into the second signal line, A fourth inductive element is inserted into the loop, which is spaced apart from the first signal line and the second signal line, and is magnetically coupled to the third inductive element. Furthermore, it is equipped with The semiconductor integrated circuit according to claim 1.

4. A resistive element inserted into the loop and connected in series with the second inductive element, A capacitive element is inserted into the loop and connected in series with the second inductive element and the resistive element, Furthermore, it is equipped with The semiconductor integrated circuit according to claim 3.

5. A first inductive element inserted into the first signal line, A second inductive element is inserted into a loop spaced apart from the first signal line and magnetically coupled to the first inductive element, A resistive element inserted into the loop and connected in series with the second inductive element, A capacitive element is inserted into the loop and connected in series with the second inductive element and the resistive element, A semiconductor integrated circuit equipped with [specific features / features].

6. A third inductive element is inserted into the second signal line, A fourth inductive element is inserted into the loop, which is spaced apart from the first signal line and the second signal line, and is magnetically coupled to the third inductive element. Furthermore, it is equipped with The semiconductor integrated circuit according to claim 5.

7. A semiconductor integrated circuit according to any one of claims 1 to 6, on which a communication line can be connected, A processing circuit connected to the aforementioned semiconductor integrated circuit and capable of processing signals received by the aforementioned semiconductor integrated circuit, A receiving device equipped with it.

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